Semiconductor package

Abstract

A semiconductor package according to an embodiment of the present invention comprises a package substrate, a substrate adhesive member disposed on the package substrate, a plurality of semiconductor chips including first and second semiconductor chips that are stacked sequentially on the substrate adhesive member in a direction perpendicular to the upper surface of the package substrate and arranged in a horizontal direction perpendicular to the vertical direction, and a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein the upper oxide layer has a first material and the lower oxide layer has a second material, and the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0003] With the trend toward lighter and higher-performance electronic devices, miniaturization and high performance are also being demanded in the semiconductor packaging field. To achieve miniaturization, lightweight design, high performance, large capacity, and high reliability in semiconductor packages, research and development on semiconductor packages with a multi-layered stacked chip structure are continuously being conducted. The problem to be solved

[0005] One of the technical problems that the present invention aims to solve is to provide a semiconductor package with improved integration density and reliability. means of solving the problem

[0007] A semiconductor package according to exemplary embodiments comprises a package substrate, a substrate adhesive member disposed on the package substrate, a plurality of semiconductor chips including first and second semiconductor chips that are stacked sequentially on the substrate adhesive member in a direction perpendicular to the upper surface of the package substrate and arranged in a horizontal direction perpendicular to the vertical direction, and a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein the upper oxide layer has a first material and the lower oxide layer has a second material, and the upper oxide layer of the first semiconductor chip may have an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip.

[0009] A semiconductor package according to exemplary embodiments comprises a package substrate, a substrate adhesive member disposed on the package substrate, a plurality of semiconductor chips sequentially stacked on the substrate adhesive member in a direction perpendicular to the upper surface of the package substrate and arranged in a horizontal direction perpendicular to the vertical direction, and a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, and an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and at least a portion of the upper oxide layer of the semiconductor chips other than the uppermost semiconductor chip among the plurality of semiconductor chips has an oxide bonding region, and the thickness of the upper oxide layer may be smaller than the thickness of the substrate adhesive member.

[0011] A semiconductor package according to exemplary embodiments comprises a package substrate, a plurality of semiconductor chips including first and second semiconductor chips that are stacked sequentially on the package substrate in a direction perpendicular to the upper surface of the package substrate and arranged in a horizontal direction perpendicular to the vertical direction, and a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein the upper oxide layer has a first material and the lower oxide layer has a second material, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in at least a portion of a first region in contact with the lower oxide layer of the second semiconductor chip, and the upper oxide layer does not have an oxide bonding region in the remaining second region excluding the first region, and the porosity of the second material in the oxide bonding region may be lower than that of the second material in the second region. Effects of the invention

[0013] According to embodiments of the present invention, in a multi-stage stacked semiconductor chip structure, a semiconductor package in which a separate adhesive member is omitted is provided by forming an oxide bonding region between adjacent semiconductor chips. Accordingly, the overall thickness of the package is reduced, and the integration density of the semiconductor package can be improved.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. FIGS. 2a and 2b are partial enlarged views illustrating a portion of a semiconductor package according to an exemplary embodiment. FIGS. 3a and FIGS. 3b are a plan view and a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment. FIG. 4 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. FIG. 5 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. FIGS. 6a to 6c are cross-sectional views illustrating a method for manufacturing a semiconductor chip according to exemplary embodiments. FIGS. 7a to 7c are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. Specific details for implementing the invention

[0017] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0019] FIG. 1 is a plan view illustrating a semiconductor package (1000a) according to an exemplary embodiment, FIG. 2a is a partial enlarged view showing an area corresponding to region 'A' of FIG. 1, and FIG. 2b is a partial enlarged view showing an area corresponding to region 'B' of FIG. 1.

[0020] Referring to FIGS. 1 to 2b, a semiconductor package (1000a) according to exemplary embodiments may include a package substrate (100), a plurality of semiconductor chips (200) on the package substrate (100), and a conductive connecting member (300). The semiconductor package (1000a) may further include a sealing material (400).

[0022] In an exemplary embodiment, the package substrate (100) may be a Printed Circuit Board (PCB) or a glass substrate, etc. For example, the package substrate (100) may include a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. Additionally, the package substrate (100) may be a double-sided printed circuit board or a multi-layer printed circuit board.

[0023] The package substrate (100) may include a core board (101), an upper connection pad (110) disposed on the upper part of the core board (101), a lower connection pad (120) disposed on the lower part of the core board (101), and an external terminal (140) connected to the lower connection pad (120).

[0024] The core board (101) may include at least one wiring layer and an insulating layer covering the wiring layer. The wiring layer may form an electrical path within the package substrate (100) and may include at least one metal or an alloy composed of two or more metals selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). An upper connection pad (110) and a lower connection pad (120) may be electrically connected through the wiring layer. The insulating layer may comprise a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler or / and glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) is impregnated into these resins, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine). In an exemplary embodiment, if the package substrate (100) is a PCB substrate, the insulating layer may comprise a core insulating layer of a copper foil laminate.

[0025] The upper connection pad (110) may be embedded in the package substrate (100), but is not limited thereto. The upper connection pad (110) may serve to electrically connect the package substrate (100) and a plurality of semiconductor chips (200) disposed on the package substrate (100). For example, the upper connection pad (110) may be connected to the plurality of semiconductor chips (200) disposed on the package substrate (100) through a conductive connection member (300). The lower connection pad (120) may serve to electrically connect the external terminal (140) and the package substrate (100).

[0026] The external terminal (140) can electrically connect the semiconductor package (1000a), which includes the package substrate (100), to another semiconductor package. The external terminal (140) can come into contact with the lower connection pad (120). In the drawing, the external terminal (140) is shown as a solder ball, but is not limited thereto and may be, for example, a solder bump, a grid array, or a conductive tab. A plurality of external terminals (140) may be formed on the lower surface of the package substrate (100).

[0028] A plurality of semiconductor chips (200) may include a plurality of semiconductor chips (200) stacked on a package substrate (100). A plurality of semiconductor chips (200) may be mounted on the package substrate (100).

[0029] In an exemplary embodiment, at least one plurality of semiconductor chips (200) may be a logic chip such as a CPU (Central Processor Unit), MPU (Micro Processor Unit), GPU (Graphic Processor Unit), or AP (Application Processor), or a non-volatile memory semiconductor chip such as Flash Memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). The Flash Memory may be, for example, V-NAND Flash Memory. According to embodiments, at least one of the plurality of semiconductor chips (200) may be a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). In an exemplary embodiment, at least one of the plurality of semiconductor chips (200) may be a dummy silicon spacer chip for supporting the rest.

[0030] In an exemplary embodiment, the plurality of semiconductor chips (200) may all be of the same type. For example, each of the plurality of semiconductor chips (200) may include a non-volatile memory, such as a flash memory, having substantially the same specifications and substantially the same storage capacity. The plurality of semiconductor chips (200) may have substantially the same size. That is, the plurality of semiconductor chips (200) may have substantially the same horizontal width, the same horizontal length, and the same thickness.

[0032] A plurality of semiconductor chips (200) may be stacked in a direction perpendicular to the upper surface of the package substrate (100), for example, in the z-direction. Each of the plurality of semiconductor chips (200) may be arranged in a horizontal direction perpendicular to the vertical direction, for example, in the x-direction. That is, the plurality of semiconductor chips (200) may be arranged in a stair-step arrangement to have a cascade structure. Accordingly, any one of the plurality of semiconductor chips (200) may be stacked with an offset in the x-direction relative to the semiconductor chip (200) adjacent to said one. That is, the plurality of semiconductor chips (200) may be sequentially offset-aligned. As each of the plurality of semiconductor chips (200) is offset-aligned, a portion of the upper surface may be exposed. In an exemplary embodiment, the plurality of semiconductor chips (200) may include a silicon (Si) material.

[0033] In an exemplary embodiment, a plurality of semiconductor chips (200) may include lower semiconductor chips stacked offset in the x-direction and upper semiconductor chips stacked offset in the direction opposite to the x-direction on the lower semiconductor chips. Although the upper and lower semiconductor chips are each depicted as four, this is not limited thereto, and the number of upper and lower semiconductor chips can be varied. Additionally, according to the embodiments, the plurality of semiconductor chips (200) may have a cascade structure in which both the lower semiconductor chips and the upper semiconductor chips are stacked offset in the same direction, for example, the x-direction.

[0035] Each of the plurality of semiconductor chips (200) may include a semiconductor chip body (210), a chip pad (220) disposed within the semiconductor chip body (210), an upper oxide layer (230) covering the upper surface of the semiconductor chip body (210), and a lower oxide layer (240) covering the lower surface of the semiconductor chip body (210).

[0036] The semiconductor chip body (210) may include a semiconductor substrate. The semiconductor substrate may include, for example, silicon (Si). However, depending on the embodiments, the semiconductor substrate may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The semiconductor substrate may have an active surface and an inactive surface opposite to the active surface. The semiconductor chip body (210) may include a semiconductor device comprising a plurality of discrete devices of various types formed on the active surface.

[0038] A chip pad (220) may be disposed on the active surface of the semiconductor substrate. The chip pad (220) may be embedded in a plurality of semiconductor chips (200), but is not limited thereto. The chip pad (220) may be electrically connected to the chip pad (220) of an adjacent semiconductor chip (200). The chip pad (220) may include a conductive layer such as a metal, a metal nitride, conductive carbon, or a combination thereof. The chip pad (220) may include, for example, Cu, Co, Al, Sn, Ni, Au, Ag, W, WN, Ti, TiN, Ta, TaN, Ru, Pt, or a combination thereof. The chip pad (220) may be electrically connected to active / passive components contained within each of the plurality of semiconductor chips (200).

[0040] The upper oxide layer (230) may cover the upper surface of the semiconductor chip body (210) and cover a portion of the upper surface of the chip pad (220). The upper oxide layer (230) may include a through-hole that exposes a portion of the upper surface of the chip pad (220). The through-hole and the chip pad (220) may be placed on the upper end of each of the plurality of semiconductor chips (200) that are exposed according to the offset alignment. The first thickness (t1) of the upper oxide layer (230) may be in the range of about 10 nm to about 1000 nm. The upper oxide layer (230) may be an oxide layer formed by a deposition process such as CVD (Chemical Vapor Deposition) or a thermal oxidation process, but is not limited thereto. The upper oxide layer (230) may have a first material. The first material may include at least one of silicon oxide (SiO2), silicon nitride (SiN), or silicon carbonitride (SiCN). The first material above may be a porous material, but is not limited thereto.

[0042] The lower oxide layer (240) may cover the lower surface of the semiconductor chip body (210). The second thickness (t2) of the lower oxide layer (240) may be thinner than the first thickness (t1) of the upper oxide layer (230). For example, the second thickness (t2) of the lower oxide layer (240) may be about 5 nm or less. The lower oxide layer (240) may be a native oxide film formed by the oxidation of the semiconductor chip body (210) at room temperature, but is not limited thereto. The lower oxide layer (240) may have a second material. The second material may include silicon oxide (SiO2). The second material may not be a porous material.

[0044] In an exemplary embodiment, a plurality of semiconductor chips (200) may include a first semiconductor chip (200a) and a second semiconductor chip (200b) that are sequentially stacked. The second semiconductor chip (200b) may be stacked on the first semiconductor chip (200a) at a certain distance in the x-direction. Accordingly, a portion of the first upper oxide layer (230a) of the first semiconductor chip (200a) and a portion of the second lower oxide layer (240b) of the second semiconductor chip (200b) may come into contact. The first upper oxide layer (230a) may have a first region (R1) where the first upper oxide layer (230a) contacts the second lower oxide layer (240b) and a remaining second region (R2). The first upper oxide layer (230a) may have an oxide bonding region in which the first material and the second material are bonded in the first region (R1). In an exemplary embodiment, the interface between the first upper oxide layer (230a) and the second lower oxide layer (240b) in the oxide bonding region may not be distinct, but is not limited thereto. The oxide bonding region may be formed, for example, by a covalent bond with oxygen (O). The first upper oxide layer (230a) of the oxide bonding region may have a different material from the first upper oxide layer (230a) of the second region (R2). In an exemplary embodiment, if the first material of the first upper oxide layer (230a) is a porous material, the first material of the second region (R2) may have a higher porosity than the first material in the oxide bonding region. This difference may be due to the relative reduction of the pores in the oxide bonding region caused by an oxide bonding process using water vapor within the pores of the first material.In an exemplary embodiment, the oxide bonding region may include an area extending in the z-direction from the upper surface of the first upper oxide layer (230a) in contact with the second lower oxide layer (240b) to the lower surface of the first upper oxide layer (230a), but is not limited thereto and may include an area extending to a predetermined depth from the upper surface of the first upper oxide layer (230a). That is, according to the embodiments, the first upper oxide layer (230a) may include a lower region where the oxide bonding process is performed only up to the predetermined depth and remains unaffected by the oxide bonding process. The first upper oxide layer (230a) may include a through-hole that does not have the oxide bonding region in the second region (R2) and exposes at least a portion of the upper surface of the chip pad (220).

[0045] In an exemplary embodiment, at least one surface roughness of the upper surface of the upper oxide layer (230) and the lower surface of the lower oxide layer (240) may be about 3 nm or less. This may be formed by surface treatment through a plasma process, as shown in FIG. 6b and FIG. 7a. This may be done to uniformly form an oxide bonding region between the upper oxide layer and the lower oxide layer.

[0046] In a semiconductor package (1000a) according to an exemplary embodiment, a plurality of semiconductor chips (200) are connected to each other through the oxide bonding region, so a separate adhesive layer such as a Die Attach Film (DAF) may be omitted. Accordingly, the overall thickness of the semiconductor package (1000a) may be relatively reduced, and thermal characteristics may be improved by improving the thermal resistance in the z-direction between the plurality of semiconductor chips (200). In addition, the oxide bonding region is formed by a bond between inorganic materials, so it may have higher adhesion than bonding using organic materials.

[0048] In an exemplary embodiment, the semiconductor package (1000a) may further include a substrate adhesive member (150) disposed between the package substrate (100) and a plurality of semiconductor chips (200). The substrate adhesive member (150) may contact the lower surface of the lowest semiconductor chip (200L) among the plurality of semiconductor chips (200). The substrate adhesive member (150) may overlap with the lowest semiconductor chip (200L) in the z-direction. The third thickness (t3) of the substrate adhesive member (150) may be greater than the sum of the first thickness (t1) of the upper oxide layer (230) and the second thickness (t2) of the lower oxide layer (240). The third thickness (t3) of the substrate adhesive member (150) may be in the range of about 3 μm to about 50 μm. The substrate adhesive member (150) may include an organic material, for example, an epoxy resin. For example, the substrate adhesive member (150) may be a die attach film (DAF). The substrate adhesive member (150) may serve to increase the adhesion between the package substrate (100) and the bottom semiconductor chip (200L). The substrate adhesive member (150) may serve to insulate between the package substrate (100) and the bottom semiconductor chip (200L). In an exemplary embodiment, the bottom semiconductor chip (200L) may adhere to the substrate adhesive member (150) without including a bottom oxide layer (240), unlike the remaining semiconductor chips (200), but is not limited thereto and may include a bottom oxide layer (240).

[0050] A conductive connecting member (300) may be formed on one side of a plurality of semiconductor chips (200). The conductive connecting member (300) may electrically connect the plurality of semiconductor chips (200). The conductive connecting member (300) may electrically connect the plurality of semiconductor chips (200) adjacent to each other and some of the plurality of semiconductor chips (200) with the package substrate (100) by contacting the chip pad (220) to the upper connecting pad (110). The conductive connecting member (300) may include a conductive material such as a metallic material. For example, the conductive connecting member (300) may include gold (Au), silver (Ag), etc.

[0052] A sealing material (400) may cover a plurality of semiconductor chips (200) and a conductive connecting member (300) on a package substrate (100). In an exemplary embodiment, the sealing material (400) may be formed to cover the sides and top of the plurality of semiconductor chips. The sides of the sealing material (400) and the package substrate (100) may be exposed substantially in the same plane. The sealing material (400) may be formed, for example, by curing an epoxy molding compound (EMC). The sealing material (400) may protect the plurality of semiconductor chips from external environments such as physical shock or moisture.

[0054] In an exemplary embodiment, the semiconductor package (1000a) may further include at least one semiconductor structure (500) disposed adjacent to a plurality of semiconductor chips (200) on a package substrate (100). The semiconductor structure (500) may be of the same type as the plurality of semiconductor chips (200), but is not limited thereto and may include a semiconductor chip of a different type or a different element. The semiconductor structure (500) may include a control unit that controls signals for the plurality of semiconductor chips (200). In an exemplary embodiment, if the plurality of semiconductor chips (200) are memory chips, the semiconductor structure (500) may be, for example, a memory controller for controlling the memory chips. The memory controller may determine the data processing order of the memory chips and prevent errors and bad sectors. The semiconductor structure (500) can be mounted on the package substrate (100) using a substrate adhesive member (150) and can be electrically connected to the package substrate (100) through a conductive connection member (300).

[0056] FIGS. 3a and 3b are a plan view and a cross-sectional view illustrating a portion of a semiconductor package (1000b) according to an exemplary embodiment. FIGS. 3a and 3b are drawings that partially illustrate only the first semiconductor chip (200a) and the second semiconductor chip (200b) described in FIGS. 1 to 2b. FIG. 3b illustrates a cross-section cut along I-I' of FIG. 3a. Since the semiconductor package (1000b) according to exemplary embodiments has the same features except for a plurality of semiconductor chips (200), a redundant description is omitted.

[0058] Referring to FIGS. 3a and 3b, each of the plurality of semiconductor chips (200) may include a central region (CR) and an edge region (ER) surrounding the central region (CR). The edge region (ER) may include each side of the plurality of semiconductor chips (200). The edge region (ER) may be an area where defects occur due to dicing during a process of dicing a wafer to form semiconductor chips.

[0059] A plurality of semiconductor chips (200) may include a semiconductor chip body (210), a chip pad (220), an upper oxide layer (230), and a lower oxide layer (240), wherein the upper oxide layer (230) includes a first material and the lower oxide layer (240) includes a second material.

[0060] The upper oxide layer (230) of the plurality of semiconductor chips (200) may include an adhesive active portion (AA) in the center region (CR) and an adhesive inactive portion (NA) in the edge region (ER). In an exemplary embodiment, the adhesive inactive portion (NA) may be a region where oxide bonding with the lower oxide layer (240) does not occur due to defects such as voids occurring or changes in material properties, unlike the adhesive active portion (AA). According to the embodiments, the adhesive inactive portion (NA) may be a region where oxide bonding with the lower oxide layer (240) does not occur due to changes in physical structure, such as having a thinner thickness than the adhesive active portion (AA) or including a concave portion. Referring to FIG. 3a and FIG. 3b, for convenience of explanation, the center region (CR), edge region (ER), adhesive active region (AA), and adhesive inactive region (NA) are shown based on the first semiconductor chip (200a), but the entire plurality of semiconductor chips (200), including the second semiconductor chip (200b), may have the same structure.

[0061] In an exemplary embodiment, the second semiconductor chip (200b) may be positioned offset in the x-direction on the first semiconductor chip (200a), and the upper oxide layer (230a) of the first semiconductor chip (200a) may have a first region (R1) in contact with the second lower oxide layer (240b) and a remaining second region (R2). Accordingly, the adhesive inactive region (NA) may extend along three outer surfaces of the first region (R1). The upper oxide layer (230a) of the first semiconductor chip (200a) may have an oxide bonding region in which the first material and the second material are bonded in the adhesive active region (AA) of the first region (R1). The upper oxide layer (230a) of the first semiconductor chip (200a) may not have the oxide bonding region in the second region (R2) and the adhesive inactive region (NA).

[0063] FIG. 4 is a cross-sectional view illustrating a semiconductor package (1000c) according to an exemplary embodiment.

[0065] Referring to FIG. 4, a plurality of semiconductor chips (200) may include lower semiconductor chips (200-1) stacked offset in the x-direction and upper semiconductor chips (200-2) stacked offset in the opposite direction to the x-direction on the lower semiconductor chips (200-1).

[0066] In an exemplary embodiment, the semiconductor package (1000c) may further include a chip adhesive member (250). The chip adhesive member (250) may adhere the lower semiconductor chips (200-1) and the upper semiconductor chips (200-2). The chip adhesive member (250) may be, for example, a die adhesive film (DAF) attached to the lower surface of the semiconductor chip (200) positioned at the bottom of the upper semiconductor chips (200-2). That is, the chip adhesive member (250) may be positioned between the uppermost semiconductor chip of the lower semiconductor chips (200-1) and the lowermost semiconductor chip of the upper semiconductor chips (200-2). Accordingly, unlike the semiconductor package (1000a) of FIG. 1, the upper and lower semiconductor chips (200-1, 200-2) are bonded using a chip adhesive member (250), and each of the upper semiconductor chips (200-2) and each of the lower semiconductor chips (200-1) can be bonded using upper and lower oxide layers (230, 240, see FIG. 2a).

[0067] However, according to the embodiments, the chip adhesive member (250) may be additionally placed between other adjacent semiconductor chips as well as between the upper and lower semiconductor chips (200-1, 200-2). That is, some of the adjacent semiconductor chips may be bonded using the upper and lower oxide layers (230, 240), and the remaining parts may be bonded using the chip adhesive member (250).

[0069] FIG. 5 is a cross-sectional view illustrating a semiconductor package (1000d) according to an exemplary embodiment.

[0071] Referring to FIG. 5, a semiconductor package (1000d) according to exemplary embodiments may include a semiconductor structure (500) disposed on a package substrate (100) and a plurality of semiconductor chips (200) disposed on the semiconductor structure (500).

[0072] Unlike the semiconductor package (1000a) of FIG. 1, the plurality of semiconductor chips (200) and the semiconductor structure (500) are not arranged side by side on the package substrate (100), and the plurality of semiconductor chips (200) are arranged on the semiconductor structure (500), thereby allowing the substrate adhesive member (150) placed at the bottom of the plurality of semiconductor chips (200) to be omitted.

[0073] In an exemplary embodiment, the plurality of semiconductor chips (200) and the semiconductor structure (500) may include different elements and may have different sizes. However, the sizes of the plurality of semiconductor chips (200) and the semiconductor structure (500) are not limited to those illustrated and may be changed in various forms.

[0074] In an exemplary embodiment, a support member (600) disposed between the package substrate (100) and a plurality of semiconductor chips (200) may be further included. The support member (600) may be a structure for supporting the plurality of semiconductor chips (200) together with the semiconductor structure (500). The support member (600) may be a semiconductor chip, but is not limited thereto.

[0076] FIGS. 6a to 6c are cross-sectional views illustrating a method for manufacturing a semiconductor chip according to exemplary embodiments.

[0078] Referring to FIG. 6a, an upper oxide layer (230) can be formed on a wafer structure (WS) including circuit elements and a chip pad (220), and a first tape (10) can be attached on the upper oxide layer (230).

[0079] A wafer structure (WS) may include a first surface (S1) on which a chip pad (220) is placed and a second surface (S2) opposite to the first surface (S1). An oxide film covering the wafer structure (WS) may be formed by performing a deposition process such as CVD (Chemical Vapor Deposition) or a thermal oxidation process on the first surface (S1) of the wafer structure (WS), and an upper oxide layer (230) may be formed by performing a polishing process such as CMP (Chemical Mechanical Polishing) and an etching process that exposes at least a portion of the upper surface of the chip pad (220). The thickness of the upper oxide layer (230) may be in the range of about 10 nm to about 1000 nm.

[0080] Next, a first tape (10) can be formed to cover the upper oxide layer (230) and the upper surface of the exposed chip pad (220). The first tape (10) can serve to protect against physical and / or chemical damage to the circuit element and the chip pad (220).

[0082] Referring to FIG. 6b, the wafer structure (WS) can be removed from the second surface (S2) to a predetermined depth, and a surface treatment process can be performed on the remaining second surface (S2).

[0083] The wafer structure (WS) can be removed from the second surface (S2) by performing a grinding process to a predetermined depth. In an exemplary embodiment, the grinding process may include a plurality of grinding processes.

[0084] In a subsequent process, when separating semiconductor chips through a stealth dicing process, at this stage, a laser can be focused inside the wafer structure (WS) to form a modified layer, and then the grinding process can be performed.

[0085] Next, a plasma process can be performed on the second surface (S2) of the wafer structure (WS) remaining after the grinding process. The plasma used in the plasma process may include, for example, at least one of N2, Ar, or O2. Through the plasma process, the surface of the natural oxide film that can be formed on the second surface (S2) of the wafer structure (WS) can be uniformly formed to form a lower oxide layer (240). The thickness of the lower oxide layer (240) may be about 5 nm or less. Through the plasma process, the surface roughness of the natural oxide film can be controlled to a range of about 10 nm or less, and preferably formed to a range of about 3 nm or less. This may be to improve the adhesion between semiconductor chips by uniformly forming an oxide bonding region through a subsequent process.

[0086] According to the embodiments, a deposition process such as CVD or a thermal oxidation process may be performed on the second surface (S2) of the wafer structure (WS) before performing the plasma process. Accordingly, the thickness of the lower oxide layer (240) can be controlled.

[0088] Referring to FIG. 6c, a second tape (20) covering the second surface (S2) of a wafer structure (WS) can be formed, and the wafer structure (WS) can be cut to form a semiconductor chip (200).

[0089] A second tape (20) can be formed to cover the second surface (S2) of the wafer structure (WS), and the first tape (10) can be removed.

[0090] Next, by extending the second tape (20) and applying tensile stress to the wafer structure (WS), the wafer structure (WS) can be cut to form a semiconductor chip (200).

[0091] However, depending on the embodiments, the method of cutting the wafer structure (WS) to form the semiconductor chip (200) can be varied.

[0092] In an exemplary embodiment, a surface treatment process and a cleaning process for the upper oxide layer (230) may be performed after cutting the wafer structure (WS), but depending on the embodiment, the process may be omitted.

[0094] FIGS. 7a to 7c are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 7a to 7c are drawings illustrating a method for manufacturing a semiconductor package (1000a) of FIG. 1 using a plurality of semiconductor chips (200) formed through the manufacturing method of FIGS. 6a to 6c.

[0096] Referring to FIG. 7a, a semiconductor chip (200) can be formed on a package substrate (100), and a plasma process and a cleaning process can be performed.

[0097] A package substrate (100) comprising a core board (101), an upper connection pad (110), and a lower connection pad (120) is formed, and the semiconductor chip (200) can be mounted on the package substrate (100) using a substrate adhesive member (150) attached to the lower surface of the semiconductor chip (200). The substrate adhesive member (150) may be, for example, a die adhesive film (DAF).

[0098] Next, a plasma process may be performed for surface treatment of the upper surface of the semiconductor chip (200). The upper oxide layer (230) placed on the upper surface of the semiconductor chip (200) may have a standard roughness of about 10 nm or less controlled through the plasma process, and preferably may be formed in a range of about 3 nm or less. This may be done to improve the adhesion between semiconductor chips by uniformly forming an oxide bonding region through a subsequent process.

[0099] Next, a cleaning process can be performed to remove impurities. The cleaning process can be performed using ultrapure water (DI water) or ultrasound. Through the cleaning process, the upper oxide layer (230) can contain a large number of hydroxyl groups (-OH).

[0101] Referring to FIG. 7b, a separate semiconductor chip (200) can be mounted on the semiconductor chip (200) offset by the x-direction, and a plasma process and a cleaning process can be performed.

[0102] In an exemplary embodiment, the semiconductor chip (200) formed in FIG. 7a corresponds to the first semiconductor chip (200a), and the separate semiconductor chip (200) in FIG. 7b may correspond to the second semiconductor chip (200b).

[0103] After performing the plasma process and cleaning process of the first semiconductor chip (200a), the second semiconductor chip (200b) is mounted, and the same plasma process and cleaning process as described in FIG. 7a can be performed.

[0105] Referring to FIG. 7c, a plurality of semiconductor chips (200) can be stacked on a package substrate (100) at a certain distance in the x direction and then an annealing process can be performed.

[0106] In the same manner as described in FIGS. 7a and 7b, the plasma process and the cleaning process can be performed at the mounting stage of each of the plurality of semiconductor chips (200) to form a plurality of semiconductor chips (200) having a certain standard roughness. Accordingly, after stacking the plurality of semiconductor chips (200) on a package substrate (100), an annealing process can be performed to form an oxide bonding region between adjacent semiconductor chips (200). The annealing process can be performed in a range of about 100°C to about 220°C and a range of about 1 atm to about 10 atm. The oxide bonding region may refer to the oxide bonding region described in FIGS. 1 to 2b. By bonding adjacent semiconductor chips (200) through the oxide bonding region, a separate adhesive layer such as DAF can be omitted, and the thickness of the semiconductor package can be reduced.

[0107] However, according to the embodiments, the annealing process may not be performed after all of the plurality of semiconductor chips (200) have been mounted, but may be performed each time each semiconductor chip (200) is stacked together with the plasma process and the cleaning process.

[0109] Next, a conductive connecting member (300, see FIG. 1) connecting the package substrate (100) and the plurality of semiconductor chips (200) can be formed. The conductive connecting member (300) can electrically connect the chip pads (220) of the plurality of semiconductor chips (200) and the upper connecting pad (110) of the package substrate (100).

[0110] In an exemplary embodiment, a plurality of semiconductor chips (200) may all be mounted to perform the annealing process and form a conductive connecting member (300), but is not limited thereto. According to the embodiments, some of the plurality of semiconductor chips (200), for example, lower semiconductor chips stacked offset in the x-direction, may be formed, the annealing process may be performed, and a lower conductive connecting member connecting the lower semiconductor chips and the package substrate (100) may be formed, and then upper semiconductor chips stacked offset in the direction opposite to the x-direction may be formed on the lower semiconductor chips, the annealing process may be performed, and an upper conductive connecting member connecting the upper semiconductor chips and the lower semiconductor chips may be formed.

[0111] Next, a sealing material (400) covering a plurality of semiconductor chips (200) and a conductive connecting member (300) is formed on a package substrate (100), and an external terminal (140) connected to a lower connecting pad (120) of the package substrate (100) is formed to form the semiconductor package (1000a) of FIG. 1.

[0113] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0115] 100: Package substrate 150: Substrate adhesive member 200: Multiple semiconductor chips 200a: First semiconductor chip 200b: Second semiconductor chip 210: Semiconductor chip body 220: Chip pad 230: Upper oxide layer 240: Lower oxide layer 300: Conductive connecting member 400: Suture material

Claims

Claim 1 A semiconductor package comprising: a package substrate; a substrate adhesive member disposed on the package substrate; a plurality of semiconductor chips including first and second semiconductor chips that are sequentially stacked, arranged in a horizontal direction perpendicular to the vertical direction while being stacked perpendicular to the upper surface of the package substrate on the substrate adhesive member; and a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein the upper oxide layer has a first material and the lower oxide layer has a second material, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip, and the upper oxide layer has a porosity in a second region other than the first region that is higher than the porosity in the first region. Claim 2 A semiconductor package according to claim 1, wherein the first material comprises at least one of silicon oxide, silicon nitride, or silicon carbonitride, and the second material comprises silicon oxide. Claim 3 In claim 1, the semiconductor package wherein the thickness of the upper oxide layer is thicker than the thickness of the lower oxide layer. Claim 4 A semiconductor package according to claim 1, wherein at least one of the upper surface of the upper oxide layer and the lower surface of the lower oxide layer has a surface roughness of 3 nm or less. Claim 5 A package substrate; a substrate adhesive member disposed on the package substrate; and a plurality of semiconductor chips including first and second semiconductor chips that are stacked on the substrate adhesive member in a direction perpendicular to the upper surface of the package substrate and arranged offset in a horizontal direction perpendicular to the vertical direction, and stacked sequentially. A semiconductor package comprising a conductive connecting member connecting the above package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein the upper oxide layer has a first material and the lower oxide layer has a second material, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip, and the upper oxide layer of the first semiconductor chip includes a second region other than the first region, wherein the second region includes a through-hole that exposes at least a portion of the upper surface of the chip pad, and the second region of the upper oxide layer has a material different from the oxide bonding region of the upper oxide layer. Claim 6 A package substrate; a substrate adhesive member disposed on the package substrate; and a plurality of semiconductor chips including first and second semiconductor chips that are stacked on the substrate adhesive member in a direction perpendicular to the upper surface of the package substrate and arranged offset in a horizontal direction perpendicular to the vertical direction, and stacked sequentially. A semiconductor package comprising a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein the upper oxide layer has a first material and the lower oxide layer has a second material, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip, and each of the plurality of semiconductor chips has a central region and an edge region surrounding the central region and including the respective side of the plurality of semiconductor chips, and wherein the upper oxide layer comprises an adhesive active portion of the central region and an adhesive inactive portion of the edge region. Claim 7 In claim 6, the oxide bonding region is disposed in a part of the adhesive active portion and not in the adhesive inactive portion of the semiconductor package. Claim 8 A semiconductor package comprising: a package substrate; a substrate adhesive member disposed on the package substrate; a plurality of semiconductor chips sequentially stacked on the substrate adhesive member, arranged in a horizontal direction perpendicular to the vertical direction while being stacked perpendicular to the upper surface of the package substrate; and a conductive connecting member connecting the package substrate and the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises a semiconductor chip body, a chip pad disposed within the semiconductor chip body, an upper oxide layer covering the upper surface of the semiconductor chip body while exposing a portion of the upper surface of the chip pad, and a lower oxide layer covering the lower surface of the semiconductor chip body, wherein at least a portion of the upper oxide layer of the semiconductor chips other than the uppermost semiconductor chip among the plurality of semiconductor chips has an oxide bonding region, and the thickness of the upper oxide layer is smaller than the thickness of the substrate adhesive member. Claim 9 In claim 8, the plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip that are sequentially stacked, and the upper oxide layer of the first semiconductor chip includes a first region bonded to the second semiconductor chip and a remaining second region, and the material of the first region is different from the material of the second region in the semiconductor package. Claim 10 In claim 9, the semiconductor package wherein the second region comprises at least a portion of the region surrounding the side of the upper oxide layer.

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