Semiconductor package and method of fabricating the same

Abstract

A method for manufacturing a semiconductor package according to one aspect of the present invention comprises: forming a plurality of first passivation patterns at the wafer level on a semiconductor substrate having a plurality of semiconductor chips each having a plurality of conductive pads formed thereon; sawing the semiconductor substrate to separate the plurality of semiconductor chips from one another; attaching the separated semiconductor chips onto a carrier substrate having an adhesive tape on its upper surface, such that the first passivation patterns face the adhesive tape; forming a molding portion on the carrier substrate to cover the semiconductor chips; removing the adhesive tape and the carrier substrate; removing a portion protruding from the surface portion of the molding portion from the first passivation pattern so that the upper surface of the first passivation pattern and the upper surface of the molding portion do not form a step difference in the boundary region and the upper surface of the first passivation pattern and the upper surface of the molding portion become flat; and forming a redistribution pattern and a bump electrically connected to the conductive pads on at least a portion of the semiconductor chips and the molding portion.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor package and a method for manufacturing the same. Background Technology

[0002] Today, the trend in the electronics industry is toward becoming lighter, smaller, faster, more multifunctional, and higher-performing. One of the key technologies that enables the setting of such product design goals is packaging technology, and accordingly, one of the packages developed recently is the Chip Scale Package (CSP).

[0003] Chip scale packaging provides miniaturized semiconductor packages at the level of a semiconductor chip. However, while chip scale packaging offers a significant advantage in terms of size, it is also true that it still has several disadvantages compared to conventional plastic packages. One of these is the high manufacturing cost, which results in poor price competitiveness; consequently, wafer level packaging (WLP) is emerging as a solution to address these issues.

[0004] For these wafer-level packages, Fan-in Wafer Level Packages (FI WLP) and Fan-out Wafer Level Packages (FO WLP) are being developed. Since Fan-out Wafer Level Packages (FO WLP) allow wiring to be extended to the molding portion, which is the outer part of the semiconductor chip, defects caused by solder ball size and pitch can be reduced, and a standardized ball layout can be used even if the semiconductor chip size varies.

[0005] However, there is a problem where a step difference occurs at the boundary between the semiconductor chip and the molding part, causing defects in subsequent processes. The problem to be solved

[0006] Accordingly, the present invention aims to solve the aforementioned problems by providing a semiconductor package and a method for manufacturing the same that can suppress defects in subsequent processes by preventing the occurrence of a step difference at the boundary between the semiconductor chip and the molding part.

[0007] However, these tasks are exemplary and do not limit the scope of the invention. means of solving the problem

[0008] A method for manufacturing a semiconductor package according to one aspect of the present invention for solving the above technical problem comprises: forming a plurality of first passivation patterns at the wafer level on a semiconductor substrate on which a plurality of semiconductor chips, each including a plurality of conductive pads, are formed; sawing the semiconductor substrate to separate the plurality of semiconductor chips from one another; attaching the separated semiconductor chips onto a carrier substrate on which an adhesive tape is located on the upper surface, such that the first passivation pattern faces the adhesive tape; forming a molding portion on the carrier substrate to cover the semiconductor chips; removing the adhesive tape and the carrier substrate; removing a portion protruding from the surface portion of the molding portion from the first passivation pattern so that the upper surface of the first passivation pattern and the upper surface of the molding portion do not form a step difference in the boundary region and the upper surface of the first passivation pattern and the upper surface of the molding portion become flat; and forming a redistribution pattern and a bump electrically connected to the conductive pads on at least a portion of the semiconductor chips and the molding portion.

[0009] In the method for manufacturing the semiconductor package above, the attachment step may include a step of attaching the adhesive tape with a portion of the first passivation pattern drawn into the interior of the adhesive tape.

[0010] In the method for manufacturing the semiconductor package above, after performing the attachment step, the first passivation pattern may be attached to the adhesive tape in a state where only a portion of the thickness of the first passivation pattern is drawn into the interior of the adhesive tape.

[0011] In the method for manufacturing the semiconductor package above, immediately after performing the step of removing the adhesive tape and the carrier substrate, the portion protruding from the surface portion of the molding portion may be a part of the first passivation pattern rather than the conductive pad and the semiconductor substrate.

[0012] In the method for manufacturing the semiconductor package above, the step of removing a portion protruding from the surface portion of the molding portion among the first passivation pattern may include a step of removing a portion protruding from the surface portion of the molding portion among the first passivation pattern by a grinding process.

[0013] In the method for manufacturing the semiconductor package described above, in the step of forming a plurality of first passivation patterns at the wafer level, the thickness of the first passivation pattern is 10 μm or more, and after performing the step of removing a portion protruding from the surface portion of the molding portion among the first passivation patterns, the thickness of the first passivation pattern may be 5 μm or more.

[0014] In the method for manufacturing the semiconductor package above, the step of forming the molding portion may include the step of forming the molding portion to cover the exposed side of the first passivation pattern.

[0015] The method for manufacturing the semiconductor package may further include the step of forming a second passivation pattern interposed between the redistribution pattern and the bump or between the redistribution pattern and the conductive pad.

[0016] In the method for manufacturing the semiconductor package above, the redistribution pattern can be formed across the boundary between the semiconductor chip and the molding portion.

[0017] In the method for manufacturing the semiconductor package above, after the step of forming the molding portion, the first passivation pattern is located only on the semiconductor chip that is inside the molding portion, and the second passivation pattern is located on the semiconductor chip and can extend further to be located on the molding portion.

[0018] A semiconductor package according to another aspect of the present invention for solving the above problem may include a semiconductor package manufactured according to the manufacturing method described above. Effects of the invention

[0019] According to some embodiments of the present invention as described above, a semiconductor package and a method for manufacturing the same can be implemented to prevent the occurrence of a step difference at the boundary between the semiconductor chip and the molding part, thereby suppressing defects in subsequent processes.

[0020] Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0021] FIGS. 1 to 6 are schematic cross-sectional views illustrating a semiconductor package and a method for manufacturing the same according to a comparative example of the present invention. FIGS. 7 to 15 are schematic cross-sectional views illustrating a semiconductor package and a method for manufacturing the same according to an embodiment of the present invention. Specific details for implementing the invention

[0022] Hereinafter, several preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0023] The embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention to those skilled in the art.

[0024] Throughout the specification, the same reference numerals denote the same elements. In the drawings, the thickness or size of each layer is exaggerated for convenience and clarity of explanation. Additionally, variations in the depicted shapes may be expected in the drawings depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be interpreted as being limited to specific shapes of the areas depicted in this specification, but should include variations in shape resulting from manufacturing, for example.

[0025] FIGS. 1 to 6 are schematic cross-sectional views illustrating a semiconductor package and a method for manufacturing the same according to a comparative example of the present invention.

[0026] Referring to FIGS. 1 and 2, a semiconductor substrate (110) may be provided on which a plurality of semiconductor chips (120), each including a plurality of conductive pads (122), are formed. Structures of semiconductor devices constituting the semiconductor chips (120) may be formed on the semiconductor substrate (110). Subsequently, the semiconductor substrate (110) is sawed to separate the plurality of semiconductor chips (120) from each other. Referring to FIGS. 9 and 10, the semiconductor chips (120) are attached to a carrier substrate (160).

[0027] Referring to FIGS. 3 and 4, a separated semiconductor chip (120) is attached to a carrier substrate (160) on which an adhesive tape (162) is positioned on the upper surface. Since the adhesive tape (162) includes a soft adhesive layer, the upper surface of the conductive pad (122) and the semiconductor substrate (110) can be drawn into the adhesive tape (162) during the process of attaching the semiconductor chip (120) to the carrier substrate (160). After attaching the semiconductor chip (120) to the carrier substrate (160), the upper surface of the conductive pad (122) and the semiconductor substrate (110) remains in a state where it is drawn into the adhesive tape (162).

[0028] Referring to FIG. 5, a molding portion (164) is formed on a carrier substrate (160) to cover a semiconductor chip (120). The molding portion (164) is formed to cover the rear and side surfaces of the semiconductor substrate (110).

[0029] Referring to FIG. 6, the adhesive tape (162) and the carrier substrate (160) are removed. Immediately after removing the adhesive tape (162) and the carrier substrate (160), the portion protruding from the surface of the molding portion (164) is the conductive pad (122) and the semiconductor substrate (110). The thickness (T1) of the semiconductor substrate (110) protruding from the surface of the molding portion (164) may be 10 μm to 15 μm or more.

[0030] A step is formed in the boundary region between the semiconductor substrate (110) and the molding portion (164) that protrudes from the surface portion of the molding portion (164). Under conditions where such a step is formed, a redistribution pattern can be formed in a subsequent process. In a fan-out wafer level package (FOWLP) structure, the redistribution pattern can be formed across the boundary between the semiconductor chip (120) and the molding portion (164).

[0031] In this case, since a step difference is formed in the boundary area between the semiconductor chip (120) and the molding part (164), defects may occur during the process of forming the redistribution pattern, and the implemented redistribution pattern may be disconnected. Due to the roughness defect on the surface of the molding part (164), there is a problem in that the step coverage is poor when depositing the seed layer of the redistribution pattern during the process of forming the redistribution pattern, and the redistribution pattern is disconnected.

[0032] In the following, a semiconductor package and a method for manufacturing the same are disclosed according to the technical concept of the present invention for solving these problems.

[0033] FIGS. 7 to 15 are schematic cross-sectional views illustrating a semiconductor package and a method for manufacturing the same according to an embodiment of the present invention.

[0034] Referring to FIG. 7, a semiconductor substrate (110) may be provided, wherein a plurality of semiconductor chips (120), each comprising a plurality of conductive pads (122), are formed. For example, the semiconductor substrate (110) may include a semiconductor wafer and / or a semiconductor epitaxial layer. For example, the semiconductor substrate (110) may include silicon, germanium, silicon-germanium, etc., as a semiconductor material.

[0035] Structures of semiconductor devices constituting semiconductor chips (120) may be formed on the semiconductor substrate (110). For example, the structures of semiconductor devices may include transistors and / or passive components, and furthermore, wiring structures connecting them may be formed. Conductive pads (122) may function as external terminals of the semiconductor chips (120). The conductive pads (122) may be, for example, conductive pads containing aluminum.

[0036] Next, a plurality of first passivation patterns (166) are formed at the wafer level on a semiconductor substrate (110) on which a plurality of semiconductor chips (120), each including a plurality of conductive pads (122), are formed. The first passivation patterns (166) may include, for example, polyimide (PI). Specifically, the first passivation patterns (166) can be realized by coating a polyimide layer, performing exposure and development processes to pattern, and then performing a curing process.

[0037] Referring to FIGS. 7 and 8, the semiconductor substrate (110) is subsequently sawed to separate a plurality of semiconductor chips (120) from each other. Optionally, before sawing the semiconductor substrate (110), a portion of the semiconductor substrate (110) may be removed from its back surface through a back grinding process so that it can be thinned.

[0038] The thickness (T2) of the first passivation pattern (166) can be formed to be 10 μm or more, taking into account the part to be ground in a subsequent process.

[0039] Referring to FIGS. 9 and 10, a semiconductor chip (120) is attached to a carrier substrate (160). Specifically, the separated semiconductor chip (120) is attached to a carrier substrate (160) on which an adhesive tape (162) is located on the upper surface, in a direction in which a first passivation pattern (166) faces the adhesive tape (162).

[0040] The adhesive tape (162) may be, for example, an adhesive tape for temporary fixation that can be easily attached at room temperature and easily detached at high temperature by applying heat, and may be, for example, a high-temperature release tape such as REVALPHA tape. Since the adhesive tape (162) includes a soft adhesive layer, a portion of the first passivation pattern (166) may be drawn into the adhesive tape (162) during the process of attaching the semiconductor chip (120) onto the carrier substrate (160). After attaching the semiconductor chip (120) onto the carrier substrate (160), only a portion of the thickness of the first passivation pattern (166) is maintained within the adhesive tape (162).

[0041] Referring to FIG. 11, a molding portion (164) is formed to cover a semiconductor chip (120) on a carrier substrate (160). For example, the molding portion (164) can be formed with an epoxy molding compound (EMC) using a method such as transfer molding or insert molding.

[0042] The molding portion (164) is formed to cover the rear and side of the semiconductor substrate (110) and further to cover the exposed side of the first passivation pattern (166). The exposed side of the first passivation pattern (166) refers to the side of the first passivation pattern (166) that is exposed and not inserted into the adhesive tape (162).

[0043] Referring to FIG. 12, the adhesive tape (162) and the carrier substrate (160) are removed. Immediately after removing the adhesive tape (162) and the carrier substrate (160), the portion protruding from the surface of the molding portion (164) may be part of the first passivation pattern (166), rather than the conductive pad (122) and the semiconductor substrate (110). The thickness (T3) of the first passivation pattern (166) protruding from the surface of the molding portion (164) is smaller than the thickness (T2) of the first passivation pattern (166) shown in FIG. 8.

[0044] Referring to FIG. 13, a portion protruding from the surface of the molding portion (164) among the first passivation pattern (166) can be removed. This removal process can be implemented as a front grinding process of the semiconductor chip (120).

[0045] The portion of the first passivation pattern (166) protruding from the surface of the molding portion (164) as a target for removal has a thickness of T3. After performing the step of removing the portion of the first passivation pattern (166) protruding from the surface of the molding portion (164), the thickness of the first passivation pattern (166) may be 5 μm or more.

[0046] By removing the portion protruding from the surface of the molding portion (164) in the first passivation pattern (166), the upper surface of the first passivation pattern (166) and the upper surface of the molding portion (164) do not form a step difference in the boundary area, and the upper surface of the first passivation pattern (166) and the upper surface of the molding portion (164) become flat.

[0047] Referring to FIG. 14, a method for manufacturing a semiconductor package according to one embodiment of the present invention forms a redistribution pattern (170) electrically connected to a conductive pad (122) on a semiconductor chip (120) and on a molding portion (164). For example, the redistribution pattern (170) may include a copper (Cu) pattern as a conductive layer pattern. In a fan-out wafer level package (FOWLP) structure, the redistribution pattern (170) may be formed across the boundary between the semiconductor chip (120) and the molding portion (164).

[0048] In this case, no step is formed in the boundary area between the semiconductor chip (120) and the molding part (164), and the upper surface of the semiconductor chip (120), that is, the upper surface of the first passivation pattern (166) and the upper surface of the molding part (164) are connected flatly, so defects can be prevented in the process of forming the redistribution pattern (170), and the implemented redistribution pattern (170) is not disconnected. By improving the roughness of the surface of the molding part (164), the step coverage is improved when depositing the seed layer of the redistribution pattern during the process of forming the redistribution pattern (170), and the redistribution pattern (170) can be prevented from being disconnected.

[0049] In this way, the semiconductor package can be seen as having a fan-out wafer level package (FO WLP) structure in that the redistribution pattern (170) extends beyond the semiconductor chip (120) onto the molding portion (164). According to this semiconductor package, since the area up to the molding portion (164) can be utilized, the number of bumps (176), such as conductive balls, can be increased.

[0050] Meanwhile, a second passivation pattern (171) can be formed on the redistribution pattern (170). The second passivation pattern (171) may include, for example, polyimide (PI). Specifically, the second passivation pattern (171) can be realized by coating a polyimide layer, performing exposure and development processes to pattern it, and then proceeding with a curing process. In the area where the redistribution pattern (170) is exposed through the second passivation pattern (171), an Under Bump Metallization (UBM) pattern (174) and a bump pattern (176) are formed. The bump pattern (176) can be formed by placing a solder ball on the UBM pattern (174) and then performing a heat treatment process. The UBM pattern (174) and the bump pattern (176) can be electrically connected to the conductive pad (122) through the rewiring pattern (170).

[0051] As explained above, the second passivation pattern (171) interposed between the redistribution pattern (170) and the bump pattern (176) is located on the semiconductor chip (120) and can extend further onto the molding portion (164). In contrast, the first passivation pattern (166) is located only on the semiconductor chip (120) inside the molding portion (164).

[0052] Referring to FIG. 15, a method for manufacturing a semiconductor package according to another embodiment of the present invention forms a second-1 passivation pattern (171_1) on a semiconductor chip (120) and on a molding portion (164). The second-1 passivation pattern (171_1) may include, for example, polyimide (PI). Specifically, the second-1 passivation pattern (171_1) can be realized by coating a polyimide layer, performing exposure and development processes to pattern, and then performing a curing process. Subsequently, a redistribution pattern (170) electrically connected to a conductive pad (122) is formed on the second-1 passivation pattern (171_1). For example, the redistribution pattern (170) may include a copper (Cu) pattern as a conductive layer pattern.

[0053] In a fan-out wafer level package (FOWLP) structure, a redistribution pattern (170) can be formed across the boundary between the semiconductor chip (120) and the molding portion (164). In this case, no step is formed in the boundary area between the semiconductor chip (120) and the molding portion (164), and the upper surface of the semiconductor chip (120), that is, the upper surface of the first passivation pattern (166) and the upper surface of the molding portion (164), are connected flatly, so defects can be prevented in the process of forming the redistribution pattern (170), and the implemented redistribution pattern (170) is not disconnected. By improving the roughness of the surface of the molding portion (164), the step coverage is improved when depositing the seed layer of the redistribution pattern during the process of forming the redistribution pattern (170), and the redistribution pattern (170) can be prevented from being disconnected.

[0054] In this way, the semiconductor package can be seen as having a fan-out wafer level package (FO WLP) structure in that the redistribution pattern (170) extends beyond the semiconductor chip (120) onto the molding portion (164). According to this semiconductor package, since the area up to the molding portion (164) can be utilized, the number of bumps (176), such as conductive balls, can be increased.

[0055] Meanwhile, a second-second passivation pattern (171_2) can be formed on the redistribution pattern (170). The second-second passivation pattern (171_2) may include, for example, polyimide (PI). Specifically, the second-second passivation pattern (171_2) can be realized by coating a polyimide layer, performing exposure and development processes to pattern it, and then proceeding with a curing process. The second passivation pattern (171) is composed of the second-first passivation pattern (171_1) and the second-second passivation pattern (171_2). An Under Bump Metallization (UBM) pattern (174) and a bump pattern (176) are formed in the area where the redistribution pattern (170) is exposed through the second-second passivation pattern (171_2). The bump pattern (176) can be formed by placing a solder ball on the UBM pattern (174) and then performing a heat treatment process. The UBM pattern (174) and the bump pattern (176) can be electrically connected to the conductive pad (122) through the redistribution pattern (170).

[0056] As described above, the second passivation pattern (171), which is interposed between the redistribution pattern (170) and the conductive pad (122) or between the redistribution pattern (170) and the bump pattern (176), is located on the semiconductor chip (120) and can extend further onto the molding portion (164). In contrast, the first passivation pattern (166) is located only on the semiconductor chip (120) which is inside the molding portion (164).

[0057] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0058] 110: Semiconductor substrate 120: Semiconductor chip 122: Challenge Pad 160: Carrier substrate 162: Adhesive tape 164: Molding part 166: The first passivation pattern 170: Rewiring pattern 171: The Second Passivation Pattern 174: UBM Pattern 176: Bump Pattern

Claims

Claim 1 A step of forming a plurality of first passivation patterns at the wafer level on a semiconductor substrate having a plurality of semiconductor chips each comprising a plurality of conductive pads; a step of sawing the semiconductor substrate to separate the plurality of semiconductor chips from each other; a step of attaching the separated semiconductor chips on a carrier substrate having an adhesive tape located on its upper surface, such that the first passivation pattern faces the adhesive tape, and attaching the semiconductor chips in such a state where only a portion of the thickness of the first passivation pattern is recessed into the interior of the adhesive tape; a step of forming a molding portion to cover the semiconductor chips on the carrier substrate; a step of removing the adhesive tape and the carrier substrate; and a step in which, while the portion protruding from the surface of the molding portion is not the semiconductor chip or the conductive pad but a part of the first passivation pattern, only the portion protruding from the surface of the molding portion within the first passivation pattern is removed by a grinding process so that the upper surface of the first passivation pattern and the upper surface of the molding portion become flat without a step difference in the boundary region. A method for manufacturing a semiconductor package, comprising the step of forming a redistribution pattern and a bump electrically connected to the conductive pad on at least a portion of the semiconductor chip and the molding portion. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 A method for manufacturing a semiconductor package according to claim 1, wherein, in the step of forming a plurality of first passivation patterns at the wafer level, the thickness of the first passivation pattern is 10 μm or more, and after performing the step of removing a portion protruding from the surface portion of the molding part among the first passivation patterns, the thickness of the first passivation pattern is 5 μm or more. Claim 7 A method for manufacturing a semiconductor package according to claim 1, wherein the step of forming the molding portion comprises the step of forming the molding portion to cover the exposed side of the first passivation pattern. Claim 8 A method for manufacturing a semiconductor package according to claim 1, further comprising the step of forming a second passivation pattern on the first passivation pattern after removing a portion protruding from the surface portion of the molding portion among the first passivation patterns, wherein the first passivation pattern is located only on the semiconductor chip which is inside the molding portion, and the second passivation pattern is located on the semiconductor chip and further extends to be located on the molding portion. Claim 9 A method for manufacturing a semiconductor package according to claim 8, wherein the rewiring pattern is formed across the boundary between the semiconductor chip and the molding portion. Claim 10 delete Claim 11 delete

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