Memory device and operating method thereof

Abstract

The present invention relates to an electronic device, and the memory device according to the present invention includes memory cells, a peripheral circuit that performs a verification operation to identify threshold voltages of the memory cells using a first verification voltage and a second verification voltage greater than the first verification voltage, and a program operation control unit that controls the peripheral circuit to apply a first control signal having a magnitude of a first voltage during a first interval to a page buffer connected to a first memory cell having a threshold voltage greater than the first verification voltage and smaller than the second verification voltage among the memory cells after the verification operation is terminated, and then applies a second control signal having a magnitude of a second voltage lower than the first voltage.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] The programming operation is an operation that raises the threshold voltage of memory cells. Since the physical characteristics of each memory cell are different, the degree to which the threshold voltage of each memory cell rises varies during the programming operation. Accordingly, the memory device applies voltages of different magnitudes to the bit lines according to the magnitude of the threshold voltage of each memory cell to form a narrow distribution of threshold voltages among memory cells that have the same programming state as the target programming state during the programming operation. However, if voltages of different magnitudes are applied between bit lines, coupling phenomena caused by parasitic capacitance may occur between bit lines as the wiring spacing between bit lines narrows. Furthermore, if coupling phenomena occur between bit lines, the voltage may not rise by the amount intended to be applied to the bit lines. Prior art literature

[65535] Korean Patent Publication No. 10-2017-0011324 The problem to be solved

[0003] An embodiment of the present invention provides a memory device capable of improving the threshold voltage distribution of memory cells during program operation and a method of operating the same. means of solving the problem

[0004] A memory device according to an embodiment of the present invention includes memory cells, a peripheral circuit that performs a verification operation to identify threshold voltages of the memory cells using a first verification voltage and a second verification voltage greater than the first verification voltage, and a program operation control unit that, after the verification operation is terminated, controls the peripheral circuit to apply a first control signal having a magnitude of a first voltage during a first interval to a page buffer connected to a first memory cell having a threshold voltage greater than the first verification voltage and smaller than the second verification voltage among the memory cells, and then applies a second control signal having a magnitude of a second voltage lower than the first voltage.

[0005] A method of operating a memory device according to an embodiment of the present invention includes the steps of: performing a verification operation to identify threshold voltages of memory cells using a first verification voltage and a second verification voltage greater than the first verification voltage; after the verification operation is terminated, applying a first control signal having a magnitude of a first voltage during a first interval to a page buffer connected to a first memory cell having a threshold voltage greater than the first verification voltage and smaller than the second verification voltage among the memory cells; and applying a second control signal having a magnitude of a second voltage lower than the first voltage to a page buffer connected to the first memory cell. Effects of the invention

[0006] According to the present technology, a memory device capable of improving the threshold voltage distribution of memory cells during program operation and a method of operating the same are provided. Brief explanation of the drawing

[0007] FIG. 1 is a drawing for explaining a memory system including a memory device according to an embodiment of the present invention. Figure 2 is a diagram illustrating the structure of the memory device of Figure 1. FIG. 3 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BKLz) of FIG. 2. Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device. Figure 5 is a diagram illustrating the program operation of a memory device. Figure 6 is a diagram illustrating the operation of the DPGM of a memory device. FIG. 7 is a diagram illustrating the operation of a page buffer circuit according to an embodiment of the present invention. Figure 8 is a diagram illustrating the program voltage application operation in the program operation of a memory device. FIG. 9 is a diagram illustrating the program voltage application operation in the program operation of a memory device according to an embodiment of the present invention. FIG. 10 is a flowchart for explaining program operation according to an embodiment of the present invention. FIG. 11 is a block diagram showing a memory card system to which a memory system according to one embodiment of the present invention is applied. FIG. 12 is a block diagram showing a user system to which a memory system according to one embodiment of the present invention is applied. Specific details for implementing the invention

[0008] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0010] FIG. 1 is a drawing for explaining a memory system including a memory device according to an embodiment of the present invention.

[0011] Referring to FIG. 1, the memory system (50) may include a memory device (100) and a memory controller (200). The memory system (50) may be a device that stores data under the control of a host (300), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0012] The memory system (50) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (300). For example, the memory system (50) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc.

[0013] The memory system (50) can be manufactured in any one of various types of package forms. For example, the memory system (50) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0014] The memory device (100) can store data. The memory device (100) operates in response to the control of the memory controller (200). The memory device (100) may include a memory cell array (not shown) comprising a plurality of memory cells that store data.

[0015] Memory cells can be configured as Single Level Cells (SLC) that store one bit of data, Multi Level Cells (MLC) that store two bits of data, Triple Level Cells (TLC) that store three bits of data, or Quad Level Cells (QLC) that can store four bits of data.

[0016] A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A single memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in a memory device (100) or reading data stored in a memory device (100). A memory block may be a unit for erasing data.

[0017] In the embodiment, the memory device (100) may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0018] A memory device (100) receives a command and an address from a memory controller (200) and is configured to access an area selected by the address among memory cell arrays. The memory device (100) can perform operations instructed by the command on the area selected by the address. For example, the memory device (100) can perform a write operation (program operation), a read operation, and an erase operation. During a write operation, the memory device (100) will program data in the area selected by the address. During a read operation, the memory device (100) will read data from the area selected by the address. During an erase operation, the memory device (100) will erase data stored in the area selected by the address.

[0019] In an embodiment, the memory device (100) may include a program operation control unit (140).

[0020] The program operation control unit (140) can control the program operation for the memory cells. The program operation may be an operation of storing data in the memory cells. Specifically, the program operation may be an operation of raising the threshold voltage of the memory cells according to the data to be stored in the memory cells. When the program operation is performed, the memory cells may have a threshold voltage corresponding to any one of a plurality of program states. The plurality of program states may be determined according to the number of data bits stored in a single memory cell. For example, if a single memory cell is programmed as a Triple Level Cell (TLC) that stores three bits of data, the plurality of program states may mean an erase state and first to seventh program states. The threshold voltage of the memory cells after the program operation is performed may be determined according to the data to be stored in the memory cells. Each memory cell may have one of the plurality of program states as a target program state according to the data to be stored.

[0021] In an embodiment, the program operation may include a plurality of program loops. Each program loop may include a program voltage application operation and a verification operation. The program voltage application operation may be an operation of raising the threshold voltage of memory cells using a program voltage. The verification operation may be an operation of identifying whether the threshold voltage of memory cells has reached a threshold voltage corresponding to a target program state using a verification voltage.

[0022] The program operation control unit (140) can determine the voltage to be applied to the bit lines connected to the memory cells during the program voltage application operation according to the threshold voltage of the memory cells identified by the verification voltage. For example, if the threshold voltage of the memory cells during the verification operation is greater than the verification voltage corresponding to the target program state, the memory cells may be identified as having reached the target program state. Memory cells having a threshold voltage corresponding to the target program state may not have their threshold voltage rise any further. At this time, the program operation control unit (140) may apply a program prohibition voltage to the bit lines connected to the memory cells having a threshold voltage corresponding to the target program state during the program voltage application operation. As another example, if the threshold voltage of the memory cells during the verification operation is less than the verification voltage corresponding to the target program state, the memory cells may be identified as not having reached the target program state. Memory cells that have not reached the threshold voltage corresponding to the target program state may have their threshold voltage rise further. At this time, the program operation control unit (140) can apply a program allowable voltage to the bit lines connected to memory cells that do not have a threshold voltage corresponding to the target program state when the program voltage application operation is performed.

[0023] In an embodiment, the verification operation may be an operation that identifies the threshold voltages of memory cells using a plurality of verification voltages. The program operation control unit (140) may determine the magnitude of the voltage to be applied to the bit lines connected to the memory cells during the program voltage application operation according to the magnitude of the threshold voltages of the memory cells identified by the plurality of verification voltages. For example, in the case of a Double Verify PGM (DPGM) that identifies the threshold voltages of memory cells using two verification voltages, a program allowable voltage may be applied to the bit lines connected to memory cells having a threshold voltage lower than the pre-verification voltage during the program voltage application operation. A precharge voltage may be applied to the bit lines connected to memory cells having a threshold voltage greater than the pre-verification voltage and smaller than the main verification voltage during the program voltage application operation. The magnitude of the main verification voltage may be a voltage greater than the pre-verification voltage. The main verification voltage may be a threshold voltage corresponding to the target program state of the memory cells. The magnitude of the precharge voltage may be a voltage greater than the program allowable voltage.

[0024] The memory controller (200) can control the overall operation of the memory system (50).

[0025] When power is applied to the memory system (50), the memory controller (200) can execute firmware (FW). If the memory device (100) is a flash memory device, the firmware (FW) may include a Host Interface Layer (HIL) that controls communication with the host (300), a Flash Translation Layer (FTL) that controls communication between the host (300) and the memory device (100), and a Flash Interface Layer (FIL) that controls communication with the memory device (100).

[0026] In an embodiment, the memory controller (200) receives data and a logical block address (LBA) from the host (300) and can convert the logical block address into a physical block address (PBA) representing the addresses of memory cells to which data included in the memory device (100) will be stored. In this specification, the logical block address (LBA) and “logical address” or “logical address” may be used interchangeably. In this specification, the physical block address (PBA) and “physical address” or “physical address” may be used interchangeably.

[0027] The memory controller (200) can control the memory device (100) to perform write operations, read operations, or erase operations, etc., according to a request from the host (300). When performing a write operation, the memory controller (200) can provide a write command, a physical block address, and data to the memory device (100). When performing a read operation, the memory controller (200) can provide a read command and a physical block address to the memory device (100). When performing an erase operation, the memory controller (200) can provide an erase command and a physical block address to the memory device (100).

[0028] In an embodiment, the memory controller (200) can independently generate commands, addresses, and data and transmit them to the memory device (100) regardless of a request from the host (300). For example, the memory controller (200) can provide commands, addresses, and data to the memory device (100) for performing read and write operations associated with performing wear leveling, read reclaim, garbage collection, etc.

[0029] In an embodiment, the memory controller (200) can control at least two memory devices (100). In this case, the memory controller (200) can control the memory devices (100) according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling the operation of at least two memory devices (100) so that it overlaps.

[0030] The host (300) can communicate with the memory system (50) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0031] In an embodiment, the memory system (50) may include a buffer memory (not shown). For example, the buffer memory may temporarily store data received from the host (300) or data received from the memory device (100), or temporarily store metadata of the memory device (100) (e.g., a mapping table). The buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0032] Figure 2 is a diagram illustrating the structure of the memory device of Figure 1.

[0033] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0034] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to an address decoder (121) via row lines (RL). The plurality of memory blocks (BLK1 to BLKz) are connected to a page buffer group (123) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells. The plurality of memory cells are defined as a single page if the memory cells connected to the same word line. That is, the memory cell array (110) is composed of a plurality of pages. According to an embodiment of the present invention, each of the plurality of memory blocks (BLK1 to BLKz) included in the memory cell array (110) may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain select transistor and the memory cells and between the source select transistor and the memory cells.

[0035] The memory cells of the memory device (100) may each be configured as a single-level cell (SLC) that stores one bit of data, a multi-level cell (MLC) that stores two bits of data, a triple-level cell (TLC) that stores three bits of data, or a quad-level cell (QLC) that can store four bits of data.

[0036] The peripheral circuit (120) drives the memory cell array (110). For example, the peripheral circuit (120) can drive the memory cell array (110) to perform program operations, read operations, and erase operations under the control of the control logic (130). As another example, the peripheral circuit (120) can apply various operating voltages to row lines (RL) and bit lines (BL1~BLm) or discharge the applied voltages under the control of the control logic (130).

[0037] The peripheral circuit (120) may include an address decoder (121), a voltage generator (122), a page buffer group (123), a data input / output circuit (124), and a sensing circuit (125).

[0038] The address decoder (121) is connected to the memory cell array (110) through row lines (RL). The row lines (RL) may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present invention, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present invention, the row lines (RL) may further include a pipe select line.

[0039] The address decoder (121) is configured to operate in response to the control of the control logic (130). The address decoder (121) receives an address (ADDR) from the control logic (130).

[0040] The address decoder (121) is configured to decode a block address among the received addresses (ADDR). The address decoder (121) selects at least one memory block among the memory blocks (BLK1~BLKz) according to the decoded block address. The address decoder (121) is configured to decode a row address (RADD) among the received addresses (ADDR). The address decoder (121) can select at least one word line of the selected memory block by applying voltages provided by the voltage generation unit (122) to at least one word line (WL) according to the decoded row address (RADD).

[0041] During program operation, the address decoder (121) will apply a program voltage to the selected word lines and a pass voltage of a level lower than the program voltage to the unselected word lines. During program verification operation, the address decoder (121) will apply a verification voltage to the selected word lines and a verification pass voltage of a level higher than the verification voltage to the unselected word lines.

[0042] During a read operation, the address decoder (121) will apply a read voltage to the selected word lines and apply a read pass voltage of a higher level than the read voltage to the unselected word lines.

[0043] The erase operation of the memory device (100) is performed in units of memory blocks. The address (ADDR) input to the memory device (100) during the erase operation includes a block address. The address decoder (121) decodes the block address and can select one memory block according to the decoded block address. During the erase operation, the address decoder (121) can apply a ground voltage to the word lines input to the selected memory block.

[0044] The address decoder (121) may be configured to decode the column address among the transmitted addresses (ADDR). The decoded column address may be transmitted to the page buffer group (123). For example, the address decoder (121) may include components such as a row decoder, a column decoder, an address buffer, etc.

[0045] The voltage generation unit (122) is configured to generate a plurality of operating voltages (Vop) using an external power supply voltage supplied to the memory device (100). The voltage generation unit (122) operates in response to the control of the control logic (130).

[0046] As an example, the voltage generating unit (122) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (122) is used as the operating voltage of the memory device (100).

[0047] As an example, the voltage generator (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG). The voltage generator (122) can generate multiple operating voltages (Vop) using an external power supply voltage or an internal power supply voltage. The voltage generator (122) can be configured to generate various voltages required by the memory device (100). For example, the voltage generator (122) can generate multiple erase voltages, multiple program voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0048] The voltage generation unit (122) includes a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages (Vop) having various voltage levels, and will selectively activate the plurality of pumping capacitors in response to the control of the control logic (130) to generate a plurality of operating voltages (Vop).

[0049] The generated multiple operating voltages (Vop) can be supplied to the memory cell array (110) by the address decoder (121).

[0050] The page buffer group (123) includes first to m page buffers (PB1 to PBm). The first to m page buffers (PB1 to PBm) are each connected to a memory cell array (110) through first to m bit lines (BL1 to BLm). The first to m page buffers (PB1 to PBm) operate in response to the control of the control logic (130).

[0051] The first to m-th page buffers (PB1 to PBm) communicate data (DATA) with the data input / output circuit (124). During programming, the first to m-th page buffers (PB1 to PBm) receive data (DATA) to be stored through the data input / output circuit (124) and data lines (DL).

[0052] During a program operation, the first to m-page buffers (PB1 to PBm) will transmit data (DATA) to be stored through the data input / output circuit (124) to the selected memory cells through the bit lines (BL1 to BLm) when a program pulse is applied to a selected word line. The memory cells of the selected page are programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied will have an elevated threshold voltage. A memory cell connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied will maintain its threshold voltage. During a program verification operation, the first to m-page buffers (PB1 to PBm) read data (DATA) stored in the memory cells from the selected memory cells through the bit lines (BL1 to BLm).

[0053] When a read operation is performed, the page buffer group (123) can read data (DATA) from the memory cells of the selected page through bit lines (BL1~BLm) and store the read data (DATA) in the first to mth page buffers (PB1~PBm).

[0054] During an erase operation, the page buffer group (123) can float bit lines (BL1 to BLm). As an example, the page buffer group (123) may include a column selection circuit.

[0055] In an embodiment, while data stored in some of the page buffers among the plurality of page buffers included in the page buffer group (123) is programmed into the memory cell array (110), other page buffers can receive and store new data from the memory controller (200).

[0056] The data input / output circuit (124) is connected to the first to m-page buffers (PB1 to PBm) through data lines (DL). The data input / output circuit (124) operates in response to the control of the control logic (130).

[0057] The data input / output circuit (124) may include a plurality of input / output buffers (not shown) that receive input data (DATA). During program operation, the data input / output circuit (124) receives data (DATA) to be stored from an external controller (not shown). During a read operation, the data input / output circuit (124) outputs data (DATA) transmitted from the first to m-th page buffers (PB1~PBm) included in the page buffer group (123) to the external controller.

[0058] The sensing circuit (125) can generate a reference current in response to an allow bit (VRYBIT) signal generated by the control logic (130) during a read operation or a verification operation, and output a pass signal or a fail signal to the control logic (130) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current. For example, the sensing circuit (125) can output a pass signal to the control logic (130) if the magnitude of the sensing voltage (VPB) is smaller than the reference voltage. As another example, the sensing circuit (125) can output a fail signal to the control logic (130) if the magnitude of the sensing voltage (VPB) is smaller than the reference voltage.

[0059] The control logic (130) may be connected to an address decoder (121), a voltage generator (122), a page buffer group (123), a data input / output circuit (124), and a sensing circuit (125). The control logic (130) may be configured to control the general operation of the memory device (100). The control logic (130) may operate in response to a command (CMD) transmitted from an external device.

[0060] The control logic (130) can control the peripheral circuit (120) by generating various signals in response to the command (CMD) and address (ADDR). For example, the control logic (130) can generate an operation signal (OPSIG), a row address (RADD), a page buffer control signal (PBSIGNALS), and an allow bit (VRYBIT) in response to the command (CMD) and address (ADDR). The control logic (130) can output the operation signal (OPSIG) to the voltage generation unit (122), output the row address (RADD) to the address decoder (121), output the page buffer control signal to the page buffer group (123), and output the allow bit (VRYBIT) to the sensing circuit (125). Additionally, the control logic (130) can determine whether the verification operation has passed or failed in response to a pass or fail signal (PASS / FAIL) output by the sensing circuit (125).

[0061] The program operation control unit (140) shown in FIG. 1 may be included in the control logic (130) shown in FIG. 2.

[0062] The program operation control unit (140) can control the peripheral circuit (120) to apply operating voltages to be used for the program operation to row lines (RL) and bit lines (BL1~BLm). The program operation control unit (140) can determine the voltage to be applied to the bit lines connected to the memory cells during the program voltage application operation according to the threshold voltage of the memory cells identified as a result of the verification operation. In an embodiment, the program operation control unit (140) can provide page buffer control signals (PBSIGNALS) to the page buffer group (123) to apply a program allow voltage, a precharge voltage, and a program prohibit voltage to the bit lines connected to the memory cells according to the threshold voltage of the memory cells. Each of the page buffers (PB1~PBm) included in the page buffer group (123) can raise the potential of the bit line to a program allow voltage, a precharge voltage, or a program prohibit voltage according to the page buffer control signals (PBSIGNALS) received from the control logic (130).

[0063] FIG. 3 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BKLz) of FIG. 2.

[0064] Memory block (BLKi) represents any one of the memory blocks (BLK1~BLKz) shown in FIG. 2.

[0065] Referring to FIG. 3, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line (SSL), and the second selection line may be a drain selection line (DSL). More specifically, a memory block (BLKi) may include a plurality of strings (ST) connected between bit lines (BL1~BLn) and a source line (SL). Bit lines (BL1~BLn) may each be connected to the strings (ST), and the source line (SL) may be connected to the strings (ST) in common. Since the strings (ST) may be configured identically, the string (ST) connected to the first bit line (BL1) will be described specifically as an example.

[0066] A string (ST) may include a source select transistor (SST), a plurality of memory cells (MC1 to MC16), and a drain select transistor (DST) connected in series between a source line (SL) and a first bit line (BL1). A single string (ST) may include at least one source select transistor (SST) and one drain select transistor (DST), and may also include more memory cells (MC1 to MC16) than the number shown in the drawing.

[0067] The source of the source select transistor (SST) can be connected to the source line (SL), and the drain of the drain select transistor (DST) can be connected to the first bit line (BL1). Memory cells (MC1~MC16) can be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gates of the source select transistors (SST) included in different strings (ST) can be connected to the source select line (SSL), the gates of the drain select transistors (DST) can be connected to the drain select line (DSL), and the gates of the memory cells (MC1~MC16) can be connected to multiple word lines (WL1~WL16). Among the memory cells included in different strings (ST), a group of memory cells connected to the same word line can be called a physical page (PG). Accordingly, the memory block (BLKi) may contain as many physical pages (PG) as there are word lines (WL1~WL16).

[0068] A single memory cell can store one bit of data. This is commonly referred to as a single-level cell (SLC). In this case, a single physical page (PG) can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as the number of cells contained within a single physical page (PG).

[0069] A single memory cell can store two or more bits of data. In this case, a single physical page (PG) can store two or more logical pages (LPG) of data.

[0070] Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device.

[0071] In Figure 4, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0072] Referring to Fig. 4, the threshold voltage distribution of memory cells can change from an initial state to a final program state depending on the program operation.

[0073] Figure 4 explains the case assuming that one memory cell is programmed as TLC to store three bits of data.

[0074] The initial state is a state where no program operation is performed, and the threshold voltage distribution of the memory cells may be in an erased state (E).

[0075] The final program state may be the threshold voltage distribution of the memory cells that performed the program operation. The threshold voltage of the memory cells that performed the program operation may have a threshold voltage corresponding to any one of the multiple program states. For example, if a single memory cell is programmed as a TLC storing three bits of data, the multiple program states may refer to an erase state (E) and first to seventh program states (PV1~PV7). In the embodiment, the threshold voltage of the memory cells that performed the program operation may have a threshold voltage corresponding to any one of the erase state (E) and first to seventh program states (PV1~PV7). The threshold voltage of the memory cells in the initial state may be raised through the program operation to a threshold voltage corresponding to any one of the erase state (E) and first to seventh program states (PV1~PV7).

[0076] Each memory cell may have an erase state (E) and one of the first to seventh program states (PV1~PV7) as a target program state. The target program state may be determined based on the data to be stored in the memory cell. Each memory cell may have a threshold voltage corresponding to the target program state among the final program states through a program operation.

[0077] Figure 5 is a diagram illustrating the program operation of a memory device.

[0078] In FIG. 5, the horizontal axis of the graph represents time, and the vertical axis of the graph represents the voltage (V) applied to the word line. The voltage (V) applied to the word line may include a program voltage (Vpgm) and a verification voltage (V_vfy).

[0079] Figure 5 describes the case where a single memory cell is programmed as a TLC to store three bits of data. However, the scope of the present invention is not limited thereto, and a single memory cell may be programmed to store two bits or less of data or four bits or more of data.

[0080] Referring to FIG. 5, the program operation of the memory device (100) may include a plurality of program loops (PL1 to PLn). The memory device (100) may perform a program operation by executing a plurality of program loops (PL1 to PLn) so that selected memory cells connected to selected word lines have a threshold voltage corresponding to any one of a plurality of program states. For example, when a memory cell is programmed as TLC, the memory device (100) may perform a program operation by executing a plurality of program loops (PL1 to PLn) so that it has a threshold voltage corresponding to an erase state (E) or any one of the first to seventh program states (PV1 to PV7).

[0081] Each of the multiple program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step).

[0082] The program voltage application operation (PGM Step) may be an operation of applying a program voltage to a selected word line connected to selected memory cells. For example, the memory device (100) may apply a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1). After the first program voltage (Vpgm1) is applied to the selected word line, the threshold voltage of each of the selected memory cells may have a threshold voltage corresponding to a target program state among a plurality of program states.

[0083] The Verify Step may be an operation of applying a verification voltage to a selected word line connected to selected memory cells. The Verify Step may be an operation of determining whether the threshold voltage of each of the selected memory cells has a threshold voltage corresponding to a target program state among a plurality of program states. The Verify Step may be an operation of applying a verification voltage corresponding to a target program state of each of the selected memory cells.

[0084] In an embodiment, the memory device (100) may apply a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1), and then apply first to seventh verification voltages (V_vfy1 to V_vfy7). At this time, memory cells whose target program state is the first program state may perform a verification operation (Verify Step) using the first verification voltage (V_vfy1). Memory cells whose target program state is the second program state may perform a verification operation (Verify Step) using the second verification voltage (V_vfy2). Memory cells whose target program state is the third program state may perform a verification operation (Verify Step) using the third verification voltage (V_vfy3). Memory cells whose target program state is the fourth program state may perform a verification operation (Verify Step) using the fourth verification voltage (V_vfy4). Memory cells whose target program state is the 5th program state can perform a verification operation (Verify Step) using the 5th verification voltage (V_vfy5). Memory cells whose target program state is the 6th program state can perform a verification operation (Verify Step) using the 6th verification voltage (V_vfy6). Memory cells whose target program state is the 7th program state can perform a verification operation (Verify Step) using the 7th verification voltage (V_vfy7). As the verification voltage progresses from the 1st verification voltage (V_vfy1) to the 7th verification voltage (V_vfy7), the magnitudes of the verification voltages (V_vfy1~V_vfy7) may increase. Specifically, the magnitudes of the verification voltages (V_vfy1~V_vfy7) may be smallest at the 1st verification voltage (V_vfy1) and largest at the 7th verification voltage (V_vfy7). The number of verification voltages is not limited to this embodiment.

[0085] The threshold voltage of memory cells that have passed the Verify Step by each of the Verify voltages (V_vfy1~V_vfy7) can be determined to have a threshold voltage corresponding to the target program state. Memory cells that have passed the Verify Step can be programmed inhibited in the second program loop (PL2). A program inhibit voltage can be applied to the bit lines connected to the programmed memory cells.

[0086] The threshold voltage of memory cells for which the Verify Step failed by each of the verification voltages (V_vfy1~V_vfy7) can be determined to not have a threshold voltage corresponding to the target program state. Memory cells for which the Verify Step failed can perform the second program loop (PL2).

[0087] In the second program loop (PL2), the memory device (100) can apply a second program voltage (Vpgm2) that is higher than the first program voltage (Vpgm1) by a unit voltage (△Vpgm) to a selected word line connected to the selected memory cells. Afterward, the memory device (100) can perform the verification step of the second program loop (PL2) in the same way as the verification step of the first program loop (PL1).

[0088] Afterwards, the memory device (100) can perform the next program loop in the same way as the second program loop (PL2) a preset number of times.

[0089] In an embodiment, if the program operation is not completed within a preset number of program loops, the program operation may fail. If the program operation is completed within a preset number of program loops, the program operation may pass. Whether the program operation is completed may be determined by whether all verification steps for the selected memory cells have passed. If the verification steps for all selected memory cells have passed, the next program loop may not be executed.

[0090] In the embodiment, the program voltage can be determined according to the Incremental Step Pulse Programming (ISPP) method. The level of the program voltage can be increased or decreased stepwise as the program loops (PL1 to PLn) are repeated. The number of times the program voltages used in each program loop are applied, the voltage level, and the voltage application time can be determined in various forms according to the control of the memory controller (200).

[0091] Figure 6 is a diagram illustrating the operation of the DPGM of a memory device.

[0092] In Figure 6, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0093] Referring to FIG. 6, the DPGM (Double Verify PGM; DPGM) operation may be an operation that identifies the threshold voltages of memory cells using at least two verification voltages in a verification operation. Specifically, the DPGM operation may be an operation that verifies whether the threshold voltages of memory cells have reached a threshold voltage corresponding to a target program state using at least two verification voltages. The two or more verification voltages may include a pre-verification voltage (Vvfyp) and a main verification voltage (Vvfym).

[0094] The program state (P) shown in FIG. 6 may be any one of the first to seventh program states (PV1 to PV7) shown in FIG. 4. The verification voltages (V_vfy1 to V_vfy7) shown in FIG. 5 may each include a pre-verification voltage (Vvfyp) and a main verification voltage (Vvfym).

[0095] In an embodiment, the main verification voltage (Vvfym) may be a threshold voltage corresponding to a program state (P). The main verification voltage (Vvfym) may be a threshold voltage corresponding to a target program state of memory cells. For example, the main verification voltage (Vvfym) may be any one of the verification voltages (V_vfy1 to V_vfy7) shown in FIG. 5.

[0096] In an embodiment, the threshold voltage of memory cells for which the program voltage application operation has ended in any one of the multiple program loops may have the threshold voltage of the first to third cells (Cell1~Cell3). In a verification operation performed after the program voltage application operation has ended, the memory device (100) may perform a DPGM operation to identify the threshold voltage of memory cells using a pre-verification voltage (Vvfyp) and a main verification voltage (Vvfym). In the verification operation, the memory device (100) may perform a DPGM operation to identify the degree to which the threshold voltage of memory cells has risen using the pre-verification voltage (Vvfyp) and the main verification voltage (Vvfym).

[0097] In an embodiment, the first cell (Cell1) may have a threshold voltage smaller than the pre-verification voltage (Vvfyp) after the program voltage application operation of one program loop is terminated. The second cell (Cell2) may have a threshold voltage larger than the pre-verification voltage (Vvfyp) and smaller than the main verification voltage (Vvfym). The third cell (Cell3) may have a threshold voltage larger than the main verification voltage (Vvfym).

[0098] In the embodiment, the target program state of the first to third cells (Cell1 to Cell3) is assumed to be the program state (P) shown in FIG. 6. That is, the threshold voltage of the first to third cells (Cell1 to Cell3) may be raised to a threshold voltage corresponding to the program state (P).

[0099] When a program voltage is applied, the threshold voltage of the first cell (Cell1) may need to rise significantly to a threshold voltage corresponding to the program state (P) compared to the threshold voltage of the second cell (Cell2). In this case, the first cell (Cell1) may be a PGM cell to be programmed. The threshold voltage of the second cell (Cell2) may need to rise less to a threshold voltage corresponding to the program state (P) compared to the threshold voltage of the first cell (Cell1). In this case, the second cell (Cell2) may be a DGPM cell. Since the threshold voltage of the third cell (Cell3) has a threshold voltage corresponding to the program state (P), the threshold voltage may not rise any further. In this case, the third cell (Cell3) may be an inhibitor cell.

[0100] That is, after the program voltage application operation is terminated, the degree to which the threshold voltage of the first to third cells (Cell1~Cell3) has risen may differ. Then, during the verification operation, the degree to which the threshold voltage of the first to third cells (Cell1~Cell3) has risen can be identified using the pre-verification voltage (Vvfyp) and the main verification voltage (Vvfym). Subsequently, during the program voltage application operation performed repeatedly, the magnitude of the voltage applied to the bit line connected to each of the first to third cells (Cell1~Cell3) can be determined according to the magnitude of the threshold voltage of the first to third cells (Cell1~Cell3).

[0101] FIG. 7 is a diagram illustrating the operation of a page buffer circuit according to an embodiment of the present invention.

[0102] The page buffer circuit (700) shown in FIG. 7 may be a page buffer (PBi) of any one of the page buffer groups (123) shown in FIG. 2.

[0103] Referring to FIG. 7, the page buffer circuit (700) may include a precharge section (710), a discharge section (720), and a latch section (730). The precharge section (710), the discharge section (720), and the latch section (730) may be connected between a bit line (BL) and a data line (DL). The bit line (BL) may be connected to a memory cell. Data corresponding to the target program state of the memory cell may be input through the data line (DL).

[0104] The precharge unit (710) can precharge the voltage of the bit line (BL) when the program voltage is applied. In an embodiment, the precharge unit (710) can apply a program allowance voltage to the bit line (BL) when the memory cell connected to the bit line (BL) is a cell to be programmed (PGM Cell). The program allowance voltage may be a ground voltage. The precharge unit (710) can apply a program prohibition voltage to the bit line (BL) when the memory cell connected to the bit line (BL) is an inhibit cell. The program prohibition voltage may be a power supply voltage. The precharge unit (710) can apply a precharge voltage to the bit line (BL) when the memory cell connected to the bit line (BL) is a DPGM cell. The precharge voltage may be a voltage smaller than the program prohibition voltage and larger than the program allowance voltage. The precharge unit (710) can increase the voltage of the bit line (BL) according to the precharge control signal (PBSENSE) received from the program operation control unit (140) shown in FIG. 1. For example, the voltage of the bit line (BL) can increase to a precharge voltage according to the precharge control signal (PBSENSE). Specifically, the degree to which the voltage of the bit line (BL) increases may vary depending on the magnitude of the voltage of the precharge control signal (PBSENSE). The greater the magnitude of the voltage of the precharge control signal (PBSENSE), the greater the magnitude of the increase in the voltage of the bit line (BL). In an embodiment, the precharge control signal (PBSENSE) may be any one of the page buffer control signals (PBSIGNALS) provided by the control logic (130) in FIG. 2 to the page buffer group (123).

[0105] The discharge unit (720) can lower the voltage of the bit line (BL) to ground voltage. In an embodiment, the discharge unit (720) can discharge the potential of the bit line (BL), which has been raised to a program prohibition voltage or a precharge voltage, to ground voltage.

[0106] The latch unit (730) can store data corresponding to the threshold voltage of the memory cell identified using a plurality of verification voltages. The latch unit (730) can store data sensing the potential of the bit line that varies when a verification voltage is applied to the memory cell connected to the bit line (BL). In an embodiment, the latch unit (730) can store data distinguishing whether the memory cell connected to the bit line (BL) is a programmable cell (PGM Cell), a DPGM cell (DPGM Cell), or an inhibitor cell.

[0107] Figure 8 is a diagram illustrating the program voltage application operation in the program operation of a memory device.

[0108] Referring to FIG. 8, the program operation of the memory device (100) may include a plurality of program loops (PL1 to PLn). Each of the plurality of program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step).

[0109] The program voltage application operation (PGM Step) included in each of the multiple program loops (PL1~PLn) may include a precharge section, a program pulse (Pgm Pulse) section, and a discharge section.

[0110] The t1~t2 interval may be a precharge interval. The precharge interval may be a interval for precharging a bit line (BL). In the precharge interval, the precharge control signal (PBSENSE) may rise to a first control voltage (Vpb1). The voltage of the bit line (BL (Inhibit Cell)) connected to the inhibit cell may rise to a program prohibition voltage (VCC) in response to the precharge control signal (PBSENSE). The memory device (100) may apply a program allowance voltage (Gnd) to the bit line (BL (PGM Cell)) connected to the cell to be programmed in the precharge interval. Afterward, the precharge control signal (PBSENSE) may drop from the first control voltage (Vpb1) to a ground voltage. At this time, the bit line connected to the inhibitor cell (BL(Inhibit Cell)) and the bit line connected to the cell to be programmed (BL(PGM Cell)) can be floated. The voltage of the bit line connected to the inhibitor cell (BL(Inhibit Cell)) and the bit line connected to the cell to be programmed (BL(PGM Cell)) can be maintained.

[0111] The t2~t3 interval may be a program pulse (Pgm Pulse) interval. The program voltages (Vpgm1~Vpgmn) shown in FIG. 5 may be applied to a selected word line (Sel_WL) connected to the selected memory cells during the program pulse (Pgm Pulse) interval. The program pulse (Pgm Pulse) interval may be a interval for storing data in the selected memory cells. For example, the memory device (100) may apply a pass voltage (Vpass) to a selected word line (Sel_WL) connected to the selected memory cells during the program pulse (Pgm Pulse) interval for a certain period of time, and then apply a program voltage (Vpgm). The memory device (100) may maintain the voltage of the bit line (BL(PGM Cell)) connected to the cell to be programmed during the program pulse (Pgm Pulse) interval at a ground voltage (Gnd). The memory device (100) can maintain the voltage of the bit line (BL(Inhibit Cell)) connected to the inhibitor cell at the program prohibition voltage (VCC) during the program pulse (Pgm Pulse) interval.

[0112] During the program pulse (Pgm Pulse) interval, the precharge control signal (PBSENSE) can rise to the second control voltage (Vpb2). The potential of the bit line (BL(DPGM Cell)) connected to the DPGM cell can rise in response to the precharge control signal (PBSENSE). Specifically, the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell can rise to the first precharge voltage (Vm1) or the second precharge voltage (Vm2). For example, if the memory cells adjacent to the DPGM cell are inhibit cells, the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell can rise to the first precharge voltage (Vm1). As another example, if the memory cells adjacent to the DPGM cell are the cells to be programmed (PGM Cell), the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell can be raised to a second precharge voltage (Vm2). The first precharge voltage (Vm1) may be a voltage greater than the second precharge voltage (Vm2).

[0113] The potential of the bit line (BL(DPGM Cell)) connected to the DPGM cell may need to rise to the target level (TBL) by the second control voltage (Vpb2). However, due to coupling phenomena caused by parasitic capacitance between the bit line (BL(DPGM Cell)) connected to the DPGM cell and adjacent bit lines, the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell may not rise to the target level (TBL). In this case, if the memory cells adjacent to the DPGM cell are programmed cells (PGM Cells), the coupling phenomenon caused by parasitic capacitance described above may be more severe than if they are inhibit cells. Accordingly, the magnitude of the voltage rise of the bit line (BL(DPGM Cell)) connected to the DPGM cell may vary depending on the extent to which the threshold voltage of the memory cells connected to the adjacent bit lines needs to rise. Specifically, the magnitude of the voltage rise of the bitline (BL(DPGM Cell)) connected to the DPGM cell may vary depending on whether the memory cell connected to the bitline adjacent to the bitline (BL(DPGM Cell)) connected to the DPGM cell is a programmed cell (PGM Cell) or an inhibitor cell.

[0114] The t3~t4 interval may be a discharge interval. The memory device (100) may apply a ground voltage (Gnd) to a selected word line (Sel_WL) during the discharge interval. The memory device (100) may apply a ground voltage (Gnd) to a bit line (BL(PGM Cell)) connected to a cell to be programmed, a bit line (BL(Inhibit Cell)) connected to an inhibitor cell, and a bit line (BL(DPGM Cell)) connected to a DPGM cell during the discharge interval.

[0115] FIG. 9 is a diagram illustrating the program voltage application operation in the program operation of a memory device according to an embodiment of the present invention.

[0116] In Fig. 9, the explanation of content that overlaps with Fig. 8 will be omitted.

[0117] Referring to FIG. 9, the program operation of the memory device (100) may include a plurality of program loops (PL1 to PLn). Each of the plurality of program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step).

[0118] The program voltage application operation (PGM Step) included in each of the multiple program loops (PL1~PLn) may include a precharge section, a program pulse (Pgm Pulse) section, and a discharge section.

[0119] The t1~t2 interval may be a precharge interval. The precharge interval may be an interval for precharging the bitline (BL).

[0120] The interval between t2 and t3 may be a program pulse (Pgm Pulse) interval. During the program pulse (Pgm Pulse) interval, the precharge control signal (PBSENSE) may rise to the 2-1 control voltage (Vpb2-1). The precharge control signal (PBSENSE) may rise to the 2-1 control voltage (Vpb2-1) for a predetermined interval, and then lower to the 2-2 control voltage (Vpb2-2). The 2-1 control voltage (Vpb2-1) may be a voltage smaller than the 1 control voltage (Vpb1). The 2-1 control voltage (Vpb2-1) may be a voltage larger than the 2 control voltage (Vpb2) shown in FIG. 8. The voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell can rise to a first precharge voltage (Vm1) or a second precharge voltage (Vm2) in response to a precharge control signal (PBSENSE). Specifically, if the bit line adjacent to the bit line (BL(DPGM Cell)) connected to the DPGM cell is a bit line (BL(Inhibit Cell)) connected to an inhibitor cell, the bit line (BL(DPGM Cell)) connected to the DPGM cell can rise to a first precharge voltage (Vm1) in response to the precharge control signal (PBSENSE). That is, the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell can reach a target level (TBL) by the second-1 control voltage (Vpb2-1). And, the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell can reach the target level (TBL) faster than the time it takes to reach the first precharge voltage (Vm1) in FIG. 8 by the second-1 control voltage (Vpb2-1). If the bit line adjacent to the bit line (BL(DPGM Cell)) connected to the DPGM cell is the bit line (BL(PGM Cell)) connected to the cell to be programmed, the bit line (BL(DPGM Cell)) connected to the DPGM cell can rise to the second precharge voltage (Vm2) in response to the precharge control signal (PBSENSE).The second precharge voltage (Vm2) shown in FIG. 9 may be greater than the second precharge voltage (Vm2) shown in FIG. 8. That is, by overdriving the precharge control signal (PBSENSE) of the memory device (100), the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell may rise to a voltage closer to the target level (TBL). Also, by overdriving the precharge control signal (PBSENSE) of the memory device (100), the difference in magnitude between the first precharge voltage (Vm1) and the second precharge voltage (Vm2) shown in FIG. 9 may be smaller than the difference in magnitude between the first precharge voltage (Vm1) and the second precharge voltage (Vm2) shown in FIG. 8. In addition, the threshold voltage distribution of the DPGM cell can be improved by raising the voltage of the bit line (BL(DPGM Cell)) connected to the DPGM cell to a voltage closer to the target level (TBL).

[0121] FIG. 10 is a flowchart for explaining program operation according to an embodiment of the present invention.

[0122] Referring to FIG. 10, in step S1001, the memory device (100) can identify the threshold voltages of memory cells using a first verification voltage and a second verification voltage. The second verification voltage may be a voltage greater than the first verification voltage.

[0123] In step S1003, the memory device (100) may apply a first control signal having a magnitude of a first voltage for a first period to a page buffer connected to a first memory cell having a threshold voltage greater than a first verification voltage and less than a second verification voltage among the memory cells. The first memory cell may be a DPGM cell. In an embodiment, after applying the first control signal to the page buffer connected to the first memory cell, the memory device (100) may apply a program voltage to a word line connected to the first memory cell.

[0124] In step S1005, the memory device (100) may apply a program allowance voltage to a bit line connected to the second memory cells if the threshold voltage of the second memory cells adjacent to the first memory cell is less than the first verification voltage. The second memory cells may be cells to be programmed (PGM Cell). In an embodiment, after applying a program allowance voltage to the bit line connected to the second memory cells, the memory device (100) may apply a first control signal to a page buffer connected to the first memory cell.

[0125] In step S1007, the memory device (100) may apply a second control signal having a second voltage magnitude lower than the first voltage to a page buffer connected to the first memory cell.

[0126] FIG. 11 is a block diagram showing a memory card system to which a memory system according to one embodiment of the present invention is applied.

[0127] Referring to FIG. 11, the memory card system (2000) includes a memory controller (2100), a memory device (2200), and a connector (2300).

[0128] The memory controller (2100) is connected to the memory device (2200). The memory controller (2100) is configured to access the memory device (2200). For example, the memory controller (2100) may be configured to control the read, write, erase, and background operations of the memory device (2200). The memory controller (2100) is configured to provide an interface between the memory device (2200) and a host. The memory controller (2100) is configured to run firmware for controlling the memory device (2200). The memory controller (2100) may be implemented in the same way as the memory controller (200) described with reference to FIG. 1. The memory device (2200) may be implemented in the same way as the memory device (100) described with reference to FIG. 1.

[0129] For example, the memory controller (2100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0130] The memory controller (2100) can communicate with an external device through a connector (2300). The memory controller (2100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller (2100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (2300) may be defined by at least one of the various communication standards described above.

[0131] For example, the memory device (2200) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque-Magnetic RAM), etc.

[0132] The memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card. For example, the memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash card (CF), Smart Media card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0133] FIG. 12 is a block diagram showing a user system to which a memory system according to one embodiment of the present invention is applied.

[0134] Referring to FIG. 12, the user system (4000) includes an application processor (4100), a memory module (4200), a network module (4300), a storage module (4400), and a user interface (4500).

[0135] The application processor (4100) can run components included in the user system (4000), an operating system (OS), or user programs, etc. For example, the application processor (4100) may include controllers, interfaces, graphics engines, etc. that control components included in the user system (4000). The application processor (4100) may be provided as a system-on-chip (SoC).

[0136] The memory module (4200) can operate as the main memory, operational memory, buffer memory, or cache memory of the user system (4000). The memory module (4200) may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc. or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. For example, the application processor (4100) and the memory module (4200) may be packaged based on POP (Package on Package) and provided as a single semiconductor package.

[0137] The network module (4300) can communicate with external devices. For example, the network module (4300) can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the network module (4300) can be included in the application processor (4100).

[0138] The storage module (4400) can store data. For example, the storage module (4400) can store data received from the application processor (4100). Alternatively, the storage module (4400) can transfer data stored in the storage module (4400) to the application processor (4100). For example, the storage module (4400) can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, or a three-dimensional NAND flash. For example, the storage module (4400) can be provided as a removable storage medium such as a memory card or an external drive of the user system (4000).

[0139] For example, the storage module (4400) may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as the memory device (100) described with reference to FIG. 1. The storage module (4400) may operate in the same manner as the memory system (50) described with reference to FIG. 1.

[0140] The user interface (4500) may include interfaces for inputting data or commands to the application processor (4100) or outputting data to an external device. For example, the user interface (4500) may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, etc. The user interface (4500) may include user output interfaces such as an LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display, AMOLED (Active Matrix OLED) display, LED, speaker, monitor, etc. Explanation of the symbols

[0141] 50: Memory System 100: Memory device 140: Program operation control unit 200: Memory controller 300: Host

Claims

Claim 1 A memory device comprising: memory cells; a peripheral circuit that performs a verification operation to identify threshold voltages of the memory cells using a first verification voltage and a second verification voltage greater than the first verification voltage; and a program operation control unit that, after the verification operation is terminated, controls the peripheral circuit to apply a first control signal having a magnitude of a first voltage while the pass voltage is applied to the word line connected to the memory cells during a period in which a pass voltage and a program voltage are sequentially applied to the word line connected to the memory cells, and then applies a second control signal having a magnitude of a second voltage smaller than the first voltage while the program voltage is applied to the word line. Claim 2 A memory device according to claim 1, wherein the threshold voltage of the second memory cells adjacent to the first memory cell is smaller than the first verification voltage, and the program operation control unit controls the peripheral circuit to apply a program allowance voltage to the bit lines connected to the second memory cells after the verification operation is terminated. Claim 3 In claim 2, the program operation control unit controls the peripheral circuit to apply the first control signal to the page buffer connected to the first memory cell after applying the program allowable voltage to the bit line connected to the second memory cells. Claim 4 In claim 3, the program operation control unit controls the peripheral circuit to apply the program voltage to the word line connected to the memory cells after applying the first control signal to the page buffer connected to the first memory cell. Claim 5 A memory device according to claim 4, wherein the voltage of the bit line connected to the first memory cell rises to a precharge voltage in response to the first and second control signals, and the precharge voltage is a voltage greater than the program allowable voltage. Claim 6 In claim 5, the above program allowable voltage is a memory device that is a ground voltage. Claim 7 In claim 6, the memory device wherein the second verification voltage is a threshold voltage corresponding to the target program state of the memory cells. Claim 8 A memory device according to claim 1, wherein the threshold voltage of the second memory cells adjacent to the first memory cell is greater than the second verification voltage, and the program operation control unit controls the peripheral circuit to apply a program prohibition voltage to the bit lines connected to the second memory cells after the verification operation is terminated. Claim 9 A memory device according to claim 8, wherein the voltage of the bit line connected to the first memory cell rises to a precharge voltage in response to the first and second control signals, and the precharge voltage is a voltage smaller than the program prohibition voltage. Claim 10 In claim 9, the program prohibition voltage is a memory device that is a power supply voltage. Claim 11 A memory device according to claim 10, wherein, when the second control signal is applied to the page buffer excluding the first control signal during the interval in which the program voltage is applied, the voltage of the bit line connected to the first memory cell rises to a voltage lower than the precharge voltage in response to the second control signal. Claim 12 A method of operating a memory device comprising: a step of performing a verification operation to identify threshold voltages of memory cells using a first verification voltage and a second verification voltage greater than the first verification voltage; a step of, after the verification operation is terminated, applying a first control signal having a magnitude of a first voltage while the pass voltage is applied to the word line during a period in which a pass voltage and a program voltage are sequentially applied to a page buffer connected to a first memory cell having a threshold voltage greater than the first verification voltage and smaller than the second verification voltage among the memory cells, wherein the pass voltage is applied to the word line; and a step of applying a second control signal having a magnitude of a second voltage smaller than the first voltage to the page buffer connected to the first memory cell while the program voltage is applied to the word line. Claim 13 A method of operation of a memory device according to claim 12, wherein the threshold voltage of the second memory cells adjacent to the first memory cell is smaller than the first verification voltage, and after the verification operation is terminated, a program allowance voltage is applied to the bit lines connected to the second memory cells. Claim 14 A method of operation of a memory device according to claim 13, wherein the program allowable voltage is applied to a bit line connected to the second memory cells, and then the first control signal is applied to a page buffer connected to the first memory cell. Claim 15 A method of operation of a memory device according to claim 14, wherein the program voltage is applied to the word line after the pass voltage is applied to the word line. Claim 16 A method of operation of a memory device according to claim 15, wherein the voltage of a bit line connected to the first memory cell rises to a precharge voltage in response to the first and second control signals, and the precharge voltage is a voltage greater than the program allowable voltage. Claim 17 In claim 16, the above program allowable voltage is a ground voltage, a method of operation of a memory device. Claim 18 In claim 17, the method of operation of a memory device wherein the second verification voltage is a threshold voltage corresponding to the target program state of the memory cells. Claim 19 A method of operation of a memory device according to claim 12, wherein the threshold voltage of the second memory cells adjacent to the first memory cell is greater than the second verification voltage, and after the verification operation is terminated, a program prohibition voltage is applied to the bit line connected to the second memory cells. Claim 20 A method of operation of a memory device according to claim 19, wherein the voltage of a bit line connected to the first memory cell rises to a precharge voltage in response to the first and second control signals, and the precharge voltage is a voltage smaller than the program prohibition voltage. Claim 21 In claim 20, the above program prohibition voltage is a method of operation of a memory device that is a power supply voltage. Claim 22 A method of operation of a memory device according to claim 21, wherein, when the second control signal is applied to the page buffer excluding the first control signal during the interval in which the program voltage is applied, the voltage of the bit line connected to the first memory cell rises to a voltage lower than the precharge voltage in response to the second control signal.

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