Memory device and operating method of the memory device

Abstract

The present invention includes a memory device and a method of operation thereof, comprising: a first memory block and a second memory block including a plurality of memory cells; a voltage generator configured to apply operating voltages to first global lines, selectively apply a positive voltage to global select lines included in the second global lines while applying the operating voltages, and apply a ground voltage to the remaining global lines among the second global lines excluding the global select lines; and a row decoder configured to turn on first pass switches between first local lines connected to the first memory block and the first global lines, and turn off second pass switches between second local lines connected to the second memory block and the second global lines.

Description

Technology Field

[0001] The present invention relates to a memory device and a method of operating the same, and more specifically, to a memory device configured to perform a program operation and a method of operating the same. Background Technology

[0002] A memory device may include a memory cell array in which data is stored, a peripheral circuit configured to perform program, read, or erase operations, and control logic for controlling the peripheral circuit.

[0003] A memory cell array may include a plurality of memory blocks, and each of the plurality of memory cells may include a plurality of memory cells. The memory device may be implemented in a two-dimensional structure or a three-dimensional structure.

[0004] In a memory device implemented with a two-dimensional structure, memory cells can be arranged in a direction parallel to the substrate. Because the memory cells are arranged parallel to the substrate, the channels of the memory cells can be formed of single-crystal silicon.

[0005] In a memory device implemented with a three-dimensional structure, memory cells can be stacked in a direction perpendicular to the substrate. Since memory cells are stacked on the substrate, the channels of the memory cells can be formed from polycrystalline silicon. As polycrystalline silicon consists of multiple grains, the boundaries between the grains can become trap sites. If a hole is filled in a trap site, the channel can enter a donor-like state. In this case, the channel potential can rise to a positive level. This phenomenon can occur in non-selected memory blocks while a program operation is being performed in a selected memory block. If channel boosting occurs in non-selected memory blocks, subsequent operations that can be performed in the non-selected memory blocks may be affected, thereby degrading the reliability of the memory device.

[0006] delete Prior art literature

[65535] Republic of Korea Published Patent Application No. 10-2020-0109820 The problem to be solved

[0007] An embodiment of the present invention provides a memory device capable of suppressing channel boosting in non-selected memory blocks during a program operation of a selected memory block, and a method of operating the same. means of solving the problem

[0008] A memory device according to an embodiment of the present invention comprises: a first memory block and a second memory block including a plurality of memory cells; a voltage generator configured to apply operating voltages to first global lines, selectively apply a positive voltage to global select lines included in second global lines while applying the operating voltages, and apply a ground voltage to the remaining global lines among the second global lines excluding the global select lines; and a row decoder configured to turn on first pass switches between first local lines connected to the first memory block and the first global lines, and turn off second pass switches between second local lines connected to the second memory block and the second global lines.

[0009] A memory device according to an embodiment of the present invention comprises: a first memory block and a second memory block including a plurality of memory cells; a voltage generator configured to apply operating voltages to first global lines, selectively apply a positive voltage to global select lines included in second global lines while applying the operating voltages, and apply a ground voltage to the remaining global lines among the second global lines excluding the global select lines; and a row decoder configured to apply a first block select signal having a high voltage to first pass switches between first local lines connected to the first memory block and the first global lines, and selectively apply a negative voltage to second pass switches between second local lines connected to the second memory block and the second global lines.

[0010] A method of operating a memory device according to an embodiment of the present invention comprises: turning on first pass switches between first local lines and first global lines connected to a first memory block; turning off second pass switches between second local lines and second global lines connected to a second memory block; applying a program voltage to a selected global word line among the first global lines; applying a positive voltage to global select lines among the second global lines when the program voltage is applied to the selected global word line; and applying a negative voltage to the gates of the second pass switches when the program voltage is applied to the selected global word line. Effects of the invention

[0012] This technology can improve the reliability of subsequent operations that can be performed in unselected memory blocks by suppressing channel boosting in unselected memory blocks during the program operation of a selected memory block. Brief explanation of the drawing

[0013] Figure 1 is a diagram illustrating a memory device. Figure 2 is a diagram illustrating a memory block. Figure 3 is a diagram illustrating a voltage generator and a row decoder. FIGS. 4a and FIGS. 4b are diagrams illustrating the selection transistors of the selected memory block and the non-selected memory block during program operation. FIGS. 5A and FIGS. 5B are drawings illustrating gate-induced drain leakage (GIDL) that can occur in an unselected memory block. FIG. 6 is a diagram illustrating the voltages used during program operation according to the present invention. FIG. 7 is a diagram illustrating the operation of a program according to the present invention. FIGS. 8a and FIGS. 8b are drawings for explaining the operation of selection transistors according to the present invention. FIG. 9 is a diagram illustrating the voltage of the selected lines in the voltage change section according to the present invention. Specific details for implementing the invention

[0014] The specific structural or functional descriptions disclosed below are illustrative of embodiments according to the concept of the present invention. Embodiments according to the concept of the present invention are not to be interpreted as being limited to the embodiments described below, but can be modified in various ways and replaced with other equivalent embodiments.

[0015] In the following description, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used for the purpose of distinguishing one component from another.

[0017] Figure 1 is a diagram illustrating a memory device.

[0018] Referring to FIG. 1, a memory device (100) may include a memory cell array (110), a peripheral circuit (120), and a control circuit (130).

[0019] The memory cell array (110) may include a plurality of memory blocks (BLK1 to BLKj). The plurality of memory blocks (BLK1 to BLKj) may be implemented in a three-dimensional structure. For example, each of the plurality of memory blocks (BLK1 to BLKj) may include a plurality of memory cells, and the plurality of memory cells may be stacked vertically on a substrate.

[0020] The peripheral circuit (120) may be configured to perform a program operation, a read operation, or an erase operation of the memory cell array (110) under the control of the control circuit (130). For example, the peripheral circuit (120) may include a voltage generator (21), a row decoder (22), a source voltage generator (23), a page buffer group (24), a column decoder (25), and an input / output circuit (26).

[0021] The voltage generator (21) can be configured to generate various operating voltages using the internal power supply voltage supplied to the memory device (100). For example, the voltage generator (21) can generate a program voltage, pass voltage, verification voltage, read voltage, erase voltage, turn-on voltage, turn-off voltage, and ground voltage, and can also generate various levels of positive or negative voltages. The voltage generator (21) can adjust the levels and output times of the operating voltages in response to the operation code (OPCD). The voltage generator (21) can output operating voltages through first global lines (1GL) and second global lines (2GL). For example, the voltage generator (21) may include a first operating voltage generator (10VG) configured to output operating voltages through first global lines (1GL) and a second operating voltage generator (20VG) configured to output operating voltages through second global lines (2GL). The first operating voltage generator (10VG) and the second operating voltage generator (20VG) may each be configured to output different voltages according to an operating code. For example, when voltages to be transmitted to a selected memory block are output from the first operating voltage generator (10VG), the second operating voltage generator (20VG) may be configured to output a ground voltage or a positive voltage through the second global lines (2GL). Alternatively, when voltages to be transmitted to a selected memory block are output from a second operating voltage generator (20VG), the first operating voltage generator (10VG) may be configured to output a ground voltage or a positive voltage through the first global lines (1GL).

[0022] The row decoder (22) may be configured to receive voltages output from the voltage generator (21) through the first global lines (1GL) and the second global lines (2GL), and to transmit the received voltages to local lines (LL). The local lines (LL) may each be connected to a plurality of memory blocks (BLK1 to BLKj). The row decoder (22) may transmit operating voltages to the local lines (LL) connected to the selected memory block in response to a row address (RADD). For example, the row decoder (22) may transmit operating voltages to the local lines (LL) connected to the selected memory block, and transmit ground voltage or positive voltage to the local lines (LL) connected to the unselected memory blocks. The row decoder (22) may be configured to increase the voltage of some lines of the local lines (LL) connected to the unselected memory blocks using gate-induced drain leakage (GIDL).

[0023] The source voltage generator (23) can be configured to generate a source voltage in response to a source voltage control signal (SVCS) and output the source voltage through a source line (SL). Since the source line (SL) can be commonly connected to a plurality of memory blocks (BLK1 to BLKj), the source voltage applied to the source line (SL) can be commonly transmitted to a plurality of memory blocks (BLK1 to BLKj).

[0024] A page buffer group (24) can be connected to a plurality of memory blocks (BLK1 to BLKj) via bit lines (BL) and can be connected to a column decoder (25) via column lines (CL). The page buffer group (24) may include page buffers (not shown) configured to operate in response to a page buffer control signal (PBSIG). The page buffers (not shown) may be configured to temporarily store data during a program operation, a read operation, or an erase operation. For example, during a program operation, the page buffer group (24) may temporarily store data received via column lines (CL) and output a program allow voltage or a program prohibit voltage to the bit lines (BL) according to the temporarily stored data. Additionally, the page buffer group (24) may determine data by sensing the voltage or current of the bit lines (BL) during a program verification operation performed during a program operation or an erase verification operation performed during an erase operation. When a read operation is performed, the page buffer group (24) can sense the voltage or current of the bit lines to read the data and output the read data through the column lines (CL).

[0025] The column decoder (25) can be connected to the page buffer group (24) via column lines (CL) and to the input / output circuit (26) via data lines (DL). The column decoder (25) can transmit data by connecting the data lines (DL) and the column lines (CL) to each other in response to a column address (CADD).

[0026] The input / output circuit (26) is connected to the column decoder (25) via data lines (DL) and can be connected to an external device via input / output lines (I / O). The external device may be a controller (not shown) that transmits a command (CMD), an address (ADD), or data to the memory device (100). The input / output circuit (26) can transmit the command (CMD) and address (ADD) received via the input / output lines (I / O) to the control circuit (130) and transmit the data received via the input / output lines (I / O) to the column decoder (25) via data lines (DL). Alternatively, the input / output lines (I / O) can output the data received via the data lines (DL) via the input / output lines (I / O).

[0027] The control circuit (130) may include circuits and software configured to output an operation code (OPCD), a row address (RADD), a source voltage control signal (SVCS), a page buffer control signal (PBSIG), and a column address (CADD) according to a command (CMD) and an address (ADD). For example, the control circuit (130) may include software that executes a program, read, or erase algorithm in response to a command (CMD), and may include circuits configured to output various signals according to a selected algorithm in response to a command (CMD). Taking a program operation as an example, the control circuit (130) may execute a program algorithm in response to a command (CMD) for a program operation. The control circuit (130) may output an operation code (OPCD), a source voltage control signal (SVCS), and a page buffer control signal (PBSIG) according to the program algorithm, and may output a row address (RADD) and a column address (CADD) according to the address (ADD).

[0029] Figure 2 is a diagram illustrating a memory block.

[0030] Referring to FIG. 2, one memory block (BLK) among the plurality of memory blocks (BLK1 to BLKj) shown in FIG. 1 is illustrated. The memory block (BLK) may include strings (ST) connected between the first to n bit lines (BL1 to BLn) and the source line (SL). Each of the strings (ST) may include a source select transistor (SST), memory cells (MC1 to MCi), and a drain select transistor (DST) connected in series with each other. Each of the strings (ST) shown in FIG. 2 includes one source select transistor (SST) and one drain select transistor (DST), but a single string (ST) may include multiple source select transistors (SST) and multiple drain select transistors (DST).

[0031] The gates of source select transistors (SST) included in different strings (ST) can be connected to a first or second source select line (SSL1 or SSL2). For example, source select transistors (SST) arranged in the X direction can be connected to the same source select line, and some source select transistors (SST) arranged in the Y direction can be connected to different source select lines. For example, among source select transistors (SST) arranged along the Y direction, the first and second source select transistors (SST) can be connected to the first source select line (SSL1), and the third and fourth source select transistors (SST) can be connected to the second source select line (SSL2).

[0032] The gates of memory cells (MC1 to MCi) included in different strings (ST) can be connected to word lines (WL1 to WLi). For example, memory cells arranged along the X and Y planes can be connected to the same word line, and memory cells arranged along the Z direction can be connected to different word lines. For example, the first memory cells (MC1) arranged along the X and Y planes can be commonly connected to the first word line (WL1), and the i-th memory cells (MCi) arranged along the X and Y planes can be commonly connected to the i-th word line (WLi).

[0033] The gates of drain select transistors (DST) included in different strings (ST) can be connected to any one of the first to fourth drain select lines (DSL1 to DSL4). Among the drain select transistors (DST), the gates of the drain select transistors (DST) arranged in the X direction are commonly connected to the same drain select line, but the drain select transistors (DST) arranged in the Y direction can be connected to different drain select lines. For example, if the drain select transistors (DST) are arranged sequentially along the Y direction, the first drain select transistors can be connected to the first drain select line (DSL1), the second drain select transistors can be connected to the second drain select line (DSL2), the third drain select transistors can be connected to the third drain select line (DSL3), and the fourth drain select transistors can be connected to the fourth drain select line (DSL4).

[0034] The number of source selection lines and drain selection lines connected to the memory block (BLK) is not limited to the number shown in Figure 2.

[0035] When a program or read operation is performed, strings (ST) connected to the selected drain selection line within the selected memory block may become selected strings, and strings (ST) connected to the unselected drain selection lines may become unselected strings. For example, if a positive turn-on voltage is applied to the first drain selection line (DSL1) and a 0V turn-off voltage is applied to the second to fourth drain selection lines (DSL2~DSL4), the first drain selection line (DSL1) becomes the selected drain selection line, and the second to fourth drain selection lines (DSL2~DSL4) may become unselected drain selection lines. Accordingly, the strings (ST) connected to the first drain selection line (DSL1) can be selected strings, and the strings (ST) connected to the second to fourth drain selection lines (DSL2~DSL4) can be unselected strings.

[0036] When a program or read operation is performed, the first source selection line (SSL1) connected to the selected strings among the first and second source selection lines (SSL1, SSL2) can be the selected source selection line, and the second source selection line (SSL2) connected to the unselected strings can be the unselected source selection line. Accordingly, the selected source selection line can be connected to the selected strings and a portion of the unselected strings, and the unselected source selection line can be connected to only the unselected strings.

[0037] Memory cells connected to the same word line can form a single page (PG). Here, a page refers to a physical page. For example, among the first memory cells (MC1) connected to the first word line (WL1), memory cells arranged along the X direction can form a single page (PG). Accordingly, multiple pages can be connected to each of the first to i-th word lines (WL1 to WLi).

[0038] A program or read operation may be performed on a selected page. The selected page may be determined by a selected word line and a selected drain selection line. For example, during a program operation, if the first word line (WL1) is the selected word line and the first drain selection line (DSL1) is the selected drain selection line, then among the memory cells connected to the first word line (WL1), the memory cells included in the strings connected to the first drain selection line (DSL1) may constitute the selected page.

[0039] Memory cells can be programmed in various ways. For example, programming operations can be classified into single-level cell or multi-level cell methods depending on the number of bits of data stored in a single memory cell. A single-level cell method may be one in which 1 bit of data is stored in a single memory cell, while a multi-level cell method may be one in which 2 bits of data are stored in a single memory cell. Additionally, programming operations can be classified into triple-level cell methods, in which 3 bits of data are stored in a single memory cell, and quad-level cell methods, in which 4 bits of data are stored. Furthermore, programming operations may be performed using various methods in which 5 bits or more of data are stored in a single memory cell.

[0041] Figure 3 is a diagram illustrating a voltage generator and a row decoder.

[0042] Referring to FIG. 3, the voltage generator (21) may include a first operating voltage generator (10VG) and a second operating voltage generator (20VG). The first operating voltage generator (10VG) or the second operating voltage generator (20VG) may generate operating voltages used for program, read, or erase operations and may output the operating voltages through the first global lines (1GL) or the second global lines (2GL). When the first operating voltage generator (10VG) outputs operating voltages to be applied to a selected memory block, the second operating voltage generator (20VG) may output a ground voltage or a positive voltage. When the second operating voltage generator (20VG) outputs operating voltages to be applied to a selected memory block, the first operating voltage generator (10VG) may output a ground voltage or a positive voltage.

[0043] The first global lines (1GL) may include a global drain selection line (GDSL), first to i-th global word lines (GWL1~GWLi) and a global source selection line (GSSL). The second global lines (2GL) may also include a global drain selection line (GDSL), first to i-th global word lines (GWL1~GWLi) and a global source selection line (GSSL).

[0044] The row decoder (22) may include a first decoder (1DEC), a second decoder (2DEC), and first to fourth pass switch groups (1PSG to 4PSG). Each of the first to fourth pass switch groups (1PSG to 4PSG) may include pass switches (PS) connected in parallel with each other. Since the pass switches (PS) must transmit a high voltage such as a program voltage, they may be implemented as high voltage transistors. For example, the pass switches (PS) may be implemented as high voltage NMOS transistors. The first and second decoders (1DEC, 2DEC) may determine the levels of the first and second block select signals (1BLKST, 2BLKST) in response to a row address (RADD).

[0045] The first decoder (1DEC) may be configured to output a first block select signal (1BLKST) that is commonly applied to the second and fourth pass switch groups (2PSG, 4PSG). The second decoder (2DEC) may be configured to output a second block select signal (2BLKST) that is commonly applied to the first and third pass switch groups (1PSG, 3PSG).

[0046] A first pass switch group (1PSG) may be configured to connect or disconnect local lines (LL) connected to the first global lines (1GL) and the first memory block (BLK1) in response to a second block select signal (2BLKST) output from a second decoder (2DEC). A second pass switch group (2PSG) may be configured to connect or disconnect local lines (LL) connected to the second global lines (2GL) and the second memory block (BLK2) in response to a first block select signal (1BLKST) output from a first decoder (1DEC). A third pass switch group (3PSG) may be configured to connect or disconnect local lines (LL) connected to the second global lines (2GL) and the third memory block (BLK3) in response to a second block select signal (2BLKST) output from a second decoder (2DEC). The fourth pass switch group (4PSG) can be configured to connect or disconnect the first global lines (1GL) and the local lines (LL) connected to the fourth memory block (BLK4) in response to the first block select signal (1BLKST) output from the first decoder (1DEC).

[0047] Since the first to fourth pass switch groups (1PSG~4PSG) are configured similarly to one another, the first pass switch group (1PSG) is described in detail as follows.

[0048] The first pass switch group (1PSG) can be turned on when the second block select signal (2BLKST) is high voltage and turned off when it is ground voltage. The high voltage is a positive voltage higher than 0V and can have a level higher than the program voltage. For example, the high voltage can be set to a level that is the sum of the threshold voltage at which the pass switch (PS) is turned on and the program voltage.

[0049] When the second block select signal (2BLKST) is high voltage, the pass switches (PS) included in the first pass switch group (1PSG) are turned on, so the global drain select line (GDSL), the first to i-th global word lines (GWL1~GWLi), and the global source select line (GSSL) included in the first global lines (1GL) can be connected to the drain select line (DSL), the first to i-th word lines (WL1~WLi), and the source select line (SSL) connected to the first memory block (BLK1). Accordingly, the operating voltages applied to the first global lines (1GL) can be transmitted to the first memory block (BLK1) through the first pass switch group (1PSG).

[0050] If the second block selection signal (2BLKST) is ground voltage, the pass switches (PS) included in the first pass switch group (1PSG) are turned off, so the local lines (LL) connected to the first memory block (BLK1) can be floating.

[0051] If the second block select signal (2BLKST) is a negative voltage lower than the ground voltage, the pass switches (PS) can be turned off. Even if the level of the negative voltage rises and a GIDL occurs in some of the pass switches (PS), the voltage applied to the global drain and global source select lines (GDSL, GSSL) is not transmitted to the drain and source select lines (DSL, SSL) due to the distance between the pass switches (PS) and the memory blocks.

[0053] FIGS. 4a and 4b are drawings for explaining the selection transistors of a selected memory block and a non-selected memory block during program operation, where FIG. 4a shows a selected memory block and FIG. 4b shows a non-selected memory block.

[0054] Referring to FIGS. 4a and 4b, a turn-on voltage (Von) is applied to the drain select line (DSL) and source select line (SSL) connected to the selected memory block (Sel_BLK), a program voltage (Vpgm) is applied to the selected word line, and a pass voltage (Vpass) may be applied to the unselected word lines (Unsel_WL). A source voltage (Vsl) having a positive voltage is applied to the source line (SL), and a program allow voltage (Val) or a program prohibit voltage (Vinh) may be applied to the first to n-th bit lines (BL1~BLn). The program allow voltage (Val) may be set to ground voltage or 0V, and the program prohibit voltage (Vinh) may be set to a positive voltage. In the selected memory block (Sel_BLK), since the first to nth bit lines (BL1~BLn) must be electrically connected to the strings, a turn-on voltage (Von) having a positive voltage is applied to the drain select line (DSL), and the drain select transistors (DST) can be turned on by the turn-on voltage (Von). A source voltage (Vsl) having a positive voltage can be applied to the source line (SL), but a ground voltage may also be applied to the source line (SL) depending on the program operation. Since the turn-on voltage (Von) is applied to the source select line (SSL), the source select transistors (SST) can also be turned on. Assuming that the first word line (WL1) is the selected word line, the remaining second to ith word lines (WL2~WLi) become the unselected word lines. A program voltage (Vpgm) may be applied to the first word line (WL1), which is a selected word line, and a pass voltage (Vpass) may be applied to the second to i-th word lines (WL2~WLi), which are unselected word lines.

[0055] The first to nth bit lines (BL1 to BLn) are commonly connected to the selected memory block (Sel_BLK) and the unselected memory block (Unsel_BLK). Therefore, to prevent channel boosting from occurring in the unselected memory block (Unsel_BLK), the drain select transistors (DST) and source select transistors (SST) included in the unselected memory block (Unsel_BLK) must be turned off. To turn off the drain select transistors (DST) and source select transistors (SST), a ground voltage may be applied to the drain select line (DSL), source select line (SSL), and the first to ith word lines (WL1 to WLi), or the drain select line (DSL), source select line (SSL), and the first to ith word lines (WL1 to WLi) may be floated.

[0056] However, when a ground voltage (VSS) is applied to the drain select line (DSL) or source select line (SSL), leakage current may occur in the drain select transistor (DST) or source select transistor (SST) due to the voltage difference between the drain and the gate or the voltage difference between the source and the gate. If leakage current occurs in the drain select transistor (DST) or source select transistor (SST), the positive voltage applied to the bit lines or source line (SL) may flow into the strings, causing channel boosting.

[0057] The specific reasons why leakage current occurs in a drain select transistor (DST) or source select transistor (SST) are as follows.

[0059] FIGS. 5A and FIGS. 5B are drawings illustrating gate-induced drain leakage (GIDL) that may occur in an unselected memory block, FIG. 5A is a drawing illustrating GIDL that may occur in a drain select transistor (DST), and FIG. 5B is a drawing illustrating GIDL that may occur in a source select transistor (SST).

[0060] Referring to FIG. 5a, the drain select transistor (DST) may include a channel film (CH), a tunnel insulating film (Tx), a charge trap film (Ct), a blocking film (Bx), and a drain select line (DSL). If the memory device is implemented in a three-dimensional structure, the channel film (CH) may be formed of polycrystalline silicon. The tunnel insulating film (Tx) and the blocking film (Bx) may be formed of insulating materials. For example, the tunnel insulating film (Tx) and the blocking film (Bx) may be formed of an oxide film or a silicon oxide film. The charge trap film (Ct) may be formed of a nitride film. The drain select line (DSL) may be formed of a conductive material. For example, the drain select line (DSL) may be formed of a conductive material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni).

[0061] The drain (DR) of the drain select transistor (DST) can be connected to the bit line (BL). When a positive program prohibition voltage (Vinh) is applied to the bit line (BL) and a ground voltage (VSS) is applied to the drain select line (DSL), the drain (DR) region may extend into the region adjacent to the drain select line (DSL) due to the voltage difference between the drain (DR) and the drain select line (DSL). Consequently, a hole (H) may escape from the channel film (CH) between the drain (DR) and the tunnel insulating film (Tx), and an electron (e) may move into the region from which the hole (H) has escaped, causing a GIDL. When a GIDL occurs, leakage current is generated in the drain select transistor (DST), which must remain in the turned-off state, so the program prohibition voltage (Vinh) applied to the bit line (BL) may gradually flow into the channel film (CH). As a result, channel boosting may occur in the channel membrane (CH).

[0062] Referring to Fig. 5b, the source select transistor (SST) is implemented with the same structure as the drain select transistor (DST), so the description of the structure of the source select transistor (SST) is omitted.

[0063] The source (SC) of the source select transistor (SST) can be connected to the source line (SL). When a positive source voltage (Vsl) is applied to the source line (SL) and a ground voltage (VSS) is applied to the source select line (SSL), the source (SC) region may extend into the region adjacent to the source select line (SSL) due to the voltage difference between the source (SC) and the source select line (SSL). Consequently, holes (H) may escape from the channel film (CH) between the source (SC) and the tunnel insulating film (Tx), and electrons (e) may move into the region from which the holes (H) have escaped, causing a GIDL. When a GIDL occurs, leakage current is generated in the source select transistor (SST), which should remain in the turned-off state, so the source voltage (Vsl) applied to the source line (SL) may gradually flow into the channel film (CH). As a result, channel boosting may occur in the channel film (CH).

[0064] In the following embodiments, an operation method is disclosed to prevent GIDL from occurring in drain select transistors (DST) or source select transistors (SST) included in unselected memory blocks.

[0066] FIG. 6 is a diagram illustrating the voltages used during program operation according to the present invention.

[0067] Referring to FIGS. 3 and FIGS. 6, when a program operation is performed on a selected memory block (Sel_BLK), the voltage of the global lines corresponding to the unselected memory blocks (Unsel_BLK) and the voltage of the block selection signal can be adjusted.

[0068] It is assumed that among the first to fourth memory blocks (BLK1~BLK4), the fourth memory block (BLK4) is the selected memory block (Sel_BLK), and the first to third memory blocks (BLK1~BLK3) are the unselected memory blocks (Unsel_BLK).

[0069] Since the operating voltages (Vop) applied to the selected memory block (Sel_BLK) are applied to the selected memory block (Sel_BLK) through the first global lines (1GL) and the fourth pass switch group (4PSG), the first operating voltage generator (10VG) generates the operating voltages (Vop), and the first decoder (1DEC) can output a first block selection signal (1BLKST) having a high voltage.

[0070] Among the unselected memory blocks (Unsel_BLK), the first memory block (BLK1) corresponds to the first pass switch group (1PSG) and the first global lines (1GL), the second memory block (BLK2) corresponds to the second pass switch group (2PSG) and the second global lines (2GL), and the third memory block (BLK3) corresponds to the third pass switch group (3PSG) and the second global lines (2GL).

[0071] During the program operation of the selected memory block (Sel_BLK), a ground voltage (VSS) is applied to the second global lines (2GL), but a positive voltage (Vp) may be applied to some global lines during some parts of the program operation. For example, the second operation voltage generator (20VG) may apply a positive voltage (Vp) to the global drain select line (GDSL) and the global source select line (GSSL) during some parts of the program operation. The reason for applying a positive voltage (Vp) to the global drain select line (GDSL) and the global source select line (GSSL) is to prevent GIDL from occurring in the drain select transistors and source select transistors by delivering a positive voltage to the drain select line (DSL) and source select line (SSL) connected to the unselected memory blocks (Unsel_BLK). In order to transfer the positive voltage (Vp) applied to the second global lines (2GL) to the unselected memory blocks (Unsel_BLK), the second decoder (2DEC) can output a second block select signal (2BLKST) having a negative voltage (Vn) in some sections.

[0072] Among the unselected memory blocks (Unsel_BLK), the first memory block (BLK1) may be affected by the voltages applied to the first global lines (1GL) and the voltage of the second block selection signal (2BLKST), the second memory block (BLK2) may be affected by the voltages applied to the second global lines (2GL) and the voltage of the first block selection signal (1BLKST), and the third memory block (BLK3) may be affected by the voltages applied to the second global lines (2GL) and the voltage of the second block selection signal (2BLKST).

[0073] The interval during which the voltages applied to the second global lines (2GL) change from ground voltage (VSS) to positive voltage (Vp) and the interval during which the second block select signal (2BLKST) changes from ground voltage (VSS) to negative voltage (Vn) may be the same. For example, when a pass voltage or program voltage is applied to the word lines, it may change from ground voltage (VSS) to positive voltage (Vp) or negative voltage (Vn).

[0074] The specific method for changing the voltages applied to each line and the block selection signal voltage during program operation is as follows.

[0076] FIG. 7 is a diagram illustrating a program operation according to the present invention, and FIG. 8a and FIG. 8b are diagrams illustrating the operation of selection transistors according to the present invention.

[0077] Referring to FIGS. 6 and 7, in the pass voltage application interval (T1-T2), a turn-on voltage (Von) set to a positive voltage is applied to the global drain select line (GDSL) and global source select line (GSSL) included in the first global lines (1GL), and a pass voltage (Vpass) may be applied to the selected global word line (Sel_GWL) and the unselected global word lines (Unsel_GWL). In order to transfer the operating voltages (Vop) applied to the first global lines (1GL) to the selected memory block (Sel_BLK), the first block select signal (1BLKST) may have a high voltage (HV). The high voltage (HV) may be set to a voltage that is at least the sum of the threshold voltage of the pass switch and the program voltage (Vpgm). A ground voltage (VSS) may be applied to the global word lines (GWL) included in the second global lines (2GL), and a ground voltage (VSS) or a positive voltage (Vp) may be applied to the global drain select line (GDSL) and the global source select line (GSSL). The second block select signal (2BLKST) may have a ground voltage (VSS).

[0078] In the program voltage application period (T2-T3), a program voltage (Vpgm) may be applied to a selected global word line (Sel_GWL) included in the first global lines (1GL). Since the first block selection signal (1BLKST) has a high voltage (HV), the program voltage (Vpgm) applied to the selected global word line (Sel_GWL) may be transferred to a selected word line connected to a selected memory block (Sel_BLK).

[0079] Referring to FIG. 8a, when the voltage of the drain select line (DSL) increases from the ground voltage (VSS) to a low positive voltage (L_Vp), the voltage difference between the gate and the drain (DR) of the drain select transistor (DST) can be reduced. For example, when a program prohibition voltage (Vinh) is applied to the bit line (BL), when the voltage of the drain select line (DSL) increases to a low positive voltage (L_Vp), the voltage difference between the drain (DR) and the gate can be reduced. As a result, the drain (DR) region of the drain select transistor (DST) does not expand, and since a channel is not formed in the channel film (CH), the drain select transistor (DST) can be turned off.

[0080] Referring to FIG. 8b, when the voltage of the source select line (SSL) increases from the ground voltage (VSS) to a low positive voltage (L_Vp), the voltage difference between the gate and the source (SC) of the source select transistor (SST) can be reduced. For example, when a source voltage (Vsl) is applied to the source line (SL), if the voltage of the source select line (SSL) increases to a low positive voltage (L_Vp), the voltage difference between the source (SC) and the gate can be reduced. As a result, the source (SC) region of the source select transistor (SST) does not expand, and since a channel is not formed in the channel film (CH), the source select transistor (SST) can be turned off.

[0081] As described above, by keeping the drain select transistors (DST) and source select transistors (SST) of the unselected memory blocks in a turned-off state, the phenomenon of channel boosting occurring in the strings of the unselected memory blocks can be prevented.

[0082] Referring to FIGS. 6 and 7, after a positive voltage (Vp) is applied to the global drain select line (GDSL) and the global source select line (GSSL) during the first time period (tk1), a ground voltage (VSS) can be applied again to the global drain select line (GDSL) and the global source select line (GSSL). The second block select signal (2BLKST) can also be raised back to the ground voltage (VSS) after maintaining a negative voltage (Vn) during the second time period (tk2).

[0084] FIG. 9 is a diagram illustrating the voltage of the selected lines in the voltage change section according to the present invention.

[0085] Since FIG. 9 is a simplified drawing of FIG. 3, the detailed circuit of multiple lines and pass switch groups is omitted, and the connection relationships between each component are shown.

[0086] Referring to FIG. 9, during the first or second time (tk1 or tk2) of FIG. 7, different voltages may be applied to the drain select lines (DSL) and source select lines (SSL) connected to the selected memory block (Sel_BLK) or the unselected memory blocks (Unsel_BLK).

[0087] The drain and source selection lines (DSL, SSL) connected to the fourth memory block (BLK4), which is the selected memory block (Sel_BLK), may be affected by the voltage applied to the first global lines (1GL) and the voltage of the first block selection signal (1BLKST). For example, since a turn-on voltage (Von) is applied to the global drain and global source lines included in the first global lines (1GL) and the first block selection signal (1BLKST) is a high voltage (HV), the turn-on voltage (Von) applied to the global drain and global source lines may be transmitted to the drain and source selection lines (DSL, SSL) of the selected memory block (Sel_BLK).

[0088] Drain and source select lines (DSL, SSL) connected to the third memory block (BLK3), which is an unselected memory block (Unsel_BLK), may be affected by the voltage applied to the second global lines (2GL) and the voltage of the second block select signal (2BLKST). For example, since a positive voltage (Vp) is applied to the global drain and global source lines included in the second global lines (2GL) and the second block select signal (2BLKST) is a negative voltage (Vn), the drain and source select lines (DSL, SSL) of the third memory block (BLK3) may be floating.

[0089] Drain and source selection lines (DSL, SSL) connected to the second memory block (BLK2), which is an unselected memory block (Unsel_BLK), may be affected by the voltage applied to the second global lines (2GL) and the voltage of the first block selection signal (1BLKST). For example, a positive voltage (Vp) is applied to the global drain and global source lines included in the second global lines (2GL), and since the first block selection signal (1BLKST) is a high voltage (HV), the high voltage (Vp) applied to the global drain and global source lines may be transmitted to the drain and source selection lines (DSL, SSL) of the second memory block (BLK2).

[0090] Drain and source select lines (DSL, SSL) connected to the first memory block (BLK1), which is an unselected memory block (Unsel_BLK), may be affected by the voltage applied to the first global lines (1GL) and the voltage of the second block select signal (2BLKST). For example, since a turn-on voltage (Von) is applied to the global drain and global source lines included in the first global lines (1GL) and the second block select signal (2BLKST) is a negative voltage (Vn), the drain and source select lines (DSL, SSL) of the first memory block (BLK1) may be floating.

[0091] As described above, when the program operation of the selected memory block is completed, the drain select transistors and source select transistors included in the unselected memory blocks are kept in a turned-off state, thereby preventing channel boosting from occurring in the strings of the unselected memory blocks. Therefore, when a subsequent operation is performed in the unselected memory blocks after the program operation of the selected memory block is completed, the time required to initialize the channels of the unselected memory blocks can be shortened, and since there is no residual channel voltage, the reliability of the subsequent operation performed in the unselected memory blocks can be improved. Explanation of the symbols

[0093] 100: Memory device 110: Memory cell array 120: Peripheral circuits 130: Control circuits 21: Voltage generator 22: Row decoder 23: Source voltage generator 24: Page buffer group 25: Column decoder 26: Input / output circuit OVG: Operating voltage generator DEC: Decoder PSG: Pass Switch Group PS: Pass Switch

Claims

Claim 1 A memory device comprising: a first memory block connected to first local lines and a second memory block connected to second local lines, each comprising a plurality of memory cells; a voltage generator connected to first and second global lines, configured to apply operating voltages to the first global lines, selectively apply a positive voltage to global select lines included in the second global lines while applying the operating voltages, and apply a ground voltage to the remaining global lines among the second global lines excluding the global select lines; and a row decoder configured to turn on first pass switches connecting the first local lines and the first global lines to each other, and turn off second pass switches connecting the second local lines and the second global lines to each other. Claim 2 A memory device according to claim 1, wherein the voltage generator comprises: a first operating voltage generator configured to apply the operating voltages, the ground voltage, or the positive voltage to the first global lines; and a second operating voltage generator configured to apply the operating voltages, the ground voltage, or the positive voltage to the second global lines. Claim 3 A memory device according to claim 2, wherein when the first operating voltage generator applies the operating voltages to the first global lines, the second operating voltage generator applies the ground voltage to the second global lines, and in the interval in which the first operating voltage generator applies a program voltage to a selected global word line among the first global lines, the second operating voltage generator is configured to apply the positive voltage to the global select lines included in the second global lines. Claim 4 In paragraph 3, the second operating voltage generator is a memory device configured to apply the ground voltage to the global select lines after applying the positive voltage to the global select lines for a certain period of time while the program voltage is applied to the selected global word line among the first global lines. Claim 5 In claim 1, the operating voltages include a program voltage, a pass voltage, and a turn-on voltage in a memory device. Claim 6 A memory device according to claim 1, wherein the row decoder further comprises: a first decoder configured to output a first block selection signal for simultaneously controlling the first pass switches in response to a row address; and a second decoder configured to output a second block selection signal for simultaneously controlling the second pass switches in response to the row address. Claim 7 A memory device according to claim 6, wherein the first pass switches are connected between the first global lines and the first local lines, the first global lines include global select lines and global word lines, and the first local lines include local select lines and local word lines. Claim 8 A memory device according to claim 7, wherein the local select lines are connected to the gates of the select transistors of the first memory block, and the local word lines are connected to the gates of the memory cells between the select transistors. Claim 9 In claim 6, the second pass switches are memory devices respectively connected between the global select lines and global word lines included in the second global lines and the local select lines and local word lines included in the second local lines. Claim 10 A memory device according to claim 9, wherein the local select lines are connected to the gates of the select transistors of the second memory block, and the local word lines are connected to the gates of the memory cells between the select transistors. Claim 11 In claim 6, the first decoder is a memory device configured to output the first block selection signal as a high voltage to turn on the first pass switches. Claim 12 In claim 11, the memory device wherein the high voltage is set to a voltage equal to the sum of the threshold voltage of the first pass switches and the program voltage, or a voltage higher than the sum voltage. Claim 13 In claim 6, the memory device configured such that the second decoder outputs the second block selection signal as a negative voltage so that the second pass switches are turned off. Claim 14 A memory device comprising: a first memory block connected to first local lines and a second memory block connected to second local lines, each comprising a plurality of memory cells; a voltage generator connected to first and second global lines, configured to apply operating voltages to the first global lines, selectively apply a positive voltage to global select lines included in the second global lines while applying the operating voltages, and apply a ground voltage to the remaining global lines among the second global lines excluding the global select lines; and a row decoder configured to apply a first block select signal having a high voltage to first pass switches connecting the first local lines and the first global lines to each other, and selectively apply a negative voltage to second pass switches connecting the second local lines and the second global lines to each other. Claim 15 In claim 14, the voltage generator is configured to apply a ground voltage to the second global lines while the operating voltages are applied to the first global lines, and to apply the positive voltage to the global select lines included in the second global lines when the operating voltages include a program voltage. Claim 16 A memory device according to claim 14, wherein while the voltage generator applies the positive voltage to the global select lines included in the second global lines, the row decoder is configured to apply the negative voltage to the second pass switches. Claim 17 A method of operating a memory device comprising: turning on first pass switches connecting first local lines connected to a first memory block and first global lines connected to a voltage generating unit; turning off second pass switches connecting second local lines connected to a second memory block and second global lines connected to the voltage generating unit; applying a program voltage to a selected global word line among the first global lines; applying a positive voltage to global select lines among the second global lines when the program voltage is applied to the selected global word line; and applying a negative voltage to the gates of the second pass switches when the program voltage is applied to the selected global word line. Claim 18 A method of operation of a memory device according to claim 17, wherein, in the step of turning on the first pass switches, a first block selection signal having a high voltage is applied to the gates of the first pass switches. Claim 19 A method of operation of a memory device according to claim 18, wherein the high voltage is the sum of the threshold voltage of the first pass switches and the program voltage, or a voltage higher than the sum. Claim 20 A method of operation of a memory device according to claim 17, wherein, in the step of turning off the second pass switches, a second block selection signal having a ground voltage is applied to the gates of the second pass switches. Claim 21 In claim 17, the step of applying the negative voltage to the gates of the second pass switches is performed within the step of applying the program voltage to the selected global word line among the first global lines. Claim 22 In claim 21, the step of applying the positive voltage to the global select lines among the second global lines is performed within the step of applying the negative voltage to the gates of the second pass switches. Claim 23 A method of operation of a memory device according to claim 17, wherein, prior to the step of applying the positive voltage to the global select lines among the second global lines, a ground voltage is applied to the second global lines. Claim 24 In claim 17, the second pass switches are turned off between local select lines connected to select transistors of the second memory block and the global select lines. A method of operation of a memory device.

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