Semiconductor device

Abstract

The semiconductor device of the present invention comprises a channel layer located on a substrate; and a gate structure formed on the channel layer. The channel layer is composed of a single layer of oxide semiconductor material, and the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. The channel layer comprises a first region adjacent to the substrate and adjacent to the gate structure, a third region adjacent to the gate structure, and a second region located between the first region and the third region. The first region and the third region are regions in which the atomic composition of gallium (Ga) atoms is higher than that of indium (In) atoms, and the second region is a region in which the composition of indium (In) atoms is higher than that of gallium (Ga) atoms. The channel layer is formed in a U-shaped structure on the substrate, and the gate structure is embedded within the U-shaped channel layer.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a transistor. Background Technology

[0002] A semiconductor device (or integrated circuit device) may include multiple transistors. As the semiconductor industry develops, semiconductor devices containing transistors are becoming highly integrated, that is, miniaturized. Highly integrated semiconductor devices are required to improve both the performance of transistors, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics). The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor device having a transistor with improved leakage characteristics and channel characteristics. means of solving the problem

[0004] To solve the above-mentioned problem, a semiconductor device according to one embodiment of the technical concept of the present invention comprises a channel layer located on a substrate; and a gate structure formed on the channel layer. The channel layer is composed of a single layer of oxide semiconductor material, and the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. The channel layer comprises a first region adjacent to the substrate and adjacent to the gate structure, a third region adjacent to the gate structure, and a second region located between the first region and the third region. The first region and the third region are regions in which the atomic composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is a region in which the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms. The channel layer is formed in a U-shaped structure on the upper surface of the substrate, and the gate structure is embedded within the U-shaped channel layer.

[0005] A semiconductor device according to one embodiment of the technical concept of the present invention comprises: a channel layer located on a substrate; a gate structure formed on or below the channel layer; a first contact structure formed on the channel layer on one side of the gate structure; and a second contact structure formed on the channel layer on the other side of the gate structure.

[0006] The channel layer is composed of a single layer of oxide semiconductor material, and the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. The channel layer comprises a first region adjacent to the substrate and adjacent to the gate structure, a third region adjacent to the gate structure, and a second region located between the first region and the third region. The first region and the third region are regions where the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is a region where the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms. The channel layer is formed in a U-shaped structure on the upper surface of the substrate, and the gate structure is embedded within the U-shaped channel layer.

[0007] A semiconductor device according to one embodiment of the technical concept of the present invention comprises: a first conductive line extended in a first direction on a substrate; a second conductive line extended in a second direction perpendicular to the first direction on the substrate; and a transistor located between the first conductive line and the second conductive line.

[0008] The transistor comprises a channel layer; a gate structure including a gate insulating layer formed on the channel layer and a gate electrode formed on the gate insulating layer and composed of the second conductive line, wherein the channel layer is composed of a single layer of oxide semiconductor material, and the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms, and the channel layer comprises a first region adjacent to the gate electrode, a third region adjacent to the gate electrode, and a second region located between the first region and the third region, wherein the first region and the third region are regions in which the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is a region in which the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms. The channel layer is formed in a U-shaped structure on the upper surface of the substrate, and the gate structure is embedded inside the U-shaped channel layer. Effects of the invention

[0009] The semiconductor device of the present invention comprises a transistor having a gate structure and a channel layer. The semiconductor device of the present invention comprises a channel layer in contact with the gate structure composed of a single layer of oxide semiconductor material. The channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms.

[0010] The channel layer includes a first region adjacent to the gate structure, a third region adjacent to the gate structure, and a second region located between the first region and the second region. The first region and the third region are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms. The semiconductor device can improve the performance of the transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics). Brief explanation of the drawing

[0011] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the technical concept of the present invention. Figure 2 is an enlarged view of the "EN1" portion of Figure 1. Figures 3 and 4 are enlarged views of the "EN2" and "EN3" sections of Figure 2, respectively. Figure 5 is a diagram illustrating the change in atomic composition according to the scanning direction of Figure 2. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a channel layer as illustrated in FIG. 2. FIG. 7 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the technical concept of the present invention. Figure 8 is an enlarged view of the "EN4" portion of Figure 7. FIG. 9 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 10 is a cross-sectional view along X-X' of FIG. 9. Figure 11 is a cross-sectional view along Y-Y' of Figure 9. FIG. 12 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention. Figure 13 is a cross-sectional view along B-B' of Figure 12. Fig. 14 is an enlarged view of the "EN5" portion of Fig. 12. FIG. 15 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 16 is a cross-sectional view along X-X' of FIG. 15. FIG. 17 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 18 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 19 is a cross-sectional view along X-X' of FIG. 18. Fig. 20 is an enlarged view of the "EN6" portion of Fig. 19. FIG. 21 is a block diagram for explaining an electronic system including a semiconductor device according to one embodiment of the technical concept of the present invention. Specific details for implementing the invention

[0012] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The following embodiments of the present invention may be implemented as only one, and may also be implemented by combining one or more of the following embodiments. Accordingly, the technical concept of the present invention is not to be interpreted as being limited to a single embodiment.

[0013] In this specification, the singular form of the components may include the plural form unless the context clearly indicates otherwise. In this specification, the drawings are illustrated in an exaggerated manner to more clearly explain the invention.

[0014] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the technical concept of the present invention, and FIG. 2 is an enlarged view of the "EN1" portion of FIG. 1.

[0015] Specifically, the semiconductor device (10) may include a substrate (12), a channel layer (14), a gate structure (GE1), a first contact structure (CT1a), and a second contact structure (CT1b). The semiconductor device (10) may be named a transistor. The substrate (12) may be a silicon substrate. A channel layer (14) may be formed on the substrate (12).

[0016] The channel layer (14) may be composed of a single layer of oxide semiconductor material. The channel layer (14) may include indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In addition to indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms, the channel layer (14) may include zinc (Zn) atoms or tin (Sn) atoms.

[0017] In some embodiments, the channel layer (14) is In x Ga y Zn z O(IGZO), In x Ga y Si zO(IGSO), In x Sn y Ga z O(ITGO), or In x Ga y It may include O(IGO). In some embodiments, the channel layer (14) is In x Ga y Zn z O(IGZO), In x Ga y Si z O(IGSO) or In x Sn y Ga z When composed of O(ITGO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0018] The channel layer (14) may have a bandgap energy greater than the bandgap energy of silicon. The channel layer (14) may have a bandgap energy of about 1.5 eV to 5.6 eV. The channel layer (14) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. The channel layer (14) may be polycrystalline or amorphous, but is not limited thereto.

[0019] The channel layer (14) may include a first region (14a) in contact with the substrate (12) and in contact with the gate structure (GE1), a third region (14c) in contact with the gate structure (GE1), and a second region (14b) located between the first region (14a) and the third region (14c). The second region (14b) may be thicker than the first region (14a) and the third region (14c), as shown in FIG. 2.

[0020] The second region (14b) is an inner region of the channel layer (14), and the first region (14a) and the third region (14c) may be outer regions of the channel layer (14). In FIG. 2, for convenience, the boundary lines of the first region (14a) and the second region (14b), and the boundary lines of the second region (14b) and the third region (14c) are shown in a straight line form, but they may be in a curved form.

[0021] The first region (14a) and the third region (14c) are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms. In the first region (14a) and the third region (14c), if the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, the generation of oxygen vacancies within the channel layer (14) is reduced, thereby improving the leakage characteristics of the semiconductor device (10). In other words, the reliability of the semiconductor device (10) can be improved.

[0022] The second region (14b) is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms. In the second region (14b), if the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms, the carrier concentration (i.e., oxygen vacancy concentration) and carrier mobility (i.e., oxygen vacancy mobility) can be improved, thereby improving channel characteristics, i.e., channel-on characteristics.

[0023] A gate structure (GE1) is formed on the channel layer (14). The gate structure (GE1) may include a gate insulating layer (22) formed on the channel layer (14), a first barrier layer (24) formed on the gate insulating layer (22), and a gate electrode (26) formed on the first barrier layer (24).

[0024] The gate insulating layer (22) may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be made of a metal oxide or a metal oxynitride. In some embodiments, the high dielectric film usable as the gate insulating layer (22) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0025] The first barrier layer (24) may be made of a metal, such as titanium or titanium nitride. The gate electrode (26) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. In some embodiments, the gate electrode (26) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of , or a combination thereof, but is not limited to these.

[0026] A first contact structure (CT1a) is formed on a channel layer (14) on one side of a gate structure (GE1). The first contact structure (CT1a) may be a source contact structure. The first contact structure (CT1a) may be positioned horizontally (i.e., in the -X direction) away from the surface of the substrate (12).

[0027] The first contact structure (CT1a) may include a second barrier layer (28) and a first contact layer (30). The second barrier layer (28) and the first contact layer (30) may each be composed of the same material as the first barrier layer (24) and the gate electrode (26).

[0028] A second contact structure (CT1b) is formed on the channel layer (14) on the other side of the gate structure (GE1). The second contact structure (CT1b) may be a drain contact structure. The second contact structure (CT1b) may be positioned horizontally (i.e., in the X direction) away from the surface of the substrate (12).

[0029] The second contact structure (CT1b) may include a third barrier layer (32) and a second contact layer (34). The third barrier layer (32) and the second contact layer (34) may each be composed of the same material as the second barrier layer (28) and the first contact layer (30).

[0030] Figures 3 and 4 are enlarged views of the "EN2" and "EN3" sections of Figure 2, respectively.

[0031] Specifically, FIG. 3 is provided to illustrate the boundary region between the third region (14c) of the channel layer (14) of FIG. 2 and the second contact structure (CT1b). At the interface between the third region (14c) of the channel layer (14) and the second contact structure (CT1b), out-diffusion of oxygen (O) is suppressed by strong bonding between gallium (Ga) and oxygen (O), and penetration of impurities (e.g., hydrogen (H), chlorine (Cl)) from the second contact structure (CT1b) is suppressed, thereby improving the leakage characteristics of the semiconductor device (10 of FIG. 1).

[0032] In other words, if the composition of gallium (Ga) atoms in the third region (14c) is higher than the composition of indium (In) atoms, the generation of oxygen vacancies within the third region (14c) is reduced, and the leakage characteristics of the semiconductor device (10 in FIG. 1) can be improved.

[0033] Additionally, FIG. 4 is provided to illustrate the boundary region between the first region (14a) and the second region (14b) of the channel layer (14) of FIG. 2. At the interface between the second region (14b), in which the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms, and the first region (14a), in which the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, the oxygen vacancy (Vo) generated in the second region (14b) is unlikely to pass through the first region (14a), so the density of oxygen vacancies (Vo) in the second region (14b) can be maintained.

[0034] In this case, the carrier concentration (i.e., the concentration of oxygen vacancies (Vo)) and carrier mobility (i.e., the mobility of oxygen vacancies (Vo)) in the second region (14b) can be improved to enhance the channel characteristics, i.e., the channel-on characteristics, of the semiconductor device (10 in FIG. 1).

[0035] Figure 5 is a diagram illustrating the change in atomic composition according to the scanning direction of Figure 2.

[0036] Specifically, FIG. 5 is a diagram illustrating the composition ratio of gallium (Ga) atoms and indium (In) atoms in a channel layer (14 in FIG. 2) according to the scan direction (SC) of FIG. 2. The scan direction (SC) may be the direction from the third region (14c) of the channel layer (14) to the first region (14a).

[0037] In the channel layer (14 in FIG. 2), the composition of gallium (Ga) atoms is not discretely separated from the third region (14c) to the first region (14a) but increases and decreases continuously. That is, the composition of gallium (Ga) atoms is large in the third region (14c), the composition of gallium (Ga) atoms is small in the second region (14b), and the composition of gallium (Ga) atoms is large in the third region (14c).

[0038] In the channel layer (14 in FIG. 2), the composition of indium (In) atoms is not discretely separated from the third region (14c) to the first region (14a) but increases and decreases continuously. That is, the composition of indium (In) atoms is small in the third region (14c), the composition of indium (In) atoms is large in the second region (14b), and the composition of indium (In) atoms is small in the third region (14c).

[0039] Overall, the channel layer (14 in FIG. 2) may have a large composition of gallium (Ga) atoms and a small composition of indium (In) atoms in the third region (14c) and the first region (14a). The channel layer (14 in FIG. 2) may have a large composition of indium (In) atoms and a small composition of gallium (Ga) atoms in the second region (14b).

[0040] FIG. 6 is a cross-sectional view illustrating a method for manufacturing a channel layer as illustrated in FIG. 2.

[0041] Specifically, the channel layer (14) may include a first region (14a), a second region (14b), and a third region (14c) as described above. In FIG. 6, the thickness (T2) of the second region (14b) is shown as being greater than the thicknesses (T1, T3) of the first region (14a) and the third region (14c), and the thickness (T1) of the first region (14a) and the thickness (T3) of the third region (14c) are shown as being the same, but the present invention is not limited thereto.

[0042] The channel layer (14) can be formed on the substrate (12) using atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). The first region (14a), second region (14b), and third region (14c) constituting the channel layer (14) can be formed in situ at once without moving from the deposition chamber to an external space.

[0043] As previously explained, the atomic composition of the first region (14a), second region (14b), and third region (14c) constituting the channel layer (14) may differ. In FIG. 6, the channel layer (14) is In x Ga y Zn z The example is to explain the formation of O(IGZO). Here, X is 0.3 to 0.6, Y is 0.3 to 0.6, Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0044] When forming a channel layer (14) using atomic layer deposition (ALD), in the first step (1st), the number of sub-cycles of the gallium (Ga) source is increased to form a first region (14a) of the channel layer (14). In the second step (2nd), the number of sub-cycles of the gallium (Ga) source is reduced and the number of sub-cycles of the indium (In) source is increased to form a second region (14b) of the channel layer (14). In the third step (3rd), the number of sub-cycles of the gallium (Ga) source is increased in the same way as in the first step (1st) to form a third region (14c) of the channel layer (14). In the first step (1st), the second step (2nd), and the third step (3rd), the number of sub-cycles of the zinc (Zn) source is controlled to be the same.

[0045] When forming a channel layer (14) using physical vapor deposition (PVD), in the first step (1st), In which the gallium (Ga) ratio is high x Ga y Zn z A first region (14a) of the channel layer (14) is formed by a deposition method using an O(IGZO) target. In the second step (2nd), a gallium (Ga) ratio is low and an indium (In) ratio is high. x Ga y Zn zThe second region (14b) of the channel layer (14) is formed by a deposition method using an O(IGZO) target. In the third step (3rd), similar to the first step (1st), an In with a high gallium (Ga) ratio is formed. x Ga y Zn z A third region (14c) of the channel layer (14) is formed by a deposition method using an O(IGZO) target.

[0046] When forming a channel layer (14) using a chemical vapor deposition (CVD) method, in the first step (1st), the first region (14a) of the channel layer (14) is formed by increasing the ratio of the gallium (Ga) source and using a deposition method. In the second step (2nd), the second region (14b) of the channel layer (14) is formed by increasing the ratio of the indium (In) source and using a deposition method. In the third step (3rd), the third region (14c) of the channel layer (14) is formed by increasing the ratio of the gallium (Ga) source and using a deposition method, similar to the first step (1st).

[0047] As described above, the channel layer (14) can form a first region (14a), a second region (14b), and a third region (14c) with different atomic compositions in various ways.

[0048] FIG. 7 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the technical concept of the present invention, and FIG. 8 is an enlarged view of the "EN4" portion of FIG. 7.

[0049] Specifically, the semiconductor device (40) is almost identical to the semiconductor device (10) of FIG. 1, except that a gate structure (GE2) is formed on the lower part of the channel layer (50). In FIG. 7, the same content as FIG. 1 is briefly explained or omitted.

[0050] The semiconductor device (40) may be named a transistor. The semiconductor device (40) may include a substrate (42), a gate structure (GE2), a channel layer (50), a first contact structure (CT2a), a second contact structure (CT2b), and an insulating structure (56). The substrate (42) may be a silicon substrate.

[0051] The gate structure (GE2) may be formed by being defined by an insulating layer (46) on the substrate (42). The gate structure (GE2) may include a gate electrode (44) formed on the substrate (42) and a gate insulating layer (48) formed on the gate electrode (44).

[0052] In FIG. 7, the gate electrode (44) is shown having an uneven surface, but the present invention is not limited thereto. A gate insulating layer (48) may be formed on the gate electrode (44) having an uneven surface. The gate electrode (44) and the gate insulating layer (48) may each be formed of the same material as the gate electrode (26) and the gate insulating layer (22) of FIG. 1.

[0053] A channel layer (50) may be formed on a gate structure (GE2). A channel layer (50) may be formed on a gate insulating layer (48). A channel layer (50) may be formed along the upper surface of a gate electrode (44) having an uneven surface. A channel layer (50) may be formed of the same material as the channel layer (14) of FIG. 1. For example, a channel layer (50) may include indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In some embodiments, a channel layer (50) is In x Ga y Zn z O(IGZO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0054] As illustrated in FIG. 8, the channel layer (50) may include a first region (50a) in contact with the gate structure (GE2), a third region (50c) in contact with the gate structure (GE2), and a second region (50b) located between the first region (50a) and the third region (50c). As illustrated in FIG. 2, the second region (50b) may be thicker than the first region (50a) and the third region (50c).

[0055] The first region (50a), the second region (50b), and the third region (50c) may correspond to the first region (14a), the second region (14b), and the third region (14c) of FIG. 1, respectively. That is, the first region (50a) and the third region (50c) are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms. The second region (50b) is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms.

[0056] An insulating structure (56) may be formed on the channel layer (50). A first contact structure (CT2a) may be formed by connecting it to the channel layer (50) on one side of the gate structure (GE2). The first contact structure (CT2a) may include a first contact layer (54, or a first contact region) formed by connecting it to the channel layer (50). The first contact structure (CT2a) may be a source contact structure.

[0057] The second contact structure (CT2b) may be formed by connecting to the channel layer (50) on the other side of the gate structure (GE2). The second contact structure (CT2b) may include a second contact layer (55, or a second contact region) formed by connecting to the channel layer (50). The second contact structure (CT2b) may be a drain contact structure. The semiconductor device (40) described above can improve the performance of the transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics).

[0058] FIG. 9 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention, FIG. 10 is a cross-sectional view along X-X' of FIG. 9, and FIG. 11 is a cross-sectional view along Y-Y' of FIG. 9.

[0059] Specifically, the semiconductor device (60) may be nearly identical to the semiconductor device (10) of FIG. 1, except that the channel layer (68) is formed in a fin-type structure. In FIG. 9 to FIG. 11, details identical to FIG. 1 are briefly explained or omitted.

[0060] The semiconductor device (60) may include a fin-type field effect transistor (FINFET). As shown in FIG. 9, the semiconductor device (60) may have a fin-type active region (66) and a channel layer (68) extended in a first direction (X direction), and a gate structure (GE3) including a gate electrode (72) extended in a second direction (Y direction) perpendicular to the first direction.

[0061] As illustrated in FIGS. 10 and 11, the semiconductor device (60) may include a substrate (62), an insulating layer (64), a fin-type active region (66), a channel layer (68), a gate structure (GE3), a first contact structure (CT3a), and a second contact structure (CT3b). The fin-type active region (66) may be named a fin-type active pattern. The substrate (62) may be a silicon substrate.

[0062] An insulating layer (64) may be formed on a substrate (62). A pin-shaped active region (66) may be formed on the insulating layer (64). The pin-shaped active region (66) may be a pin-shaped pattern protruding in a vertical direction (Z direction) on the substrate (62) and the insulating layer (64) in a second direction (Y direction) as shown in FIG. 10. The pin-shaped active region (66) may be formed with a uniform thickness on the insulating layer (64) in a first direction (X direction) as shown in FIG. 11.

[0063] A channel layer (68) may be formed on the pin-shaped active region (66). The channel layer (68) may be formed of the same material as the channel layer (14) of FIG. 1. For example, the channel layer (68) may include indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In some embodiments, the channel layer (68) is In x Ga y Zn z O(IGZO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0064] The channel layer (68) may be a fin-shaped structure surrounding the fin-shaped active region (66) in the second direction (Y direction) as shown in FIG. 10. In other words, the channel layer (68) may be a fin-shaped structure protruding from the substrate (62). The channel layer (68) may be formed flatly on the fin-shaped active region (66) in the first direction (X direction) as shown in FIG. 11.

[0065] A gate structure (GE3) may be formed on the channel layer (68). The gate structure (GE3) may include a gate insulating layer (70) and a gate electrode (72). The gate structure (GE3) may be formed to surround the channel layer (68) of the fin-shaped structure.

[0066] As shown in FIG. 11, gate spacers (74) may be formed on both side walls of the gate structure (GE3). The gate insulating layer (70) and the gate electrode (72) may each be formed of the same material as the gate insulating layer (22) and the gate electrode (26) of FIG. 1.

[0067] As illustrated in FIGS. 10 and 11, the channel layer (68) may include a first region (68a) in contact with the gate structure (GE3), a third region (68c) in contact with the gate structure (GE3), and a second region (68b) located between the first region (68a) and the third region (68c). As illustrated in FIGS. 10 and 11, the second region (68b) may be thicker than the first region (68a) and the third region (68c).

[0068] The first region (68a), the second region (68b), and the third region (68c) may correspond to the first region (14a), the second region (14b), and the third region (14c) of FIG. 1, respectively. That is, the first region (68a) and the third region (68c) are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms. The second region (68b) is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms.

[0069] As illustrated in FIG. 11, the first contact structure (CT3a) may be formed on a channel layer (68) on one side of the gate structure (GE3). The first contact structure (CT3a) may include a first contact layer (76, or a first contact region). The first contact structure (CT3a) may be a source contact structure.

[0070] A second contact structure (CT3b) may be formed on the channel layer (68) on the other side of the gate structure (GE3). The second contact structure (CT3b) may include a second contact layer (77, or a second contact region). The second contact structure (CT3b) may be a drain contact structure. A semiconductor device (60) such as the above can improve the performance of a transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics).

[0071] FIG. 12 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention, FIG. 13 is a cross-sectional view along B-B' of FIG. 12, and FIG. 14 is an enlarged view of the "EN5" portion of FIG. 12.

[0072] Specifically, the semiconductor device (100) may be identical to the semiconductor device (10) of FIG. 1 except that a channel layer (128) is formed inside a substrate (110) and further includes a capacitor structure (CS). In FIG. 12 to FIG. 14, details identical to those in FIG. 1 are briefly described or omitted.

[0073] The semiconductor device (100) may include a buried channel array transistor (BCAT). The semiconductor device (200) may be a DRAM device. As shown in FIG. 12, the semiconductor device (60) may have a first conductive line (ML1) including a bit line (134) extended in a first direction (X direction), and a second conductive line (ML2) including a gate electrode (124) extended in a second direction (Y direction) perpendicular to the first direction.

[0074] In some embodiments, the first conductive line (ML1) and the second conductive line (ML2) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof.

[0075] For example, the first conductive line (ML1) and the second conductive line (ML2) are doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of, or a combination thereof, but is not limited thereto. The first challenge line (ML1) may include a single layer or multiple layers of the aforementioned materials.

[0076] As described below, the bit line (134) is included in the bit line structure (130), and the gate electrode (124) may be included in the gate structure (GE4). In the semiconductor device (100), the active region (AC) and the channel layer (128) may be arranged in the diagonal direction (D3 direction) between the first direction (X direction) and the second direction (Y direction).

[0077] As illustrated in FIG. 13, the semiconductor device (100) may include a substrate (110), a device isolation layer (112), an active region (AC), a channel layer (128), a gate structure (GE4), a first contact structure (CT4a), and a second contact structure (CT4b). The substrate (110) may be a silicon substrate.

[0078] The active region (AC) may be limited by a device isolation layer (112) within the substrate. The device isolation layer (112) may include an insulating material that fills a first trench (112T) for device isolation formed within the substrate (110). A second trench (120T) for gate isolation with a U-shaped structure may be formed inside the substrate (110).

[0079] A U-shaped channel layer (128) and a gate structure (GE4) may be formed inside the second trench (120T). The channel layer (128) may be formed on the inner wall of the second trench (120T). The channel layer (128) may be formed of the same material as the channel layer (14) of FIG. 1. For example, the channel layer (128) may contain indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In some embodiments, the channel layer (128) is In x Ga y Zn z O(IGZO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0080] A gate structure (GE4) may be formed on the channel layer (128). The gate structure (GE4) may include a gate insulating layer (122), a gate electrode (124), and a gate capping layer (126) formed sequentially on the channel layer (128) inside the second trench (120T). The gate capping layer (126) may not be formed if necessary. The gate insulating layer (122) and the gate electrode (124) may each be formed of the same material as the gate insulating layer (22) and the gate electrode (26) of FIG. 1.

[0081] As illustrated in FIGS. 13 and 14, the channel layer (128) may include a first region (128a) in contact with the gate structure (GE4), a third region (128c) in contact with the gate structure (GE4), and a second region (128b) located between the first region (128a) and the third region (128c). As illustrated in FIGS. 13 and 14, the second region (128b) may be thicker than the first region (128a) and the third region (128c).

[0082] The first region (128a), the second region (128b), and the third region (128c) may correspond to the first region (14a), the second region (14b), and the third region (14c) of FIG. 1, respectively. That is, the first region (128a) and the third region (128c) are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms. The second region (128b) is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms.

[0083] A first contact structure (CT4a) may be formed on a gate structure (GE4) on one side and a channel layer (128) on the other side, as illustrated in FIG. 13. The first contact structure (CT4a) may include a first contact layer (150, or a first contact region). The first contact structure (CT4a) may be a source contact structure. The first contact layer (150) may be insulated by a first insulating layer (142) and a second insulating layer (144).

[0084] The second contact structure (CT3b) may be formed on the other side gate structure (GE4) and the other side channel layer (128) as shown in FIG. 13. The second contact structure (CT4b) may include a second contact layer (132, or a second contact region). The second contact structure (CT4b) may be a drain contact structure. The second contact layer (132) may be insulated by the first insulating layer (142).

[0085] A bit line (134) and a bit line capping layer (136) may be formed on the second contact layer (132). The second contact layer (132), the bit line (134), and the bit line capping layer (136) may constitute a bit line structure (130). The second contact layer (132) may include polysilicon, and the bit line (134) may include a metallic material. The bit line capping layer (136) may include an insulating material such as silicon nitride or silicon oxynitride.

[0086] The semiconductor device (100) described above can improve the performance of the transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics). Additionally, the semiconductor device (100) may have a capacitor structure (CS) formed on the second insulating layer (144). The capacitor structure (CS) may include a lower electrode (LE) electrically connected to the first contact layer (150), a dielectric layer (DI) conformally covering the lower electrode (LE), and an upper electrode (UE) on the dielectric layer (DI). An etching stop layer (160) having an opening (160T) may be formed on the second insulating layer (144), and the bottom portion of the lower electrode (LE) may be disposed within the opening (160T) of the etching stop layer (160).

[0087] FIG. 15 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention, and FIG. 16 is a cross-sectional view along X-X' of FIG. 15.

[0088] Specifically, the semiconductor device (200) may be nearly identical to the semiconductor device (10) of FIG. 1, except that the channel layer (235) is formed in a U-shaped structure on the substrate (201) and further includes a capacitor structure (298). In FIG. 15 and FIG. 16, details identical to those in FIG. 1 are briefly described or omitted.

[0089] The semiconductor device (200) may include a vertical channel transistor. The vertical channel transistor (VCT) may have a structure in which the channel length of the channel layer (235) extends vertically from the substrate (201), i.e., along the Z direction. The semiconductor device (200) may be a memory device including a vertical channel transistor. The semiconductor device (200) may be a DRAM device.

[0090] As illustrated in FIG. 15, the semiconductor device (200) may have a first conductive line (ML1) including a bit line (204) extended in a first direction (X direction), and a second conductive line (ML2) including a gate electrode (250) extended in a second direction (Y direction) perpendicular to the first direction.

[0091] As described below, the bit line (204) may be a second contact structure (CT5b), and the gate electrode (250) may be included in the gate structure (GE5). The first conductive line (ML1) and the second conductive line (ML2) may use the same material as described in FIG. 12.

[0092] The semiconductor device (200) may have a first vertical channel transistor (VCT1) placed on one side of the second conductive line (ML2) and a second vertical channel transistor (VCT2) placed on the other side of the second conductive line (ML2). A gate insulating layer (244) may be placed on both sides of the gate electrode (250).

[0093] A first contact structure (CT5a) may be disposed on the channel layers (235) on both sides of the gate electrode (250). The first contact structure (CT5a) may include a single first contact layer (228). A lower electrode (292) of a capacitor structure (298 in FIG. 16) may be disposed on the first contact structure (CT5a).

[0094] As illustrated in FIG. 16, the semiconductor device (200) may include a substrate (201), a first insulating layer (202), a bit line (204), a second insulating layer (206), a channel layer (235), a gate structure (GE5), a third insulating layer (251), a first contact structure (CT5a), and a second contact structure (CT5b).

[0095] The substrate (201) may be a silicon substrate. A first insulating layer (202) and a bit line (204) may be formed on the substrate (201). A second insulating layer (206) may be formed on the bit line (204). The first insulating layer (202) and the second insulating layer (206) may be formed as silicon oxide layers. A U-shaped trench (208) may be formed within the second insulating layer (206).

[0096] The channel layer (235) may be formed inside the U-shaped trench (208) within the second insulating layer (206). In other words, the channel layer (235) may be formed inside the trench (208). The channel layer (235) may be formed on the inner wall of the trench (208). The channel layer (235) may be formed on the bottom (208a), one side wall (208b), and the other side wall (208c) of the trench (208).

[0097] The channel layer (235) may be formed of the same material as the channel layer (14) of FIG. 1. For example, the channel layer (235) may contain indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In some embodiments, the channel layer (235) is In x Ga y Zn z O(IGZO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1. The gate insulating layer (224) can be formed on the channel layer (128) inside the trench (208).

[0098] A gate electrode (250) may be formed on a gate insulating layer (224) on the upper side walls of a trench (208). A third insulating layer (251) may be formed between the gate electrodes (250) within the trench (208). The third insulating layer (251) may be formed as a silicon oxide layer. The gate electrodes (250) may be separated from each other within the trench (208).

[0099] The gate structure (GE5) may include a gate insulating layer (224) and a gate electrode (250). The gate insulating layer (224) and the gate electrode (250) may each be formed of the same material as the gate insulating layer (22) and the gate electrode (26) of FIG. 1.

[0100] As illustrated in FIG. 16, the channel layer (235) may include a first region (235a) in contact with the gate structure (GE5), a third region (235c) in contact with the gate structure (GE5), and a second region (235b) located between the first region (235a) and the third region (235c). As illustrated in FIG. 16, the second region (235b) may be thicker than the first region (235a) and the third region (235c).

[0101] The first region (235a), the second region (235b), and the third region (235c) may correspond to the first region (14a), the second region (14b), and the third region (14c) of FIG. 1, respectively. That is, the first region (235a) and the third region (235c) are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms. The second region (235b) is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms.

[0102] The first contact structure (CT5a) may be in contact with the channel layer (235) on one side of the gate structure (GE5) in the vertical direction (Z direction). The first contact structure (CT5a) may include a single first contact layer (228, or first contact region). The first contact structure (CT5a) may be a source contact structure. The first contact structure (CT5a) may be insulated by a second insulating layer (206) and a third insulating layer (251).

[0103] The second contact structure (CT5b) can be formed by contacting the channel layer (235) on the other side of the gate structure (GE5) in a vertical direction (Z direction). The second contact structure (CT5b) can be composed of a bit line (204). The second contact structure (CT5b) can be a drain contact structure.

[0104] The semiconductor device (200) described above can improve the performance of the transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics). Additionally, the semiconductor device (200) may further form a capacitor structure (298) on the first vertical channel transistor (VCT1) and the second vertical channel transistor (VCT2). The capacitor structure (298) may include a lower electrode (292), a dielectric layer (294), and an upper electrode (296). The lower electrode (292) may be formed as a pillar type extending in a third direction (Z direction), but is not limited thereto.

[0105] FIG. 17 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0106] Specifically, the semiconductor device (200a) may be nearly identical to the semiconductor device (200) of FIGS. 15 and 16, except that the channel layer (235-1) is separated by gate structure (GE5) and a second contact structure (CT5b) is formed on the bit line (204). In FIG. 17, the same content as in FIGS. 15 and 16 is briefly described or omitted.

[0107] The semiconductor device (200a) may include a bit line (204), a second insulating layer (206), a channel layer (235-1), a gate structure (GE5), a fourth insulating layer (280), a first contact structure (CT5a), and a second contact structure (CT5b).

[0108] Two channel layers (235-1) may be formed inside the U-shaped trench (208) within the second insulating layer (206). Channel layers (235-1) may be formed on a part of the inner wall of the trench (208). Channel layers (235-1) may be formed on a part of the bottom (208a), one side wall (208b), and the other side wall (208c) of the trench (208). The two channel layers (235-1) may be formed separated by the fourth insulating layer (280).

[0109] The channel layer (235-1) may be formed of the same material as the channel layer (14) of FIG. 1. For example, the channel layer (235-1) may contain indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In some embodiments, the channel layer (14) is In x Ga y Zn z O(IGZO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0110] A gate insulating layer (224) may be formed on a channel layer (235-1) inside a trench (208). Two gate insulating layers (224) may be formed inside the trench (208). The two gate insulating layers (224) may be formed separated by a fourth insulating layer (280).

[0111] A gate electrode (250) may be formed on the gate insulating layer (224) on the upper side walls of the trench (208). Two gate electrodes (250) may be formed inside the trench (208). The two gate electrodes (250) may be formed separated by a fourth insulating layer (280). The gate structure (GE5) may include a gate insulating layer (224) and a gate electrode (250). The gate insulating layer (224) and the gate electrode (250) may each be formed of the same material as the gate insulating layer (22) and the gate electrode (26) of FIG. 1.

[0112] As illustrated in FIG. 16, the channel layer (235-1) may include a first region (235a) in contact with the gate structure (GE5), a third region (235c) in contact with the gate structure (GE5), and a second region (235b) located between the first region (235a) and the third region (235c). The atomic composition of the first region (235a), the second region (235b), and the third region (235c) has been described above and is therefore omitted.

[0113] The first contact structure (CT5a) may be formed on the channel layer (235-1) on one side of the gate structure (GE5) in a vertical direction (Z direction). The first contact structure (CT5a) may include a single first contact layer (228, or first contact region). The first contact structure (CT5a) may be a source contact structure. The first contact structure (CT5a) may be insulated by a second insulating layer (206) and a fourth insulating layer (251).

[0114] The second contact structure (CT5b) may be formed in contact with the channel layer (235) on the other side of the gate structure (GE5) in the vertical direction (Z direction). The second contact structure (CT5b) may include a single second contact layer (205) formed on the bit line (204). The second contact structure (CT5b) may be a drain contact structure.

[0115] The semiconductor device (200) described above can improve the performance of the transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics). Additionally, the semiconductor device (200) may further form a capacitor structure (298) on the first vertical channel transistor (VCT1) and the second vertical channel transistor (VCT2). The capacitor structure (298) may include a lower electrode (292), a dielectric layer (294), and an upper electrode (296).

[0116] FIG. 18 is a layout diagram of a semiconductor device according to one embodiment of the technical concept of the present invention, FIG. 19 is a cross-sectional view along X-X' of FIG. 18, and FIG. 20 is an enlarged view of the "EN6" portion of FIG. 19.

[0117] Specifically, the semiconductor device (300) may be identical to the semiconductor device (10) of FIG. 1 except that the channel layer (322) is composed of sub-channel layers of a nanosheet stacked structure (NSS). In FIG. 12 to 14, the same content as in FIG. 1 is briefly described or omitted.

[0118] The semiconductor device (300) may include a multi-bridge channel transistor (MBC). As illustrated in FIG. 18, the semiconductor device (300) may have an active region (326) arranged in a first direction (X direction) and a gate structure (GE6) including a gate electrode (356) arranged in a second direction (Y direction) perpendicular to the first direction.

[0119] A nanosheet stacked structure (NSS) may be located in the overlapping portion where the active region (326) and the gate electrode (356) intersect. The gate structure (GE6) and the nanosheet stacked structure (NSS) may form a multi-bridge channel transistor (MBC).

[0120] As illustrated in FIG. 19, the semiconductor device (300) may include a substrate (310), an active region (AC), a nanosheet stacking structure (NSS), a first contact structure (CT6a), and a second contact structure (CT6b).

[0121] The active region (326) may be formed on a substrate. The substrate (310) may be a silicon substrate. A nanosheet stacked structure (NSS) may be formed on the active region (326). The nanosheet stacked structure (NSS) may include a plurality of subchannel layers (322-1, 322-2, 322-3, 322-4) arranged apart from each other in a vertical direction (third direction, Z direction) on the surface of the substrate (310).

[0122] The sub-channel layers (322-1, 322-2, 322-3, 322-4) can be named channel layers (322). The sub-channel layers (322-1, 322-2, 322-3, 322-4) can be named nanosheets. The sub-channel layers (322-1, 322-2, 322-3, 322-4) can be formed of the same material as the channel layer (14) of FIG. 1.

[0123] For example, the subchannel layers (322-1, 322-2, 322-3, 322-4) may contain indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms. In some embodiments, the subchannel layers (322-1, 322-2, 322-3, 322-4) are In x Ga y Zn z O(IGZO), X is 0.3 to 0.6, Y is 0.3 to 0.6, and Z is 0.1 to 0.4, and X+Y+Z can be 1.

[0124] Sub-gate structures (GE6S) may be formed between the sub-channel layers (322-1, 322-2, 322-3, 322-4). The sub-gate structures (GE6S) may include sub-gate insulating layers (330) and sub-gate electrodes (356S). The sub-gate insulating layers (330) may be located above and below the sub-channel layers (322-1, 322-2, 322-3, 322-4). The sub-gate electrodes (356S) may be formed on the sub-gate insulating layers (330).

[0125] The sub-gate insulating layers (330) can be formed to surround the sub-gate electrodes (356S). The sub-gate insulating layers (330) and the sub-gate electrodes (356S) can each be formed of the same material as the gate insulating layer (22) and the gate electrode (26) of FIG. 1.

[0126] A first contact structure (CT6a) may be formed on one side of a nanosheet stack structure (NSS), one side of sub-gate structures (GE6S), and one side of a channel layer (322) in a horizontal direction (first direction) on a substrate (310). The first contact structure (CT6a) may include a single first contact layer (360, or first contact region). The first contact structure (CT6a) may be a source contact structure.

[0127] A second contact structure (CT6b) may be formed on the substrate (310) in a horizontal direction (first direction) on the other side of the nanosheet stack structure (NSS), the other side of the sub-gate structures (GE6S), and the other side of the channel layer (322). The second contact structure (CT6b) may include a single second contact layer (361, or second contact region). The second contact structure (CT6b) may be a source contact structure.

[0128] The semiconductor device (300) may include a main gate structure (GE6M) on a nanosheet stacking structure (NSS). The main gate structure (GE6M) may be located on the uppermost sub-channel layer (322-4). The main gate structure (GE6M) may include a main gate insulating layer (364), a barrier layer (366), and a main gate electrode (356M) formed on the uppermost sub-channel layer (322-4). The sub-gate structure (GE6S) and the main gate structure (GE6M) may be referred to as gate structures.

[0129] The main gate insulating layer (364) and the main gate electrode (356M) can each be formed of the same material as the gate insulating layer (22) and the gate electrode (26) of FIG. 1. The main gate structure (GE6M) can be insulated by the insulating layer (362).

[0130] As illustrated in FIG. 20, the semiconductor device (300) may include a first region (322a) in which a channel layer (322), such as a channel layer (322-4), is in contact with a main gate structure (GE6M), a third region (322c) in contact with a main gate structure (GE6M), and a second region (322b) located between the first region (322a) and the third region (322c). As illustrated in FIG. 20, the second region (322b) may be thicker than the first region (322a) and the third region (322c).

[0131] The first region (322a), the second region (322b), and the third region (322c) may correspond to the first region (14a), the second region (14b), and the third region (14c) of FIG. 1, respectively. That is, the first region (322a) and the third region (322c) are configured such that the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms. The second region (322b) is configured such that the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms. A semiconductor device (300) as described above can improve the performance of a transistor, such as leakage characteristics and channel characteristics (i.e., channel-on characteristics).

[0132] FIG. 21 is a block diagram for explaining an electronic system including a semiconductor device according to one embodiment of the technical concept of the present invention.

[0133] Specifically, the electronic system (1000) may include a controller (1010), an input / output device (1020), a memory device (1030, or memory device), and an interface (1040). The system (1000) may be a mobile system or a system that transmits or receives information. In some embodiments, the mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

[0134] The controller (1010) is for controlling an execution program in the electronic system (1000) and may be composed of a microprocessor, a digital signal processor, a microcontroller, or a similar device. The input / output device (1020) may be used to input or output data of the system (1000). The electronic system (1000) may be connected to an external device, such as a personal computer or a network, using the input / output device (1020), and may exchange data with the external device. The input / output device (1020) may be, for example, a keypad, a keyboard, or a display.

[0135] The memory device (1030) may store code and / or data for the operation of the controller (1010) or data processed by the controller (1010). The memory device (1030) and the controller (1010) may include semiconductor devices according to the technical concept of the present invention. The interface (1040) may be a data transmission channel between the system (1000) and another external device. The controller (1010), the input / output device (1020), the memory device (1030), and the interface (1040) may communicate with each other via a bus (1050).

[0136] The electronic system (1000) according to the present embodiment can be used, for example, in a mobile phone, MP3 player, navigation, portable multimedia player (PMP), solid state disk (SSD), or household appliances.

[0137] Although the present invention has been described above with reference to the embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications, substitutions, and equivalent alternative embodiments are possible therefrom. The embodiments described above should be understood as illustrative in all respects and not restrictive. The true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0138] GE1: Gate structure, CT1a: First contact structure, CT1b: Second contact structure, 14: Channel layer, 14a, 14b, 14c: First to third regions, 22: Gate insulating layer, 24: Gate electrode

Claims

Claim 1 A semiconductor device comprising: a channel layer located on the upper surface of a substrate; and a gate structure formed on the channel layer, wherein the channel layer is composed of a single layer of oxide semiconductor material, and the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms, and the channel layer comprises a first region adjacent to the substrate and adjacent to the gate structure, a third region adjacent to the gate structure, and a second region located between the first region and the third region, wherein the first region and the third region are regions in which the atomic composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is a region in which the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms, and the channel layer is formed in a U-shaped structure on the upper surface of the substrate, and the gate structure is embedded within the U-shaped channel layer. Claim 2 A semiconductor device according to claim 1, wherein the channel layer has a composition of gallium (Ga) atoms that continuously increases or decreases in the direction of the first region from the third region, and the channel layer has a composition of indium (In) atoms that continuously increases or decreases in the direction of the first region from the third region. Claim 3 In claim 1, the channel layer is In x Ga y Zn z O(IGZO), In x Ga y Si z O(IGSO), In x Sn y Ga z O(ITGO), or In x Ga y A semiconductor device characterized by being composed of O(IGO). Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 A semiconductor device comprising: a channel layer located on the upper surface of a substrate; a gate structure formed on the channel layer; a first contact structure formed on the channel layer on one side of the gate structure; and a second contact structure formed on the channel layer on the other side of the gate structure, wherein the channel layer is composed of a single layer of oxide semiconductor material, and the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms, and the channel layer comprises a first region adjacent to the substrate and distant from the gate structure, a third region adjacent to the gate structure, and a second region located between the first region and the third region, wherein the first region and the third region are regions in which the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is a region in which the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms, and the channel layer is formed in a U-shaped structure on the upper surface of the substrate, and the gate structure is embedded inside the U-shaped channel layer. Claim 8 In claim 7, the channel layer further comprises zinc (Zn) atoms, In x Ga y Zn z A semiconductor device characterized by being composed of O (IGZO), wherein X is 0.3 to 0.6, Y is 0.3 to 0.6, Z is 0.1 to 0.4, and X+Y+Z is 1. Claim 9 A first conductive line extending in a first direction on a substrate; a second conductive line extending in a second direction perpendicular to the first direction on the substrate; A semiconductor device comprising a transistor located between the first conductive line and the second conductive line, wherein the transistor comprises: a channel layer; a gate insulating layer formed on the channel layer and a gate structure formed on the gate insulating layer and comprising the second conductive line, wherein the channel layer is composed of a single layer of oxide semiconductor material, wherein the channel layer comprises indium (In) atoms, gallium (Ga) atoms, and oxygen (O) atoms, wherein the channel layer comprises a first region adjacent to the gate electrode, a third region adjacent to the gate electrode, and a second region located between the first region and the third region, wherein the first region and the third region are regions in which the composition of gallium (Ga) atoms is higher than the composition of indium (In) atoms, and the second region is a region in which the composition of indium (In) atoms is higher than the composition of gallium (Ga) atoms, and wherein the channel layer is formed in a U-shaped structure on the upper surface of the substrate, and wherein the gate structure is embedded within the U-shaped channel layer. Claim 10 delete

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