Method of manufacturing semiconductor device

Abstract

The technical concept of the present invention provides a method for manufacturing a semiconductor device having a vertical stacking structure, wherein a carbon layer is selectively deposited on the sidewall of a substrate mold before depositing a sacrificial metal film to prevent defects or substrate pitting phenomena that may occur on the substrate.

Description

Technology Field

[0001] The technical concept of the present invention relates to a method for manufacturing a semiconductor device. More specifically, it relates to a method for manufacturing a semiconductor device capable of improving substrate gouging phenomena of the semiconductor device. Background Technology

[0002] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data, and accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of a semiconductor device, a semiconductor device including a vertical memory element equipped with memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a method for manufacturing a semiconductor device that can prevent substrate pitting caused by a chemical reaction between the sacrificial film and the substrate when an etching process and a process of filling a sacrificial film are performed to manufacture a multi-stack structure.

[0004] Furthermore, the problems that the technical concept of the present invention aims to solve are not limited to those mentioned above, and other problems can be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0005] To achieve a technical objective, the present invention provides a method for manufacturing a semiconductor device as follows.

[0006] To solve the above-mentioned problem, the technical concept of the present invention comprises the steps of: forming a first stack by alternately stacking a plurality of first films and a plurality of second films one layer at a time on a substrate; forming a first vertical hole penetrating the first stack in a vertical direction; depositing a first carbon layer on the inner sidewall of the first vertical hole so as to be in contact with the portions of the plurality of first films and the plurality of second films exposed through the first vertical hole; forming a first sacrificial metal film that fills the first vertical hole on the first carbon layer; forming a second stack on the first stack by alternately stacking the plurality of first films and the plurality of second films one layer at a time; forming a second vertical hole penetrating the second stack in a vertical direction; depositing a second carbon layer on the inner sidewall of the second vertical hole so as to be in contact with the portions of the plurality of first films and the plurality of second films exposed through the second vertical hole; and forming a second sacrificial metal film that fills the second vertical hole on the second carbon layer. A method for manufacturing a semiconductor device is provided, comprising: a step of forming a third stack on the second stack; a step of forming a third vertical hole penetrating the third stack in a vertical direction; and a step of removing the first sacrificial metal film, the second sacrificial metal film, the first carbon layer, and the second carbon layer.

[0007] To solve the above-mentioned problem, the technical concept of the present invention comprises the steps of: forming a first stack by alternately stacking a plurality of first films and a plurality of second films one layer at a time on a substrate; forming a first vertical hole penetrating the first stack in a vertical direction; depositing a first carbon layer on the inner sidewall of the first vertical hole so as to be in contact with the portions of the plurality of first films and the plurality of second films exposed through the first vertical hole; forming a first sacrificial metal film that fills the first vertical hole on the first carbon layer; forming a second stack on the first stack by alternately stacking the plurality of first films and the plurality of second films one layer at a time; forming a second vertical hole penetrating the second stack in a vertical direction; depositing a second carbon layer on the inner sidewall of the second vertical hole so as to be in contact with the portions of the plurality of first films and the plurality of second films exposed through the second vertical hole; and forming a second sacrificial metal film that fills the second vertical hole on the second carbon layer. A method for manufacturing a semiconductor device is provided, comprising: a step of forming a third stack by alternately stacking a plurality of first films and a plurality of second films on the second stack; a step of forming a third vertical hole penetrating the third stack in a vertical direction; and a step of removing the first sacrificial metal film, the second sacrificial metal film, the first carbon layer, and the second carbon layer.

[0008] To solve the above-mentioned problem, the technical concept of the present invention comprises: a process cycle comprising the steps of: forming a film stack composed of a plurality of alternating layers of a silicon oxide film and a silicon nitride film on a substrate; forming a plurality of openings extending to a depth from the uppermost surface to the lowermost surface of the film stack; selectively depositing a carbon layer having a thickness in the range of 5 nm to 15 nm only on the silicon nitride film of the film stack on the surface of the film stack, and on the lowermost surface of the opening and the inner sidewalls of the plurality of openings; and filling the plurality of openings with a sacrificial metal film; preparing a plurality of features by repeating the process cycle once on the sacrificial metal film; forming a silicon dioxide stack on some of the plurality of features, and forming a first feature by forming an opening extending to a depth from the uppermost surface to the lowermost surface of the silicon dioxide stack. A method for manufacturing a semiconductor device is provided, comprising: a step of forming a new film stack composed of a plurality of alternating layers of silicon oxide film and silicon nitride film on the remaining feature among the plurality of features, and forming a second feature by forming an opening extending to a depth from the top surface to the bottom surface of the new film stack; and a strip process step of simultaneously removing a sacrificial metal film and a carbon layer formed on the first feature and the second feature. Effects of the invention

[0009] A method for manufacturing a semiconductor device according to the technical concept of the present invention can prevent pitting phenomena that may occur on a substrate by depositing a carbon (C) layer on a substrate before depositing a sacrificial metal film in a High Aspect Ratio Contact (HARC) etching process.

[0010] In addition, the method for manufacturing a semiconductor device according to the technical concept of the present invention can prevent the formation of peelable defects or reactive films on the substrate by selectively depositing a carbon layer only on the sidewalls of the substrate mold. Brief explanation of the drawing

[0011] FIG. 1 is a schematic plan view of a semiconductor device that can be obtained according to a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 2 is a schematic perspective view of some configurations of a memory cell array region included in a chip region of a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 3 is a schematic plan view of some regions of a chip area included in a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 4 and FIGS. 5a to 5d are drawings for explaining in more detail the configurations of a chip region of a semiconductor device according to embodiments of the technical concept of the present invention, FIG. 4 is a schematic plan view of some components of a memory cell block of the chip region, FIG. 5a is a cross-sectional view along the Y1 - Y1' line of FIG. 4, FIG. 5b is a cross-sectional view along the X1 - X1' line of FIG. 4, FIG. 5c is an enlarged cross-sectional view along the X2 - X2' line of FIG. 4, and FIG. 5d is an enlarged cross-sectional view of some components included in the area indicated as "EX1" in FIG. 5a. FIG. 6 is a cross-sectional view illustrating a partial configuration of a scribe lane region of a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 7a, 7b, and 7c are cross-sectional views illustrating exemplary configurations in the chip region of a semiconductor device according to other embodiments of the technical concept of the present invention. FIGS. 8a to 15c are cross-sectional views for explaining a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention, wherein FIGS. 8a, 11a, 12a, 13a, 14a, and 15a are cross-sectional views according to the process sequence of some components of a portion corresponding to the Y1-Y1' line cross-section of FIG. 4, FIGS. 8b, 9a, 10a, 11b, 12b, 13b, 14b, and 15b are cross-sectional views according to the process sequence of some components of a portion corresponding to the X1-X1' line cross-section of FIG. 4, and FIGS. 8c, 9b, 10b, 11c, 12c, 13c, 14c, and 15c are cross-sectional views according to the process sequence of some components of a portion corresponding to the X2-X2' line cross-section of FIG. 4, and FIGS. 10c and FIGS. 11d are cross-sectional views according to the process sequence of some components in the scribe lane area. FIG. 16 is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. FIG. 17 is a schematic perspective view of an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. FIG. 18 is a diagram illustrating the configuration along the II-II' line cross-section of FIG. 17 in more detail, and is a cross-sectional view schematically showing semiconductor packages according to an exemplary embodiment of the present invention. Specific details for implementing the invention

[0012] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0013] The embodiments are subject to various modifications and may have various examples; therefore, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the scope of specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the scope of the disclosed concept and technology. In describing the embodiments, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may obscure the gist of the matter.

[0014] FIG. 1 is a schematic plan view of a semiconductor device (100) that can be obtained according to a method for manufacturing a semiconductor device according to one embodiment of the technical concept of the present invention.

[0015] Referring to FIG. 1, a semiconductor device (100) comprises a substrate (110) having a plurality of chip regions (CR) and a scribe lane region (SLR) surrounding each of them. The plurality of chip regions (CR) may be arranged in a matrix form on the substrate (110). The scribe lane region (SLR) may include a cutting region for individualizing the plurality of chip regions (CR).

[0016] A plurality of chip regions (CR) may each be high-density regions with a relatively high pattern density, and scribe lane regions (SLR) may be low-density regions with a relatively low pattern density. A plurality of chip regions (CR) may include a memory cell array region of a semiconductor memory device, a peripheral circuit region including circuits configured to be electrically connected to the memory cells included in the memory cell array region, and a core region. In exemplary embodiments, a non-volatile memory cell array, such as a vertical NAND flash memory, may be formed in the memory cell array region. A plurality of patterns having a relatively small width may be spaced apart from each other to form a regular arrangement and may be repeatedly formed at a relatively small pitch.

[0017] FIG. 2 is a schematic perspective view of some configurations of memory cell array regions included in each of the plurality of chip regions (CR) exemplified in FIG. 1.

[0018] Referring to FIG. 2, the chip region (CR) of the semiconductor device (100) may include a cell array structure (CAS). The cell array structure (CAS) may include a plurality of tiles (24). Each of the plurality of tiles (24) may include a plurality of memory cell blocks (BLK1, BLK2, , BLKp). Each of the plurality of memory cell blocks (BLK1, BLK2, , BLKp) may include memory cells arranged in three dimensions.

[0019] FIG. 3 is a schematic plan view of a portion of a chip region (CR) included in a semiconductor device (100) according to embodiments of the technical concept of the present invention.

[0020] Referring to FIG. 3, the cell array structure (CAS) in the chip region (CR) may include a substrate (110) and a plurality of memory cell blocks (BLK1, BLK2, , BLKp-1, BLKp) disposed on the substrate (110).

[0021] A cell array structure (CAS) may include a memory cell region (MEC) and connection regions (CON) disposed on both sides of the memory cell region (MEC) in a first horizontal direction (X direction). A plurality of memory cell blocks (BLK1, BLK2, BLKp-1, BLKp) may each include a memory stack structure (MST) extending in a first horizontal direction (X direction) across the memory cell region (MEC) and the connection region (CON). The memory stack structure (MST) may include a plurality of gate lines (130) stacked to overlap each other in a vertical direction (Z direction) in the memory cell region (MEC) and the connection region (CON) on the substrate (110). In each of the plurality of memory stack structures (MST), the plurality of gate lines (130) may form a gate stack (GS). A plurality of memory stack structures (MSTs) may each include a plurality of memory stacks that are arranged at different vertical levels in the vertical direction (Z direction) and overlap each other along the vertical direction (Z direction). Each of the plurality of memory stacks may include a plurality of gate lines (130) that overlap each other along the vertical direction (Z direction). In exemplary embodiments, the plurality of memory stacks may each include 48, 64, or 96 gate lines (130) stacked to overlap each other along the vertical direction (Z direction), but are not limited thereto.

[0022] In exemplary embodiments, the area of ​​a plurality of gate lines (130) included in a plurality of memory stack structures (MST) in the XY plane may gradually decrease as the distance from the substrate (110) increases. The central portion of each of the plurality of gate lines (130) that overlap each other in the vertical direction (Z direction) may form a memory cell region (MEC), and the edge portion of each of the plurality of gate lines (130) may form a connection region (CON).

[0023] A plurality of word line cut structures (WLC) that extend in a first horizontal direction (X direction) from a memory cell region (MEC) and a connection region (CON) may be disposed on the substrate (110). The plurality of word line cut structures (WLC) may be disposed spaced apart from each other along a second horizontal direction (Y direction). A plurality of memory cell blocks (BLK1, BLK2, BLKp-1, BLKp) may be disposed one by one between each of the plurality of word line cut structures (WLC).

[0024] FIGS. 4 and FIGS. 5a through 5d are drawings for explaining in detail the configurations of the chip region (CR) of the semiconductor device (100). More specifically, FIG. 4 is a schematic plan view of some components of the memory cell blocks (BLK11, BLK12) of the chip region (CR). FIG. 5a is a cross-sectional view along the Y1 - Y1' line of FIG. 4. FIG. 5b is a cross-sectional view along the X1 - X1' line of FIG. 4. FIG. 5c is an enlarged cross-sectional view along the X2 - X2' line of FIG. 4. FIG. 5d is an enlarged cross-sectional view of some components included in the area marked "EX1" in FIG. 5a. The memory cell blocks (BLK11, BLK12) exemplified in FIG. 4 can each constitute any one of the plurality of memory cell blocks (BLK1, BLK2, , BLKp-1, BLKp) exemplified in FIG. 3.

[0025] Referring to FIG. 4 and FIG. 5a through 5d, the chip region (CR) of the semiconductor device (100) may include a memory cell region (MEC) and a connection region (CON) on the substrate (110). In the memory cell region (MEC) and the connection region (CON), a first stack (STA) disposed at a first vertical level on the substrate (110), a second stack (STB) disposed at a second vertical level higher than the first vertical level on the substrate (110), and a third stack (STC) disposed at a third vertical level higher than the second vertical level on the substrate (110) may be disposed. As used herein, the term "vertical level" refers to a distance along a vertical direction (Z direction or -Z direction) from the upper surface of the substrate (110).

[0026] The first stack (STA), the second stack (STB), and the third stack (STC) may each include a plurality of gate lines (130) that overlap each other along the vertical direction (Z direction) in the memory cell region (MEC), and a stepped connection portion (STP) having a plurality of conductive pad portions (130A) disposed in the connection region (CON) and integrally connected to the plurality of gate lines (130). The first stack (STA), the second stack (STB), and the third stack (STC) may form a cell array structure (CAS) as illustrated in FIG. 3.

[0027] As illustrated in FIG. 5a, a first conductive plate (114) and a second conductive plate (118) may be disposed on a substrate (110) in a memory cell region (MEC), and as illustrated in FIG. 5b and FIG. 5c, an insulating plate (112) and a second conductive plate (118) may be disposed on a substrate (110) in a connection region (CON). A memory stack structure (MST) comprising a first stack (STA), a second stack (STB), and a third stack (STC) may be disposed on the second conductive plate (118) in the memory cell region (MEC) and the connection region (CON). In exemplary embodiments, the first conductive plate (114) and the second conductive plate (118) in the memory cell region (MEC) may function as source regions that supply current to vertical memory cells included in a cell array structure (CAS).

[0028] In exemplary embodiments, the substrate (110) may be made of a semiconductor material such as polysilicon. The first conductive plate (114) and the second conductive plate (118) may each be made of a doped polysilicon film, a metal film, or a combination thereof. The metal film may be made of tungsten (W), but is not limited thereto. In the memory stack structure (MST), a plurality of gate lines (130) may extend in a horizontal direction parallel to each other and overlap each other in a vertical direction (Z direction). The plurality of gate lines (130) may each be made of a metal, a metal silicide, an impurity-doped semiconductor, or a combination thereof. For example, the plurality of gate lines (130) may each include a metal such as tungsten, nickel, cobalt, tantalum, etc., a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, etc., doped polysilicon, or a combination thereof.

[0029] An insulating film (132) may be interposed between the second conductive plate (118) and the plurality of gate lines (130), and between each of the plurality of gate lines (130). In each of the first stack (STA), the second stack (STB), and the third stack (STC), the uppermost gate line (130) among the plurality of gate lines (130) may be covered with an insulating film (132). The insulating film (132) may be made of silicon oxide.

[0030] As illustrated in FIGS. 5b and 5c, in the connection region (CON), the edge portions of each of the plurality of gate lines (130), plurality of conductive pad portions (130A), and plurality of insulating films (132) included in the first stack (STA) may be covered by a lower insulating block (133). In the connection region (CON), the edge portions of each of the plurality of gate lines (130), plurality of conductive pad portions (130A), and plurality of insulating films (132) included in the second stack (STB) may be covered by an intermediate insulating block (137). In the connection region (CON), the third stack (STC) may be covered by an upper insulating block (137A). Although not shown in the drawings, a plurality of gate lines (130) and a conductive pad portion (130A) at one end of the plurality of gate lines (130) may also be formed in the third stack (STC). The lower insulation block (133), the middle insulation block (137), and the upper insulation block (137A) can each be made of a silicon oxide film.

[0031] Between the first stack (STA) and the second stack (STB), a first intermediate insulating film (135) and a second intermediate insulating film (136) may be sequentially stacked on the first stack (STA). The first intermediate insulating film (135) and the second intermediate insulating film (136) may each be made of a silicon oxide film. Between the second stack (STB) and the third stack (STC), a first intermediate insulating film (135) and a second intermediate insulating film (136) may be sequentially stacked on the second stack (STB). The first intermediate insulating film (135) and the second intermediate insulating film (136) may each be made of a silicon oxide film.

[0032] As illustrated in FIGS. 4 and 5a, a plurality of word line cut structures (WLC) may be extended along a first horizontal direction (X direction) on a substrate (110) in a memory cell region (MEC) and a connection region (CON). The width of each of the plurality of gate lines (130) included in the memory cell blocks (BLK11, BLK12) in the second horizontal direction (Y direction) may be limited by the plurality of word line cut structures (WLC).

[0033] A plurality of word line cut structures (WLCs) may each be composed of an insulating structure. In exemplary embodiments, the insulating structure may be composed of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric material. For example, the insulating structure may be composed of a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, a SiCN film, or a combination thereof. In other exemplary embodiments, at least a portion of the insulating structure may be composed of an air gap. As used herein, the term "air" refers to the atmosphere or other gases that may be present during the manufacturing process.

[0034] A plurality of gate lines (130) may be stacked on a second conductive plate (118) between two adjacent word line cut structures (WLC) so as to overlap each other in a vertical direction (Z direction). The plurality of gate lines (130) may include a ground selection line, a plurality of word lines, and a string selection line.

[0035] In a plurality of gate lines (130), the upper two gate lines (130) can each be separated in a second horizontal direction (Y direction) with a string select line cut structure (SSLC) in between. The two gate lines (130) separated from each other with a string select line cut structure (SSLC) in between can each form a string select line. FIG. 5a illustrates a case where one string select line cut structure (SSLC) is formed in one gate stack (GS) (see FIG. 3) defined by two adjacent string select line cut structures (SSLC), but the technical concept of the present invention is not limited to what is illustrated in FIG. 5a. For example, at least two string select line cut structures (SSLC) may be formed in one gate stack (GS). The string select line cut structure (SSLC) may be filled with an insulating film. In exemplary embodiments, the string select line cut structure (SSLC) may include an insulating film made of an oxide film, a nitride film, or a combination thereof. In exemplary embodiments, at least a portion of the string select line cut structure (SSLC) may be made of an air gap.

[0036] As illustrated in FIG. 5a, a plurality of channel structures (140) on a substrate (110) in a memory cell region (MEC) may be extended in a vertical direction (Z direction) through a plurality of gate lines (130), a plurality of insulating films (132), a first intermediate insulating film (135), a second intermediate insulating film (136), a second conductive plate (118), and a first conductive plate (114). The plurality of channel structures (140) may be arranged spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction) at a predetermined interval. Each of the plurality of channel structures (140) may include a gate dielectric film (142), a channel region (144), a buried insulating film (146), and a drain region (148). In this specification, each of the plurality of channel structures (140) may be referred to as a plug structure.

[0037] As illustrated in FIG. 5d, the gate dielectric film (142) may include a tunneling dielectric film (TD), a charge storage film (CS), and a blocking dielectric film (BD) formed sequentially from the channel region (144) toward the gate line (130). The relative thicknesses of the tunneling dielectric film (TD), the charge storage film (CS), and the blocking dielectric film (BD) are not limited to those illustrated in FIG. 5d and may vary in many ways.

[0038] The tunneling dielectric film (TD) may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film (CS) is a region in which electrons passing through the tunneling dielectric film (TD) from the channel region (144) can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric film (BD) may be made of silicon oxide, silicon nitride, or a metal oxide with a dielectric constant greater than that of silicon oxide. The metal oxide may be made of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0039] As illustrated in FIGS. 5a and 5d, the first conductive plate (114) may penetrate a portion of the gate dielectric film (142) in a horizontal direction (X direction and / or Y direction) and come into contact with the channel region (144). The thickness (Z direction size) of the portion of the first conductive plate (114) that overlaps vertically with the gate dielectric film (142) may be greater than the thickness (Z direction size) of the portion of the first conductive plate (114) that overlaps vertically with the second conductive plate (118). The gate dielectric film (142) may include a portion covering the sidewall of the channel region (144) at a level higher than the first conductive plate (114) and a portion covering the bottom surface of the channel region (144) at a level lower than the first conductive plate (114). The channel region (144) may be spaced apart from the substrate (110) with the lowest portion of the gate dielectric film (142) in between. The side wall of the channel area (144) may be configured to be in contact with the first conductive plate (114) and electrically connected to the first conductive plate (114).

[0040] As illustrated in FIGS. 5a and 5d, the channel region (144) may have a cylindrical shape. The channel region (144) may comprise doped polysilicon or undoped polysilicon. A buried insulating film (146) may fill the internal space of the channel region (144). The buried insulating film (146) may be made of an insulating material. For example, the buried insulating film (146) may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In exemplary embodiments, the buried insulating film (146) may be omitted. In this case, the channel region (144) may have a pillar structure without an internal space.

[0041] As illustrated in FIG. 5a, a plurality of drain regions (148) may be mutually insulated by a first upper insulating film (UL1) covering a third stack (STC). A plurality of drain regions (148) may be made of a doped polysilicon film.

[0042] As illustrated in FIGS. 5a to 5c, a second upper insulating film (UL2) and a third upper insulating film (UL3) may be formed sequentially on a plurality of channel structures (140) and a first upper insulating film (UL1) in a memory cell region (MEC) and a connection region (CON). The first upper insulating film (UL1), the second upper insulating film (UL2), and the third upper insulating film (UL3) may each be made of an oxide film, a nitride film, or a combination thereof.

[0043] As illustrated in FIGS. 4 and 5a, a plurality of bit lines (BL) may be disposed on the second upper insulating film (UL2) of the memory stack structure (MST) in the memory cell region (MEC) of the chip region (CR). The plurality of bit lines (BL) may be extended parallel to each other along the second horizontal direction (Y direction). The space between each of the plurality of bit lines (BL) may be filled with a third upper insulating film (UL3) (see FIGS. 5b and 5c). The drain region (148) of each of the plurality of channel structures (140) may be connected to the bit lines (BL) through a contact plug (176) that penetrates the second upper insulating film (UL2).

[0044] As illustrated in FIGS. 5b and 5c, an insulating plate (112) and a second conductive plate (118) may be sequentially stacked on a substrate (110) in the connection region (CON) of the chip region (CR). The insulating plate (112) may have a multilayer structure comprising a first insulating film (112A), a second insulating film (112B), and a third insulating film (112C) sequentially stacked on the substrate (110). In exemplary embodiments, the first insulating film (112A) and the third insulating film (112C) may be made of silicon oxide, and the second insulating film (112B) may be made of silicon nitride.

[0045] In the connection region (CON), a conductive pad portion (130A) having a greater thickness in the vertical direction (Z direction) than other parts of the gate line (130) may be formed at one end of each of the plurality of gate lines (130) included in the first stack (STA) and the second stack (STB). Although not shown in the drawing, a plurality of gate lines (130) and a conductive pad portion (130A) at one end of the plurality of gate lines (130) may also be formed in the third stack (STC). The conductive pad portion (130A) may be integrally connected to the edge portion furthest from the memory cell region (MEC) among the gate lines (130). In FIGS. 5a and 5b, only a conductive pad portion (130A) connected to one end of some gate lines (130) among the plurality of gate lines (130) is shown, but other conductive pad portions (130A) integrally connected to other gate lines (130) may be arranged in other parts not visible in FIGS. 5b and 5c.

[0046] As illustrated in FIGS. 4 and 5c, a plurality of memory cell contacts (MC) and a plurality of insulating support structures (SP) may be disposed in the connection area (CON). Each of the plurality of memory cell contacts (MC) may be configured to be electrically connected to one of the plurality of conductive pad portions (130A) selected from among the plurality of conductive pad portions (130A) included in the first stack (STA) and the second stack (STB). The plurality of insulating support structures (SP) may penetrate the first stack (STA), the second stack (STB), and the third stack (STC) in a vertical direction (Z direction) to support each of the first stack (STA), the second stack (STB), and the third stack (STC) in the connection area (CON). In this specification, the plurality of memory cell contacts (MC) and the plurality of insulating support structures (SP) may each be referred to as plug structures.

[0047] Some of the memory cell contacts (MC) selected from among the plurality of memory cell contacts (MC) may be positioned at a location spaced apart in the horizontal direction (X direction in FIG. 5a) from the stepped connection part (STP) included in the second stack (STB). Some of the memory cell contacts (MC) among the plurality of memory cell contacts (MC) may be configured to penetrate in the vertical direction (Z direction) the stepped connection part (STP), lower insulating block (133), first intermediate insulating film (135), second intermediate insulating film (136), and upper insulating block (137) included in the first stack (STA), and to be electrically connected to one of the conductive pad parts (130A) selected from among the plurality of conductive pad parts (130A) included in the first stack (STA).

[0048] Among the multiple memory cell contacts (MC), other selected memory cell contacts (MC) can each penetrate the stepped connection portion (STP) included in the second stack (STB) in the vertical direction (Z direction) and be configured to be electrically connected to one selected conductive pad portion (130A) among the multiple conductive pad portions (130A) included in the second stack (STB).

[0049] As illustrated in FIG. 5c, a plurality of memory cell contacts (MC) can each penetrate at least a portion of a plurality of gate lines (130) and a plurality of insulating films (132). A plurality of memory cell contacts (MC) can each be placed within a hole penetrating at least one of a plurality of gate lines (130).

[0050] A plurality of insulating support structures (SP) (see FIG. 4) can each penetrate at least a portion of a plurality of gate lines (130) and a plurality of insulating films (132), similar to a plurality of memory cell contacts (MC). A plurality of insulating support structures (SP) can each be placed within a hole penetrating at least one of a plurality of gate lines (130).

[0051] Each of the multiple memory cell contacts (MC) is connected to one selected gate line (130) among the multiple gate lines (130), and may not be connected to any other gate lines (130) other than the selected gate line (130). Each of the multiple memory cell contacts (MC) contacts the conductive pad portion (130A) of one selected gate line (130) among the multiple gate lines (130), and may be connected to the selected gate line (130) through the conductive pad portion (130A).

[0052] In exemplary embodiments, a plurality of memory cell contacts (MC) may each be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof, but are not limited thereto. A plurality of insulating support structures (SP) may each be made of silicon oxide, but are not limited thereto.

[0053] A plurality of memory cell contacts (MC) may each be spaced horizontally apart from other gate lines (130) except for the selected gate line (130). In the first stack (STA), a first insulating ring (152A) may be disposed between each of the plurality of memory cell contacts (MC) and other gate lines (130) not connected thereto. In the second stack (STB), a second insulating ring (152B) may be disposed between each of the plurality of memory cell contacts (MC) and other gate lines (130) not connected thereto. In exemplary embodiments, the first insulating ring (152A) and the second insulating ring (152B) may be made of silicon oxide, but are not limited thereto.

[0054] As illustrated in FIGS. 4 and 5b, a plurality of dummy channel structures (140D) may be disposed in the connection area (CON). The plurality of dummy channel structures (140D) may include a plurality of dummy channel structures (140D) that penetrate in the vertical direction (Z direction) a stepped connection part (STP) included in the first stack (STA), and a plurality of dummy channel structures (140D) that penetrate in the vertical direction (Z direction) a stepped connection part (STP) and an intermediate insulating film (135, 136) included in each of the first stack (STA) and the second stack (STB). FIG. 5b illustrates a case where a plurality of dummy channel structures (140D) penetrate in the vertical direction (Z direction) a conductive pad part (130A) included in the stepped connection part (STP), but the technical concept of the present invention is not limited to that illustrated in FIG. 5b. For example, at least some of the plurality of dummy structures (140D) may penetrate in the vertical direction (Z direction) a portion of the gate line (130) that is spaced horizontally from the conductive pad portion (130A) in the connection area (CON). In this specification, the plurality of dummy channel structures (140D) may each be referred to as plug structures. Some of the dummy channel structures (140D) selected from the plurality of dummy channel structures (140D) may penetrate in the vertical direction (Z direction) the stepped connection portion (STP), lower insulation block (133), first intermediate insulation film (135), second intermediate insulation film (136), intermediate insulation block (137), and upper insulation block (137A) included in the first stack (STA). Among the multiple dummy channel structures (140D), other dummy channel structures (140D) selected can penetrate the stepped connection (STP), the first intermediate insulating layer (135), the second intermediate insulating layer (136) included in the first stack (STA), the stepped connection (STP), the intermediate insulating block (137), and the upper insulating block (137A) included in the second stack (STB) in the vertical direction (Z direction).

[0055] In the connection area (CON), a plurality of dummy channel structures (140D) may be arranged spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction) at a predetermined interval. Each of the plurality of dummy channel structures (140D) may include a gate dielectric film (142), a channel region (144), a buried insulating film (146), and a drain region (148), similar to the channel structure (140) placed in the memory cell region (MEC). However, the planar size of each of the plurality of dummy channel structures (140D) may be larger than the planar size of the channel structure (140). The number and arrangement shape of the plurality of dummy channel structures (140D) exemplified in FIG. 4 are merely examples, and the technical concept of the present invention is not limited thereto. In the connection area (CON), the plurality of dummy channel structures (140D) may be arranged in various arrangements at various locations selected in the memory stack structure (MST).

[0056] As illustrated in FIGS. 5b and 5c, the upper insulating block (137A) in the connection area (CON) may be covered with a first upper insulating film (UL1). A plurality of dummy channel structures (140D) in the connection area (CON) may be covered with a second upper insulating film (UL2).

[0057] As illustrated in FIGS. 4 and 5c, a conductive plate contact (164) may be disposed in the connection area (CON). The conductive plate contact (164) may extend vertically (Z direction) to the substrate (110) through the upper insulating block (137A), the intermediate insulating block (137), the intermediate insulating film (135, 136), the lower insulating block (133), the second conductive plate (118), and the insulating plate (112). The sidewalls of the conductive plate contact (164) may be covered with an insulating spacer (162). The insulating spacer (162) may be made of a silicon oxide film.

[0058] A plurality of memory cell contacts (MC) and conductive plate contacts (164) can each be connected to one of a plurality of upper wiring layers (UML) through a contact plug (172) penetrating a first upper insulating film (UL1) and a second upper insulating film (UL2). The plurality of upper wiring layers (UML) can be placed at the same vertical level as a plurality of bit lines (BL) placed in a memory cell region (MEC). The space between each of the plurality of upper wiring layers (UML) can be filled with a third upper insulating film (UL3).

[0059] The upper surface of each of the plurality of memory cell contacts (MC), the plurality of insulating support structures (SP), and the conductive plate contact (164) may extend at approximately the same vertical level. In exemplary embodiments, the conductive plate contact (164), the plurality of contact plugs (172), the plurality of contact plugs (176), the plurality of upper wiring layers (UML), and the plurality of bit lines (BL) may each be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof, but are not limited thereto.

[0060] As illustrated in FIGS. 4 and 5c, in the chip region (CR) of the semiconductor device (100), memory cell blocks (BLK11, BLK12) may include a through electrode region (TA) comprising a plurality of through electrodes (THV) disposed in a connection region (CON). In this specification, each of the plurality of through electrodes (THV) may be referred to as a plug structure.

[0061] Each of the plurality of through electrodes (THV) can penetrate at least one of the stepped connection portion (STP) included in the first stack (STA) and the stepped connection portion (STP) included in the second stack (STB) in a vertical direction (Z direction). Each of the plurality of through electrodes (THV) can be configured not to be electrically connected to the gate line (130) and the conductive pad portion (130A) included in the first stack (STA) and the second stack (STB).

[0062] As illustrated in FIG. 5c, some of the through electrodes (THV) selected from the plurality of through electrodes (THV) may include a portion surrounded by a lower insulating block (133), a portion surrounded by an intermediate insulating film (135, 136), a portion surrounded by an intermediate insulating block (137) and an upper insulating block (137A). In the connection area (CON), the uppermost surface of each of the plurality of memory cell contacts (MC), the plurality of through electrodes (THV), and the conductive plate contact (164) may extend at approximately the same vertical level.

[0063] Each of the plurality of through electrodes (THV) may penetrate at least a portion of the plurality of gate lines (130) and the plurality of insulating films (132). Each of the plurality of through electrodes (THV) may be disposed within a hole penetrating at least one of the plurality of gate lines (130). Each of the plurality of through electrodes (THV) may not be connected to the gate line (130). Each of the plurality of through electrodes (THV) may be spaced apart horizontally from the gate line (130). Each of the plurality of through electrodes (THV) may be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof, but is not limited thereto.

[0064] A first insulating ring (152A) may be disposed between a plurality of through electrodes (THV) and an adjacent gate line (130) in the first stack (STA). If a plurality of through electrodes (THV) penetrate the second stack (STB), a second insulating ring (152B) may also be disposed between a plurality of through electrodes (THV) and an adjacent gate line (130) in the second stack (STB).

[0065] FIG. 6 is a cross-sectional view illustrating a partial configuration of a scribe lane region (SLR) (see FIG. 1) of a semiconductor device (100).

[0066] Referring to FIG. 6, an insulating structure (220) may be disposed on a substrate (110) in a scribe lane region (SLR) of a semiconductor device (100). A recess region (RR) and a plurality of key holes (KH) necessary to form an alignment key (AK) may be formed on the upper surface of the insulating structure (220). In exemplary embodiments, the insulating structure (220) may include the same material as one selected from a lower insulating block (133), a first intermediate insulating film (135), a second intermediate insulating film (136), and an intermediate insulating block (137) in a chip region (CR).

[0067] An alignment key structure (260) may be disposed within each of the recess area (RR) and the plurality of key holes (KH). The alignment key structure (260) may form an alignment key (AK).

[0068] The alignment key structure (260) located within each of the recess region (RR) and the plurality of key holes (KH) may include a carbon layer (262) and a sacrificial metal film (264, 266). In the recess region (RR), the carbon layer (262) may be selectively deposited on the portion where a silicon nitride film is exposed on the inner sidewall of the recess region (RR). In each of the plurality of key holes (KH), the carbon layer (262) may be formed to be selectively deposited on the portion where a silicon nitride film is exposed on the inner surface of each of the plurality of key holes (KH). In this specification, the carbon layer (262) formed in the scribe lane region (SLR) may be formed with a thickness of 5 nm to 15 nm. In each of the recess region (RR) and the plurality of key holes (KH), the carbon layer (262) may be in contact with the insulating structure (220). The bottom surface of the sacrificial metal film (264, 266) within each of the recess area (RR) and the plurality of key holes (KH) may come into contact with the carbon layer (262). The portion of the sacrificial metal film (264, 266) within the recess area (RR) may cover the bottom surface of the recess area (RR) and the side wall of the carbon layer (262) with the same thickness. The portions of the sacrificial metal film (264, 266) within the plurality of key holes (KH) may fill the entrance-side space of each of the plurality of key holes (KH) on the carbon layer (262).

[0069] The carbon layer (262) is composed of pure carbon atoms, but may contain some hydrogen impurities. In an exemplary embodiment, the titanium nitride layer (264) may be part of the sacrificial metal film (266), but is not limited thereto. In an exemplary embodiment, the sacrificial metal film (266) may contain tungsten (W), but is not limited thereto. The space on the sacrificial metal film (264, 266) in the recess region (RR) may be filled with an insulating film (270). The insulating film (270) may be made of a silicon nitride film, a silicon oxide film, or a combination thereof.

[0070] The alignment key (AK), which is composed of the alignment key structure (260) exemplified in FIG. 6, can be formed simultaneously with the formation of a sacrificial structure that fills the interior of a vertical hole required for the formation of at least one plug structure during a process for forming at least one plug structure selected from, for example, a plurality of channel structures (140), a plurality of memory cell contacts (MC), a plurality of insulating support structures (SP), a plurality of dummy channel structures (140D), and a plurality of through electrodes (THV), which are placed in the chip region (CR) of the semiconductor substrate (100).

[0071] FIGS. 7a, 7b, and 7c are cross-sectional views illustrating exemplary configurations in a chip region (CR) of a semiconductor device (200) according to other embodiments of the technical concept of the present invention. FIG. 7a illustrates some components of a portion corresponding to the Y1-Y1' line cross-section of FIG. 4, FIG. 7b illustrates some components of a portion corresponding to the X1-X1' line cross-section of FIG. 4, and FIG. 7c illustrates some components of a portion corresponding to the X2-X2' line cross-section of FIG. 4. In FIG. 7a, 7b, and 7c, the same reference numerals as in FIG. 1 to 6 indicate the same components, and detailed descriptions thereof are omitted here.

[0072] Referring to FIGS. 7a, 7b, and 7c, the chip region (CR) of the semiconductor device (200) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 1 through 6. However, the chip region (CR) of the semiconductor device (200) may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that overlap each other in the vertical direction (Z direction). The cell array structure (CAS) may include a memory stack structure (MST) described with reference to FIG. 3 and FIGS. 5a through 5c. The memory stack structure (MST) of the cell array structure (CAS) may have a configuration generally identical to that described with reference to FIG. 4 and FIGS. 5a through 5d.

[0073] A peripheral circuit structure (PCS) may include a lower substrate (52), a plurality of peripheral circuits formed on the lower substrate (52), and a multilayer wiring structure (MWS) for interconnecting the plurality of peripheral circuits or connecting the plurality of peripheral circuits to components in a memory cell region (MEC).

[0074] The lower substrate (52) may be made of a semiconductor substrate. For example, the lower substrate (52) may include Si, Ge, or SiGe. An active region (AC) may be defined on the lower substrate (52) by a device isolation film (54). A plurality of transistors (TR) constituting a plurality of peripheral circuits may be formed on the active region (AC). Each of the plurality of transistors (TR) may include a gate (PG) and a plurality of ion implantation regions (PSD) formed within the active region (AC) on both sides of the gate (PG). Each of the plurality of ion implantation regions (PSD) may constitute a source region or a drain region of the transistor (TR).

[0075] In exemplary embodiments, a plurality of peripheral circuits included in the peripheral circuit structure (PCS) may include, but are not limited to, a row decoder, a page buffer, a data input / output circuit, control logic, a common source line driver, etc.

[0076] A multilayer wiring structure (MWS) included in a peripheral circuit structure (PCS) may include a plurality of peripheral circuit wiring layers (ML60, ML61, ML62) and a plurality of peripheral circuit contacts (MC60, MC61, MC62). At least some of the plurality of peripheral circuit wiring layers (ML60, ML61, ML62) may be configured to be electrically connectable to a transistor (TR). The plurality of peripheral circuit contacts (MC60, MC61, MC62) may be configured to interconnect a selected portion of the plurality of transistors (TR) and the plurality of peripheral circuit wiring layers (ML60, ML61, ML62).

[0077] In FIGS. 7a, 7b, and 7c, a multilayer wiring structure (MWS) is illustrated as having three wiring layers along the vertical direction (Z direction), but the technical concept of the present invention is not limited to what is illustrated in FIGS. 7a, 7b, and 7c, and the multilayer wiring structure (MWS) may have three or more wiring layers.

[0078] A plurality of peripheral circuit wiring layers (ML60, ML61, ML62) and a plurality of peripheral circuit contacts (MC60, MC61, MC62) may each be made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, a plurality of peripheral circuit wiring layers (ML60, ML61, ML62) and a plurality of peripheral circuit contacts (MC60, MC61, MC62) may each include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0079] A plurality of transistors (TR) and multilayer wiring structures (MWS) included in the peripheral circuit structure (PCS) can be covered with an interlayer insulating film (70). The interlayer insulating film (70) may include silicon oxide, SiON, SiOCN, etc.

[0080] As illustrated in FIGS. 7b and 7c, a substrate (110) is placed on a peripheral circuit structure (PCS) in a connection area (CON) of a cell array structure (CAS), and an insulating plate (112), a second conductive plate (118), a first stack (STA), a second stack (STB), and a third stack (STC) can be stacked in sequence on the substrate (110).

[0081] As illustrated in FIG. 7c, a plurality of through-openings (420H) may be formed in a portion of the connection area (CON) that penetrate the substrate (110), the insulating plate (112), and the second conductive plate (118). Each of the plurality of through-openings (420H) may be filled with an insulating plug (420). The plurality of through-openings (420H) may be positioned to overlap in a vertical direction (Z direction) with a portion of the surrounding circuit structure (PCS). The insulating plug (420) may be made of a silicon oxide film, a silicon nitride film, or a combination thereof.

[0082] In the connection area (CON), a plurality of through electrodes (THV2) may each be configured to extend to a peripheral circuit structure (PCS) through a through opening (420H) and be electrically connected to one selected wiring layer among a plurality of peripheral circuit wiring layers (ML60, ML61, ML62). For example, a plurality of through electrodes (THV2) may each be configured to be electrically connected to the uppermost peripheral circuit wiring layer (ML62) among the peripheral circuit wiring layers (ML60, ML61, ML62) closest to the cell array structure (CAS). A plurality of through electrodes (THV2) may each be configured to be connected to at least one selected peripheral circuit through a multilayer wiring structure (MWS) included in the peripheral circuit structure (PCS). A more detailed configuration of the plurality of through electrodes (THV2) is generally the same as described for the plurality of through electrodes (THV) with reference to FIGS. 4 and 5c.

[0083] Next, a method for manufacturing a semiconductor device according to embodiments based on the technical concept of the present invention will be described in detail.

[0084] FIGS. 8a to 15c are cross-sectional views illustrating a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. In particular, FIGS. 8a, 11a, 12a, 13a, 14a, and 15a are cross-sectional views according to the process sequence of some components of the part corresponding to the Y1 - Y1' line cross-section of FIG. 4, FIGS. 8b, 9a, 10a, 11b, 12b, 13b, 14b, and 15b are cross-sectional views according to the process sequence of some components of the part corresponding to the X1 - X1' line cross-section of FIG. 4, and FIGS. 8c, 9b, 10b, 11c, 12c, 13c, 14c, and 15c are cross-sectional views according to the process sequence of some components of the part corresponding to the X2 - X2' line cross-section of FIG. 4. FIGS. 10c and FIGS. 11d are cross-sectional views according to the process sequence of some components in the scribe lane region (SLR). With reference to FIGS. 8a through 15c, an exemplary method of manufacturing a semiconductor device (100) illustrated in FIGS. 1 through 6 is described.

[0085] Referring to FIGS. 8a, 8b, and 8c, an insulating plate (112) and a second conductive plate (118) can be formed sequentially on a substrate (110) in the memory cell region (MEC) and connection region (CON) of the chip region (CR). The insulating plate (112) may be made of an insulating film having a multilayer structure including a first insulating film (112A), a second insulating film (112B), and a third insulating film (112C).

[0086] A plurality of insulating films (132) and a plurality of sacrificial insulating films (134) can be alternately stacked one by one on a second conductive plate (118) in the memory cell region (MEC) and connection region (CON) of the chip region (CR). The plurality of insulating films (132) may be made of silicon oxide, and the plurality of sacrificial insulating films (134) may be made of silicon nitride. Each of the plurality of sacrificial insulating films (134) may serve to secure space for forming a plurality of gate lines (130) in a subsequent process. A stack formed in the above manner may be referred to as the first stack.

[0087] Referring to FIGS. 9a and 9b, in the result of FIGS. 8a, 8b and 8c, an etching stop layer (not shown) covering the uppermost insulating layer (132) among the plurality of insulating layers (132) can be used as an etching mask to remove a portion of each of the plurality of insulating layers (132) and the plurality of sacrificial insulating layers (134) in the connection region (CON) of the chip region (CR), thereby forming a step structure (ST) that has a gradually smaller width in the horizontal direction as one end of each of the plurality of insulating layers (132) and the plurality of sacrificial insulating layers (134) moves further away from the substrate (110).

[0088] Referring to FIGS. 10a, 10b, and 10c, a sacrificial pad portion (134S) having an increased thickness can be formed at one end of each of a plurality of sacrificial insulating films (134) forming a step structure (ST) in the connection region (CON) of the chip region (CR).

[0089] In exemplary embodiments, to form a sacrificial pad portion (134S) at one end of each of a plurality of sacrificial insulating films (134), a portion of the plurality of insulating films (132) is removed to expose one end of each of the plurality of sacrificial insulating films (134) forming a stepped structure (ST), and then an additional film made of the same material as the constituent material of the plurality of sacrificial insulating films (134) is deposited on the exposed one end of each of the plurality of sacrificial insulating films (134), and the additional film is patterned so that the sacrificial pad portion (134S) remains.

[0090] After that, a lower insulating block (133) covering the step structure (ST) and the second conductive plate (118) can be formed, and the resulting product can be flattened by a chemical mechanical polishing (CMP) process to remove unnecessary films and expose the upper surface of the top insulating film (132). After that, a first intermediate insulating film (135) and a second intermediate insulating film (136) covering the upper surfaces of the top insulating film (132) and the lower insulating block (133), respectively, can be formed in sequence.

[0091] As illustrated in FIG. 10c, after the second intermediate insulating film (136) is formed in the chip region (CR) illustrated in FIG. 10a and FIG. 10b, an insulating structure (220) may remain on the substrate (110) in the scribe lane region (SLR). The insulating structure (220) may include the same material as at least one selected from the lower insulating block (133) in the chip region (CR), the first intermediate insulating film (135), and the second intermediate insulating film (136).

[0092] Referring to FIGS. 11a, 11b, 11c and 11d, a second intermediate insulating film (136), a first intermediate insulating film (135), a lower insulating block (133), a stacked structure of a plurality of insulating films (132) and a plurality of sacrificial insulating films (134), a second conductive plate (118), and an insulating plate (112) can be dry-etched in the connection region (CON) and memory cell region (MEC) of the chip region (CR) to form a plurality of lower vertical holes.

[0093] In the chip region (CR), as illustrated in FIGS. 11a, 11b, and 11c, the plurality of lower vertical holes may include a plurality of lower channel holes (CH1) and a plurality of lower word line cut holes (WCH1) disposed in the memory cell region (MEC), and a plurality of lower dummy channel holes (DCH1), a plurality of lower memory cell contact holes (MCH1), a lower plate contact hole (PCH1), and a plurality of lower through holes (TH1) disposed in the connection region (CON). Although not illustrated in FIGS. 11a, 11b, and 11c, the plurality of lower vertical holes may further include lower vertical holes necessary for forming a plurality of insulating support structures (SP) illustrated in FIG. 4 in the connection region (CON) of the chip region (CR).

[0094] After that, as illustrated in FIG. 11c, a portion of the sacrificial pad portion (134S) and the sacrificial insulating film (134) exposed inside each of the plurality of lower memory cell contact holes (MCH1) and the plurality of lower through holes (TH1) are etched to expand the horizontal width of each of the plurality of lower memory cell contact holes (MCH1) and the plurality of lower through holes (TH1) at the same vertical level as the sacrificial insulating film (134), thereby forming a plurality of indented spaces in which the side walls of the sacrificial pad portion (134S) and the sacrificial insulating film (134) are exposed, and among the plurality of indented spaces, the indented space exposing the sacrificial insulating film (134) can be filled with a first insulating ring (152A), and the indented space exposing the sacrificial pad portion (134S) can be filled again with the sacrificial pad portion (134S).

[0095] After that, as illustrated in FIG. 11a, FIG. 11b and FIG. 11c, a plurality of lower sacrificial structures (S1) can be formed to fill the plurality of lower vertical holes. To form the plurality of lower sacrificial structures (S1), a carbon layer (261) is first formed on the portion of the sacrificial insulating film (134) exposed on the inner side wall of each of the plurality of lower vertical holes, and then a sacrificial metal film (263, 265) containing titanium nitride is formed on the carbon layer (261). The sacrificial metal film (263, 265) can be formed to fill the remaining space of each of the plurality of lower vertical holes. In particular, the titanium nitride layer (263) can be in contact with the carbon layer (261).

[0096] While forming a sacrificial metal film (263, 265) in a chip region (CR) as illustrated in FIG. 11a, 11b, and 11c, a sacrificial metal film (264, 266) may be formed on a carbon layer (262) in a scribe lane region (SLR) as illustrated in FIG. 11d. The bottom surface of the titanium nitride layer (264) may be in contact with the top surface of the carbon layer (262). The sacrificial metal films (263, 264, 265, 266) may be formed simultaneously.

[0097] Referring to FIGS. 12a, 12b, and 12c, processes similar to those described with reference to FIGS. 8a through 9b are performed in the chip region (CR) to form a structure including a plurality of insulating films (132), a plurality of sacrificial insulating films (134), and a plurality of sacrificial pad portions (134S) necessary for forming a second stack (STB) (see FIGS. 5a through 5c), and an intermediate insulating block (137) covering the structure can be formed in the connection region (CON) of the chip region (CR). The intermediate insulating block (137) may be made of the same material as the lower insulating block (133).

[0098] In a plurality of lower vertical holes, the carbon layer (261) and the sacrificial metal film (263, 265) are removed by a process to be described later so that the inlet-side space of each of the plurality of lower vertical holes is finally emptied. The process of removing the carbon layer (261) and the sacrificial metal film (263, 265) can be carried out by a stripping process. The stripping process can be carried out by sulfuric acid (H2SO4). The carbon layer (261) as well as the sacrificial metal film (263, 265) can be removed simultaneously by sulfuric acid.

[0099] Although not illustrated in the drawings of this specification, not all of the plurality of vertical holes have the sacrificial metal film (263, 265) and carbon layer (261) removed by sulfuric acid. Some vertical holes do not undergo the above process, so even if the carbon layer (261) of other vertical holes is removed, carbon components may remain in some of the vertical holes. In a semiconductor device post-processing test, for example, a test using an optical critical dimension (OCD) measuring device, the inspection and component analysis of some vertical holes where the sacrificial metal film (263, 265) is not removed, such as an alignment key area, can be performed to determine whether the technical concept of the present invention has been applied based on whether carbon is detected.

[0100] The carbon layer (261) is composed of pure carbon atoms, but may contain some hydrogen impurities. The carbon layer (261) may be formed with a thickness of 5 nm to 15 nm. In exemplary embodiments, the titanium nitride layer (263) may be part of the sacrificial metal film (265), but is not limited thereto. In exemplary embodiments, the sacrificial metal film (265) may contain tungsten, but is not limited thereto.

[0101] The carbon layer (261) can be easily removed in a stripping process using sulfuric acid when removed in a subsequent process. The carbon constituting the carbon layer (261) can prevent the reaction between silicon nitride (SiN) and titanium nitride (TiN) that may occur on the substrate. In addition, since the carbon layer (261) is selectively deposited, it is not deposited on the oxide surface of the substrate, for example, in the silicon dioxide (SiO2) region, thereby suppressing side reactions such as the generation of SiOC.

[0102] As a comparative example, if a sacrificial metal film (263, 265) is deposited directly on the sidewall of the lower vertical hole without depositing a carbon layer (261), unwanted metal silicide byproducts may be formed on the surface of the silicon-containing film (e.g., a plurality of insulating films (132) and / or a plurality of sacrificial insulating films (134)) forming the inner sidewall of the plurality of lower vertical holes (e.g., a plurality of lower channel holes (CH1), a plurality of lower dummy channel holes (DCH1), and a plurality of lower word line cut holes (WCH1)), or metal residues such as Ti may remain in the lower vertical holes, thereby degrading the performance of the semiconductor device (100). Such metal residues may cause defects such as hole bridging.

[0103] In addition, as another comparative example, when a double layer structure is formed including a silicon oxide liner in contact with a plurality of insulating films (132) and a plurality of sacrificial insulating films (134) exposed in the plurality of lower vertical holes instead of a carbon layer (261), and a metal nitride film such as titanium nitride in contact with the silicon oxide liner, when the silicon oxide liner and the metal nitride film are removed by a wet etching process in a subsequent process, the plurality of insulating films (132) exposed in the plurality of lower vertical holes may be damaged, and a problem may occur in which surface defects such as dimples are caused in the plurality of insulating films (132).

[0104] According to the technical concept of the present invention, a plurality of lower sacrificial structures (S1) and a plurality of intermediate sacrificial structures (S2) include a carbon layer (261) in contact with a plurality of insulating films (132) and a plurality of sacrificial insulating films (134) exposed in the plurality of lower vertical holes, and the carbon layer (261) does not contain metal. Therefore, after forming the plurality of lower sacrificial structures (S1) and a plurality of intermediate sacrificial structures (S2), until the plurality of lower sacrificial structures (S1) and a plurality of intermediate sacrificial structures (S2) are removed in a subsequent process, problems such as the formation of unwanted metal silicide byproducts within the plurality of lower vertical holes or damage to the plurality of insulating films (132) and a plurality of sacrificial insulating films (134) exposed in the plurality of lower vertical holes can be prevented.

[0105] As illustrated in FIG. 11d, while the plurality of lower vertical holes are formed in the chip region (CR) illustrated in FIG. 11a, FIG. 11b, and FIG. 11c, a recess region (RR) and a plurality of key holes (KH) may be formed in the insulating structure (220) in the scribe lane region (SLR). The plurality of key holes (KH) may be positioned adjacent to the recess region (RR). Additionally, while the carbon layer (261) and sacrificial metal film (263, 265) are formed in the chip region (CR), the carbon layer (261) and the sacrificial metal film (263, 265) may be formed inside each of the recess region (RR) and the plurality of key holes (KH) in the scribe lane region (SLR).

[0106] The carbon layers (261, 262) can be formed simultaneously. In the recessed area (RR) of the scribe lane region (SLR), the carbon layer (262) can be selectively deposited on the portion where the silicon nitride film is exposed at the inner sidewall of the recessed area (RR). In each of the plurality of key holes (KH) of the scribe lane region (SLR), the carbon layer (262) can be formed to be selectively deposited on the portion where the silicon nitride film is exposed at the inner surface of each of the plurality of key holes (KH).

[0107] While removing the carbon layer (261) and sacrificial metal film (263, 265) in the chip area (CR) so that the entrance-side space of each of the plurality of lower vertical holes is emptied, the carbon layer (262) and sacrificial metal film (264, 266) may also be removed in the scribe lane area (SLR). At this time, the portions of the carbon layer (262) and sacrificial metal film (264, 266) that covered the bottom surface of the recess area (RR) are removed so that the insulating structure (220) is exposed on the bottom surface of the recess area (RR), and the entrance-side space of each of the plurality of key holes (KH) may be emptied.

[0108] Referring to FIGS. 13a, 13b, and 13c, a structure including a plurality of insulating films (132), a plurality of sacrificial insulating films (134), and a plurality of sacrificial pad portions (134S) required to form a second stack (STB) (see FIGS. 5a to 5c) in the memory cell region (MEC) and connection region (CON) of the chip region (CR) and an intermediate insulating block (137) can be dry-etched to form a plurality of intermediate vertical holes connected to the plurality of lower vertical holes. The plurality of intermediate vertical holes may include a plurality of intermediate channel holes (CH2) and a plurality of intermediate word line cut holes (WCH2) disposed in the memory cell region (MEC), and a plurality of intermediate dummy channel holes (DCH2), a plurality of intermediate memory cell contact holes (MCH2), an intermediate plate contact hole (PCH2), and a plurality of intermediate through holes (TH2) disposed in the connection region (CON). Although not illustrated in FIG. 13a, FIG. 13b, and FIG. 13c, the plurality of intermediate vertical holes may further include a plurality of intermediate holes necessary for forming a plurality of insulating support structures (SP) exemplified in FIG. 4. Through the plurality of intermediate vertical holes, the sacrificial metal film (263, 265) of each of the plurality of lower sacrificial structures (S1) may be exposed.

[0109] Referring to FIGS. 14a, 14b, and 14c, a plurality of intermediate sacrificial structures (S2) filling a plurality of intermediate vertical holes can be formed in the result of FIGS. 13a, 13b, and 13c. The process of forming the plurality of intermediate sacrificial structures (S2) is identical to the method of forming the lower sacrificial structure (S1) and the constituent material described in the present specification in relation to FIGS. 9a, 9b, 10a, 10b, and 10c, so a detailed description thereof is omitted. The intermediate sacrificial structure (S2) formed in the above manner may be referred to as the second stack. Subsequently, a third stack (STC) may be formed on the second stack (STB) (see FIGS. 13a, 13b, and 13c). The third stack (STC) may correspond to the same structure as the lower sacrificial structure (S1) and the intermediate sacrificial structure (S2). The above third stack (STC) can be made of SiO2.

[0110] The above multiple intermediate sacrificial structures (S2) are emptied by a process to be described later, and the above multiple intermediate vertical holes are left. In order to remove the above multiple intermediate sacrificial structures (S2), the sacrificial metal film (263, 265) and the carbon layer (262) can be removed through the above multiple intermediate vertical holes by a stripping process using sulfuric acid.

[0111] Referring to FIGS. 15a, 15b, and 15c, in the result of FIGS. 14a, 14b, and 14c, a plurality of insulating films (132), a plurality of sacrificial insulating films (134), and an upper insulating block (137A) required to form a third stack (STC) (see FIGS. 5a to 5c) in the memory cell region (MEC) and connection region (CON) of the chip region (CR) can be dry-etched to form a plurality of upper vertical holes connected to the plurality of intermediate vertical holes. The plurality of upper vertical holes may include a plurality of upper channel holes (CH3) and a plurality of upper word line cut holes (WCH3) disposed in the memory cell region (MEC), and a plurality of upper dummy channel holes (DCH3), a plurality of intermediate memory cell contact holes (MCH3), an upper plate contact hole (PCH3), and a plurality of upper through holes (TH3) disposed in the connection region (CON). Although not illustrated in FIG. 15a, FIG. 15b, and FIG. 15c, the plurality of upper vertical holes may further include a plurality of upper holes necessary for forming a plurality of insulating support structures (SP) exemplified in FIG. 4. Through the plurality of upper vertical holes, the sacrificial metal film (263, 265) of each of the plurality of intermediate sacrificial structures (S2) may be exposed. Additionally, although not illustrated in the drawings of the specification, the third stack (STC) may be a stack in which a plurality of insulating films (132) and a plurality of sacrificial insulating films (134) alternate, as well as a stack composed solely of an insulator such as silicon dioxide (SiO2).

[0112] Afterwards, a plurality of plug structures may be formed within the plurality of lower vertical holes, the plurality of intermediate vertical holes, and the plurality of upper vertical holes in the memory cell region (MEC) and connection region (CON) of the chip region (CR). The plurality of plug structures may include a plurality of channel structures (140), a plurality of word line cut structures (WLC), a plurality of dummy channel structures (140D), a plurality of memory cell contacts (MC), a plurality of through electrodes (THV), a plurality of insulating support structures (SP), and a conductive plate contact (164). A plug structure including a conductive plate contact (164) may further include an insulating spacer (162) surrounding the conductive plate contact (164). Afterwards, a first upper insulating film (UL1) covering the plurality of plug structures may be formed in the memory cell region (MEC) and connection region (CON) of the chip region (CR).

[0113] The formation order of each of the plurality of channel structures (140), plurality of word line cut structures (WLC), plurality of dummy channel structures (140D), plurality of memory cell contacts (MC), plurality of through electrodes (THV), plurality of insulating support structures (SP), and conductive plate contacts (164) included in the plurality of plug structures can be selected in various ways as needed.

[0114] However, after forming a plurality of channel structures (140) and a plurality of dummy channel structures (140D), and before forming a plurality of word line cut structures (WLC), a plurality of lower sacrificial structures (S1) and a plurality of intermediate sacrificial structures (S2) that fill a plurality of lower word line cut holes (WCH1) and a plurality of intermediate word line cut holes (WCH2) are removed, and an insulating plate (112) is selectively removed only in the memory cell area (MEC) among the memory cell area (MEC) and connection area (CON) of the chip area (CR) through a plurality of lower word line cut holes (WCH1) and a plurality of intermediate word line cut holes (WCH2), and the resulting empty space can be filled with a first conductive plate (114). While removing the insulating plate (112) from the memory cell region (MEC), the portions of the gate dielectric film (182) included in the channel structure (180) in the memory cell region (MEC) that were adjacent to the insulating plate (112) may be removed together with the insulating plate (112), and as a result, the first conductive plate (114) may penetrate a portion of the gate dielectric film (182) in a horizontal direction and come into contact with the channel region (184).

[0115] Additionally, after forming the first conductive plate (114) and before forming the plurality of word line cut structures (WLC), the plurality of sacrificial insulating films (134) and sacrificial pad portions (134S) in the memory cell region (MEC) and connection region (CON) can be replaced with the plurality of gate lines (130) and the plurality of conductive pad portions (130A) through the plurality of lower word line cut holes (WCH1) and the plurality of upper word line cut holes (WCH2). After the first conductive plate (114) and the plurality of gate lines (130) are formed, the plurality of word line cut structures (WLC) that fill the plurality of lower word line cut holes (WCH1) and the plurality of intermediate word line cut holes (WCH2) can be formed.

[0116] Then, referring to FIGS. 7a, 7b, and 7c, a second upper insulating film (UL2) is formed on the above-mentioned result, which sequentially covers a first upper insulating film (UL1) and a plurality of drain regions (148); a plurality of contact plugs (172) are formed in a connection region (CON) that penetrate the first upper insulating film (UL1) and the second upper insulating film (UL2); a plurality of upper wiring layers (UML) are formed on the second upper insulating film (UL2) and the plurality of contact plugs (172) in the connection region (CON); a plurality of contact plugs (176) are formed in a memory cell region (MEC) that penetrate the second upper insulating film (UL2) and are connected to the drain regions (148) of a plurality of channel structures (140); a plurality of bit lines (BL) are formed on the second upper insulating film (UL2) that are connected to the plurality of contact plugs (176); and a third filling space between each of the plurality of upper wiring layers (UML) and the plurality of bit lines (BL). By forming an upper insulating film (UL3), a semiconductor device (100) exemplified in FIGS. 1 to 6 can be manufactured.

[0117] Although the manufacturing method of the semiconductor device (100) exemplified in FIGS. 1 to 6 has been described above with reference to FIGS. 8a to 15c, those skilled in the art will be well aware that semiconductor devices having various structures with various modifications and changes can be manufactured within the scope of the technical concept of the present invention.

[0118] FIG. 16 is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0119] Referring to FIG. 16, an electronic system (1000) according to an exemplary embodiment of the present invention may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising at least one semiconductor device (1100).

[0120] The semiconductor device (1100) may be a non-volatile memory device. For example, the semiconductor device (1100) may be a NAND flash memory device comprising at least one of the structures described above for the semiconductor device (100, 200) described with reference to FIGS. 1 through 7. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In exemplary embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure comprising a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), a plurality of word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a plurality of memory cell strings (CSTR) located between the bit line (BL) and the common source line (CSL).

[0121] In the second structure (1100S), a plurality of memory cell strings (CSTR) may each include a lower transistor (LT1, LT2) adjacent to a common source line (CSL), an upper transistor (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistor (LT1, LT2) and the upper transistor (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0122] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. A plurality of gate lower lines (LL1, LL2) may each be gate electrodes of the lower transistors (LT1, LT2). The word line (WL) may be a gate electrode of the memory cell transistor (MCT), and the gate upper lines (UL1, UL2) may be gate electrodes of the upper transistors (UT1, UT2).

[0123] A common source line (CSL), a plurality of gate lower lines (LL1, LL2), a plurality of word lines (WL), and a plurality of gate upper lines (UL1, UL2) can be electrically connected to a decoder circuit (1110) through a plurality of first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). A plurality of bit lines (BL) can be electrically connected to a page buffer (1120) through a plurality of second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0124] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one of a plurality of memory cell transistors (MCT). The decoder circuit (1110) and the page buffer (1120) can be controlled by a logic circuit (1130).

[0125] The semiconductor device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0126] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1100).

[0127] The processor (1210) can control the overall operation of the electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to a plurality of memory cell transistors (MCTs) of the semiconductor device (1100), data to be read from a plurality of memory cell transistors (MCTs) of the semiconductor device (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0128] FIG. 17 is a schematic perspective view of an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0129] Referring to FIG. 17, an electronic system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by a plurality of wiring patterns (2005) formed on the main board (2001).

[0130] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In exemplary embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0131] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0132] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the DRAM (2004) is included in the electronic system (2000), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0133] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), a plurality of semiconductor chips (2200) on the package substrate (2100), an adhesive layer (2300) disposed on the lower surface of each of the plurality of semiconductor chips (2200), a connecting structure (2400) electrically connecting the plurality of semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the plurality of semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0134] The package substrate (2100) may be a printed circuit board comprising a plurality of package upper pads (2130). A plurality of semiconductor chips (2200) may each include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 18. Each of the plurality of semiconductor chips (2200) may include a plurality of gate stacks (3210) and a plurality of channel structures (3220). Each of the plurality of semiconductor chips (2200) may include at least one of the semiconductor devices (100, 200) described with reference to FIGS. 1 to 7.

[0135] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pad (2130). Accordingly, in the first and second semiconductor packages (2003a, 2003b), a plurality of semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad (2130) of the package substrate (2100). In exemplary embodiments, in the first and second semiconductor packages (2003a, 2003b), a plurality of semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0136] In exemplary embodiments, the controller (2002) and a plurality of semiconductor chips (2200) may be included in a single package. In exemplary embodiments, the controller (2002) and a plurality of semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the plurality of semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0137] FIG. 18 is a schematic cross-sectional view of semiconductor packages according to an exemplary embodiment of the present invention. FIG. 18 shows in more detail the configuration according to the cross-section along line II-II' of FIG. 17.

[0138] Referring to FIG. 18, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), a plurality of package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120) (see FIG. 16), a plurality of lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and a plurality of internal wirings (2135) that electrically connect the plurality of upper pads (2130) and the plurality of lower pads (2125) inside the package substrate body portion (2120). The plurality of upper pads (2130) may be electrically connected to a plurality of connection structures (2400). A plurality of lower pads (2125) can be connected to a plurality of wiring patterns (2005) on a main board (2001) of an electronic system (2000) illustrated in FIG. 18 through a plurality of conductive connection parts (2800).

[0139] Each of the plurality of semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including a plurality of peripheral wirings (3110). The second structure (3200) may include a common source line (3205), a gate stack (3210) on the common source line (3205), a channel structure (3220) penetrating the gate stack (3210), and a bit line (3240) electrically connected to the channel structure (3220). In exemplary embodiments, each of the plurality of semiconductor chips (2200) may include a configuration as described for the semiconductor device (100, 200) described with reference to FIGS. 1 through 7.

[0140] Each of the plurality of semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to a plurality of peripheral wires (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may be positioned outside the gate stack (3210). In other exemplary embodiments, the semiconductor package (2003) may further include a through-wire that penetrates the gate stack (3210). Each of the plurality of semiconductor chips (2200) may further include an input / output pad (2210 of FIG. 16) that is electrically connected to a plurality of peripheral wires (3110) of the first structure (3100).

[0141] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0142] 110: Substrate 220: Insulating structure 260: Alignment Key Structure 262: Conformal Liner 264: Titanium nitride layer 266: Sacrificial Metal Mesh AK: Alignment Key

Claims

Claim 1 A step of forming a first stack by alternately stacking a plurality of first films and a plurality of second films one layer at a time on a substrate; a step of forming a first vertical hole penetrating the first stack in a vertical direction; a step of depositing a first carbon layer on the inner sidewall of the first vertical hole so as to be in contact with the portions of the plurality of first films and a plurality of second films exposed through the first vertical hole; a step of forming a first sacrificial metal film filling the first vertical hole on the first carbon layer; a step of forming a second stack on the first stack by alternately stacking a plurality of first films and a plurality of second films one layer at a time; a step of forming a second vertical hole penetrating the second stack in a vertical direction; a step of depositing a second carbon layer on the inner sidewall of the second vertical hole so as to be in contact with the portions of the plurality of first films and a plurality of second films exposed through the second vertical hole; a step of forming a second sacrificial metal film filling the second vertical hole on the second carbon layer; a step of forming a third stack on the second stack; a third vertical hole penetrating the third stack in a vertical direction A method for manufacturing a semiconductor device, comprising: a step of forming a hole; and a step of removing the first sacrificial metal film, the second sacrificial metal film, the first carbon layer, and the second carbon layer. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the first carbon layer and the second carbon layer are selectively deposited on the second film, and carbon is not deposited on the first film. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the step of removing the first sacrificial metal film, the second sacrificial metal film, the first carbon layer, and the second carbon layer corresponds to a stripping process using sulfuric acid (H2SO4). Claim 4 A method for manufacturing a semiconductor device according to claim 1, wherein the third stack is made of silicon dioxide (SiO2). Claim 5 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of removing the plurality of second films and filling the removed places with word lines. Claim 6 A step of forming a first stack by alternately stacking a plurality of first films and a plurality of second films one layer at a time on a substrate; a step of forming a first vertical hole penetrating the first stack in a vertical direction; a step of depositing a first carbon layer on the inner sidewall of the first vertical hole so as to be in contact with the portions of the plurality of first films and a plurality of second films exposed through the first vertical hole; a step of forming a first sacrificial metal film filling the first vertical hole on the first carbon layer; a step of forming a second stack on the first stack by alternately stacking the plurality of first films and a plurality of second films one layer at a time; a step of forming a second vertical hole penetrating the second stack in a vertical direction; a step of depositing a second carbon layer on the inner sidewall of the second vertical hole so as to be in contact with the portions of the plurality of first films and a plurality of second films exposed through the second vertical hole; a step of forming a second sacrificial metal film filling the second vertical hole on the second carbon layer; and a step of forming a third stack on the second stack by alternately stacking the plurality of first films and a plurality of second films. A method for manufacturing a semiconductor device, comprising: a step of forming a third vertical hole penetrating the third stack in a vertical direction; and a step of removing the first sacrificial metal film, the second sacrificial metal film, the first carbon layer, and the second carbon layer. Claim 7 A method for manufacturing a semiconductor device according to claim 6, wherein the first carbon layer and the second carbon layer are selectively deposited on the second film included in the first stack and the second film included in the second stack, and carbon is not deposited on the first film. Claim 8 A method for manufacturing a semiconductor device according to claim 6, wherein the step of removing the first sacrificial metal film, the second sacrificial metal film, the first carbon layer, and the second carbon layer corresponds to a stripping process using sulfuric acid. Claim 9 A method for manufacturing a semiconductor device according to claim 6, further comprising the step of removing the plurality of second films and filling the removed places with word lines. Claim 10 A step of forming a film stack composed of a plurality of alternating layers of silicon oxide and silicon nitride films on a substrate; a step of forming a plurality of openings extending to a depth from the uppermost surface to the lowermost surface of the film stack; a step of selectively depositing a carbon layer having a thickness in the range of 5 nm to 15 nm on the surface of the film stack, and on the lowermost surface of the openings and the inner sidewalls of the plurality of openings, only on the silicon nitride film of the film stack; and a step of filling the plurality of openings with a sacrificial metal film. A method for manufacturing a semiconductor device comprising: a process cycle comprising; a step of preparing a plurality of features by repeating the process cycle once on a sacrificial metal film; a step of forming a silicon dioxide stack on some of the plurality of features and forming a first feature by forming an opening extending to a depth from the top surface to the bottom surface of the silicon dioxide stack; a step of forming a new film stack composed of a plurality of alternating layers of a silicon oxide film and a silicon nitride film on the remaining features among the plurality of features and forming a second feature by forming an opening extending to a depth from the top surface to the bottom surface of the new film stack; and a strip process step of simultaneously removing the sacrificial metal film and the carbon layer formed on the first feature and the second feature. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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