System, method and program

Abstract

[Solution] A system is provided comprising a plurality of memory units each storing a data file, a plurality of acquisition units each detachably connected to any one of the plurality of memory units and acquiring a data file from the corresponding memory unit, and a plurality of processing units each provided in correspondence with any one of the plurality of acquisition units and performing data processing on the data file acquired by the corresponding acquisition unit, wherein each of the plurality of acquisition units changes the allocation of each memory unit to each processing unit according to the connection type between the plurality of memory units and the plurality of acquisition units.

Description

Technology Field

[0001] The present invention relates to a system, a method, and a program. Background Technology

[0002] Patent Document 1 describes a tester for an image sensor that “introduces an image signal … output from a terminal in contact with the image sensor under test, processes the image … and determines the quality” (Claim 1 of Patent Document 1). Prior art literature

[0003] Japanese Patent Publication No. H4-3686

[0004] In a first aspect of the present invention, a system is provided comprising a plurality of memory units each storing a data file, a plurality of acquisition units each detachably connected to any one of the plurality of memory units and acquiring a data file from the corresponding memory unit, and a plurality of processing units each provided in correspondence with any one of the plurality of acquisition units and performing data processing on the data file acquired by the corresponding acquisition unit, wherein each of the plurality of acquisition units changes the allocation of each memory unit to each processing unit according to the connection type between the plurality of memory units and the plurality of acquisition units.

[0005] The above system further comprises a reading unit that is provided in each of the plurality of memory units and has a plurality of output ports, reads a data file from a corresponding memory unit and outputs it from the corresponding plurality of output ports, and an input unit that is provided in each of the plurality of acquisition units and has a plurality of input ports, and inputs at least a portion of a data file output from one of the output ports through the corresponding plurality of input ports, wherein each reading unit specifies an input port linked up to each of the plurality of output ports in the reading unit, and each input unit specifies an output port linked up to each of the plurality of input ports in the input unit.

[0006] In the above system, each input port is an input / output port capable of inputting and outputting data, and each introductory section can specify an output port and an input / output port linked up to each of the plurality of input / output ports in the introductory section.

[0007] In the above system, each reading unit is linked up to one of the input / output ports in one of the above-mentioned introduction units with respect to one of the above-mentioned introduction units, and also, among the plurality of output ports in the reading unit, the input port of one of the above-mentioned introduction units is linked up to some of the output ports and the input port of another of the above-mentioned introduction units is linked up to some of the output ports, and according to settings by user operation, separate data segments extracted from a single data file can be output from some of the output ports and from other of the output ports.

[0008] In any one of the above systems in which a plurality of output ports are provided in a reading unit, each reading unit can output a common data file from the plurality of output ports when the input ports of different acquisition units among the plurality of acquisition units are linked up with respect to the plurality of output ports in the reading unit.

[0009] In any one of the above systems in which a plurality of output ports are provided in a reading unit, each reading unit can output a separate data segment extracted from a single data file from the corresponding plurality of output ports when the input port of a common acquisition unit among the plurality of acquisition units is linked up with respect to the plurality of output ports in the corresponding reading unit.

[0010] Any one of the above systems may additionally have a plurality of first communication units connected to a reference number of memory units among the plurality of memory units, and the acquisition unit may have a plurality of second communication units that receive data files from the reference number of memory units by interposing a first communication unit detachably connected to each of the plurality of first communication units.

[0011] In the above system, each first communication unit and each second communication unit may be connected via a plurality of communication lanes.

[0012] In any one of the above systems, the plurality of acquisition units can acquire a data file from the memory unit via optical communication.

[0013] In any one of the above systems, among the plurality of processing units, at least two processing units may have different processing performances for the data processing.

[0014] In any one of the above systems, the data file includes image data, and the plurality of processing units can perform image processing on the image data included in the data file.

[0015] In the above system, the plurality of memory units can each store a data file containing image data acquired from a separate imaging device.

[0016] In the above system, each imaging device is a device under test, and the system may additionally be provided with a judgment unit that determines the quality of the device under test based on a test result derived from the result of image processing.

[0017] In a second aspect of the present invention, a method is provided comprising: a plurality of acquisition devices, each detachably connected to one of a plurality of memory devices that each store a data file, an acquisition step of acquiring a data file from the said memory device; and a plurality of processing devices, each provided in correspondence with one of the plurality of acquisition devices, a processing step of performing data processing on the data file acquired by the corresponding acquisition device, wherein prior to the acquisition step, each of the plurality of acquisition devices changes the allocation of each memory device to each processing device according to the connection type between the plurality of memory devices and the plurality of acquisition devices.

[0018] In a third aspect of the present invention, a computer program stored in a medium is provided, which is executed by a computer and functions as a plurality of memory units each storing a data file, a plurality of acquisition units each detachably connected to any one of the plurality of memory units and acquiring a data file from the corresponding memory unit, and a plurality of processing units each provided in correspondence with any one of the plurality of acquisition units and performing data processing on the data file acquired by the corresponding acquisition unit, wherein each of the plurality of acquisition units changes the allocation of each memory unit to each processing unit according to the connection type between the plurality of memory units and the plurality of acquisition units.

[0019] Meanwhile, the above summary of the invention does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups may also constitute the invention. Brief explanation of the drawing

[0020] FIG. 1 shows the configuration of a test device (10) according to an embodiment together with a test subject (20). FIG. 2 shows the configuration of a capture module (200) and an image processing device (194) according to an embodiment. FIG. 3 shows the test flow of a test device (10) according to an embodiment. FIG. 4 shows an example of the connection type between the memory unit (235) and the acquisition unit (265). FIG. 5 shows another example of the connection type between the memory unit (235) and the acquisition unit (265). FIG. 6 shows another example of the connection type between the memory unit (235) and the acquisition unit (265). FIG. 7 shows another example of the connection type between the memory unit (235) and the acquisition unit (265). FIG. 8 shows an example of a computer (2200) in which a plurality of aspects of the present invention may be implemented wholly or partially. Specific details for implementing the invention

[0021] The present invention will be described below through embodiments thereof, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the means of solving the invention.

[0022] FIG. 1 shows the configuration of a test device (10) according to the present embodiment together with a test subject (20). The test subject (20) includes one or more devices formed with a circuit that is the subject of testing by the test device (10) as a Device Under Test (DUT). The DUT according to the present embodiment is a photoelectric conversion device that detects light and converts it into an electrical signal. The DUT may be an imaging device such as a CMOS image sensor or other image sensors that converts an incident optical image into image data.

[0023] The test subject (20) may be a wafer on which a circuit is formed, an IC / LSI chip circuit formed on the wafer, an IC / LSI chip formed on the wafer, or an IC / LSI package in which an IC / LSI chip is packaged. In the example of the drawing, the test device (10) mounts the test subject (20), which is a wafer on which a plurality of imaging devices are formed, and tests each imaging device. The test device (10) may test imaging devices one by one, or may test two or more imaging devices simultaneously.

[0024] The test device (10) may be an example of a system, and in this embodiment, an optical input test of the DUT is performed as an example. Alternatively, or in addition to this, the test device (10) may perform an electrical test of the DUT. In this embodiment, the case where the test device (10) performs an imaging test of the DUT, which is an imaging device, is described as an example.

[0025] The test device (10) comprises a prober device (100), a test head (150), a rotating device (180), and a main frame (190). The prober device (100) comprises a stage (102), a probe card (104), and a connection unit (120).

[0026] The stage (102) carries the test specimen (20). The stage (102) has a vacuum chuck or an electrostatic chuck on its upper surface and can fix the test specimen (20).

[0027] A probe card (104) is provided above the stage (102). The probe card (104) includes one or more probes (106) and a light-blocking unit (108). One or more probes (106) are provided on the side of the probe card (104) facing the stage (102) and are connected to each electrode of the DUT, which is the test target on the test object (20). The probe card (104) includes one or more connectors connected to a connection unit (120) on the side opposite to the stage (102), and each probe (106) is electrically connected to a performance board (130) on the test head (150) side via a corresponding connector and a connection unit (120).

[0028] A light-blocking unit (108) is placed in an opening provided in the probe card (104). The light-blocking unit (108) may have an opening through which test light to be irradiated onto the DUT passes, and a light-blocking wall placed around the opening to block stray light.

[0029] A connection unit (120) is provided above the probe card (104). The connection unit (120) has an opening that passes test light. The connection unit (120) electrically connects one or more connectors of the probe card (104) to the performance board (130) of the test head (150). The probe card (104) and the connection unit (120) described above may be interchangeable depending on the type of test subject (20) or DUT.

[0030] The test head (150) tests the DUT, which is the subject of the test, on the test object (20) mounted on the stage (102) of the prober device (100). The test head (150) includes a performance board (130), a Hi-Pix (140), one or more test modules (160a to 160d) (also referred to as "test modules (160)"), a light source (170), and a light tube (175).

[0031] The performance board (130) and the Hi-Pix (140) are provided on the side of the test head (150) that is the connection unit (120). The performance board (130) and the Hi-Pix (140) have an opening that passes test light. The performance board (130) and the Hi-Pix (140) electrically connect the connection unit (120) and each test module (160) so that the terminals of each test module (160) are electrically connected to the corresponding electrodes of the DUT via the connection unit (120), the probe card (104), and each probe (106). The performance board (130) includes one or more connectors connected to the connection unit (120) and one or more connectors on the Hi-Pix (140) side. The Hi-Pix (140) accommodates cables, etc., that connect each of the multiple terminals of the connector on the Hi-Pix (140) side of the performance board (130) to the terminals of the corresponding test module (160).

[0032] Each of one or more test modules (160) is inserted into a slot within the test head (150) and is detachably connected to the back plane (upper side in the drawing) of the test head (150). The test module (160) may also be referred to as a "pin electronics card" or a "tester board." Each test module (160) is electrically connected to the DUT on the test object (20) via a connection device such as a Hi-Pix (140) and a performance board (130) mounted on the test head (150), and a connection unit (120) and a probe card (104) mounted on the prober device (100). The one or more test modules (160) input and output signals with the DUT and test the DUT by inspecting the signals input from the DUT.

[0033] At least one test module (160) can transmit and receive signals with the DUT, which is an imaging device, via an electrical signal line, and can perform the setting of the DUT and the imaging of the test light. At least one test module (160) acquires output data from the DUT and supplies the data file to an image processing device (194) within the main frame (190). Additionally, at least one test module (160) can function as a power supply to the DUT. The data output from the DUT may include metadata such as focus information in addition to image data (e.g., image data for each color such as RGB). The size of the image data may vary depending on the type of DUT (e.g., number of pixels). The number of pixels of the DUT may be 32 megapixels, 48 ​​megapixels, 100 megapixels, 200 megapixels, etc., or may be a separate number of pixels.

[0034] The light source (170) is positioned on a side opposite to the side on which the performance board (130) and Hi-Pix (140) are placed in the test head (150). The light source (170) emits test light that is irradiated onto the DUT. The light source (170) can irradiate test light of multiple emission patterns corresponding to multiple test items onto each DUT. Meanwhile, light of one emission pattern may be light that is irradiated for a time during which one image can be captured by the DUT. Light of one emission pattern may correspond to one or multiple test items and may be irradiated when performing a test of the corresponding one or multiple test items. Light of multiple emission patterns may be light that is irradiated for a time during which multiple images are captured by the DUT. The intensity or wavelength of the irradiated light of the multiple emission patterns may differ from one another depending on at least one of the irradiation position and irradiation time. Light of multiple emission patterns may correspond to one or more test items and may be irradiated when performing a test of the one or more test items.

[0035] The light tube (175) is provided in the range from the light source (170) to the performance board (130) and guides the test light from the light source (170) to the opening of the performance board (130).

[0036] The rotating device (180) holds the test head (150) so that it can rotate about the axis of rotation. When testing the DUT, the rotating device (180) rotates the test head (150) to a test position where the performance board (130) of the test head (150) is electrically connected to the connection unit (120) of the prober device (100), as shown in the drawing. Additionally, when mounting or replacing the performance board (130) and the Hi-Fix (140), or inserting and removing the test module (160), the rotating device (180) rotates the test head (150) to a maintenance position where the surface of the test head (150) that mounts the performance board (130) and the Hi-Fix (140) becomes the upper side.

[0037] The main frame (190) is connected to the prober device (100) and the test head (150). The main frame (190) has a system controller (192) and an image processing device (194). The system controller (192) is connected to the prober device (100), the test head (150), and the image processing device (194) and controls the test of the DUT. The system controller (192) controls each part of the test head (150), including one or more test modules (160), to perform a test of the DUT in accordance with the signal received from the prober device (100) indicating that the DUT of the test subject (20) has been contacted by one or more probes (106).

[0038] The system controller (192) may be a PC (personal computer), workstation, server computer, general-purpose computer, or other computer, and may be a computer system in which multiple computers are connected. Such a computer system is also a computer in the broad sense. Additionally, the system controller (192) may be implemented within a computer by one or more executable virtual computer environments. Alternatively, the system controller (192) may be a dedicated computer designed for test control, or dedicated hardware realized by dedicated circuitry.

[0039] An image processing device (194) is connected to a system controller (192) and a test head (150). The image processing device (194) receives a data file containing image data from a test module (160) within the test head (150). The image data included in the data file may be image data of an image captured by the DUT capturing test light, or image data of an image captured by the DUT in a state where it is not receiving light. The image processing device (194) performs data processing on the data file to determine the quality of the DUT. In this embodiment, as an example, the image processing device (194) may perform image processing on the image data within the data file to determine whether the captured image satisfies the image quality standards of the imaging device as the DUT.

[0040] Meanwhile, the image processing device (194) may be connected to one test head (150) as shown in the drawing, or it may be connected to a plurality of test heads (150). When the image processing device (194) is connected to a plurality of test heads (150), the image processing device (194) receives image data from each DUT that is a test target in the plurality of test heads (150) and inspects the image data.

[0041] The image processing device (194) may be a PC (personal computer), workstation, server computer, general-purpose computer, or other computer, and may be a computer system in which multiple computers are connected. Such a computer system is also a computer in the broad sense. Additionally, the image processing device (194) may be implemented within a computer by one or more executable virtual computer environments. Alternatively, the image processing device (194) may be a dedicated computer designed for image processing, or dedicated hardware realized by dedicated circuits.

[0042] FIG. 2 shows the configuration of a capture module (200) and an image processing device (194) according to the present embodiment. The capture module (200) functions as a test module (160) (e.g., test module (160c)) that acquires output data from the DUT among a plurality of test modules (160) shown in FIG. 1. The test head (150) can be equipped with one or more capture modules (200).

[0043] A capture module (200) comprises one or more capture blocks (210) (in the example of the drawing, "capture blocks (210-1 to 4)"), one or more signal transmitters (250) (in the example of the drawing, "signal transmitters (250-1 to 2)"), and a module IF (module interface) (255). In the drawing, one capture module (200) is equipped with four capture blocks (210-1 to 4) and two signal transmitters (250-1 to 2), but the number of these can be varied by the capture module (200).

[0044] Each capture block (210) is provided in correspondence with one or more DUTs that are subject to testing. The capture block (210) is electrically connected to the DUT subject to testing and acquires output data from the DUT. The capture block (210) has an image data receiving unit (220), a capture unit (230), and a memory unit (235).

[0045] The image data receiving unit (220) is electrically connected to the DUT that is the subject of the test. The image data receiving unit (220) receives output data from the DUT. The image data receiving unit (220) can receive output data including image data captured by the DUT. The image data receiving unit (220) has an image input interface suitable for an image output interface mounted on the DUT that is the subject of the test. The image data receiving unit (220) may be a PHY chip or PHY board that conforms to a physical layer (PHY) standard such as MIPI (Mobile Industry Processor Interface, registered trademark). In this case, the image data receiving unit (220) can receive image data from the DUT that has an interface conforming to such a PHY standard.

[0046] The capture unit (230) is connected to the image data receiving unit (220) and the memory unit (235). The capture unit (230) receives output data from the DUT from the image data receiving unit (220) and temporarily stores it in the memory unit (235) as a data file. The capture unit (230) may acquire identification information of the light emission pattern when the image data is captured from the system controller (192) and include identification information of the test item corresponding to the light emission pattern in the data file and store it in the memory unit (235). The capture unit (230) may sequentially receive multiple output data including multiple captured images captured by the DUT by receiving the same or different test light and store them in the memory unit (235).

[0047] A capture unit (230) may be an example of a reading unit and may be provided in each of a plurality of memory units (235) and may read a data file from the corresponding memory unit (235). In the present drawing, as an example, the capture unit (230) is provided outside the memory unit (235) with a configuration different from that of the memory unit (235). The capture unit (230) may have a plurality of ports (231) (in the example of the present drawing, "ports (231-1 to 2)"). Each port (231) may be an output port, and the capture unit (230) may output the read data file from the plurality of ports (231). In this embodiment, as an example, a plurality of ports (231-1, 231-2) in a single capture unit (230) are connected to separate signal transmitters (250-1, 250-2), but may also be connected to a common signal transmitter (250). The capture unit (230) may read a data file stored in a memory unit (235) in response to a request from an image processing device (194) and transmit it from a port (231) to the image processing device (194) via a signal transmitter (250). Details will be described later, but the capture unit (230) may transmit a single data file to the image processing device (194) from each of the ports (231-1, 231-2), or transmit separate data segments obtained from a single data file to the image processing device (194) from the ports (231-1, 231-2). Transmitting separate data segments from each of the ports (231-1, 231-2) means that the data segment transmitted by port (231-1) and the data segment transmitted by port (231-2) may be different.

[0048] The capture unit (230) may aggregate a plurality of read data files by operation and transmit them to an image processing device (194) as a data file to be examined. For example, the capture unit (230) may generate a data file to be examined by calculating a sum, average, maximum value, minimum value, or other statistical amount for each corresponding pixel of a plurality of data files, or by performing a pre-specified filter processing on a plurality of image data. The capture unit (230) may temporarily store intermediate data in a memory unit (235) while calculating a data file to be examined from image data of a plurality of captured images.

[0049] A memory unit (235) stores data files. In the test device (10) according to the present embodiment, a plurality of memory units (235) each storing data files (distinguished by the capture blocks (210-1 to 4) that include the corresponding memory units (235-1 to 4)) may be provided by at least one of the following: a plurality of test modules (160) are provided in the test head (150) and a plurality of capture blocks (210) that function as test modules (160) are provided. Each of the plurality of memory units (235) may store data files acquired from separate DUTs.

[0050] The memory unit (235) may have one or more memory banks (240a to c) (also referred to as "memory bank (240)"). One or more memory banks (240) are connected to the capture unit (230). Each memory bank (240) may be a memory device or memory module, such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). Each memory bank (240) may be composed of two or more memory devices or memory modules.

[0051] One or more signal transmitters (250) are connected to the output port (231) of one or more capture units (230) and are connected to a memory unit (235) via the capture unit (230). Here, in the test device (10) according to the present embodiment, a plurality of signal transmitters (250) (in the example of the drawing, "signal transmitters (250-1 to 2), etc.") may be provided by at least one of the following: a plurality of test modules (160) are provided in the test head (150) and a plurality of signal transmitters (250) are provided in the capture module (200) that functions as the test module (160). Each signal transmitter (250) may be an example of a first communication unit and may be connected to a reference number of memory units (235) among a plurality of memory units (235) in the test device (10) (in this drawing, as an example, four memory units (235) provided in one capture module (200)). Meanwhile, the reference number may be a number other than 4, and as an example, may be 2.

[0052] A signal transmitter (250) is detachably connected via a communication cable to a signal transmitter (290) described later within an image processing device (194) connected to it, and receives signals such as electrical signals or optical signals between it and the signal transmitter (290). Each signal transmitter (250) can be connected to a single signal transmitter (290). The communication cable may include multiple communication lanes. Accordingly, each signal transmitter (250) and each signal transmitter (290) can be connected via multiple communication lanes, and serial communication can be performed in parallel via each communication lane. The number of communication lanes may be equal to a reference number, that is, the number of memory units (235) connected to the signal transmitter (250), and in this embodiment, as an example, it may be four. Accordingly, the signal transmitter (250) can perform data file communication via a separate communication lane for each memory unit (235). The signal transmitter (250, 290) may be an optical transceiver such as a QSFP (Quad Small Form-factor Pluggable) standard. If the signal transmitter (250, 290) is a QSFP standard optical transceiver, the signal transmitter (250) is connected to the opposing signal transmitter (290) via four lanes of optical fiber.

[0053] Module IF (255) is connected to each capture block (210) and other circuits within the capture module (200) and to the system controller (192). Module IF (255) enables control of each circuit within the capture module (200) from the system controller (192) by relaying access to each circuit within the capture module (200) from the system controller (192).

[0054] The image processing device (194) has a plurality of acquisition units (265) (in the example of the drawing, four “acquisition units (265-1 ~ 4)” which are the reference number), a plurality of image processing engines (270) (in the example of the drawing, four “image processing engines (270-1 ~ 4)” which are the reference number), and a judgment unit (285).

[0055] Each of the plurality of acquisition units (265) is detachably connected to one of the plurality of memory units (235) and acquires a data file from the corresponding memory unit (235). In the present embodiment, as an example, each acquisition unit (265) is detachably connected to one of the plurality of signal transmitters (250) in the test device (10), thereby being detachably connected to each memory unit (235) connected to the corresponding signal transmitter (250) and acquiring a data file from each memory unit (235).

[0056] Each acquisition unit (265) has a plurality of signal transmitters (290) and one or a plurality of CAPIFs (capture interfaces) (280). In the present drawing, as an example, each acquisition unit (265) has two signal transmitters (290) and one CAPIF (280), and the test device (10) is equipped with a total of eight signal transmitters (290) (also referred to as "signal transmitters (290-1 to 8)") and a total of four CAPIFs (280) (also referred to as "CAPIF (280-1 to 4)").

[0057] Each signal transmitter (290) is connected to a corresponding CAPIF (280). Each signal transmitter (290) is detachably connected to a signal transmitter (250) in a capture module (200) via a communication cable and receives signals such as electrical signals or optical signals between itself and the signal transmitter (250). Each signal transmitter (290) may be an example of a second communication unit and, among a plurality of signal transmitters (250-1 to 2), can receive data files from a memory unit (235) of the aforementioned reference number (4 as an example in this drawing) connected to the signal transmitter (250) via a detachably connected signal transmitter (250). Each signal transmitter (290) can perform optical communication with the signal transmitter (250), and accordingly, each acquisition unit (265) can acquire a data file from the memory unit (235) via optical communication. Each acquisition unit (265) can supply the acquired data file to the corresponding CAPIF (280).

[0058] Each signal transmitter (290) according to the present embodiment can be detachably connected to a single signal transmitter (250). Accordingly, each signal transmitter (290) can be connected to a reference number of capture units (230) and further to a reference number of memory units (235) via a single signal transmitter (250). Each signal transmitter (290) can be connected to each signal transmitter (250) via a reference number of communication lanes and can receive data files via separate communication lanes for each memory unit (235).

[0059] Each signal transmitter (290) may be detachably connected to a single other signal transmitter (290) (see FIG. 6 described later). When two signal transmitters (290) are connected to each other, a data file may be transmitted from one signal transmitter (290) to the other signal transmitter (290) in each communication lane, and in some communication lanes, a data file may be transmitted from one signal transmitter (290) to the other signal transmitter (290), and in the remaining communication lanes, a data file may be transmitted from the other signal transmitter (290) to one signal transmitter (290). This type of communication may be controlled by a CAPIF (280) connected to the signal transmitter (290).

[0060] Each CAPIF (Capture Interface) (280) is an interface device for communicating with an image processing engine (270) and a capture block (210) within a capture module (200), and is connected to one of the image processing engines (270). Each CAPIF (280) may be mounted on a peripheral bus, such as PCI Express (registered trademark), that the image processing engine (270) has. Each CAPIF (280) is connected to two signal transmitters (290) and communicates with a capture unit (230), and further to a memory unit (235), via a signal transmitter (250) that is detachably connected to these signal transmitters (290).

[0061] Each CAPIF (280) may be an example of an introduction unit and may be provided in each of a plurality of acquisition units (265) and may introduce at least a portion of a data file output from any one port (231) of any one capture unit (230). In the present drawing, as an example, each CAPIF (280) is provided inside the acquisition unit (265) as part of the acquisition unit (265).

[0062] Each CAPIF (280) may have a plurality of ports (281) connected to a signal transmitter (290). Each port (281) may be an input port, and the CAPIF (280) may introduce data through the plurality of ports (281). Introducing data by the CAPIF (280) may mean supplying the received data to an image processing engine (270) corresponding to the CAPIF (280). Each CAPIF (280) may have a reference number of ports (281) for each connected signal transmitter (290), and in this drawing, as an example, it has 8 ports (281). The reference number of ports (281) for each signal transmitter (290) may each be connected to a reference number of communication lanes included in a communication cable that is detachably connected to the corresponding signal transmitter (290). Each CAPIF (280) can receive data files from a separate port (281) for each memory unit (235). Each CAPIF (280) can supply the received data to the image processing engine (270) serially or in parallel.

[0063] Each port (281) may be an input / output port capable of inputting and outputting data. In this case, each port (281) may function as either an input port or an output port depending on the connection type. In this embodiment, as an example, when signal transmitters (290) are connected to each other, among the four ports (281) connected to each of these signal transmitters (290), two ports (281) may function as input ports and the remaining two ports (281) may function as output ports. When at least one port (281) is an input / output port, the CAPIF (280) may pre-set which port (281) receives a data file and which port (281) receives a data file and which port (281) outputs the data file to be output from another port (281) through user operation involving a system controller (192), etc. In one CAPIF (280), if a data file input from one port (281) is output from another port (281), the data file can be transferred from the one CAPIF (280) to another CAPIF (280).

[0064] Each of the above multiple acquisition units (265) changes the allocation of each memory unit (235) to each image processing engine (270) according to the connection type between the multiple memory units (235) provided in the test device (10) and the multiple acquisition units (265) (in this embodiment, as an example, the connection type between the signal transmitters (250, 290). Changing the allocation of each memory unit (235) to each image processing engine (270) may mean changing the correspondence relationship between the data file stored in each memory unit (235) and the image processing engine (270) that performs image processing on the image data of the data file. Each acquisition unit (265) can assign the memory unit (235) connected to each specific capture unit (230) to the image processing engine (270) corresponding to itself by specifying each capture unit (230) of the counterpart that is linked up via the signal transmitters (290, 250). Meanwhile, a link-up may be a state in which a computer or communication device (or such ports, connectors, or adapters) is connected to another computer or communication device via a cable or wirelessly, and becomes capable of communication. Each of the plurality of acquisition units (265) can supply data files of each memory unit (235), which is detachably connected via a signal transmitter (290, 250), to an image processing engine (270) corresponding to itself.

[0065] Each image processing engine (270) is an example of a processing unit and is provided to correspond to one of a plurality of acquisition units (265), and performs data processing on a data file acquired by the corresponding acquisition unit (265). Each image processing engine (270) may correspond to one of the acquisition units (265) and may perform image processing on image data included in the data file. Each image processing engine (270) may perform image processing according to the test item on image data captured with a light emission pattern according to the test item. In this embodiment, as an example, each image processing engine (270) may perform image processing according to the test item represented by identification information included in the data file.

[0066] Here, image processing may be a process for extracting any one piece of information from image data. For example, image processing may be a process for calculating the average of pixel values, a process for calculating an indicator value of the sensitivity of the DUT, a process for calculating an indicator value of the uniformity of pixel values, a process for calculating an indicator value of the noise characteristics of the DUT, a process for calculating the standard deviation of pixel values ​​in at least a part of the image data, or a process for detecting unintended pixel dots or lines. The image processing engine (270) may supply data representing the result of image processing to the judgment unit (285).

[0067] Among the multiple image processing engines (270), at least two of the image processing engines (270) may have different processing performance for data processing. Accordingly, by changing the connection type of the signal transmitter (250, 290), and furthermore the connection type of the memory unit (235) and the acquisition unit (265), it becomes possible to allocate a memory unit (235) that stores a data file with a large amount of data to an image processing engine (270) with high processing performance, and to allocate a memory unit (235) that stores a data file with a small amount of data to an image processing engine (270) with low processing performance. Processing performance may be, for example, at least one of clock frequency, thermal design power, power efficiency, memory capacity, and memory bandwidth.

[0068] The image processing engine (270) may be a computer main body equipped with a CPU, memory, and input / output devices, and, if necessary, an external storage device, etc. Alternatively, the image processing engine (270) may be an image processing accelerator, such as a GPU (Graphics Processing Unit), mounted on the computer main body. The image processing engine (270) may be one or more image processing accelerators mounted on a peripheral bus, such as PCI Express (registered trademark). Alternatively, the image processing engine (270) may be a dedicated computer or dedicated circuit designed exclusively for image processing of the test device (10).

[0069] The judgment unit (285) determines the quality of the DUT based on the test results derived from the result of image processing. The judgment unit (285) can derive the test results of the test items corresponding to the image processing from the data representing the result of the image processing. The judgment unit (285) can derive a test result (e.g., pass / fail) by performing a predetermined operation (e.g., comparison with a reference value) on the result of the image processing. The judgment unit (285) can determine the quality of the DUT based on whether the test results of each test item satisfy a predetermined acceptance criterion (e.g., a criterion that the test results of all test items are pass). The judgment unit (285) can perform a judgment for each DUT.

[0070] Meanwhile, the structure of the test device (10) shown in FIGS. 1 and 2 is an example. The test device (10) may have a structure according to the method of testing (wafer testing, chip testing, IC / LSI testing, etc.), the type of testing (functional testing, parametric testing, etc.), and the scale of testing. Also, for example, the image processing device (194) may be installed at a location away from the main body of the test device (10) instead of being placed inside the main frame (190), and may be connected to the main body of the test device (10) via a communication network. The image processing device (194) may be realized by a cloud server capable of communicating with the main body of the test device (10) via the Internet. Additionally, the memory unit (235), the capture unit (230), and the signal transmitter (250) may not be built into the capture module (200), and the acquisition unit (265) and the image processing engine (270) may not be built into the image processing device (194).

[0071] According to the above test device (10), each of the plurality of acquisition units (265) that acquire data files from the detachably connected memory unit (235) changes the allocation of each memory unit (235) to each image processing engine (270) according to the connection type between the plurality of memory units (235) and the plurality of acquisition units (265). Accordingly, by changing the connection type between the plurality of memory units (235) and the plurality of acquisition units (265), the allocation of the memory unit (235) to the image processing engine (270), and furthermore the allocation of data files, can be flexibly changed.

[0072] In addition, since at least two image processing engines (270) have different processing performance for data processing, by changing the connection type of multiple memory units (235) and multiple acquisition units (265), data processing of each data file can be performed by an image processing engine (270) having processing performance suitable for data processing.

[0073] In addition, since the multiple image processing engines (270) perform image processing on image data included in the data file, the allocation of the image processing engines (270) that perform image processing for each data file can be flexibly changed by changing the connection type of the multiple memory units (235) and the multiple acquisition units (265).

[0074] In addition, since a data file containing image data acquired from a separate imaging device is stored in each of the multiple memory units (235), the allocation of the image processing engine (270) that performs image processing for each imaging device that generates the data file can be flexibly changed.

[0075] Additionally, the acquisition unit (265) receives data files from a reference number of memory units (235) by means of a detachably connected signal transmitter (250) among a plurality of signal transmitters (250) each connected to a reference number of memory units (235) (in this embodiment, as an example, 4). Accordingly, data files from a plurality of memory units (235) can be supplied to a single image processing engine (270) to perform data processing.

[0076] In addition, since the plurality of signal transmitters (250) and the plurality of signal transmitters (290) are connected via a plurality of communication lanes, the communication of data files can be accelerated.

[0077] In addition, since the multiple acquisition units (265) acquire data files from the multiple memory units (235) via optical communication, the communication of the data files can be accelerated.

[0078] In addition, based on the test results derived from the image processing results, the quality of the imaging device as a DUT is determined, so the imaging device can be tested.

[0079] FIG. 3 illustrates the test flow of a test device (10) according to the present embodiment. In step 300 (S300), the test device (10) is configured according to the DUT. Specifically, a rotating device (180) rotates the test head (150) to a maintenance position. A light source (170) according to the DUT is mounted on the test head (150). Various test modules (160) selected according to the type and number of DUTs are inserted into the test head (150) from the upper side in the maintenance position. To each signal transmitter (250) of the capture module (200) as a test module (160), one of the signal transmitters (290) of the image processing device (194) is connected by the user in any connection form. Additionally, a Hi-Pix (140) and a performance board (130) according to the DUT are mounted and fixed on the upper surface of the test head (150). A probe card (104) and a connection unit (120) according to the DUT are installed in the prober device (100). When the configuration of the test device (10) is complete, the rotating device (180) rotates the test head (150) to the test position.

[0080] Here, when signal transmitters (250, 290) are connected, each of the plurality of acquisition units (265) can change the allocation of each memory unit (235) to each image processing engine (270) according to the connection type between the plurality of memory units (235) and the plurality of acquisition units (265). Each of the plurality of acquisition units (265) can change the allocation in the current test flow with respect to the allocation in the previous test flow, and whenever the connection type is changed, the allocation can be changed according to the connection type after the change.

[0081] Each capture unit (230) can specify a port (281) linked up to each of the plurality of ports (231) in the corresponding capture unit (230) (in the present embodiment, a port (281) linked up via a signal transmitter (250, 290) as an example). Likewise, each CAPIF (280) can specify a port (231) linked up to each of the plurality of ports (281) in the corresponding CAPIF (280) (in the present embodiment, a port (231) linked up via a signal transmitter (290, 250) as an example). If the port (281) is an input / output port, each CAPIF (280) can specify a port (231) and a port (281) linked up to each of the plurality of ports (281) in the corresponding CAPIF (280). Confirmation of the link-up can be performed by outputting a doorbell signal from each port and receiving an ACK signal from the port of the output. Unique identification information may be assigned to each of the port (231) and port (281) in the doorbell signal and the ACK signal, and each port (231, 281) can identify the link-up counterpart from the corresponding identification signal. When the ports (281) are connected to each other by connecting the signal transmitters (290), a doorbell signal may be output from one port (281) to the other port (281) and an ACK signal may be returned from the other port (281). Additionally, a doorbell signal may be output from the other port (281) to one port (281) and an ACK signal may be returned from one port (281). In the case where the ports (281) are connected by connecting the signal transmitters (290) to each other, these two ports (281) may be ports (281) provided in separate CAPIF (280).When ports (281) are linked together, each CAPIF (280) can be configured to receive a data file from which port (281) and output a data file received from which port (281) through user operation involving a system controller (192), etc. Accordingly, in one CAPIF (280), a data file input from one port (281) is output from another port (281) and transmitted to another CAPIF (280).

[0082] In S310, the prober device (100) connects one or more DUTs to be tested among the DUTs formed on the test specimen (20) to the probe card (104) of the test device (10). Specifically, the prober device (100) transports the test specimen (20) and places it on the stage (102). The prober device (100) moves the stage (102) in a horizontal direction (also indicated as "XY direction") to align the position of the DUT to be tested on the test specimen (20) with the probe card (104), and then moves the stage (102) upward in a vertical direction (also indicated as "Z direction") to electrically connect each electrode of the DUT to be tested with each probe (106) of the probe card (104).

[0083] In S320, the light source (170) emits test light under the control of the system controller (192). The light tube (175), Hi-Pix (140), performance board (130), connection unit (120), and probe card (104) pass the test light. Accordingly, the test device (10) irradiates the test light onto the DUT.

[0084] In S330, the test module (160) used for controlling the DUT receives control from the system controller (192) and instructs the DUT to set up for imaging and to capture the test light. Accordingly, the DUT captures an image of the test light.

[0085] In S340, the test module (160) used for controlling the DUT receives control from the system controller (192) and outputs image data or metadata of the captured image from the DUT. The capture block (210) within the capture module (200) acquires output data from the DUT. When testing multiple captured images by aggregating them, the test device (10) repeats the processing from S320 to S340 while changing at least one of the light intensity, color, or light emission pattern of the test light as needed. The capture block (210) within the capture module (200) sequentially receives and aggregates the data files of each captured image.

[0086] In S350, the image processing device (194) tests the DUT by receiving and examining a data file containing image data acquired by the capture module (200).

[0087] Specifically, each acquisition unit (265) acquires a data file from a memory unit (235) that is detachably connected via a signal transmitter (250, 290) and supplies it to a corresponding image processing engine (270). Each acquisition unit (265) can acquire a data file from the corresponding memory unit (235) as a new data file is stored in the corresponding memory unit (235). By repeating the operation of S350 via S360 or S370 described later, a plurality of acquisition units (265), each detachably connected to a memory unit (235) that stores a data file output from the DUT, can acquire a data file from the corresponding memory unit (235).

[0088] Each capture unit (230) of the data file transmitter can output a common data file from the multiple ports (231) when the ports (281) of different acquisition units (265) among the multiple acquisition units (265) are linked up with respect to the multiple ports (231) in the capture unit (230). In this case, a single data file can be supplied from a single capture unit (230) to each separate acquisition unit (265).

[0089] Each capture unit (230) may output separate data segments extracted from a single data file from the respective multiple ports (231) when the port (281) of a common acquisition unit (265) among the multiple acquisition units (265) is linked up with respect to the multiple ports (231) of the respective capture unit (230) (see FIG. 4 and 5 described later). In this case, the separate data segments output from each port (231) are synthesized after being acquired by the common acquisition unit (265), and the original data file can be reproduced, and a single data file can be supplied from a single capture unit (230) to a single acquisition unit (265). Each capture unit (230) may generate data segments by dividing the data file. For example, when generating two data segments, data of 2n bits (where n is an integer) may be divided into a first n-bit data segment and a second n-bit data segment, or into a data segment consisting of odd-numbered bits and a data segment consisting of even-numbered bits. Each data segment may be assigned identification information of the original data file. Each capture unit (230) may output data segments from the corresponding multiple ports as the multiple ports (231) are linked up to the port (281) of the common acquisition unit (265). In addition, or instead, each capture unit (230) may output data segments from the corresponding multiple ports as the multiple ports (231) are linked up to the port (281) of the common acquisition unit (265), and also as a setting by user operation involving a system controller (192), etc. The process of reconstructing a data file by synthesizing data segments can be performed in CAPIF (280).CAPIF (280) can temporarily store one of the data segments acquired earlier among two data segments generated from a single data file, and perform synthesis upon acquiring the other data segment. Meanwhile, the synthesis of data segments may be performed by an image processing engine (270).

[0090] In the case where each capture unit (230) has one port (281) in one CAPIF (280) (also referred to as the "first CAPIF (280)") linked up to one port (281) in another CAPIF (280) (also referred to as the "second CAPIF (280)"), and furthermore, among the multiple ports (231) in the said capture unit (230), the port (281) of the first CAPIF (280) is linked up to some of the ports (231) (also referred to as the "first port (231)") and the port (281) of the second CAPIF (280) is linked up to other of the ports (231) (also referred to as the "second port (231)") (see FIG. 6 described later), separate data extracted from a single data file according to a setting by user operation Segments may be output from the corresponding first port (231) and the corresponding second port (231). Each capture unit (230) may be configured to output separate data segments extracted from a single data file from two ports (231) by user operation involving a system controller (192), etc. In this case, one data segment output from the first port (231) may be supplied to the first CAPIF (280), while another data segment output from the second port (231) may be transmitted from the second CAPIF (280) and supplied to the first CAPIF (280), and each data segment extracted from a single data file may be collected in the first CAPIF (280). In addition, one data segment output from the second port (231) is supplied to the second CAPIF (280), while another data segment output from the first port (231) is transmitted from the first CAPIF (280) and supplied to the second CAPIF (280), and each data segment extracted from one data file can be gathered in the second CAPIF (280).In these cases, separate data segments extracted from a single data file are synthesized after being acquired by CAPIF (280), and a single data file can be reproduced. Accordingly, a single data file can be supplied from a single capture unit (230) to a single acquisition unit (265).

[0091] The image processing engine (270) performs data processing (image processing as an example in this embodiment) on a data file supplied from the acquisition unit (265) according to an algorithm predetermined by a test program, etc. By repeating the operation of S350 via S360 or S370 described later, a plurality of image processing engines (270) provided corresponding to each of the acquisition units (265) can perform data processing on a data file acquired by the corresponding acquisition unit (265).

[0092] And, the judgment unit (285) determines the quality of the DUT based on the test results derived from the result of image processing. The judgment unit (285) can determine the quality of the DUT by determining whether the result of image processing on the captured image satisfies the image quality standard. Meanwhile, the test device (10) may perform an electrical test of the DUT in addition to the optical input test of the DUT.

[0093] In S360, the test device (10) determines whether the test of the DUT to be tested has been completed. If the test of the DUT has not been completed (No in S360), the test device (10) proceeds to S320 and performs test processing from S320 to S350 for the next test item. In the test processing from S320 to S350 for the next test item, the same test module (160) may be used, or a separate test module (160) may be used. If the test of the DUT has been completed (Yes in S360), the test device (10) proceeds to S370.

[0094] In S370, the test device (10) determines whether the test of the entire DUT of the test subject (20) has been completed. If the test of the entire DUT has not been completed (No in S370), the test device (10) proceeds to S310 and performs the test processing from S310 to S360. In the test processing from S310 to S360 for a new DUT, the same test module (160) may be used, or a separate test module (160) may be used. If the test of the entire DUT has been completed (Yes in S370), the test device (10) terminates the test processing of the test subject (20). Meanwhile, the prober device (100) can remove the test subject (20) that has completed testing and place the next test subject (20) on the stage (102). Accordingly, the test device (10) can perform the test treatment of the present drawing on the following test subject (20).

[0095] According to the above operation, the capture unit (230) provided in each memory unit (235) identifies a port (281) linked up to each of the plurality of ports (231) in the capture unit (230), and the CAPIF (280) provided in each acquisition unit (265) identifies a port (231) linked up to each of the plurality of ports (281) in the CAPIF (280). Accordingly, each of the plurality of ports (231) and the plurality of ports (281) can reliably identify a connection target.

[0096] Additionally, each port (281) provided in the acquisition unit (265) is an input / output port capable of inputting and outputting data, and each CAPIF (280) specifies a port (231) and a port (281) linked up for each of the multiple ports (281) in the corresponding CAPIF (280). Accordingly, a port (281) of one CAPIF (280) and a port (281) of another CAPIF (280) can be connected, and data can be communicated using the port (281) of one CAPIF (280) as the port (281) and the port (281) of the other CAPIF (280) as the port (231). Accordingly, the allocation of the memory unit (235) for the image processing engine (270) can be changed more flexibly.

[0097] Additionally, when ports (281) of different acquisition units (265) are linked up with each other for multiple ports (231) in the capture unit (230), a common data file is output from the corresponding multiple ports (231). Thus, a single data file can be output to separate acquisition units (265), and data processing can be performed by separate image processing engines (270) respectively.

[0098] Additionally, when a port (281) of a common acquisition unit (265) is linked up with a plurality of ports (231) in the capture unit (230), a separate data segment extracted from a single data file is output from the corresponding plurality of ports (231). Therefore, since separate data segments from a single data file can be output from the plurality of ports (231) to the common acquisition unit (265), the communication time of the data file can be shortened.

[0099] In addition, when a port (281) in the first CAPIF (280) is linked up to a port (281) in the second CAPIF (280), and when a port (281) of the first CAPIF (280) is linked up to a port (231) in the first CAPIF (280) among a plurality of output ports (231) in the capture unit (230), and a port (281) of the second CAPIF (280) is linked up to a port (231) in the second CAPIF (280), then a separate data segment extracted from a single data file is output from the first and second ports (231) by the corresponding capture unit (230). Therefore, since separate data segments from a single data file can be output from a plurality of ports (231) to a common acquisition unit (265), the communication time of the data file can be shortened.

[0100] Meanwhile, regarding the above operation, each acquisition unit (265) is described as changing the allocation of each memory unit (235) to each image processing engine (270) according to the connection type between the plurality of memory units (235) and the plurality of acquisition units (265) in S300, but whenever the processing of S310 or S320 is executed, the allocation of each memory unit (235) to each image processing engine (270) may also be changed according to the connection type between the plurality of memory units (235) and the plurality of acquisition units (265).

[0101] Next, the connection type of the memory unit (235) and the acquisition unit (265) will be explained. Meanwhile, in FIGS. 4 to 7 described later, the illustration of the capture module (200) is simplified for the sake of illustration simplification. Also, only some ports (231) are labeled, and the other ports (231) are labeled.

[0102] FIG. 4 shows an example of a connection type between a memory unit (235) and an acquisition unit (265). In the example of the figure, each capture module (200) is equipped with four sets of memory units (235) and capture units (230) and two signal transmitters (250) (also referred to as "signal transmitters (250-1 to 2)"), and the image processing device (194) is equipped with four sets of acquisition units (265) and an image processing engine (270).

[0103] The four sets of memory units (235) and capture units (230) of each capture module (200) are divided into two groups (G) of two sets each (also referred to as “Groups (G-1 to 2)”). The two memory units (235) of Group (G-1) are each connected to a signal transmitter (250-1) via a capture unit (230), and the two memory units (235) of Group (G-2) are each connected to a signal transmitter (250-2) via a capture unit (230), and the signal transmitters (250-1, 250-2) are detachably connected to a signal transmitter (290) of a separate acquisition unit (265). Accordingly, two memory units (235) and one acquisition unit (265) for each group (G) are detachably connected, and an image processing engine (270) corresponding to the acquisition unit (265) is assigned to the two memory units (235). Then, a data file read from these two memory units (235) is supplied to the image processing engine (270) to be assigned.

[0104] In the example of the present drawing, since the port (281) of a common CAPIF (280) is linked up to the two ports (231) of each capture unit (230), each capture unit (230) can divide a single data file read from the memory unit (235) to create two data segments and output them from separate ports (231). In this case, the CAPIF (280) or the image processing engine (270) combines the two data segments to reproduce the original data file.

[0105] Each image processing engine (270) of the image processing device (194) performs image processing on each data file read from the two memory units (235) for each group (G) and supplies the result to the judgment unit (285). Meanwhile, in the example of the present drawing, among the two signal transmitters (290) of each acquisition unit (265), one of the signal transmitters (290) may not be connected to the signal transmitters (250, 290).

[0106] FIG. 5 shows another example of the connection type between the memory unit (235) and the acquisition unit (265). In the example of the figure, one capture module (200) is equipped with eight sets of memory units (235) and capture units (230), and four signal transmitters (250) (also referred to as "signal transmitters (250-1 to 4)"), and the image processing device (194) is equipped with four sets of acquisition units (265) and image processing engines (270).

[0107] The eight sets of memory units (235) and capture units (230) of each capture module (200) are divided into two groups (G) of four sets each (also referred to as "groups (G-1 to 2)"). The four memory units (235) of group (G-1) are each connected to signal transmitters (250-1, 250-2) via capture units (230), and the four memory units (235) of group (G-2) are each connected to signal transmitters (250-3, 250-4) via capture units (230). The two signal transmitters (250-1, 250-2) and the two signal transmitters (250-3, 250-4) are detachably connected to signal transmitters (290) of separate acquisition units (265). Accordingly, four memory units (235) and one acquisition unit (265) for each group (G) are detachably connected, and an image processing engine (270) corresponding to the acquisition unit (265) is assigned to each of the four memory units (235). Then, a data file read from these four memory units (235) is supplied to the image processing engine (270) to be assigned.

[0108] In the example of the present drawing, since the port (281) of a common CAPIF (280) is linked up to the two ports (231) of each capture unit (230), each capture unit (230) can divide a single data file read from the memory unit (235) to create two data segments and output them from separate ports (231). In this case, the CAPIF (280) or the image processing engine (270) combines the two data segments to reproduce the original data file.

[0109] Each image processing engine (270) of the image processing device (194) performs image processing on each data file read from the four memory units (235) of each group (G) and supplies the result to the judgment unit (285).

[0110] FIG. 6 shows another example of the connection form between the memory unit (235) and the acquisition unit (265). In the example of the figure, one capture module (200) is equipped with eight sets of memory units (235) (also referred to as "memory units (235-1 to 8)") and a capture unit (230), and four signal transmitters (250) (also referred to as "signal transmitters (250-1 to 4)"), and the image processing device (194) is equipped with four sets of acquisition units (265) (also referred to as "acquisition units (265-1 to 4)") and an image processing engine (270) (also referred to as "image processing engine (270-1 to 4)"). The acquisition unit (265-1) has two signal transmitters (290) (also referred to as "signal transmitters (290-1 to 2)") and a CAPIF (280-1), the acquisition unit (265-2) has two signal transmitters (290) (also referred to as "signal transmitters (290-3 to 4)") and a CAPIF (280-2), the acquisition unit (265-3) has two signal transmitters (290) (also referred to as "signal transmitters (290-5 to 6)") and a CAPIF (280-3), and the acquisition unit (265-4) has two signal transmitters (290) (also referred to as "signal transmitters (290-7 to 8)") and a CAPIF (280-4). Each CAPIF (280) has eight ports (281). Meanwhile, in the description of the drawing, the eight ports (281) of each CAPIF (280) are also referred to as the first to eighth ports (281) in order from the top in the drawing.

[0111] The eight sets of memory units (235) and capture units (230) of the capture module (200) are divided into four groups (G) of two sets each (also referred to as “Groups (G-1 to 4)”). Two memory units (235-1, 235-2) of Group (G-1) and two memory units (235-3, 235-4) of Group (G-2) are each connected to signal transmitters (250-1, 250-2) via capture units (230), and two memory units (235-5, 235-6) of Group (G-3) and two memory units (235-7, 235-8) of Group (G-4) are each connected to signal transmitters (250-3, 250-4) via capture units (230).

[0112] The signal transmitter (250-1) and the signal transmitter (250-2) are detachably connected to the signal transmitters (290-1, 290-3) of the separate acquisition units (265-1, 265-2). A total of eight ports (281) connected to these two signal transmitters (290-1, 290-3) (i.e., the first to fourth ports (281) in CAPIF (280-1) and the first to fourth ports (281) in CAPIF (280-2)) may be input ports.

[0113] The remaining two signal transmitters (290-2, 290-4) in the acquisition unit (265-1, 265-2) are detachably connected to each other. Among the four ports (281) connected to the signal transmitter (290-2) (i.e., the 5th to 8th ports (281) in CAPIF (280-1)), the 5th and 6th ports (281) may be input ports, and the 7th and 8th ports (281) may be output ports. Among the four ports (281) connected to the signal transmitter (290-4) (i.e., the 5th to 8th ports (281) in CAPIF (280-2)), the 5th and 6th ports (281) may be output ports, and the 7th and 8th ports (281) may be input ports.

[0114] CAPIF (280-1) can be configured to receive data files from the first, second, fifth, and sixth ports (281) among the first to eighth ports (281) provided in the CAPIF (280-1) through user operation involving a system controller (192), and to output data files received from the third and fourth ports (281) through the seventh and eighth ports (281). CAPIF (280-2) can be configured to receive data files from the third, fourth, seventh, and eighth ports (281) among the first to eighth ports (281) provided in the CAPIF (280-2) through user operation involving a system controller (192), and to output data files received from the first and second ports (281) through the fifth and sixth ports (281). Meanwhile, in the present drawing, data files read from memory units (235-1 to 235-4) are supplied to each of the four ports (281) connected to the signal transmitters (290-1, 290-3) (i.e., the first to fourth ports (281) in CAPIF (280-1) and the first to fourth ports (281) in CAPIF (280-2)). Accordingly, CAPIF (280-1) can introduce data files read from two memory units (235-1, 235-2) of group (G-1) and transmit data files read from two memory units (235-3, 235-4) of group (G-2) to CAPIF (280-2). Likewise, CAPIF (280-2) can introduce data files read from two memory units (235-3, 235-4) of group (G-2) and transmit data files read from two memory units (235-1, 235-2) of group (G-1) to CAPIF (280-1). As a result, two memory units (235) of each group (G) and one acquisition unit (265) are detachably connected, and an image processing engine (270) corresponding to the acquisition unit (265) is assigned to the two memory units (235).And, data files read from these two memory units (235) are supplied to the image processing engine (270) that is the target of allocation.

[0115] In the example of the present drawing, the fifth to eighth ports (281) of CAPIF (280-2) are linked up to the fifth to eighth ports (281) of CAPIF (280-2), and also, among the two ports (231) of each capture unit (230) of group (G-1) and G-2, the fifth to eighth ports (281) of CAPIF (280-1) are linked up to one port (231), and the fifth to eighth ports (281) of CAPIF (280-2) are linked up to the other port (231). Accordingly, each capture unit (230) of group (G-1) and G-2 can be configured to output separate data segments extracted from a single data file from the two ports (231). Accordingly, one data segment output from the first port (231) is supplied to CAPIF (280-1), while another data segment output from the second port (231) can be transmitted from CAPIF (280-2) and supplied to CAPIF (280-1), and each data segment extracted from one data file can be gathered in CAPIF (280-1). In addition, one data segment output from the second port (231) is supplied to CAPIF (280-2), while another data segment output from the first port (231) can be transmitted from CAPIF (280-1) and supplied to CAPIF (280-2), and each data segment extracted from one data file can be gathered in CAPIF (280-2). In this case, CAPIF (280) or an image processing engine (270) combines two data segments to reconstruct the original data file.

[0116] Each image processing engine (270) of the image processing device (194) performs image processing on a data file read from two memory units (235) for each group (G) and supplies the result to a judgment unit (285).

[0117] Meanwhile, in this drawing, the connection point for the signal transmitter (250-3 to 4) is omitted, but the signal transmitter (250-3 to 4) and the signal transmitter (290-5 to 8) can be connected in the same way as the connection between the signal transmitter (250-1 to 2) and the signal transmitter (290-1 to 4).

[0118] FIG. 7 shows another example of the connection form between the memory unit (235) and the acquisition unit (265). In the example of the drawing, one capture module (200) is equipped with eight sets of memory units (235) and capture units (230), and four signal transmitters (250) (also referred to as "signal transmitters (250-1 to 4)"), and the image processing device (194) is equipped with four sets of acquisition units (265) (also referred to as "acquisition units (265-1 to 4)") and an image processing engine (270).

[0119] The eight sets of memory units (235) and capture units (230) of each capture module (200) are divided into two groups (G) of four sets each (also referred to as "groups (G-1 to 2)"). The four memory units (235) of group (G-1) are each connected to signal transmitters (250-1, 250-2), and the four memory units (235) of group (G-2) are each connected to signal transmitters (250-3, 250-4). The signal transmitter (250-1) is detachably connected to a signal transmitter (290) on one side of the acquisition unit (265-1), and the signal transmitter (250-3) is detachably connected to a signal transmitter (290) on the other side of the acquisition unit (265-1). Accordingly, eight memory units (235) and one acquisition unit (265) are detachably connected, and an image processing engine (270) corresponding to the acquisition unit (265) is assigned to each of the eight memory units (235). Then, data files read from these eight memory units (235) are supplied to the image processing engine (270) to be assigned.

[0120] Each image processing engine (270) of the image processing device (194) performs image processing on each data file read from the eight memory units (235) and supplies the result to the judgment unit (285). Meanwhile, in the example of the drawing, the signal transmitter (290) may not be connected to the signal transmitters (250-2, 250-4). Also, although the connection point for the signal transmitter (290) of the acquisition unit (265-2 ~ 4) is not shown, it may be connected to the signal transmitter (250) of another capture module (200) in the same way as the signal transmitter (290) of the acquisition unit (265-1).

[0121] Meanwhile, in the above embodiment, although it has been described as if the data file includes image data, it may be omitted. In this case, the test device (10) may include a processing unit that performs data processing on the data file instead of the image processing engine (270).

[0122] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, wherein a block may represent (1) a step of a process in which an operation is executed or (2) a section of a device having the role of executing an operation. Specific steps and sections may be implemented by dedicated circuits, programmable circuits supplied with computer-readable instructions stored on a computer-readable medium, and / or processors supplied with computer-readable instructions stored on a computer-readable medium. Dedicated circuits may include digital and / or analog hardware circuits and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuits may include reconfigurable hardware circuits such as logic AND, logic OR, logic XOR, logic NAND, logic NOR, and other logic operations, flip-flops, registers, memory elements such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc.

[0123] A computer-readable medium may include any type of device capable of storing instructions executed by a suitable device, and as a result, the computer-readable medium having instructions stored therein comprises a product that includes instructions that can be executed to create means for executing operations specified in a flowchart or block diagram. Examples of computer-readable media may include electronic memory media, magnetic memory media, optical memory media, electronic memory media, semiconductor memory media, etc. More specific examples of computer-readable media may include floppy disks (trademark), diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital multi-purpose disc (DVD), Blu-ray (trademark) disc, memory sticks, integrated circuit cards, etc.

[0124] Computer-readable instructions may include any one of source code or object code described in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or object-oriented programming languages ​​such as Smalltalk (trademark), JAVA (trademark), C++, etc., and conventional procedural programming languages ​​such as the "C" programming language or the same programming language.

[0125] Computer-readable instructions are provided to a processor or programmable circuit of a programmable data processing device, such as a general-purpose computer, a special-purpose computer, or another computer, either locally or via a wide-area network (WAN) such as a local area network (LAN) or the internet, and may be executed to create means for executing operations specified in a flowchart or block diagram. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

[0126] FIG. 8 illustrates an example of a computer (2200) in which a plurality of aspects of the present invention may be implemented wholly or partially. A program installed in the computer (2200) may enable the computer (2200) to function as an operation or one or more sections of the device associated with an embodiment of the present invention, or to execute said operation or said one or more sections, and / or enable the computer (2200) to execute a process or steps of said process according to an embodiment of the present invention. Such a program may be executed by a CPU (2212) to enable the computer (2200) to execute a specific operation associated with some or all of the blocks of the flowchart and block diagram described herein.

[0127] A computer (2200) according to the present embodiment includes a CPU (2212), RAM (2214), a graphics controller (2216), and a display device (2218), and they are interconnected by a host controller (2210). The computer (2200) also includes input / output units such as a communication interface (2222), a hard disk drive (2224), a DVD-ROM drive (2226), and an IC card drive, and they are connected to the host controller (2210) via an input / output controller (2220). The computer also includes legacy input / output units such as a ROM (2230) and a keyboard (2242), and they are connected to the input / output controller (2220) via an input / output chip (2240).

[0128] The CPU (2212) operates according to a program stored in the ROM (2230) and RAM (2214) and controls each unit accordingly. The graphics controller (2216) acquires image data generated by the CPU (2212) in a frame buffer provided in the RAM (2214) or in itself, and causes the image data to be displayed on a display device (2218).

[0129] The communication interface (2222) communicates with other electronic devices via a network. The hard disk drive (2224) stores programs and data used by the CPU (2212) in the computer (2200). The DVD-ROM drive (2226) reads programs or data from the DVD-ROM (2201) and provides programs or data to the hard disk drive (2224) via RAM (2214). The IC card drive reads programs and data from the IC card and / or writes programs and data to the IC card.

[0130] The ROM (2230) stores within it a boot program executed by the computer (2200) upon activation and / or a program dependent on the hardware of the computer (2200). The input / output chip (2240) can also connect various input / output units to the input / output controller (2220) via a parallel port, serial port, keyboard port, mouse port, etc.

[0131] A program is provided by a computer-readable medium such as a DVD-ROM (2201) or an IC card. The program is read from the computer-readable medium and installed in a hard disk drive (2224), RAM (2214), or ROM (2230), which is also an example of a computer-readable medium, and is executed by a CPU (2212). Information processing described within these programs is read by a computer (2200) and results in a linkage between the program and the various types of hardware resources. A device or method may be configured to realize the manipulation or processing of information according to the use of the computer (2200).

[0132] For example, when communication is performed between a computer (2200) and an external device, the CPU (2212) may execute a communication program loaded in RAM (2214) and, based on the processing described in the communication program, command a communication interface (2222) to perform communication processing. Under the control of the CPU (2212), the communication interface (2222) reads transmission data stored in a transmission buffer processing area provided in a recording medium such as RAM (2214), a hard disk drive (2224), a DVD-ROM (2201), or an IC card, and transmits the read transmission data to a network or writes received data received from the network to a reception buffer processing area, etc. provided on the recording medium.

[0133] Additionally, the CPU (2212) can read all or a necessary portion of a file or database stored in an external recording medium, such as a hard disk drive (2224), a DVD-ROM drive (2226) (DVD-ROM (2201)), an IC card, etc., into the RAM (2214), and perform various types of processing on the data in the RAM (2214). The CPU (2212) then writes back the processed data to the external recording medium.

[0134] Various types of information, such as various types of programs, data, tables, and databases, are stored in a recording medium and can be processed. The CPU (2212) can execute various types of processing on data read from RAM (2214), including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, searching for / replacing information, etc., as described throughout this disclosure and specified by a program instruction sequence, and writes back the results to RAM (2214). Additionally, the CPU (2212) can search for information in files, databases, etc., within the recording medium. For example, when multiple entries are stored in a recording medium, each having an attribute value of a first attribute associated with an attribute value of a second attribute, the CPU (2212) can search among the multiple entries for an entry that matches a condition in which the attribute value of the first attribute is specified, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0135] The program or software module described above may be stored on a computer (2200) or on a computer-readable medium near the computer (2200). Additionally, a recording medium such as a hard disk or RAM provided within a server system connected to a dedicated communication network or the Internet may be used as a computer-readable medium, and accordingly, the program may be provided to the computer (2200) via the network.

[0136] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the embodiments. It is evident from the description in the claims that forms with such modifications or improvements may also be included within the technical scope of the present invention.

[0137] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the device, system, program, and method shown in the claims, specification, and drawings is not specifically specified as “preceding” or “preceding,” and that the output of a preceding process can be realized in any order unless the output of a preceding process is used in a subsequent process. Even if the operation flow in the claims, specification, and drawings is described using terms such as “first,” or “next,” for convenience, this does not mean that it is mandatory to carry out the process in this order. Explanation of the symbols

[0138] 10 Test device 20 test subjects 100 Prober Device Stage 102 104 probe card 106 probes 108 Shading Units 120 connection units 130 Performance Boards 140 Hi-Fix 150 test heads 160 test modules 170 light sources 175 telescope tube 180-degree rotation device 190 mainframe 192 System Controller 194 Image processing device 200 capture modules 210 Capture Block 220 Image data receiver 230 Capture Units Port 231 235 Memory Department 240 memory banks 250 signal transmitters 255 module IF 265 Acquisition Department 270 Image Processing Engine 280 CAPIF Port 281 285 Judgment Division 290 signal transmitter 2200 computer 2201 DVD-ROM 2210 Host Controller 2212 CPU 2214 RAM 2216 Graphics Controller 2218 Display Device 2220 I / O Controller 2222 communication interface 2224 hard disk drive 2226 DVD-ROM drive 2230 ROM 2240 I / O chip 2242 keyboard

Claims

Claim 1 A system comprising a plurality of memory units each storing a data file, a plurality of acquisition units each detachably connected to any one of the plurality of memory units and acquiring a data file from the corresponding memory unit, and a plurality of processing units each provided in correspondence with any one of the plurality of acquisition units and performing data processing on the data file acquired by the corresponding acquisition unit, wherein each of the plurality of acquisition units changes the allocation of each memory unit to each processing unit according to the connection type between the plurality of memory units and the plurality of acquisition units. Claim 2 A system according to claim 1, further comprising: a reading unit provided in each of the plurality of memory units and having a plurality of output ports, reading a data file from a corresponding memory unit and outputting it from the corresponding plurality of output ports; and an introduction unit provided in each of the plurality of acquisition units and having a plurality of input ports, introducing at least a portion of a data file output from one of the output ports through the corresponding plurality of input ports, wherein each reading unit specifies an input port linked up to each of the plurality of output ports in the reading unit, and each introduction unit specifies an output port linked up to each of the plurality of input ports in the introduction unit. Claim 3 In paragraph 2, each input port is an input / output port capable of inputting and outputting data, and each introduction part specifies an output port linked up with each of the plurality of input / output ports in the introduction part and an input / output port, in a system. Claim 4 In paragraph 3, each reading unit is linked up to one of the input / output ports in one of the input units, and also, among the plurality of output ports in the reading unit, the input port of one of the input units is linked up to some of the output ports, and the input port of the other input unit is linked up to some of the output ports, and the input port of the other input unit is linked up to some of the output ports, and according to a setting by user operation, a separate data segment extracted from a single data file is output from some of the output ports and from some of the output ports. Claim 5 In paragraph 2, each reading unit outputs a common data file from the plurality of output ports when the input ports of different acquisition units among the plurality of acquisition units are linked up with respect to the plurality of output ports in the corresponding reading unit. Claim 6 A system according to paragraph 2, wherein each reading unit outputs a separate data segment extracted from a single data file from the corresponding output port when the input port of a common acquisition unit among the corresponding acquisition units is linked up with respect to the corresponding output port of the corresponding reading unit. Claim 7 A system according to claim 1, wherein among the plurality of memory units, a plurality of first communication units are additionally provided that are connected to a reference number of memory units, and the acquisition unit has a plurality of second communication units that receive a data file from the reference number of memory units by interposing a first communication unit that is detachably connected to each of the plurality of first communication units. Claim 8 In paragraph 7, each first communication unit and each second communication unit is connected via a plurality of communication lanes, in a system. Claim 9 In claim 1, the system wherein the plurality of acquisition units acquire a data file from the memory unit via optical communication. Claim 10 In claim 1, a system in which at least two of the plurality of processing units have different processing performances for the data processing. Claim 11 A system according to any one of claims 1 to 10, wherein the data file includes image data, and the plurality of processing units perform image processing on the image data included in the data file. Claim 12 In claim 11, the system wherein the plurality of memory units each store a data file containing image data acquired from a separate imaging device. Claim 13 In claim 12, each imaging device is a device under test, and the system further comprises a judgment unit that determines the quality of the device under test based on a test result derived from the result of image processing. Claim 14 A method comprising: a plurality of acquisition devices, each detachably connected to one of the plurality of memory devices that each store a data file, an acquisition step of acquiring a data file from the said memory device; and a processing step of each of the plurality of processing devices, each provided in correspondence with one of the plurality of acquisition devices, performing data processing on the data file acquired by the corresponding acquisition device, wherein, prior to the acquisition step, each of the plurality of acquisition devices changes the allocation of each memory device to each processing device according to the connection type between the plurality of memory devices and the plurality of acquisition devices. Claim 15 A computer program stored on a medium, which is executed on a computer and functions as a computer having a plurality of memory units each storing a data file, a plurality of acquisition units each detachably connected to any one of the plurality of memory units and acquiring a data file from the memory unit, and a plurality of processing units each provided in correspondence with any one of the plurality of acquisition units and performing data processing on the data file acquired by the corresponding acquisition unit, wherein each of the plurality of acquisition units changes the allocation of each memory unit to each processing unit according to the connection type between the plurality of memory units and the plurality of acquisition units.

Images