Device of semiconductor for protecting gate destruction with periphery region trench

Abstract

The present invention relates to a semiconductor device that prevents gate destruction through a peripheral region trench. When a bias voltage is applied to the gate or collector during a reliability test of a power device, the gate oxide layer is destroyed due to the phenomenon of an electric field being concentrated at the end of the gate trench, leading to a reliability failure. In particular, since the area around the gate trench forming a spherical junction in the peripheral region is vulnerable, the invention relates to a semiconductor device having a structure that prevents the phenomenon of electric field concentration by inserting a trench connected to an emitter or source around the spherical junction and connecting it to a ground (GND) or negative (-) polarity voltage terminal.

Description

Technology Field

[0001] The present invention relates to a semiconductor device that prevents gate destruction through a periphery region trench. More specifically, when a bias voltage is applied to a gate or collector during a reliability test of a power device, the gate oxide layer is destroyed due to the phenomenon of an electric field being concentrated at the end of the gate trench, leading to a reliability failure. In particular, since the periphery of the gate trench forming a spherical junction in the periphery region is vulnerable, the invention relates to a semiconductor device having a structure that prevents the phenomenon of the electric field being concentrated by inserting a trench connected to an emitter (or source) around the spherical junction and connecting it to a voltage terminal of ground (GND) or negative polarity. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) devices combine the gate structure of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the current regulation function of BJT (Bipolar Junction Transistor), playing an important role in various fields such as power converters, electric vehicles, hybrid vehicles, and thermal management systems.

[0003] IGBT applications require higher rated voltages, and various types of IGBT devices are used to achieve faster switching speeds and lower losses, featuring optimized gate structures, reduced gate capacitance, and enhanced current handling capabilities.

[0004] IGBT devices have the advantages of being capable of high-capacity power control and conversion, handling high voltage and high current, safe operation due to insulated gates, built-in internal protection functions to protect the device in conditions such as overcurrent, overheating, and short circuits, relatively easy control and driving, and fast switching speed while having low losses.

[0005] In addition, wide bandgap materials such as SiC (Silicon Carbide) and GaN (Gallium Nitride) are being adopted in high-performance and high-frequency applications because they provide superior electrical characteristics, such as higher breakdown voltage, lower switching losses, and the ability to operate at higher temperatures, compared to conventional silicon-based IGBTs.

[0006] SiC and GaN MOSFETs often have trench structures to provide excellent performance in power electronics and high-frequency applications, and IGBT devices are power semiconductor transistors composed of four layers (PNPN) that are controlled using a voltage applied to a metal oxide gate and often have a flat or plate-like structure.

[0007] A trench structure is a semiconductor device structure that allows the channel region to be penetrated deeply. By increasing the movement path of charge carriers, it can increase transmission speed and improve the performance of electronic devices.

[0008] However, for IGBT devices as well, by using a combination of trench gate and field stop structures to reduce switching losses and make them thinner, inherent parasitic NPN behavior is suppressed, thereby lowering the device's saturation voltage and total resistance and improving overall power density.

[0009] Basically, IGBTs have a problem where power loss can occur in the gate-channel region, and in particular, significant losses can occur because the electric field is concentrated in this area.

[0010] In addition, in compound semiconductors, the gate oxide layer electrically insulates the gate and the channel and allows the conductivity of the channel to be controlled according to the gate voltage. Therefore, if the gate oxide layer is absent, current leakage occurs between the gate and the channel, which reduces the power efficiency of the device and may not respond sensitively to the gate voltage, making the operation of the device unpredictable and thus reducing the reliability of the device.

[0011] Therefore, while not all semiconductor devices require a gate oxide layer, it is essential for some devices, such as SiC MOSFETs and IGBTs. Ultimately, if the gate oxide layer is destroyed, the operation of the semiconductor device becomes unreliable.

[0012] IGBT devices must operate stably for a long period, especially in harsh environments where high temperatures, transient voltages, and current surges occur. Therefore, ensuring long-term reliability and durability is a challenging task that requires robust device design, material selection, and rigorous testing.

[0013] Therefore, when applying a bias voltage to the gate or collector during reliability testing of power devices, there are many cases where the gate oxide layer is destroyed due to the phenomenon of the electric field concentrating at the end of the gate trench, leading to reliability failure. Among the peripheral regions of semiconductor devices, the area around the gate trench forming a spherical junction is particularly vulnerable.

[0014] In order to solve these problems, the present invention proposes a structure that prevents the phenomenon of electric field concentration by inserting a trench connected to an emitter or source around a gate trench forming a spherical junction in the peripheral region of a semiconductor device and connecting it to a ground (GND) or negative (-) polarity voltage terminal.

[0015] Next, we will briefly explain the prior art existing in the technical field of the present invention, and then describe the technical details that the present invention aims to achieve differently from the said prior art.

[0016] First, Korean Registered Patent No. 0297705 (May 24, 2001) relates to a power semiconductor device having low on-resistance and high breakdown voltage. By forming the body region in a stripe shape and connecting both corners of the stripe to the frame region, it prevents the concentration of the electric field at the corners and edges of the body region. Furthermore, by forming the body regions with a narrow spacing, it aims to increase the breakdown voltage of the device, improve the switching speed, and reduce the on-resistance.

[0017] In addition, to suppress the phenomenon of electric field concentration in the gate oxide of a MOSFET, designs are known to improve breakdown voltage characteristics by suppressing the electric field applied to the gate oxide through the addition of a Bottom protection p-well (BPW), a Double trench MOSFET structure, and a p-shielding structure to a SiC trench MOSFET.

[0018] As seen in the known technologies, trench MOSFETs have improved electrical characteristics compared to planar MOSFETs, but the electric field is concentrated at the corners of the gate oxide. This electric field concentration causes the gate oxide to break down and leads to reliability issues due to electrical defects in the gate oxide. Therefore, it is recognized that a design for a structure that disperses the electric field of the gate oxide is necessary to ensure the safety and productivity of trench MOSFETs, but there are many different solutions.

[0019] Unlike the prior art, the present invention aims to prevent the phenomenon of electric fields concentrating at the gate trench end by inserting a trench connected to an emitter or source around the periphery of a semiconductor device to be connected to a ground (GND) or negative (-) polarity voltage terminal, as the periphery of the gate trench forming a spherical junction in the periphery of the semiconductor device is vulnerable to electric field concentration. Thus, there is a clear difference from the structures presented in the prior art in terms of the approach and means of solving the problem. The problem to be solved

[0020] The present invention was created to solve the above-mentioned problems and aims to provide a structure that prevents gate destruction through a peripheral region trench in a semiconductor device and a method for manufacturing the same.

[0021] In addition, the present invention aims to prevent the destruction of the gate oxide layer due to the phenomenon in which an electric field is concentrated at the end of the gate trench when a bias voltage is applied to the gate or collector during a reliability test of a power device.

[0022] In addition, the present invention aims to prevent the phenomenon in which an electric field is concentrated at the end of a gate trench forming a spherical junction in the peripheral region of a semiconductor device by inserting a trench connected to an emitter or source along the periphery of the spherical region and connecting it to a ground (GND) or negative (-) polarity voltage terminal. means of solving the problem

[0023] A semiconductor device according to one embodiment of the present invention comprises at least one gate trench; and at least one dummy trench formed along the periphery of the gate trench; wherein the dummy trench is configured to prevent an electric field from concentrating at the end of the gate trench.

[0024] In addition, the semiconductor device further comprises at least one emitter trench or source trench; and the dummy trench is characterized by being connected to the emitter trench or source trench.

[0025] In addition, the semiconductor device further comprises a gate oxide layer on the inner outer edge of the gate trench; and the dummy trench is characterized by preventing the gate oxide layer from being destroyed due to the concentration of the electric field when a bias voltage is applied to the gate or collector electrode of the semiconductor device to test reliability.

[0026] The above dummy trench is configured to be connected to a ground (GND) or negative (-) polarity voltage terminal, thereby preventing the electric field from concentrating at the end of the gate trench, and thus preventing the gate oxide layer from being destroyed and causing reliability issues.

[0027] In addition, the semiconductor device is characterized by forming a spherical junction including a gate trench in a spherical region and inserting a dummy trench connected to an emitter or source terminal in a peripheral region of the spherical junction.

[0028] In addition, the semiconductor device is characterized by leaving a poly pattern on a part of a dummy trench located in the area around the end of the active region so that the dummy trench is electrically connected to an emitter or source terminal.

[0029] The above semiconductor device is characterized by being configured such that the inner gate trench of the active region is electrically connected to the gate terminal through the poly of the gate bus line.

[0030] The above semiconductor device is characterized by being configured such that the width and depth of the gate trench of the active region and the emitter or source trench of the peripheral region are formed identically.

[0031] The above semiconductor device is characterized by being configured such that the width, depth, or set of the emitter or source trench in the surrounding region is larger than the gate trench in the active region.

[0032] Meanwhile, a method for manufacturing a semiconductor device according to another embodiment of the present invention comprises the steps of: configuring at least one gate trench; and configuring at least one dummy trench along the periphery of the gate trench; wherein the dummy trench is configured to prevent an electric field from concentrating at the end of the gate trench.

[0033] In addition, the method for manufacturing the semiconductor device further comprises the step of configuring at least one emitter trench or source trench; wherein the dummy trench is connected to the emitter trench or source trench.

[0034] In addition, the method for manufacturing the semiconductor device further includes the step of forming a gate oxide layer on the inner outer edge of the gate trench; and the dummy trench is characterized by preventing the gate oxide layer from being destroyed due to the concentration of the electric field when a reliability test is performed by applying a bias voltage to the gate or collector electrode of the semiconductor device.

[0035] In addition, the method for manufacturing the semiconductor device further comprises the steps of: forming a spherical junction including a gate trench in a spherical region; and configuring a dummy trench connected to an emitter or source by inserting it into a peripheral region of the spherical junction.

[0036] In addition, the method for manufacturing the semiconductor device further comprises the step of configuring the dummy trench to be electrically connected to an emitter or source terminal by leaving a poly pattern in a part of the dummy trench in the area around the end of the active region.

[0037] In addition, the method for manufacturing the semiconductor device further comprises the step of configuring the inner gate trench of the active region to be electrically connected to the gate terminal through the poly of the gate bus line.

[0038] The method for manufacturing the above semiconductor device is characterized by configuring the gate trench of the active region and the emitter or source trench of the peripheral region to have the same width and depth.

[0039] The method for manufacturing the above semiconductor device is characterized by configuring the emitter or source trench to have a width, depth, or a combination thereof that is larger than the gate trench of the active region. Effects of the invention

[0040] As described above, a semiconductor device according to one embodiment of the present invention has the effect of preventing gate destruction through a surrounding region trench.

[0041] In addition, the semiconductor device according to the present invention has the effect of avoiding the phenomenon where the electric field is concentrated at the end of the gate trench when a bias voltage is applied to the gate or collector during a reliability test of a power device.

[0042] In addition, the semiconductor device according to the present invention has the effect of preventing the destruction of the gate oxide layer due to the phenomenon in which an electric field is concentrated at the end of the gate trench forming a spherical junction in the surrounding region.

[0043] In addition, the semiconductor device according to the present invention has the effect of reducing the probability of reliability failure when a bias voltage is applied to the gate or collector during a reliability test.

[0044] In addition, the semiconductor device according to the present invention has the effect of compensating for vulnerability to gate trenches, particularly around spherical regions.

[0045] In addition, the semiconductor device according to the present invention has the effect of preventing the phenomenon of an electric field being concentrated at the end of the gate trench by inserting a dummy trench around the outer edge of the gate trench around the square region and connecting it to an emitter or source terminal so as to be connected to a ground (GND) or negative (-) polarity voltage terminal. Brief explanation of the drawing

[0046] FIG. 1 is a drawing illustrating the peripheral region structure of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a diagram illustrating the phenomenon in which an electric field is concentrated at the gate trench end in a spherical region of an IGBT semiconductor device according to one embodiment of the present invention. FIG. 3 is a diagram illustrating the impact ionization process in a semiconductor device according to one embodiment of the present invention. FIG. 4 is a plan view showing a structure in which a dummy trench is created around the outer perimeter of a gate trench in a semiconductor device according to one embodiment of the present invention and connected to an emitter or source trench. FIG. 5 is a plan view showing a structure in which a dummy trench is created around the outer perimeter of a gate trench in a semiconductor device according to another embodiment of the present invention and connected to an emitter or source trench. FIG. 6 is a diagram showing a structure in which a plurality of gate trenches in an active region are electrically connected to a gate terminal through a gate poly in a semiconductor device according to an embodiment of the present invention, and a structure in which a plurality of dummy trenches formed in a peripheral region are connected to a poly pattern of a plurality of emitter or source trenches in the active region. FIG. 7 is a diagram showing examples of structures in a semiconductor device according to an embodiment of the present invention, where the width of the gate trench and the emitter trench of the active region are the same, and where the width of the emitter or source trench is wider than the gate trench of the active region. Specific details for implementing the invention

[0047] Hereinafter, preferred embodiments of a semiconductor device that prevents gate destruction through a peripheral region trench according to the present invention will be described in detail with reference to the attached drawings. Identical reference numerals in each drawing indicate identical components. Furthermore, specific structural or functional descriptions regarding embodiments of the present invention are merely illustrative for the purpose of explaining embodiments according to the present invention. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined in this specification, it is preferable not to interpret them in an ideal or overly formal sense. Additionally, although the present invention is described using two microphones, it is acceptable to use two or more microphones.

[0048] In the present invention, since the dummy trench formed in the surrounding area is connected to the emitter or source trench, the dummy trench is described as being identical to the emitter or source trench. However, in the present invention, it is also possible to configure the dummy trench to be connected to ground through a separate terminal without connecting it to the emitter or source trench.

[0049] FIG. 1 is a drawing illustrating the peripheral region structure of a semiconductor device according to one embodiment of the present invention.

[0050] As illustrated in FIG. 1, the semiconductor device (1) is composed of a plane region (30), a cylindrical region (C, cylindrical region) (20), and a spherical region (S, spherical region) (10). A spherical junction is formed in the spherical region (S) (10). The present invention aims to identify problems occurring in the spherical junction and to present a method and structure for solving related problems.

[0051] In general, in semiconductor devices, during the drive-in diffusion process in which particles or molecules move from a high-concentration region to a low-concentration region to form a junction, the materials forming the junction meet or interact with each other to form a junction, the drive-in diffusion occurs not only in the vertical direction but also in the horizontal direction, resulting in the formation of a one-dimensional planar junction, a two-dimensional cylindrical junction, and a three-dimensional spherical junction.

[0052] The cylindrical region (20) is a region formed in a cylindrical shape in the upper, lower, left, and right regions of the semiconductor device, the spherical region (10) is a region formed in a spherical shape at each edge, and the planar region (30) is a region formed in a planar shape on the front and back sides of the semiconductor device (1). A spherical junction including a trench is formed in the spherical region (10) of the above edge.

[0053] Next, we intend to explain the phenomenon in which the electric field is concentrated at the gate trench termination of a square junction in a square region of an IGBT semiconductor device.

[0054] FIG. 2 is a diagram illustrating the phenomenon in which an electric field is concentrated at the gate trench end in a spherical region of an IGBT semiconductor device according to one embodiment of the present invention.

[0055] First, IGBTs are semiconductor devices widely used for switching and amplifying power, and are referred to as insulated gate bipolar transistors. IGBTs combine the advantages of MOSFETs and bipolar junction transistors (BJTs), making them suitable for high-voltage and high-current applications.

[0056] The structure of an IGBT device consists of three layers in which P-type and N-type semiconductors alternately form two junctions, and the terminal connections are the collector, emitter, and gate.

[0057] The collector and emitter terminals are connected to the power circuit, and the gate terminal controls the current flow through the device. The IGBT operates in a manner similar to a BJT, controlling a larger current flow between the collector and emitter terminals with a small gate current. However, unlike the BJT, the IGBT has a gate structure similar to a MOSFET, which provides voltage-controlled switching characteristics and can efficiently control high power levels.

[0058] IGBTs offer various advantages in power electronics applications, such as high rated voltage, low on-state voltage drop, fast switching speed, and high thermal stability. They are commonly used in applications such as motor drives, power supplies, renewable energy systems, traction systems, and industrial control.

[0059] As shown in FIG. 2, in the structure of an IGBT semiconductor device according to one embodiment of the present invention, the polysilicon gate is configured as a trench.

[0060] An emitter electrode is formed on the upper side, and a metal barrier layer called a barrier metal layer is provided below it. A gate electrode is formed below the barrier metal layer, and a polysilicon gate is configured in a trench shape below it.

[0061] A gate oxide layer is formed on the inner wall of the gate trench to form an insulating film. Diffusion layers are formed on both sides of the gate trench, and an emitter layer is formed next to the diffusion layers.

[0062] Next, a P base layer is formed, and below it is an n layer where carriers are stored, N - Layer, N + P passing through N layers including the layer + A sub-layer is formed and the above P + The sublayer is connected to the collector electrode.

[0063] In such cases, if the gate trench is configured in a spherical region among the surrounding regions, the electric field is concentrated at the outer edge of the spherical region, and the gate oxide layer is destroyed.

[0064] In semiconductor devices, the gate trench has a structure where the gate surrounds the channel, so the electric field tends to concentrate around the gate trench in a rectangular region. The gate trench serves to define the path for current flow, and when a voltage is applied to the gate, the electric field around the gate increases, causing the electric field to concentrate inside the gate trench. This plays an important role in controlling the movement of electrons in the device region that contacts the gate.

[0065] Therefore, since the concentration of the electric field in the gate trench is one of the critical factors controlling the operation of semiconductor devices, the design and optimization of the gate trench have a significant impact on the performance and characteristics of the semiconductor device.

[0066] As the electric field is concentrated at the end of the gate trench in this way, the problem of the gate oxide layer being destroyed occurs.

[0067] In order to solve this problem, the present invention is configured to provide an additional separate dummy trench that goes around the outer edge of the gate trench.

[0068] FIG. 3 is a diagram illustrating the impact ionization process in a semiconductor device according to one embodiment of the present invention.

[0069] The aforementioned impact ionization is a phenomenon in which high-energy carriers under a high electric field collide with other carriers in semiconductor devices handling high voltage or high current, generating new electron-hole pairs before energy loss occurs. It is a process in which, if one free electron collides with a shared electron, two free electrons and one hole are generated.

[0070] When free electrons generated by such impact ionization are accelerated by an electric field and cause another ionization collision, an avalanche breakdown phenomenon occurs.

[0071] Therefore, in semiconductor devices handling high voltage or high current, impact ionization causes a rapid increase in electrons and can alter characteristics such as current or voltage.

[0072] As illustrated in FIG. 3, it can be seen that in a semiconductor device according to one embodiment of the present invention, impact ionization intensifies as it moves from the active region to the peripheral region. The fact that the color changes to a deeper red as it moves toward the peripheral region of the semiconductor device confirms that the electric field is applied more strongly in the spherical region (10) among the peripheral regions of the semiconductor device.

[0073] In semiconductor devices, particles generated by lattice vibrations interact with other particles or structures to transfer energy, and the scattering rate (cm²) -3 * sec -1 This represents ), and as it moves toward the surrounding area, 10 at the end of the gate trench +18It exhibits a scattering rate close to .

[0074] Discharging such a strong electric field to the outside in some way helps the performance and safety of the semiconductor device.

[0075] On the other hand, in the active region, the electric field formed at the end of the gate trench is in a much better state compared to the electric field formed at the end of the gate trench in the surrounding region.

[0076] Therefore, in the present invention, a separate dummy trench is provided along the distortion centered on the gate trench, and then the dummy trench is connected to an emitter or source terminal that serves as a ground (GND) or negative (-) voltage terminal to reduce the diffusion effect of the electric field.

[0077] FIG. 4 is a plan view showing a structure in which a dummy trench (11) is created around the outer perimeter of a gate trench (12) in a semiconductor device (1) according to one embodiment of the present invention and connected to an emitter or source terminal.

[0078] As illustrated in FIG. 4, a dummy trench (11) according to one embodiment of the present invention is configured to surround the end of a gate trench (12). A plurality of gate trenches (12) are formed along the surrounding area (200), and in this case, more electric fields are concentrated starting from the outermost one, so there is a high possibility that the gate oxide layer (13) will be destroyed.

[0079] In order to prevent destruction of the gate oxide layer (13) of the gate trench (12), a dummy trench (11) is formed to surround the gate trench (12) near the surrounding region (200) and connected to the emitter or source terminal of the active region (100). Since the electric field concentrated in the gate trench (12) is discharged through the emitter or source trench (11) to the ground or negative (-) voltage terminal, the risk of the gate trench (12) being destroyed is greatly reduced.

[0080] In one embodiment of the present invention, a case is illustrated in which the arrangement of gate trenches is formed sequentially in a rounded shape.

[0081] FIG. 5 is a plan view showing a structure in which a dummy trench (11) is created around the outer perimeter of a gate trench (12) in a semiconductor device (1) according to another embodiment of the present invention and connected to an emitter or source terminal.

[0082] As illustrated in FIG. 5, a gate trench (12) according to another embodiment of the present invention is configured in a stepped manner, and in this case, a dummy trench (11) is configured to surround the outer edge of the gate trench to mitigate the concentration of the electric field in the gate trench (12).

[0083] These dummy trenches (11) are connected to the emitter or source terminals, and since the emitter or source trenches act as ground, the electric field concentrated in the gate trenches is discharged to the ground or negative (-) voltage terminal through the emitter or source terminals connected to the dummy trenches.

[0084] The present invention includes all various embodiments of the gate trench model, including configuring the electric field concentrated at the end of the gate trench to be discharged through the emitter or source terminal through a dummy trench.

[0085] Meanwhile, it is disclosed in advance that the shape of the dummy trench, the spacing from the gate trench, or the thickness and depth of the dummy trench can be configured variably according to the application field, specifications, or requirements of the semiconductor device. In other words, it is natural to consider that various variations regarding such shape, spacing, thickness, and depth are included within the technical scope of the present invention.

[0086] FIG. 6 is a diagram showing a structure in which a plurality of gate trenches (12) in an active region (100) of a semiconductor device according to one embodiment of the present invention are electrically connected to a gate terminal through a gate poly, and a plurality of dummy trenches (11) formed in a peripheral region (200) are connected to a plurality of emitter or source poly (14) patterns of the active region (100).

[0087] As shown in FIG. 6, a poly pattern is left in a portion of the end trench of the active region and electrically connected to the emitter or source terminal. At this time, there may be multiple trenches. In addition, the inner trench of the active region is electrically connected to the gate terminal with a poly of the gate bus line.

[0088] The above poly can be used as an electrode for the emitter or source or as an electrode for the gate, and is applied as a thin layer on the emitter trench (11) and gate trench (12), respectively, and can be oxidized or doped in various forms.

[0089] Here, "poly" refers to polysilicon, which has the ability to conduct electricity. However, pure polysilicon has very low electrical conductivity, making it unsuitable for transporting electrons. Therefore, polysilicon is typically manufactured as doped polysilicon to improve electrical conductivity.

[0090] Therefore, the electrical properties of polysilicon vary significantly depending on the doping level. Electrical conductivity can be controlled through an appropriate doping process, which is important for obtaining desired electrical characteristics in semiconductor devices.

[0091] Furthermore, polysilicon welds well with other materials and is used in the manufacture of various semiconductor devices. In particular, it is useful for forming structures by combining with other materials in semiconductor processes.

[0092] Furthermore, polysilicon possesses the characteristic of operating stably at high temperatures. This enables reliable operation even when the operating temperature of semiconductor devices is high.

[0093] Due to these electrical properties, polysilicon is used in various parts of semiconductor devices, and is particularly widely used in areas where electrical characteristics are critical, such as gate electrodes.

[0094] FIG. 7 is a drawing showing an example of a structure in which the width of the gate trench (12) of the active region (100) and the emitter trench (11) of the peripheral region (200) are the same in a semiconductor device (1) according to one embodiment of the present invention, and the width of the emitter or source trench (11) of the peripheral region (200) is wider than the width of the gate trench (12) of the active region (100).

[0095] As illustrated in FIG. 7, the width of the gate trench (12) formed in the active region (100) and the width and depth of the emitter trench (11) formed in the surrounding region (200) may be configured to be the same (Edge 1), or the width and depth of the emitter trench (11) in the surrounding region (200) may be configured to be deeper and wider than the gate trench (12) in the active region (100) (Edge 2).

[0096] Typically, when the edges of a semiconductor device are configured in the shape of edge 2, the phenomenon of electric field concentration in the spherical junction becomes more severe. However, if the trench width is wide, it is easier to configure the depth more deeply. In this case, a problem may arise where the widths of the dummy trench and the gate trench of the active region differ from each other.

[0097] Meanwhile, since the trench formed at the outer edge of the gate trench in the surrounding area is a dummy trench, the electric field that was concentrated at the end of the gate trench near the surrounding area escapes to the emitter or source of the active area through the dummy trench. Therefore, having a wider and deeper dummy trench structure can be advantageous in preventing the concentration of the electric field.

[0098] In other words, depending on the application, it is desirable to select and configure a more efficient structure by considering the ease of the manufacturing process and the ability to block the concentration of electric fields between edge 1 and edge 2.

[0099] Meanwhile, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes the step of configuring at least one gate trench separately from the sequence of processes and the step of configuring at least one dummy trench along the periphery of said gate trench, wherein the dummy trench is configured to prevent a phenomenon in which an electric field is concentrated at the end of said gate trench.

[0100] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention further includes the step of configuring at least one emitter trench or source trench, wherein the dummy trench is configured to be connected to the emitter trench or source trench. Of course, in the present invention, the dummy trench may be connected to ground through a separate terminal.

[0101] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention further includes the step of forming a gate oxide layer on the inner outer edge of the gate trench, and the dummy trench is configured to prevent the gate oxide layer from being destroyed due to the concentration of the electric field when a bias voltage is applied to the gate or collector electrode of the semiconductor device to test reliability.

[0102] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention further includes the steps of forming a spherical junction including a gate trench in a spherical region and inserting a dummy trench connected to an emitter or source into a peripheral region of the spherical junction.

[0103] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention further includes the step of configuring a poly pattern to be left on a part of an end dummy trench of an active region so that the dummy trench is electrically connected to an emitter or source terminal.

[0104] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention further includes the step of configuring an inner gate trench of an active region to be electrically connected to a gate terminal through a polygon of a gate bus line.

[0105] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes configuring the gate trench of an active region and the emitter or source trench of a peripheral region to have the same width and depth, or configuring the emitter or source trench of a peripheral region to have a larger width, depth, or combination thereof than the gate trench of an active region.

[0106] As described above, a semiconductor device according to one embodiment of the present invention prevents gate destruction through a dummy trench in the surrounding region, and can avoid the phenomenon of an electric field concentrating at the end of the gate trench when a bias voltage is applied to the gate or collector during a reliability test of a power device, and can prevent the gate oxide layer from being destroyed due to the phenomenon of an electric field concentrating at the end of the gate trench forming a square junction in the surrounding region, and can reduce the probability of reliability failure when a bias voltage is applied to the gate or collector during a reliability test, and can particularly compensate for the vulnerability of the gate trench around the square region, and has the effect of preventing the phenomenon of an electric field concentrating at the end of the gate trench by inserting a dummy trench on the outer edge of the gate trench around the square region and connecting it to an emitter or source terminal to be connected to a ground (GND) or negative (-) polarity voltage terminal.

[0107] As described above, the present invention has been explained with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the technical scope of protection of the present invention should be determined by the following claims. Explanation of the symbols

[0108] 1: Semiconductor device 10: Spherical region 11: Dummy / Emitter / Source Trench 12: Gate Trench 13: Gate oxide layer 14: Dummy / Emitter / Source poly 20: Cylindrical region 30: Planar region 100: Active area 200: Surrounding area

Claims

Claim 1 A semiconductor device comprising: at least one gate trench provided in an active region of the semiconductor device; and at least one dummy trench formed along a peripheral region of the gate trench; wherein the semiconductor device is configured such that a poly pattern is left on the upper side of the dummy trench located in the peripheral region at the end of the active region, so that the at least one dummy trench is electrically connected to an emitter terminal or a source terminal through the poly pattern, and the dummy trench is configured to be connected to the emitter terminal or the source terminal and connected to a ground (GND) or a negative (-) polarity voltage terminal, thereby preventing the phenomenon of an electric field being concentrated at the end of the gate trench, so as to prevent the gate oxide layer formed on the inner outer side of the gate trench from being destroyed due to the concentration of the electric field when a bias voltage is applied to the gate or collector electrode of the semiconductor device to test reliability. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 A semiconductor device according to claim 1, wherein the dummy trench is configured to be inserted into a peripheral region of a spherical junction formed including a gate trench in a spherical region of the semiconductor device and connected to the emitter terminal or source terminal. Claim 6 delete Claim 7 A semiconductor device according to claim 1, wherein the semiconductor device is configured such that the inner gate trench of the active region is electrically connected to the gate terminal through a polygon of the gate bus line. Claim 8 A semiconductor device according to claim 1, wherein the semiconductor device is configured such that the width and depth of the gate trench of the active region and the dummy trench of the surrounding region are formed identically. Claim 9 A semiconductor device according to claim 1, wherein the semiconductor device is configured such that the width, depth, or set thereof of a dummy trench in a peripheral region is formed larger than the gate trench in the active region. Claim 10 A method for manufacturing a semiconductor device comprising: a step of configuring at least one gate trench in an active region of a semiconductor device; and a step of configuring at least one dummy trench along a peripheral region of the gate trench; wherein the semiconductor device is configured such that a poly pattern is left on the upper side of the dummy trench located in the peripheral region at the end of the active region, so that the at least one dummy trench is electrically connected to an emitter terminal or a source terminal through the poly pattern, and the dummy trench is configured to be connected to the emitter terminal or the source terminal and connected to a ground (GND) or a negative (-) polarity voltage terminal, thereby preventing the phenomenon of an electric field being concentrated at the end of the gate trench, so as to prevent the gate oxide layer formed on the inner outer edge of the gate trench from being destroyed due to the concentration of the electric field when a bias voltage is applied to the gate or collector electrode of the semiconductor device to test reliability.

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