Image sensor

Abstract

According to embodiments of the present invention, an image sensor comprises a substrate having a first pixel region and a second pixel region; and a microlens layer disposed on a first surface of the substrate, wherein the microlens layer comprises: a first lens pattern provided on the first pixel region of the substrate; and a second lens pattern provided on the second pixel region of the substrate, wherein the width of the first pixel region is greater than the width of the second pixel region, and the height of the first lens pattern may be greater than the height of the second lens pattern.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to a microlens layer of an image sensor and a method for forming the same. Background Technology

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. A CMOS type image sensor is abbreviated as CIS (CMOS Image Sensor). The CIS comprises a plurality of pixels arranged in two dimensions. Each pixel includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal. The problem to be solved

[0003] The problem that the present invention aims to solve is to improve the image quality of an image sensor.

[0004] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] An image sensor is provided. According to embodiments of the present invention, the image sensor comprises a substrate having a first pixel region and a second pixel region; and a microlens layer disposed on a first surface of the substrate, wherein the microlens layer comprises: a first lens pattern provided on the first pixel region of the substrate; and a second lens pattern provided on the second pixel region of the substrate, wherein the width of the first pixel region is greater than the width of the second pixel region, and the height of the first lens pattern may be greater than the height of the second lens pattern.

[0006] According to embodiments of the present invention, an image sensor comprises: a substrate having a first pixel region and a second pixel region; photoelectric conversion regions provided within the first and second pixel regions of the substrate, respectively; and a microlens layer disposed on a first surface of the substrate and covering the first pixel region and the second pixel region of the substrate, wherein the microlens layer comprises a first lens pattern having a first curved surface provided on the first pixel region of the substrate; and a second lens pattern having a second curved surface provided on the second pixel region of the substrate, wherein at the point where the first curved surface and the second curved surface meet, the width of the first lens pattern is greater than the width of the second lens pattern, and the height of the first lens pattern may be greater than the height of the second lens pattern.

[0007] According to embodiments of the present invention, an image sensor comprises: a substrate having a first pixel region and a second pixel region having a width different from that of the first pixel region; photoelectric conversion regions respectively provided within the first and second pixel regions of the substrate; a separation pattern interposed between the photoelectric conversion regions within the substrate; a color filter disposed on a first surface of the first substrate; a microlens layer disposed on the color filter; a first gate pattern provided within the first pixel region of the substrate and disposed on a second surface of the substrate; a second gate pattern provided within the second pixel region of the substrate and disposed on the second surface of the substrate; and a wiring layer disposed on the second surface of the substrate and covering the first gate pattern and the second gate pattern, wherein the substrate comprises: a first floating diffusion region provided within the first pixel region of the substrate; and a second floating diffusion region provided within the second pixel region of the substrate, and the microlens layer comprises: a first lens pattern provided on the first pixel region of the substrate; and a second lens pattern provided on the second pixel region of the substrate. The method includes a flattening layer interposed between the color filter and the first lens pattern and between the color filter and the second lens pattern, wherein the first lens pattern and the second lens pattern are placed on the color filter, the width of the first pixel area is greater than the width of the second pixel area, and the height of the first lens pattern may be greater than the height of the second lens pattern. Effects of the invention

[0008] According to the present invention, the curvature of the upper surface of the first lens pattern is adjusted so that the amount of light incident on the first photoelectric conversion region can be increased. Accordingly, the optical characteristics of the image sensor can be improved. Brief explanation of the drawing

[0009] FIG. 1 is a circuit diagram of a pixel of an image sensor according to embodiments. FIG. 2a is a plan view showing an image sensor according to embodiments. Figure 2b is a cross-section taken along line I-II of Figure 2a. FIGS. 3a to 3g are drawings for explaining a method of manufacturing an image sensor according to embodiments. FIG. 4a is a drawing illustrating an image sensor according to embodiments. FIG. 4b is a drawing illustrating an image sensor according to embodiments. FIG. 4c is a drawing illustrating an image sensor according to embodiments. Specific details for implementing the invention

[0010] In this specification, the same reference numerals throughout the text may refer to the same components. An image sensor according to embodiments of the present invention is described.

[0012] FIG. 1 is a circuit diagram of a pixel of an image sensor according to embodiments.

[0013] Referring to FIG. 1, each pixel of the image sensor may include a photoelectric conversion region (PD), a transfer transistor (Tx), a source follower transistor (Sx), a reset transistor (Rx), and a select transistor (Ax). The transfer transistor (Tx), the source follower transistor (Sx), the reset transistor (Rx), and the select transistor (Ax) may each include a transfer gate (TG), a source follower gate (SG), a reset gate (RG), and a select gate (AG).

[0014] The photoelectric conversion region (PD) may be a photodiode comprising an n-type impurity region and a p-type impurity region. The floating diffusion region (FD) may function as the drain of a transfer transistor (Tx). The floating diffusion region (FD) may function as the source of a reset transistor (Rx). The floating diffusion region (FD) may be electrically connected to the source follower gate (SG) of the source follower transistor (Sx). The source follower transistor (Sx) is connected to a selection transistor (Ax).

[0015] The operation of the image sensor is explained as follows with reference to FIG. 1. First, in a state where light is blocked, a power supply voltage (V) is applied to the drain of the reset transistor (Rx) and the drain of the source follower transistor (Sx). DD ) is applied and the reset transistor (Rx) is turned on to release the charges remaining in the floating diffusion region (FD). Then, the reset transistor (Rx) is turned off, and when external light is incident on the photoelectric conversion region (PD), electron-hole pairs are generated in the photoelectric conversion region (PD). Holes move to the P-type impurity region of the photoelectric conversion region (PD), and electrons move to the n-type impurity region and accumulate. When the transfer transistor (Tx) is turned on, charges such as these electrons and holes are transferred to the floating diffusion region (FD) and accumulated. The gate bias of the source follower transistor (Sx) changes in proportion to the amount of accumulated charge, causing a change in the source potential of the source follower transistor (Sx). At this time, when the select transistor (Ax) is turned on, a signal due to the charge is read through the column line.

[0016] A wiring line may be electrically connected to at least one of a transfer gate (TG), a source follower gate (SG), a reset gate (RG), and a select gate (AG). The wiring line is connected to the drain of the reset transistor (Rx) or the drain of the source follower transistor (Sx) with a power supply voltage (V DD It can be configured to apply ). The wiring line may include a column line connected to a select transistor (Ax). The wiring line may be a conductive structure (830) described later in FIG. 2b.

[0017] Although FIG. 1 illustrates a pixel having one photoelectric conversion region (PD) and four transistors (Tx, Rx, Ax, Sx), embodiments according to the present invention are not limited thereto. For example, pixels may be provided in plurality, and a reset transistor (Rx), a source follower transistor (Sx), or a select transistor (Ax) may be shared by neighboring pixels. Accordingly, the integration density of the image sensor may be improved.

[0019] FIG. 2a is a plan view showing an image sensor according to embodiments. FIG. 2b is a cross-section taken along line I-II of FIG. 2a.

[0020] Referring to FIGS. 2a and 2b, the image sensor may include a substrate (100), a pixel separation pattern (210), an element separation pattern (220), a first gate pattern (G1), a second gate pattern (G2), a wiring layer (800), an insulating layer (400), a protective film (430), a fence pattern (450), color filters (CF), and a microlens layer (500).

[0021] The substrate (100) may include a pixel array region and an edge region in a planar view. The pixel array region may be positioned in the center portion of the substrate (100) in a planar view. The edge region may surround the pixel array region. Pad terminals (not shown) may be provided on the edge region. The pixel array region may include a plurality of unit pixel groups (UPG), and each of the unit pixel groups (UPG) may include a first pixel region (PX1) and a second pixel region (PX2). The unit pixel groups (UPG) may form an array. The pixels described with reference to FIG. 1 may be formed in the first and second pixel regions (PX1, PX2) of the substrate (100), respectively. For example, components of the pixels may be provided on the first pixel region (PX1) and the second pixel region (PX2), respectively. Each of the first and second pixel regions (PX1, PX2) may output a corresponding photoelectric signal from incident light. According to the embodiments, the first pixel area (PX1) may function as a main pixel, and the second pixel area (PX2) may function as an auxiliary pixel. For example, during image sensor operation, the photoelectric signal output from the first pixel area (PX1) in each of the unit pixel groups (UPG) may be corrected using the photoelectric signal output from the second pixel area (PX2). Accordingly, the optical characteristics and sensing accuracy of the image sensor may be improved. However, the function of the second pixel area (PX2) is not limited thereto.

[0022] A plurality of first pixel regions (PX1) may form rows and columns and be arranged two-dimensionally. The rows may be parallel to the first direction (D1). The columns may be parallel to the second direction (D2). The first pixel regions (PX1) may be arranged in the first diagonal direction (D3). The first pixel regions (PX1) may be arranged in the second diagonal direction (D4). In this specification, the first direction (D1) may be parallel to the first surface (100a) of the substrate (100). The second direction (D2) may be parallel to the first surface (100a) of the substrate (100) and may differ from the first direction (D1). For example, the second direction (D2) may be substantially perpendicular to the first direction (D1). The first diagonal direction (D3) is parallel to the first surface (100a) of the substrate (100) and may intersect the first direction (D1) and the second direction (D2). For example, the angle between the first diagonal direction (D3) and the first direction (D1) may be about 45 degrees. The angle between the first diagonal direction (D3) and the second direction (D2) may be about 45 degrees. The second diagonal direction (D4) is parallel to the first surface (100a) and may intersect the first direction (D1), the second direction (D2), and the first diagonal direction (D3). For example, the second diagonal direction (D4) may be substantially perpendicular to the first diagonal direction (D3). The fifth direction (D5) may intersect the first direction (D1), the second direction (D2), the first diagonal direction (D3), and the second diagonal direction (D4). For example, the third direction (D5) may be substantially perpendicular to the first surface (100a) of the substrate (100).

[0023] Each of the first pixel regions (PX1) may have an octagonal shape in a planar view. Each of the first pixel regions (PX1) may have a first width (W11). The first width (W11) may be measured in a first direction (D1) and may be the width on the first surface (100a) of the substrate (100). The first width (W11) may correspond to the gap between two corresponding sidewalls of the separation pattern (210) to be described later.

[0024] Each of the plurality of second pixel regions (PX2) may be surrounded by four adjacent first pixel regions (PX1) in a planar view. The second pixel regions (PX2) may be arranged two-dimensionally along the first direction (D1) and the second direction (D2) in a planar view. The second pixel regions (PX2) may be placed between the first pixel regions (PX1) in the first direction (D1). That is, the first pixel regions (PX1) and the second pixel regions (PX2) may be placed alternately in the first direction (D1). The second pixel regions (PX2) may be placed between the first pixel regions (PX1) in the second direction (D2).

[0025] Each of the second pixel regions (PX2) may have a rectangular shape in a planar view. The size of the second pixel regions (PX2) may be smaller than the size of the first pixel regions (PX1). For example, each of the second pixel regions (PX2) may have a second width (W12). The second width (W12) may be smaller than the first width (W11). The second width (W12) may be the width in the first direction (D1). The second width (W12) may correspond to the gap between two corresponding sidewalls of the separation pattern (210) to be described later, and may be measured on the first surface (100a) of the substrate (100). Additionally, the width of the second pixel regions (PX2) in the second direction (D2) may be smaller than the widths of the first pixel regions (PX1). In this specification, the width relationship of any two components may be compared in the same direction and at the same vertical level.

[0026] According to the embodiments, the planar shape and first width (W11) of the first pixel regions (PX1) and the planar shape and second width (W12) of the second pixel regions (PX2) are adjusted so that the arrangement of the pixel regions (PX1, PX2) can be highly integrated. Accordingly, the optical characteristics of the image sensor can be improved.

[0027] A substrate (100) may have a first surface (100a) and a second surface (100b) facing each other. The first surface (100a) of the substrate (100) may be a rear surface, and the second surface (100b) may be a front surface. Light may be incident on the first surface (100a) of the substrate (100). The substrate (100) may be a semiconductor substrate or an SOI (Silicon on Insulator) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate (100) may further include a group 3 element. The group 3 element may be an impurity of the first conductivity type. The substrate (100) may have the first conductivity type by including the impurity of the first conductivity type. For example, the first type of impurity may include p-type impurities such as aluminum (Al), boron (B), indium (In) and / or gallium (Ga).

[0028] The substrate (100) may include first photoelectric conversion regions (PD1) and second photoelectric conversion regions (PD2). The first and second photoelectric conversion regions (PD1, PD2) may be interposed between a first surface (100a) and a second surface (100b) of the substrate (100). The first photoelectric conversion regions (PD1) may each be provided to first pixel regions (PX1) within the substrate (100). The second photoelectric conversion regions (PD2) may each be provided to second pixel regions (PX2) within the substrate (100). The first and second photoelectric conversion regions (PD1, PD2) may further include a group 5 element. A group 3 element may be an impurity of the second conductivity type. The first and second photoelectric conversion regions (PD1, PD2) may be regions doped with an impurity of the second conductivity type within the substrate (100). The second conductivity type impurity may have a conductivity type opposite to that of the first conductivity type impurity. The second conductivity type impurity may include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. The first and second photoelectric conversion regions (PD1, PD2) may be deeply disposed on the second surface (100b) of the substrate (100).

[0029] Each of the first and second photoelectric conversion regions (PD1, PD2) can perform the same function and role as described in the example of the photoelectric conversion region (PD) of FIG. 1. However, the volumes of the second photoelectric conversion regions (PD2) may be smaller than the volumes of the first photoelectric conversion regions (PD1). For example, the widths of the second photoelectric conversion regions (PD2) may be smaller than the widths of the first photoelectric conversion regions (PD1). The charge storage capacity of the second photoelectric conversion regions (PD2) may be smaller than the charge storage capacity of the first photoelectric conversion regions (PD1). Hereinafter, a singular first pixel region (PX1) and a singular second pixel region (PX2) will be described.

[0030] An isolation pattern (210) is provided within the substrate (100) and may define pixel regions (PX1, PX2). For example, the isolation pattern (210) may be provided between the pixel regions (PX1, PX2) of the substrate (100). The isolation pattern (210) may be a pixel isolation pattern. The isolation pattern (210) may be provided within a first trench (191), and the first trench (191) may be recessed from the second surface (100b) of the substrate (100). The isolation pattern (210) may be a deep trench isolation film. The isolation pattern (210) may further penetrate the first surface (100a) of the substrate (100). The width (W21) of the upper surface of the isolation pattern (210) may be smaller than the width (W22) of the lower surface of the isolation pattern (210). At this time, the upper surface of the separation pattern (210) may be coplanar with the first surface (100a) of the substrate (100). The lower surface of the separation pattern (210) may be opposite to the upper surface.

[0031] The isolation pattern (210) may include an insulating pattern (211), a conductive isolation pattern (215), and a capping pattern (217). The insulating isolation pattern (211) may be provided along the sidewall of the first trench (191). The insulating isolation pattern (211) may include, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). As another example, the insulating isolation pattern (211) may include a plurality of layers, and said layers may include different materials. The insulating isolation pattern (211) may have a lower refractive index than the substrate (100). Accordingly, crosstalk between the first and second pixel regions (PX1, PX2) of the substrate (100) may be prevented / reduced.

[0032] A conductive separation pattern (215) may be provided within an insulating separation pattern (211). An insulating separation pattern (211) may be interposed between the conductive separation pattern (215) and the substrate (100). When the image sensor is in operation, a negative bias voltage is applied to the conductive separation pattern (215) to prevent the occurrence of dark current between the separation pattern (210) and the substrate (100). The conductive separation pattern (215) may be separated from the substrate (100) by the insulating separation pattern (211). Accordingly, the conductive separation pattern (215) may be electrically separated from the substrate (100). The conductive separation pattern (215) may include a crystalline semiconductor material, for example, polysilicon. As an example, the conductive separation pattern (215) may further include a dopant, said dopant may include an impurity of a first conductivity type or an impurity of a second conductivity type. For example, the conductive separation pattern (215) may include doped polysilicon. The lower surface of the conductive separation pattern (215) may be convex upward. However, the shape of the lower surface of the conductive separation pattern (215) is not limited thereto and may be varied in many ways.

[0033] The capping pattern (217) is placed on the lower surface of the conductive separation pattern (215) and may cover the lower sidewall of the insulating separation pattern (211). The capping pattern (217) may fill the lower portion of the first trench (191). The insulating separation pattern (211) may extend further between the substrate (100) and the capping pattern (217). The capping pattern (217) may include, for example, a silicon-containing insulating material (e.g., silicon oxide, tetraethyl orthosilicate (TEOS) and / or silicon oxynitride). As another example, the separation pattern (210) may not include the capping pattern (217), and the lower surface of the conductive separation pattern (215) may be placed at substantially the same level as the second surface (100b) of the substrate (100).

[0034] A first gate pattern (G1) and a second gate pattern (G2) may be disposed on a second surface (100b) of a substrate (100). The first gate pattern (G1) may be provided within a first pixel area (PX1). The second gate pattern (G2) may be provided within a second pixel area (PX2). Each of the first gate pattern (G1) and the second gate pattern (G2) may function as a gate electrode of a transfer transistor (Tx), a source follower transistor (Sx), a reset transistor (Rx), or a select transistor (Ax) as previously described in FIG. 1. For example, each of the first gate pattern (G1) and the second gate pattern (G2) may include a transfer gate (TG), a source follower gate (SG), a reset gate (RG), or a select gate (AG).

[0035] In FIG. 2b, for simplification, a single first gate pattern (G1) is shown placed on the first pixel area (PX1), but multiple first gate patterns (G1) may be placed on the first pixel area (PX1). Additionally, multiple second gate patterns (G2) may be placed on the second pixel area (PX2). Hereinafter, for simplification, a single first gate pattern (G1) and a second gate pattern (G2) will be described.

[0036] Each of the first and second gate patterns (G1, G2) may have a vertical gate structure or a buried gate structure. For example, each of the first and second gate patterns (G1, G2) may include a first part (310) and a second part (320). The first part (310) of each of the first and second gate patterns (G1, G2) may protrude into the substrate (100). The first part (310) may be a vertical part and may have a major axis parallel to the fifth direction (D5). The second part (320) may be disposed on the second surface (100b) of the substrate (100). The second part (320) may be a horizontal part. The second part (320) may be connected to the first part (310). The second part (320) may include the same material as the first part (710). The first and second gate patterns (G1, G2) may include a metallic material, a metallic silicide material, polysilicon, and a combination thereof. In this case, the polysilicon may include doped polysilicon.

[0037] Gate insulation patterns (340) may be interposed between the first and second gate patterns (G1, G2) and the substrate (100), respectively. The gate insulation patterns (340) may include, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide).

[0038] The substrate (100) may include a first floating diffusion region (FD1) and a second floating diffusion region (FD2). The first floating diffusion region (FD1) may be provided within a first pixel region (PX1) and may be disposed on one side of a first gate pattern (G1). The second floating diffusion region (FD2) may be provided within a second pixel region (PX2) and may be disposed on one side of a second gate pattern (G2). The first and second floating diffusion regions (FD1, FD2) may be disposed adjacent to a second surface (100b) of the substrate (100). The bottom surfaces of the first and second floating diffusion regions (FD1, FD2) may be spaced apart from the first and second photoelectric conversion regions (PD1, PD2). The first and second floating diffusion regions (FD1, FD2) may be regions doped with impurities of a second conductivity type (e.g., n-type impurities). Each of the first and second floating diffusion regions (FD1, FD2) can perform substantially the same function and role as described in the example of the floating diffusion region (FD) of FIG. 1. For example, during image sensor operation, the first floating diffusion region (FD1) can receive charge generated in the first photoelectric conversion region (PD1). The second floating diffusion region (FD2) can receive charge generated in the second photoelectric conversion region (PD2).

[0039] The substrate (100) may include an impurity region (111). The impurity region (111) may be placed in a first pixel region (PX1) within the substrate (100). The impurity region (111) may be placed adjacent to a second surface (100b) of the substrate (100). The bottom surface of the impurity region (111) may be spaced apart from the first photoelectric conversion region (PD1). Although not illustrated, the impurity region (111) may be further placed in a second pixel region (PX2) within the substrate (100). The impurity region (111) may be a region doped with an impurity of a second conductivity type (e.g., n-type impurity). The impurity region (111) may be an active region. In this case, the active region may mean a region for the operation of the transistor and may include the source / drain regions of the transistor described with reference to FIG. 1. The transistor may include a source follower transistor (Sx), a reset transistor (Rx), or a select transistor (Ax) as described with reference to FIG. 1.

[0040] A device isolation pattern (220) may be provided within the substrate (100). The device isolation pattern (220) may define active regions. Specifically, in each pixel region (PX1, PD2), the device isolation pattern (220) may define an impurity region (111), a first floating diffusion region (PD1), and a second floating diffusion region (PD2), and the impurity region (111), the first floating diffusion region (PD1), and the second floating diffusion region (PD2) may be separated from each other by the device isolation pattern (220). For example, the device isolation pattern (220) may be placed on one side of any one of the impurity region (111), the first floating diffusion region (PD1), and the second floating diffusion region (PD2) within the substrate (100). The device isolation pattern (220) may be provided within the second trench (192), and the second trench (192) may be recessed from the second surface (100b) of the substrate (100). The device isolation pattern (220) may be a shallow device isolation (STI) film. For example, the height of the device isolation pattern (220) may be smaller than the height of the isolation pattern (210). A portion of the device isolation pattern (220) may be connected to the sidewall of the insulating isolation pattern (211). The device isolation pattern (220) may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0041] Color filters (CF) may each be disposed on a plurality of unit pixel groups (UPG) on a first surface (100a) of a substrate (100). The color filters (CF) may form color filter arrays. The planar shape of each color filter (CF) may correspond to the planar shape of the corresponding unit pixel group (UPG). Each color filter (CF) may include any one of a red filter, a blue filter, and a green filter.

[0042] Each of the color filters (CF) may be placed on the first pixel area (PX1) and the second pixel area (PX2) of the corresponding unit pixel group (UPG). Each color filter (CF) may be vertically overlapped with the first photoelectric conversion area (PD1) and the second photoelectric conversion area (PD2). Accordingly, the first photoelectric conversion area (PD1) and the second photoelectric conversion area (PD2) may share the color filter (CF). The first photoelectric conversion area (PD1) and the second photoelectric conversion area (PD2) may output a photoelectric signal of light that has passed through a single color filter (CF). However, the photoelectric signal output from the first pixel area (PX1) may be corrected using the photoelectric signal output from the second pixel area (PX2).

[0043] The image sensor may further include a fence pattern (550). The fence pattern (550) may be interposed between two adjacent color filters (CF) to separate the color filters (CF). For example, a plurality of color filters (CF) may be optically separated from each other by the fence pattern (550). The fence pattern (550) may overlap vertically with some of the separation patterns (210). The fence pattern (550) may include a metal, a metal nitride, or a low-refractive index material. For example, the fence pattern (550) may include titanium nitride. The low-refractive index material may include a polymer and nanoparticles within the polymer and may have insulating properties. The nanoparticles may include, for example, silica.

[0044] The image sensor may further include an insulating layer (400). The insulating layer (400) may be interposed between the substrate (100) and the color filters (CF) and between the separation pattern (210) and the fence pattern (550). The insulating layer (400) may be a rear insulating layer. The insulating layer (400) may include a bottom antireflective coating (hereinafter BARC) layer. The insulating layer (400) may include a plurality of layers. For example, the insulating layer (400) may include a fixed charge film, a buried insulating film, a silicon nitride film, and a capping film laminated on a first surface (100a) of the substrate (100). The fixed charge film may include a metal oxide such as a laminated aluminum oxide and a hafnium oxide film. The buried insulating film may include tetraethyl orthosilicate (TEOS) or silicon oxide. The capping film may include a metal oxide such as hafnium oxide. At least one of the fixed charge film, buried insulating film, silicon nitride film, and capping film may be omitted.

[0045] The image sensor may further include a protective film (430). The protective film (430) may be interposed between the insulating layer (400) and the color filters (CF) and between the fence pattern (550) and the color filters (CF). For example, the protective film (430) may include aluminum oxide or hafnium oxide. The protective film (430) may protect the first and second photoelectric conversion regions (PD1, PD2) from the external environment.

[0046] The microlens layer (500) is disposed on a first surface (100a) of the substrate (100) and can cover a plurality of unit pixel groups (UPG). For example, the microlens layer (500) can be disposed on color filters (CF). The microlens layer (500) may include a flattening layer (530), a first lens pattern (510), and a second lens pattern (520). The flattening layer (530) of the microlens layer (500) can be disposed on color filters (CF).

[0047] The first lens pattern (510) of the microlens layer (500) may be placed on the flattening layer (530). The first lens pattern (510) may be provided on the first pixel area (PX1) and may be provided at a position corresponding to the first photoelectric conversion area (PD1). The first lens pattern (510) may have a first surface (100a) and a bottom surface. The bottom surface of the first lens pattern (510) may be a virtual surface and may face the substrate (100). The first surface (510a) of the first lens pattern (510) may be an upper surface and may not face the substrate (100). The first surface (510a) of the first lens pattern (510) may protrude away from the first surface (100a) of the substrate (100). The first surface (510a) of the first lens pattern (510) may be a curved surface. For example, the first lens pattern (510) may have a hemispherical cross-section. Light may be focused into the first photoelectric conversion region (PD1) by the first lens pattern (510). The focus of the first lens pattern (510) may be adjusted by the curvature of the first surface (510a) of the first lens pattern (510). Accordingly, the amount of light incident on the first photoelectric conversion region (PD1) may be adjusted. According to embodiments, the maximum distance (A) between the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100) may be 2.5 to 3.5 times the first radius. Here, the first radius may be the radius of a virtual semicircle formed by at least three points selected on the first surface (510a) of the first lens pattern (510). The above maximum gap (A) may correspond to the gap between the top of the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100). If the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100) is smaller than 2.5 times the first radius, the amount of light incident on the first photoelectric conversion region (PD1) may be reduced.When the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100) is greater than 3.5 times the first radius, the focus of the incident light may be directed toward the device isolation pattern (200) or the first gate pattern (G1). In this case, the light may be scattered by the device isolation pattern (200) or the first gate pattern (G1). According to the embodiments, since the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100) is 2.5 to 3.5 times the first radius, the optical characteristics of the image sensor may be improved.

[0048] The first lens pattern (510) may have a first lens width (W1) and a first height (H1). The first lens width (W1) may be the width of the lower surface of the first lens pattern (510). The lower surface of the first lens pattern (510) is a virtual surface and may be placed at the same level as the point where the first surface (510a) of the first lens pattern (510) meets the second surface (520a) of the second lens pattern (520). The first height (H1) may be the gap between the top of the first surface (510a) of the first lens pattern (510) and the lower surface of the first lens pattern (510). For example, the first height (H1) may be the maximum height of the first lens pattern (510). The first height (H1) may correspond to the difference between the maximum level and the minimum level of the first surface (510a) of the first lens pattern (510). The first height (H1) may be 30% to 50% of the first lens width (W1). If the first height (H1) is less than 30% of the first lens width (W1) or greater than 50%, the amount of light incident on the first photoelectric conversion region (PD1) may be reduced. Since the first height (H1) is 30% to 50% of the first lens width (W1), the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100) may satisfy the condition of being 2.5 to 3.5 times the first radius.

[0049] The second lens pattern (520) of the microlens layer (500) is placed on the flattening layer (530) and may be placed next to the first lens pattern (510). The second lens pattern (520) may be placed on the second pixel area (PX2) and provided at a position corresponding to the second photoelectric conversion area (PD2). The second lens pattern (520) may have a second surface (520a) and a bottom surface. The second surface (520a) of the second lens pattern (520) may not face the substrate (100). The second surface (520a) of the second lens pattern (520) may protrude away from the first surface (100a) of the substrate (100). The second surface (520a) of the second lens pattern (520) may be a curved surface. For example, the second lens pattern (520) may have a hemispherical cross-section. Light can be focused into the second photoelectric conversion region (PD2) by the second lens pattern (520). The amount of light incident on the second photoelectric conversion region (PD2) can be controlled by the curvature of the second surface (520a) of the second lens pattern (520). The curvature of the second surface (520a) of the second lens pattern (520) may be different from the curvature of the first surface (510a) of the first lens pattern (510), but is not limited thereto.

[0050] The second lens pattern (520) may have a second lens width (W2) and a second height (H2). The second lens width (W2) may be the width of the lower surface of the second lens pattern (520). The lower surface of the second lens pattern (520) is a virtual surface and may be positioned at the same level as the point where the first surface (510a) of the first lens pattern (510) and the second surface (520a) of the second lens pattern (520) meet. The lower surface of the second lens pattern (520) may face the substrate (100). The second lens width (W2) may be smaller than the first lens width (W1). For example, the second lens width (W2) may be 30% to 50% of the first lens width (W1). The second height (H2) may be the maximum height of the second lens pattern (520). The second height (H2) may be the gap between the uppermost part of the second surface of the second lens pattern (520) and the lower surface of the second lens pattern (520). The second height (H2) may correspond to the difference between the maximum level and the minimum level of the second surface (520a) of the second lens pattern (520). The second height (H2) may be smaller than the first height (H1). For example, the second height (H2) may be 20% to 30% of the first height (H1). According to the embodiments, since the second height (H2) is 20% to 30% of the first height (H1) and the second lens width (W2) is 30% to 50% of the first lens width (W1), the amount of light incident on the second photoelectric conversion region (PD2) is increased, and the arrangement of the pixel regions (PX1, PX2) of the image sensor can be highly integrated.

[0051] As shown in FIG. 2a, a plurality of second lens patterns (520) may each be arranged between the first lens patterns (510) in the first direction (D1). That is, the first lens patterns (510) and the second lens patterns (520) may be arranged alternately in the first direction (D1). The second lens patterns (520) may each be arranged between the first lens patterns (510) in the second direction (D2). The first lens patterns (510) may be arranged along the first diagonal direction (D3) and along the second diagonal direction (D4). Each of the plurality of second lens patterns (520) may be surrounded by four adjacent first lens patterns (510) in a planar view. Since the second lens width (W2) is smaller than the first lens width (W1), the second lens patterns (520) can be placed in areas not occupied (areas not occupied) by the first lens patterns (510). Accordingly, the placement of the first pixel areas (PX1) and the second pixel areas (PX2) can be highly integrated. The unoccupied areas may be the second pixel areas (PX2).

[0052] The flattening layer (530) of the microlens layer (500) may be interposed between the first substrate (100) and the first lens pattern (510) and between the first substrate (100) and the second lens pattern (520). The flattening layer (530) may have a third height (H3). The third height (H3) may be the gap between the lower surface of the flattening layer (530) and the upper surface of the flattening layer (530), and the upper surface of the flattening layer (530) may be a virtual surface and may be placed at the same level as the point where the first lens patterns (510) and the second lens patterns (520) meet. The third height (H3) may be 0.8 to 1.5 times the first height (H1). Since the third height (H3) is greater than 0.8 times the first height (H1), the focus of the first lens pattern (510) may not be provided within the flattening layer (530), color filters (CF), or insulating layer (400). Since the third height (H3) is less than 1.5 times the first height (H1), the phenomenon of light passing through the first lens pattern (510) being scattered by the element separation pattern (220) may be prevented. The first lens pattern (510) and the second lens pattern (520) are formed integrally with the flattening layer (530) and can be connected without a boundary surface.

[0053] The microlens layer (500) is transparent and can transmit light. The microlens layer (500) may include an organic material such as a polymer. For example, the microlens layer (500) may include a photoresist material or a thermosetting resin.

[0054] The image sensor may further include a coating layer (not shown). The coating layer (not shown) may conformally cover the first surface (510a) of the first lens pattern (510) and the second surface (520a) of the second lens pattern (520). The transparent coating layer may include an organic material and be transparent.

[0055] A wiring layer (800) may be disposed on a second surface (100b) of a substrate (100). The wiring layer (800) may include a first insulating layer (810), second insulating layers (820), and a conductive structure (830). The first insulating layer (810) may cover the second surface (100b) of the substrate (100), the sidewall of a first gate pattern (G1), and the sidewall of a second gate pattern (G2). The second insulating layers (820) may be laminated on the first insulating layer (810). The first and second insulating layers (810, 820) may include silicon-based insulating materials, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0056] A conductive structure (830) may be provided within insulating layers (810, 820). The conductive structure (830) may include a contact plug portion, a wiring portion, and a via portion. The contact plug of the conductive structure (830) is provided within the first insulating layer (810) and may be electrically connected to any one of the first floating diffusion region (FD1), the second floating diffusion region (FD2), the first gate pattern (G1), and the second gate pattern (G2). The wiring portion of the conductive structure (830) may be interposed between two adjacent insulating layers (810, 820). The wiring portion may be connected to the contact plug portion. The via portion of the conductive structure (830) penetrates at least one of the second insulating layers (820) and may be connected to the wiring portion.

[0057] The wiring layer (800) may further include a capacitor (840). The capacitor (840) may include a first electrode pattern (831), a second electrode pattern (832), and a dielectric layer (820D). The first electrode pattern (831) may be provided within the second insulating layers (820). The first electrode pattern (831) may be electrically connected to the second floating diffusion region (FD2) through the conductive structure (830). The second electrode pattern (832) may be provided within the second insulating layers (820) and may be spaced apart from the first electrode pattern (831). The first electrode pattern (831) and the second electrode pattern (832) may include a metal or a conductive polymer. For example, the first electrode pattern (831) may be any one of a plurality of wiring portions of the conductive structure (830). The second electrode pattern (832) may be another of the plurality of wiring portions of the conductive structure (830). A dielectric layer (820D) may be interposed between the first electrode pattern (831) and the second electrode pattern (832). The dielectric layer (820D) may be a part of any one of the second insulating layers (820). For example, any one of the second insulating layers (820) may be interposed between the first electrode pattern (831) and the second electrode pattern (832) to form the dielectric layer (820D). In this case, the dielectric layer (820D) may be connected to any one of the second insulating layers (820) without an interface. The capacitor (840) may not be connected to the first floating diffusion region (FD1), but is not limited thereto.

[0058] According to the embodiments, the time for accumulating charge in the second photoelectric conversion region (PD2) may differ from the time for accumulating charge in the first photoelectric conversion region (PD1). During the first period in which the charge accumulated in the first photoelectric conversion region (PD1) is transferred to the first floating diffusion region (FD1), the first pixel region (PX1) may have difficulty acquiring information regarding the incident light. During the first period, charge may be accumulated in the second photoelectric conversion region (PD2) by the incident light. The first photoelectric conversion region (PD1) and the second photoelectric conversion region (PD2) may share a single color filter (CF). The photoelectric signal output from the first pixel region (PX1) may be corrected using the photoelectric signal output from the second pixel region (PX2). Accordingly, loss of information regarding light during the first period may be prevented.

[0059] According to the embodiments, the storage capacity of the second photoelectric conversion region (PD2) may be smaller than the storage capacity of the first photoelectric conversion region (PD1). Since the capacitor (840) is connected to the second floating diffusion region (FD2) of the second pixel region (PX2), the storage capacity of the second photoelectric conversion region (PD2) may be supplemented. Accordingly, the optical characteristics of the image sensor may be further improved.

[0061] Unlike the illustration in FIGS. 2a and 2b, the substrate (100) may not include a second pixel area (PX2), and the microlens layer (500) may not include a second lens pattern (520). Components on the second pixel area (PX2), such as a second gate pattern (G2) and a second floating diffusion area (FD2), may not be provided. In this case, the first pixel area (PX1) may have a rectangular shape in a planar view. Nevertheless, the first height (H1) and first lens width (W1) of the first lens pattern (510), and the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the substrate (100) may satisfy the conditions described above.

[0063] FIGS. 3a to 3g are drawings for explaining a method of manufacturing an image sensor according to embodiments. Hereinafter, content that overlaps with what has been previously described is omitted.

[0064] Referring to FIG. 3a, a substrate (100) having first and second pixel regions (PX1, PX2) may be prepared. The substrate (100) may be doped with an impurity of a first conductivity type. An impurity of a second conductivity type may be injected into the substrate (100) to form first and photoelectric conversion regions (PD1, PD2). A second trench (192) and a device isolation pattern (220) may be formed on a second surface (100b) of the substrate (100). A first trench (191) and an isolation pattern (210) may be formed within the substrate (100). An impurity of a first conductivity type may be injected into the second surface (100b) of the substrate (100) to form first and second floating diffusion regions (FD1, FD2) and an impurity region (111). A first gate pattern (G1) and a second gate pattern (G2) may be formed in a first pixel area (PX1) and a second pixel area (PX2), respectively. A wiring layer (800) may be manufactured by forming first and second insulating layers (810, 820) and conductive structures (230) on a second surface (100b) of a substrate (100). At this time, a capacitor (840) may be further formed.

[0065] A grinding process can be performed on the first surface (100a) of the substrate (100) to thin the substrate (100). An insulating layer (400), fence patterns (450), a protective film (430), and a plurality of color filters (CF) can be formed on the first surface (100a) of the thinned substrate (100).

[0066] A preliminary lens layer (501) may be formed on a first surface (100a) of a substrate (100) to cover the upper surfaces of color filters (CF). The preliminary lens layer (501) may be formed by a coating process using a photoresist material or a thermosetting resin. The upper surface of the preliminary lens layer (501) may be substantially flat. For example, the upper surface of the preliminary lens layer (501) may be parallel to the first direction (D1).

[0067] A first sacrificial layer (611) may be formed on the pre-lens layer (501). The first sacrificial layer (611) may be formed by a coating process, for example. The first sacrificial layer (611) may include an organic material. For example, the first resist layer may include a polymer such as photoresist. The first sacrificial layer (611) may be, for example, a resist layer.

[0068] Referring to FIG. 3b, a first sacrificial layer (611) can be patterned to form a first pre-sacrificial pattern (610P). The patterning of the first sacrificial layer (611) can be carried out by an exposure process and a development process. For example, after the exposure process, the first sacrificial layer (611) may include an exposed portion and a non-exposed portion. The exposed portion of the first sacrificial layer (611) may include a material having a different chemical structure from the non-exposed portion. During the development process, either the exposed portion or the non-exposed portion of the first sacrificial layer (611) may be removed to form a first pre-sacrificial pattern (610P). A plurality of first pre-sacrificial patterns (610P) may be provided, and a plurality of first pre-sacrificial patterns (610P) may be formed in first and second pixel regions (PX1, PX2), respectively. The first preliminary sacrifice patterns (610P) may be spaced apart from each other. The first preliminary sacrifice patterns (610P) may have substantially the same height from each other. The upper surfaces of the first preliminary sacrifice patterns (610P) may be parallel to the first direction (D1), but are not limited thereto.

[0069] Referring to FIG. 3c, the first pre-sacrifice patterns (610P) can be reflowed to form the first sacrifice patterns (610). Reflowing the first pre-sacrifice patterns (610P) can be performed at a temperature of approximately 130°C to 200°C. During the reflow process, the first pre-sacrifice patterns (610P) can flow down onto the upper surface of the pre-lens layer (501) as indicated by the arrow. The upper surfaces and sidewalls of the first pre-sacrifice patterns (610P) can form the first surfaces (610a) of the first sacrifice patterns (610). Each of the first surfaces (610a) of the first sacrifice patterns (610) may be a curved surface. Each of the first surfaces (610a) of the first sacrifice patterns (610) may have an upwardly convex shape. The first surfaces (610a) of the first sacrifice patterns (610) may be exposed without facing the pre-lens layer (501). For example, each of the first sacrifice patterns (610) may have a hemispherical shape.

[0070] The first sacrifice patterns (610) may each be provided at positions corresponding to the first and second pixel regions (PX1, PX2) of the substrate (100). The first sacrifice patterns (610) may be spaced apart from each other. The heights of the first sacrifice patterns (610) may be the same or similar to each other. The widths of the first sacrifice patterns (610) may be the same or similar to each other.

[0071] Referring to FIG. 3d, a second sacrificial layer (621) may be formed on the pre-lens layer (501) to cover the first sacrificial patterns (610). The formation of the second sacrificial layer (621) may include coating an organic material onto the pre-lens layer (501) and the first sacrificial patterns (610). The second sacrificial layer (621) may include a polymer such as a photoresist. The second sacrificial layer (621) may be, for example, a resist layer. The second sacrificial layer (621) may include the same material as the first sacrificial patterns (610). As another example, the second sacrificial layer (621) may include a material different from the first sacrificial patterns (610).

[0072] Referring to FIG. 3e, a second sacrifice layer (621) can be patterned to form second pre-sacrifice patterns (620P). The patterning of the second sacrifice layer (621) can be carried out by an exposure process and a development process. The second pre-sacrifice patterns (620P) can be spaced apart from each other. The second pre-sacrifice patterns (620P) can each be formed on the first pixel regions (PX1) of the substrate (100) to cover the first pre-sacrifice patterns (610P) respectively. For example, each of the second pre-sacrifice patterns (620P) can cover a corresponding one of the first sacrifice patterns (610). The second pre-sacrifice patterns (620P) may not be formed on the second pixel regions (PX2). The first sacrifice patterns (610) on the first pixel regions (PX1) can be exposed by the second reserve sacrifice patterns (620P).

[0073] Referring to FIG. 3f, the second pre-sacrificial patterns (620P) can be reflowed to form the second sacrificial patterns (620), respectively. Accordingly, sacrificial structures (630) can be formed on the first pixel regions (PX1) of the substrate (100), respectively. Each of the sacrificial structures (630) may include the second sacrificial pattern (620) and the corresponding first sacrificial pattern (610). The sacrificial structures (630) may not be formed on the second pixel region (PX2).

[0074] Reflowing the second pre-sacrifice patterns (620P) can be performed at a temperature of approximately 130°C to 200°C. During the reflow process, the second pre-sacrifice patterns (620P) may flow down onto the upper surface of the pre-lens layer (501) as indicated by the arrow. The upper surfaces and side walls of the second pre-sacrifice patterns (620P) may form the second surfaces (620a) of the second sacrifice patterns (620). The second surfaces (620a) of the second sacrifice patterns (620) may be exposed to the outside. The second surfaces (620a) of the second sacrifice patterns (620) may form curved surfaces. For example, the second surfaces of the first sacrifice patterns (610) may have an upwardly convex shape. For example, each of the sacrifice structures (630) may have a hemispherical shape.

[0075] The second sacrifice patterns (620) may be spaced apart from each other. The second sacrifice patterns (620) may each be provided at a position corresponding to the first pixel regions (PX1) of the substrate (100). The second sacrifice patterns (620) may not be provided on the second pixel regions (PX2). According to the embodiments, since the second pre-sacrifice patterns (620P) are formed on the first sacrifice patterns (610), the uppermost portions of the second faces of the second pre-sacrifice patterns (620P) may be placed at a relatively high level. Accordingly, the uppermost portions of the second faces (620a) of the second sacrifice patterns (620) may be placed at a higher level than the uppermost portions of the first faces (610a) of the first sacrifice patterns (610) on the first pixel regions (PX1). The curvature of the second surfaces (620a) of the second sacrifice patterns (620) may be different from the curvature of the first surfaces (610a) of the first sacrifice patterns (610). The heights of the second sacrifice patterns (620) may be substantially the same as each other. The widths of the second sacrifice patterns (620) may be substantially the same as each other.

[0076] Referring to FIG. 3g and FIG. 2b in turn, an etch-back process may be performed on first sacrificial patterns (610) and second sacrificial patterns (620) to form a microlens layer (500). By the etch-back process, the shape of the first sacrificial patterns (610) may be transferred to a preliminary lens layer (501) to form second lens patterns (520). The shape of the sacrificial structures (630) may be transferred to the preliminary lens layer (501) to form first lens patterns (510).

[0077] When a sacrifice pattern is formed by reflowing a single resist pattern, it may be difficult for the height of the sacrifice pattern to exceed a certain value. The curvature of a lens pattern manufactured using the sacrifice pattern may be constrained by the curvature of the sacrifice pattern.

[0078] The sacrificial structures (630) each include the first sacrificial patterns (610) and the second sacrificial patterns (620), so they can have relatively large heights. As described in FIG. 3f, the second preliminary sacrificial patterns (620P) can be reflowed on the first sacrificial patterns (610) to form the second sacrificial patterns (620). Accordingly, the curvatures of the second faces (620a) of the second sacrificial patterns (620) may differ from the curvature of the sacrificial pattern by reflow of a single resist. The curvatures of the first faces (510a) of the first lens patterns (510) may be determined by the curvatures of the second faces (620a) of the second sacrificial pattern (620). The etch-back process may be performed until the removal of the first sacrificial patterns (610) and the sacrificial structures (630) is completed. As a result of the above etch-back process, a microlens layer (500) including a planarization layer (530), a first lens pattern (510), and a second lens pattern (520) can be manufactured. As shown in FIG. 2b, the first height (H1) of each of the first lens patterns (510) can satisfy the condition of being 30% to 50% of the first lens width (W1). In addition, the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the first surface (100a) of the substrate (100) can be 2.5 to 3.5 times the first radius. The manufacturing of the image sensor described in FIG. 2a and FIG. 2b can be completed by the examples described so far.

[0079] Unlike what is described, the substrate (100) may not include second pixel regions (PX), and components on the second pixel regions (PX2) may not be formed. The second sacrifice patterns (620) described in FIG. 3f may each be formed on the first sacrifice patterns (610). The etch-back process of FIG. 3g may be performed on the sacrifice structures (630). Accordingly, the first height (H1) and first lens width (W11) of the first lens pattern (510), and the maximum gap (A) between the first surface (510a) of the first lens pattern (510) and the substrate (100) may satisfy the conditions described above.

[0081] FIG. 4a is a drawing illustrating an image sensor according to embodiments, corresponding to a cross-section cut along line II-II of FIG. 2a.

[0082] Referring to FIG. 4a, the image sensor may include a substrate (100), a separation pattern (210A), a device separation pattern (220), a first gate pattern (G1), a second gate pattern (G2), a wiring layer (800), an insulating layer (400), a protective film (430), a fence pattern (450), color filters (CF), and a microlens layer (500).

[0083] A separation pattern (210A) may be provided within the substrate (100) to define first and second pixel regions (PX1, PX2). The separation pattern (210A) may be identical or similar to the separation pattern (210) described in FIGS. 2a and 2b. For example, the separation pattern (210A) may define first and second pixel regions (PX1, PX2). However, the separation pattern (210A) may be provided within a rear trench (191A), and the rear trench (191A) may penetrate the first surface (100a) of the substrate (100). The bottom surface of the rear trench (191A) may be provided within the substrate (100). The lower surface of the separation pattern (210A) may be spaced apart from the second surface (100b) of the substrate (100) and may be positioned at a higher level than the second surface (100b). Alternatively, the separation pattern (210A) may further penetrate the second surface (100b) of the substrate (100). The width (W21') of the upper surface of the separation pattern (210A) may be greater than the width (W22') of the lower surface of the separation pattern (210A). The upper surface of the separation pattern (210A) may be positioned at substantially the same level as the first surface (100a) of the substrate (100). The separation pattern (210A) may not include the conductive separation pattern (215) and capping pattern (317) described in FIG. 2b, and may include the same material as the insulating pattern (211). For example, the separation pattern (210A) may include a silicon-based insulating material filled within the rear trench (191A).

[0084] Unlike what is described, the separation pattern (210A) may be further extended onto the first surface (100a) of the substrate (100) and further provided between the substrate (100) and the insulating layer (400).

[0085] As another example, the separation pattern (210A) may contain the same material as the insulating layer (400) and may be connected without an interface. The separation pattern (210A) may be formed integrally with the insulating layer (400).

[0086] A pixel separation region (120) may be further provided within the substrate (100). The pixel separation region (120) may be provided between the lower surface of the separation pattern (210A) and the first surface (100a) of the substrate (100). The pixel separation region (120) may include a group 3 element. For example, the pixel separation region (120) may be a region doped with an impurity of a first conductivity type (e.g., p-type). The pixel separation region (120) may define first and second pixel regions (PX1, PX2) together with the separation pattern (210A). As another example, the substrate (100) may not include the pixel separation region (120).

[0087] The first and second gate patterns (G1, G2) may have a planar gate structure. Each of the first and second gate patterns (G1, G2) may include a second portion (320) but may not include the first portion (310) described in FIG. 2b. The first and second gate patterns (G1, G2) may be placed at the same or lower level as the second surface (100b) of the substrate (100). Gate insulation patterns (240) may be interposed between the substrate (100) and the first and second gate patterns (G1, G2), respectively. The gate insulation patterns (240) may not extend into the substrate (100).

[0089] FIG. 4b is a drawing illustrating an image sensor according to embodiments, corresponding to a cross-section cut along line II-II of FIG. 2a.

[0090] Referring to FIG. 4b, the image sensor may include a substrate (100), a first separation pattern (210'), a second separation pattern (210A'), a device separation pattern (220), a first gate pattern (G1), a second gate pattern (G2), a wiring layer (800), an insulating layer (400), a protective film (430), a fence pattern (450), color filters (CF), and a microlens layer (500).

[0091] A first separation pattern (210') may be provided within the substrate (100) and between the first and second photoelectric conversion regions (PD1, PD2). The first separation pattern (210') and the first trench (191') may be substantially the same as those described in the first separation pattern (210) and the first trench (191) of FIG. 2B, respectively. For example, the first separation pattern (210') may include an insulating pattern (211), a conductive separation pattern (215), and a capping pattern (217). However, the upper surface of the first separation pattern (210') may be positioned at a lower level than the first surface (100a) of the substrate (100).

[0092] A second separation pattern (210A') may be provided within the substrate (100) between the first and second photoelectric conversion regions (PD1, PD2). The rear trench (191A') and the second separation pattern (210A') may be substantially the same as those described in the rear trench (191A) and separation pattern (210A) of FIG. 4a, respectively. However, the second separation pattern (210A') may be placed on the first separation pattern (210'). The first separation pattern (210') and the second separation pattern (210A') may be connected to each other. For example, the lower surface of the second separation pattern (210A') may be in contact with the upper surface of the first separation pattern (210'). Accordingly, the first separation pattern (210') and the second separation pattern (210A') may define the first and second pixel regions (PX1, PX2).

[0094] FIG. 4c is a drawing illustrating an image sensor according to embodiments, corresponding to a cross-section cut along line II-II of FIG. 2a.

[0095] Referring to FIG. 4c, the image sensor may include a substrate (100), a separation pattern (210), a device separation pattern (220), a first gate pattern (G1), a second gate pattern (G2), a wiring layer (800), a protective film (430), a fence pattern (450), color filters (CF), and a microlens layer (500).

[0096] The microlens layer (500) may include a first lens pattern (510) and a second lens pattern (520). The first lens pattern (510) and the second lens pattern (520) may be substantially the same as those described in the examples of FIG. 2a and FIG. 2b. However, the microlens layer (500) may not include the flattening layer (530) described in FIG. 2b. The second lens pattern (520) may be spaced apart from the first lens pattern (510).

[0097] The image sensor may further include a transparent protective layer (470). The transparent protective layer (470) may be interposed between the color filters (CF) and the microlens layer (500). The transparent protective layer (470) may include an insulating material. The upper surface of the transparent protective layer (570) may be substantially flat.

[0099] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention. The appended claims should be interpreted as including other embodiments.

Claims

Claim 1 An image sensor comprising: a substrate having a first photoelectric conversion region on a first pixel region and a second photoelectric conversion region on a second pixel region; color filters on the substrate; and a microlens layer disposed on a first surface of the substrate, wherein the microlens layer comprises: a first lens pattern provided on the first pixel region of the substrate; and a second lens pattern provided on the second pixel region of the substrate, wherein the width of the first pixel region is greater than the width of the second pixel region, the maximum height of the second lens pattern is 20% to 30% of the maximum height of the first lens pattern, the width of the lower surface of the second lens pattern is 30% to 50% of the width of the lower surface of the first lens pattern, the maximum height of the first lens pattern is 30% to 50% of the width of the lower surface of the first lens pattern, and each of the color filters overlaps commonly with both the first lens pattern and the second lens pattern having different widths and different heights. Claim 2 In claim 1, the image sensor further comprises a color filter interposed between the first surface of the substrate and the microlens layer, wherein the color filter is vertically overlapping with the first lens pattern and the second lens pattern. Claim 3 An image sensor according to claim 1, wherein the first lens pattern has a curved surface, the maximum distance between the curved surface of the first lens pattern and the first surface of the substrate is 2.5 to 3.5 times the first radius, and the first radius is the radius of a virtual circle formed by at least three points selected on the curved surface of the first lens pattern. Claim 4 An image sensor according to claim 1, wherein the first pixel region of the substrate has an octagonal planar shape, and the second pixel region of the substrate has a planar shape different from the first pixel region. Claim 5 In claim 1, the microlens layer further comprises a planarization layer interposed between the substrate and the first lens pattern and between the substrate and the second lens pattern, and the first lens pattern and the second lens pattern are connected to the planarization layer in an image sensor. Claim 6 An image sensor according to claim 5, wherein the height of the flattening layer is 0.8 to 1.5 times the height of the first lens pattern. Claim 7 delete Claim 8 delete Claim 9 An image sensor according to claim 1, further comprising a separation pattern provided within the substrate and interposed between the first photoelectric conversion region and the second photoelectric conversion region. Claim 10 A substrate having a first photoelectric conversion region on a first pixel region and a second photoelectric conversion region on a second pixel region having a width different from that of the first pixel region; color filters on the substrate; and a microlens layer disposed on a first surface of the substrate and covering the first pixel region and the second pixel region of the substrate, wherein the microlens layer comprises: a first lens pattern provided on the first pixel region of the substrate and having a first curved surface; An image sensor comprising a second lens pattern having a second curved surface provided on the second pixel area of ​​the substrate, wherein at the point where the first curved surface and the second curved surface meet, the width of the lower surface of the second lens pattern is 30% to 50% of the width of the lower surface of the first lens pattern, the maximum height of the second lens pattern is 20% to 30% of the maximum height of the first lens pattern, the maximum height of the first lens pattern is 30% to 50% of the width of the lower surface of the first lens pattern, and each of the color filters overlaps commonly with both the first lens pattern and the second lens pattern having different widths and heights. Claim 11 In claim 10, the image sensor further comprises a color filter disposed on the first surface of the substrate, wherein the first lens pattern and the second lens pattern are disposed on the color filter. Claim 12 An image sensor according to claim 10, wherein the first pixel area of ​​the substrate is octagonal in a planar view and the second pixel area of ​​the substrate is square in a planar view. Claim 13 delete Claim 14 An image sensor according to claim 10, wherein the maximum distance between the first curved surface of the first lens pattern and the first surface of the substrate is 2.5 to 3.5 times the first radius, and the first radius is the radius of a virtual circle formed by at least three points selected on the first curved surface of the first lens pattern. Claim 15 In claim 10, the substrate comprises: a first floating diffusion region provided within the first pixel region of the substrate; and a second floating diffusion region provided within the second pixel region of the substrate, an image sensor. Claim 16 In claim 10, the microlens layer further comprises a planarization layer interposed between the substrate and the first lens pattern and between the substrate and the second lens pattern, and the planarization layer is an image sensor connected to the first lens pattern and the second lens pattern. Claim 17 A substrate having a first photoelectric conversion region on a first pixel area and a second photoelectric conversion region on a second pixel area having a width different from that of the first pixel area; color filters disposed on a first surface of the substrate; a fence pattern interposed between two adjacent color filters; a separation pattern interposed between the first photoelectric conversion region and the second photoelectric conversion region within the substrate; a microlens layer disposed on the color filter; a first gate pattern provided within the first pixel area and disposed on a second surface of the substrate; a second gate pattern provided within the second pixel area and disposed on the second surface of the substrate; and a wiring layer disposed on the second surface of the substrate and covering the first gate pattern and the second gate pattern, wherein the substrate comprises: a first floating diffusion region; and a second floating diffusion region spaced apart from the first floating diffusion region, and the microlens layer comprises: a first lens pattern provided on the first pixel area; and a second lens pattern provided on the second pixel area. An image sensor comprising a flattening layer interposed between the color filter and the first lens pattern and between the color filter and the second lens pattern, wherein the first lens pattern and the second lens pattern are disposed on the color filter, the width of the first pixel area is greater than the width of the second pixel area, the height of the first lens pattern is greater than the height of the second lens pattern, each of the color filters overlaps commonly with both the first lens pattern and the second lens pattern having different widths and heights, the width of the lower surface of the second lens pattern is 30% to 50% of the width of the lower surface of the first lens pattern, the maximum height of the second lens pattern is 20% to 30% of the maximum height of the first lens pattern, and the maximum height of the first lens pattern is 30% to 50% of the width of the lower surface of the first lens pattern. Claim 18 An image sensor according to claim 17, wherein the height of the flattening layer is 0.8 to 1.5 times the height of the first lens pattern. Claim 19 In claim 17, the first lens pattern comprises a plurality of first lens patterns, and the second lens pattern comprises a plurality of second lens patterns, wherein, in a planar view, the second lens patterns are each disposed between the plurality of first lens patterns in a first direction, and in a planar view, the second lens patterns are each disposed between the plurality of first lens patterns in a second direction, and the second direction intersects the first direction. Claim 20 An image sensor according to claim 17, wherein the first lens pattern has a curved surface, the maximum distance between the curved surface of the first lens pattern and the first surface of the substrate is 2.5 to 3.5 times the first radius, and the first radius is the radius of a virtual circle formed by at least three points selected from the curved surface of the first lens pattern.

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