Searchable array circuit and related method utilizing load-matched signals to reduce hit signal timing margin

Abstract

A CAM array of comparison memory cell circuits includes a decode column corresponding to each set, and each set includes at least one row of comparison memory cell circuits. Each decode column receives a set clock signal addressing the corresponding set and generates a set match signal in each row of the corresponding set. A column comparison circuit generates comparison data representing a bit of a comparison tag. For each row, a row match circuit generates a row match signal in response to the set match signal, indicating that the comparison tag matches a binary tag stored in the row. The circuits and loads within the decode column employed to generate the set clock signal correspond to the circuits generating the row match signal in each column of the CAM array, thereby reducing the timing margin of the match indication and reducing the access time for the CAM array.

Description

Technology Field

[0001] The technology of the present disclosure relates to memory arrays, and in particular further, to content-addressable random-access memory (CAM-RAM) arrays. Background Technology

[0002] Computers and electronic devices process information stored in binary form. Various technologies exist for storing binary data. The technology selected to store binary data in a specific situation depends on various factors, including the amount of time the binary data needs to be stored, the frequency of access to the binary data, whether the data needs to be stored when power is off, and the speed at which the binary data needs to be accessed by the processing element. Binary data can be stored within an array of memory cell circuits on an integrated circuit (IC). The array comprises rows and columns of memory cell circuits efficiently arranged on a semiconductor substrate. If the storage location of the desired binary data within random access memory (RAM) is known, the processor can access the binary information by identifying the rows and columns.

[0003] In some situations, rather than tracking row and column information, the location of binary data can be tracked by an identifier based on the binary data itself (usually referred to as a tag). By locating the corresponding identifier, the location of the desired binary data can be found. The identifier can consist of a few bits of the binary data, or a binary pattern can be generated using an algorithm that utilizes the binary data as input. The identifier is stored at a location corresponding to the binary data, so that if the identifier is found, the location of the binary data can be determined. In an exhaustive random access method, all identifiers within the array can be read and compared with the known identifier of the desired binary data. However, the time required for such an approach will significantly increase the time it takes for the processor to access the desired binary data. Alternatively, Content Addressing Memory (CAM) has the ability to compare the known identifier of the desired binary data with all identifiers stored within the array. The location of the desired binary data can be determined when a matching identifier is found. While this approach is faster than the front access method, to further minimize data access time for the CAM array, it would be desirable to minimize the time spent comparing known identifiers with identifiers (tags) within the array.

[0004] Exemplary embodiments disclosed herein include searchable array circuits that utilize load-matched signals to reduce the hit signal timing margin. A content addressing memory (CAM) includes columns and rows of comparison memory cell circuits that store bits of binary tags. Triggered by a clock signal, a compare tag is compared with binary tags stored in each row of the CAM array to determine which row the binary tag matching the compare tag is stored in, if any. A compare bit signal indicating the compare bit of the compare tag is provided in each column of the comparison memory cell circuits for comparison with the corresponding bits of the binary tags stored in each row. A hit signal (also referred to herein as a row match signal) is an indication that the compare tag matches the binary tag in the row based on the comparison in each column.

[0005] In an exemplary embodiment, the CAM array includes at least one decode column where each decode column corresponds to a set, wherein each set includes at least one row of comparison memory cell circuits. Each decode column receives a set clock signal for addressing the corresponding set and generates a set match signal at each row of the corresponding set. A column comparison circuit generates comparison true data and comparison complement data representing bits of a comparison tag at each column. A row match circuit, for each row, generates a row match signal indicating that the comparison tag matches a binary tag stored in the row in response to the set match signal. In one example, each row may include a row match line, and the row match circuit may generate a row match signal for the row in response to the row match line indicating that the comparison tag matches a binary tag in the row. Accordingly, the row match signal is generated in response to both the set clock signal and the row match line, both of which are triggered by the clock signal. The difference between the activation timing of the set clock signal and the comparison tag match indication on the low match line depends on the difference in propagation delay, which is affected by manufacturing process variations in each circuit and the number of loads on each circuit. In an exemplary embodiment, the circuits employed to generate the set clock signal in the decode column and to generate a load on the set clock signal correspond to the circuits that generate the low match signal in each column of the CAM array. This correspondence reduces the timing margin of the match indication, thereby reducing the access time to the CAM array.

[0006] In exemplary embodiments, an array of comparison memory cell circuits is disclosed. The array of comparison memory cell circuits comprises at least one set, each set comprises at least one row of a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store a binary tag. The array of comparison memory cell circuits comprises a plurality of columns of comparison memory cell circuits, each column of the plurality of columns comprises a comparison memory cell circuit within each row of the plurality of rows. The array of comparison memory cell circuits comprises at least one decode column, each of the at least one decode column corresponds to a set of at least one set, and the at least one decode column is configured to receive a set clock signal for the corresponding set and generate a set match signal on a set match line at each row of the corresponding set. The array of comparison memory cell circuits comprises a dynamic comparator circuit comprising a set clock circuit, a column comparison circuit, and a row match circuit. The set clock circuit is configured to generate a set clock signal for addressing the corresponding set for each of the at least one decode column. A column comparison circuit is configured to generate comparison true data representing the comparison true bit of a comparison tag for each column of a plurality of columns. A row match circuit is configured to generate a row match signal for each row of a plurality of rows, in response to a set match signal generated in the row, indicating that the comparison tag matches a binary tag stored in the row.

[0007] In other exemplary embodiments, an integrated circuit comprising an array of comparison memory cell circuits is disclosed. The array of comparison memory cell circuits comprises at least one set, each set comprising at least one row of a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store a binary tag. The array of comparison memory cell circuits comprises a plurality of columns of comparison memory cell circuits, each column of the plurality of columns comprises a comparison memory cell circuit within each row of the plurality of rows. The array of comparison memory cell circuits comprises at least one decode column, each of the at least one decode column corresponds to a set of at least one set, and the at least one decode column is configured to receive a set clock signal for a corresponding set and generate a set match signal on a set match line at each row of the corresponding set. The array of comparison memory cell circuits comprises a dynamic comparator circuit comprising a set clock circuit, a column comparison circuit, and a row match circuit. The set clock circuit is configured to generate a set clock signal for addressing a corresponding set for each of the at least one decode column. A column comparison circuit is configured to generate comparison true data representing the comparison true bit of a comparison tag for each column of a plurality of columns. A row match circuit is configured to generate a row match signal for each row of a plurality of rows, in response to a set match signal generated in the row, indicating that the comparison tag matches a binary tag stored in the row. Brief explanation of the drawing

[0008] The accompanying drawings, incorporated into and forming part of this specification, illustrate some aspects of the present disclosure and serve to explain the principles of the present disclosure together with the detailed description. FIG. 1 is a schematic diagram of a comparison memory cell circuit comprising a 6-transistor (6T) static random access memory (SRAM) cell circuit and true and complement comparison circuits coupled to a match line, as employed in a content addressing memory (CAM) array; FIG. 2 is a schematic diagram of a CAM array including a 6T SRAM cell circuit as shown in FIG. 1 within a row of memory cell circuits; FIG. 3 is a timing diagram illustrating the timing margin—according to process variation—of a set clock used to generate a hit signal indicating that a comparison tag is matched with a binary tag stored within a row of the CAM array of FIG. 2; FIG. 4 is a schematic diagram of a CAM array, such as the CAM array of FIG. 2, which uses a programmable delay in the clock signal to adjust process variation to reduce the timing margin; FIG. 5 is a schematic diagram of an exemplary CAM array comprising a decode column corresponding to each set to receive a set clock signal, generate a set match signal, and generate a hit signal indicating a match with a reduced timing margin; FIG. 6 is a schematic diagram of a non-comparison memory cell circuit of a CAM array for storing data that is not subject to comparison; FIG. 7 is a schematic diagram of an exemplary non-comparison memory cell circuit modified to form a circuit of a decode column corresponding to each row of the comparison memory cell circuits of FIG. 5; FIG. 8 is a schematic diagram of a CAM array including an alternative example of a non-comparison memory cell circuit within a decode column further modified to fine-tune the delay of the row match line and the set match signal; FIG. 9 is a schematic diagram of a CAM array in which the decode columns are separate from the non-comparison memory cell circuits; and FIG. 10 is a block diagram of an exemplary processor-based system comprising a plurality of devices coupled to a system bus, wherein any CAM array in the processor-based system may be a CAM array in any one of FIG. 5, FIG. 8, and FIG. 9. Specific details for implementing the invention

[0009] Exemplary embodiments disclosed herein include searchable array circuits that utilize load-matched signals to reduce the hit signal timing margin. A content addressing memory (CAM) includes columns and rows of comparison memory cell circuits that store bits of binary tags. Triggered by a clock signal, a comparison tag is compared with binary tags stored in each row of the CAM array to determine which row the binary tag matching the comparison tag is stored in, if any. A comparison bit signal indicating the comparison bit of the comparison tag is provided to each column of the comparison memory cell circuits for comparison with the corresponding bits of the binary tags stored in each row. A hit signal (also referred to herein as a row match signal) is an indication that the comparison tag matches a binary tag in the row based on the comparison in each column.

[0010] In an exemplary embodiment, the CAM array includes at least one decode column where each decode column corresponds to a set, wherein each set includes at least one row of comparison memory cell circuits. Each decode column receives a set clock signal for addressing the corresponding set and generates a set match signal at each row of the corresponding set. A column comparison circuit generates comparison true data and comparison complement data representing bits of a comparison tag at each column. A row match circuit, for each row, generates a row match signal indicating that the comparison tag matches a binary tag stored in the row in response to the set match signal. In one example, each row may include a row match line, and the row match circuit may generate a row match signal for the row in response to the row match line indicating that the comparison tag matches a binary tag in the row. Accordingly, the row match signal is generated in response to both the set clock signal and the row match line, both of which are triggered by the clock signal. The difference between the activation timing of the set clock signal and the comparison tag match indication on the low match line depends on the difference in propagation delay, which is affected by manufacturing process variations in each circuit and the number of loads on each circuit. In an exemplary embodiment, the circuits employed to generate the set clock signal in the decode column and to generate a load on the set clock signal correspond to the circuits that generate the low match signal in each column of the CAM array. This correspondence reduces the timing margin of the match indication, thereby reducing the access time to the CAM array.

[0011] Before describing exemplary embodiments of the Content Addressing Memory (CAM) arrays illustrated in FIGS. 5 through 9, existing CAM array circuits and their operation are first discussed with reference to FIGS. 1 through 4. A CAM array is configured to compare bit patterns (binary tags) stored within the CAM array with comparison bit patterns (comparison tags) known, for example, to a processor. The location of the binary tag that matches the comparison tag indicates the location where the desired data corresponding to the comparison tag is stored. To minimize the time required to access the desired binary data in the CAM array, the time required to compare the comparison tag with all binary tags and generate a match indication must be minimized.

[0012] FIG. 1 is a schematic diagram of a comparison memory cell circuit (100) that may be employed in a CAM array (not shown) to store bits of a binary tag. The comparison memory cell circuit (100) includes a six-transistor (6T) static random access memory cell circuit (102). The comparison memory cell circuit (100) also includes a true comparison circuit (104T) and a complement comparison circuit (104C) coupled to a match line (106). The true comparison circuit (104T) and the complement comparison circuit (104C) are employed to compare true data (108T) at a true data node (110T) and complement data (108C) at a complement data node (110C), respectively, with the comparison true data (112T) and the comparison complement data (112C). The complement data (108C) is complementary (e.g., opposite) to the true data (108T). The result of the comparison is displayed on the match line (106).

[0013] When operating, the match line (106) is supplied with a voltage (V) by a precharge circuit (not shown). DD It is precharged with ). The transistor (114A) in the true comparison circuit (104T) is coupled to the true data node (110T), and, for example, the true data node (110T) is supplied with a supply voltage (V DDIt is turned on by being at ) — which corresponds to the true data (108T) being binary "1". In this example, the true data (108T) being binary "0" is that the true data node (110T) is at ground voltage (V ss It corresponds to being at (e.g., 0 volts). The transistor (114B) in the comparison circuit corresponds to the comparison complement data (112C) being binary "1" voltage V DD It is turned on by ). Accordingly, if there is a mismatch between the true data (108T) and the comparison true data (112T), and both the true data (108T) and the comparison complement data (112C) become binary '1', then both transistors (114A and 114B) will be turned on, and the match line (106) will be at ground voltage (V ss It will be discharged as ) and will indicate a mismatch. The match line (106) is a wire or conductive element connected to the transistor (114A) and the transistor (116A).

[0014] Similarly, the transistor (116A) in the complement comparison circuit (104C) is coupled to the complement data node (110C) and is turned on when the complement data (108C) is binary "1". The transistor (116B) in the complement comparison circuit is turned on when the comparison true data (112T) is binary "1". Accordingly, if there is a mismatch between the true data (108T) and the comparison true data (112T), and if both the complement data (108C) and the comparison true data (112T) are binary '1', both transistors (116A and 116B) will be turned on, and the match line (106) will be at ground voltage (V ssIt will be discharged to ). Accordingly, the match line (106) in the discharged state (e.g., 0 volts) indicates a mismatch between the true data (108T) and the comparison true data (112T), regardless of the polarity of the true data (108T). In a CAM array (not shown), the match line (106) may be shared among a plurality of comparison memory cell circuits (100) that store bits of binary tags. The match line (106) will be kept charged to indicate that all bits of the binary tags stored in the CAM array match the corresponding bits of the comparison tags. The time for discharging the match line (106) is the capacitance (C) of the match line (106). 106 It depends on the current flowing through the true comparison circuit (104T) or the complement comparison circuit (104C). Capacitance (C 106 ) is partially determined by the length of the match line (106) and the number of loads, such as transistors, to which the match line (106) is combined or electrically connected.

[0015] FIG. 2 is a schematic diagram of a CAM array (200) comprising rows (202) of comparison memory cell circuits (204) corresponding to the comparison memory cell circuit (100) of FIG. 1. The CAM array (200) of FIG. 2 comprises only one set (206), and the set (206) comprises only rows (202), but the CAM array (200) may comprise a plurality of rows (202) within the set (206), and / or a plurality of sets (206) each having at least one row (202). A row (202) comprises six comparison memory cell circuits (204), but depending on the number of bits of the binary tag (BT) stored in the row (202), more or fewer comparison memory cell circuits (204) may be included in the row (202). Details of one of the comparison memory cell circuits (204) are shown for reference. Each comparison memory cell circuit (204) corresponds to a column (208) of the CAM array (200). Accordingly, any additional row (202) in the CAM array (200) will include comparison memory cell circuits (204) in each of the columns (208).

[0016] The comparison memory cell circuit (204) includes a memory cell circuit (210) which may be the 6T SRAM cell circuit (102) of FIG. 1 or another type of memory cell circuit. The comparison memory cell circuit (204) includes a true comparison circuit (212T) corresponding to the true comparison circuit (104T) of FIG. 1, and a complement comparison circuit (212C) corresponding to the complement comparison circuit (104C). The true and complement comparison circuits (212T and 212C) compare true data (214T) stored in the comparison memory cell circuit (204) with comparison true data (216T), and the complement data (214C) stored in the comparison memory cell circuit (204) is compared with comparison complement data (216C). The true data (214T) and the complement data (214C) represent 1 bit of a binary tag (BT) stored in row (202). The comparison true data (216T) and comparison complement data (216C) represent one bit of the comparison tag (CT) corresponding to the data being accessed by the processor. If the comparison tag (CT) matches one of the binary tags (BT) stored in the CAM array (200), the data corresponding to the binary tag (BT) in the CAM array (200) can be accessed.

[0017] Each comparison memory cell circuit (204) is coupled to a match line (218). The match line (218) is precharged by a precharge circuit (220) controlled by a match line precharge signal (MLP). The match line (218) is discharged (i.e., pulled down) if a mismatch is detected in any comparison memory cell circuit (204) within row (202). The match line (218) and the set clock signal (222) are received by the row match circuit (224). The set clock signal (222) indicates that row (202) within set (206) (and any other rows (202) within set (206)) are targets for comparison with the comparison tag (CT). If the set clock signal (222) is active, the state of the match line (218) determines whether a hit signal (226) is activated to indicate that the comparison tag (CT) is matched with the binary tag (BT) stored in the row (202). Each row (202) in the CAM array (200) includes a row match circuit among the row match circuits (224).

[0018] Returning to the comparison memory cell circuit (204), the transistor (228A) of the true comparison circuit (212T) is coupled to the true data node (230T) that stores the true data (214T) within the memory cell circuit (210). The transistor (228B) of the true comparison circuit (212T) receives the comparison complement data (216C). Both the true data node (230T) and the comparison complement data (216C) are supplied at the supply voltage (V DD In this case, if a mismatch is indicated, both transistor (228A) and transistor (228B) are turned on, and the true comparison circuit (212T) discharges the match line (218). Alternatively, the complement data node (230C) and the comparison true data (216T) of the memory cell circuit (210) are both at the supply voltage (V DD If it is in ), the complement comparison circuit (212C) discharges the match line (218).

[0019] The column comparison circuit (232) receives a comparison true bit (234T) and a comparison complement bit (234C), which are the true and complement values ​​of the corresponding bits of the comparison tag (CT). The column comparison circuit (232) generates comparison true data (216T) and comparison complement data (216C) based on the comparison true bit (234T) and the comparison complement bit (234C), respectively. The comparison true data (216T) and comparison complement data (216C) are generated at ground voltage (V) until activated by the clock signal (CLK). ss ) is maintained. When the clock signal (CLK) is activated, one of the compare true data (216T) and the compare complement data (216C) is maintained at the supply voltage (V) according to the values ​​of the compare true bit (234T) and the compare complement bit (234C). DD It is driven by ). If true data (214T) does not match comparison true data (216T), one of the true and complement comparison circuits (212T and 212C) discharges the match line (218). Similar comparisons are performed in other comparison memory cell circuits (204) within all columns (208) in row (202), and any of the comparison memory cell circuits (204) can discharge the match line (218).

[0020] A set clock signal (222) is generated by a set address circuit (236) to address a corresponding set (206) and is activated by a clock signal (CLK). The set address circuit (236) receives an active set address signal (238) to indicate that the set (206) is being addressed. The set address circuit (236) activates the set clock signal (222) when the set address signal (238) is active and the clock signal (CLK) is activated.

[0021] Since both the set clock signal (222) and the match line (218) contribute to the hit signal (226) and both are activated in response to the CLK signal, the state of the hit signal (226) is represented by a timing margin after the activation of the CLK signal. The timing margin depends on the propagation delay through the set address circuit (236) before the set address signal (238) reaches the set address circuit (236) and in response to the clock signal (CLK). The timing margin also depends on the time required to discharge the match line (218) through one or more of the comparison memory cell circuits (204) within the row (202). The time required to discharge the match line (218) after the activation of the clock signal (CLK) depends on the propagation delay through the column comparison circuit (232) and the number of loads for the comparison true data (216T) and the comparison complement data (216C). The number of loads for the comparison true data (216T) and comparison complement data (216C) depends on the number of rows (202) in the CAM array (200). Additionally, the time for discharging the match line (218) depends on the total capacitance (C) of the match line (218). 218 It follows the number of bits of the binary tag (BT) combined with the match line (218) in row (202).

[0022] It should be evident that the propagation delay through the set address circuit (236) typically lasts much shorter than the time it takes to discharge the match line (218). The circuit paths from the column comparison circuit (232) and the match line (218) are more complex than the paths through the set address circuit (236). Additionally, such propagation timing can be affected by manufacturing process variations, causing timing uncertainty that increases the timing margin to produce an indication of a match or mismatch on the heat signal (226).

[0023] It would be desirable to reduce any propagation timing mismatch between the circuit path from the set clock signal (222) to the hit signal (226) and the circuit paths from the compare true bit (234T) and the compare complement bit (234C) to the hit signal (226). Reducing such mismatch makes it possible to reduce the timing margin for the hit signal (226), which consequently reduces the access time of the CAM array (200).

[0024] FIG. 3 is a timing diagram (300) illustrating the signals of a CAM array (200), including the timing margin of a set clock signal (222) used to generate a hit signal in response to an indication on a match line (218) that a comparison tag (CT) in the CAM array of FIG. 2 is matched or not matched with a binary tag (BT).

[0025] In this example, the clock signal (CLK) is a square wave with a 50% duty cycle, but the duty cycle may be longer or shorter. The match line precharge signal (MLP) controlling the low-active precharge circuit (220) is deactivated at time T1 in response to the activation of the clock signal (CLK). The compare true bit (234T) and the compare complement bit (234C) are provided to the column comparison circuit (232) at time T2. In the case of a mismatch, the match line (218) is discharged in the timing margin between time T3 and time T4. The hit signal (226) is active after time T4. At time T5, the clock signal (CLK) is activated again, and the compare true bit (234T) and the compare complement bit (234C) are provided to the column comparison circuit (232) again at time T6. In the case of a match, the match line (218) is not discharged, but since the match line (218) can be discharged at any time within the timing margin between time T7 and time T8 in the case of a mismatch, the match line (218) in a charged state does not reliably indicate a match until after time T8. Accordingly, since reducing the time it takes for the processor to access the CAM array (200) makes it possible to increase the speed of the processor for higher performance of the electronic device or application, it would be desirable to reduce the timing margin to reduce the access time of the CAM array (200) of FIG. 2.

[0026] FIG. 4 is a schematic diagram of a CAM array (400) similar to the CAM array (200) of FIG. 2. In an example of a technique to reduce the timing margin, the CAM array (400) includes a programmable delay (PD) in the clock signal (CLK) to adjust the timing of the set clock signal (222) so that it is better synchronized with the discharge time of the match line (218). The programmable delay (PD) can add a delay to the clock signal (CLK) to delay the set clock signal (222) to adjust for manufacturing process variations. Adopting the programmable delay (PD) requires a calibration step in each integrated circuit where the CAM array (400) is manufactured. A CAM array in which the circuit path from the set address signal (238) to the hit signal (226) and the circuit path from the compare true bit (234T) (or compare complement bit (234C)) to the hit signal (226) are more closely synchronized without a calibration step (e.g., having a smaller timing margin) would be desirable.

[0027] FIG. 5 is a schematic diagram illustrating an exemplary CAM array (500) including a decode column (502) corresponding to each set (504). The CAM array (500) of FIG. 5 includes only one set (504) and, accordingly, one decode column (502), but may include multiple sets (504). The decode column (502) receives a set address signal (506) and generates a set match signal (508) at each row (510) of each set (504) so ​​that a match indication on the set match signal (508) and the row match line (512) is generated within a reduced timing margin. FIG. 5 illustrates a decode column (502) corresponding to a single row (510) within a set (504). Before explaining how the decode column (502) reduces the timing margin, a detailed description of the comparison memory cell circuit (514) is provided first.

[0028] The CAM array (500) functionally corresponds to the CAM array (200) of FIG. 2. A row (510) includes a plurality of comparison memory cell circuits (514) corresponding to the comparison memory cell circuits (204) within the row (202) of FIG. 2. The CAM array (500) may include additional sets (504) each comprising one or more rows (510). The comparison memory cell circuits (514) each include a true comparison circuit (516T) and a complement comparison circuit (516C) that discharge a row match line (512) in response to a mismatch between stored true data (518T) stored in the comparison memory cell circuit (514) and comparison true data (520T) provided to the CAM array (500). The complement comparison circuit (516C) is coupled to the low match line (512) and discharges the low match line (512) in response to a mismatch between the stored complement data (518C) stored in the comparison memory cell circuit (514) and the comparison complement data (520C) provided to the CAM array (500).

[0029] The CAM array (500) receives comparison true data (520T) and comparison complement data (520C) on the true comparison bit line (521T) and the complement comparison bit line (521C), respectively. The true comparison circuit (516T) within the comparison memory cell circuit (514) is coupled to the row match line (512) of the row (510) containing the comparison memory cell circuit (514), and the row match line (512) is connected to the ground voltage (V ssIt is coupled to a fixed voltage such as ). The true comparison circuit (516T) is controlled by the stored true data (518T) and the comparison complement data (520C) on the complement comparison bit line (521T). The low match line (512) is a wire, metal trace, or other conductive element coupled to the true comparison circuit (516T) and the complement comparison circuit (516C). The true comparison circuit (516T) sets the low match line (512) to ground voltage (V) to indicate that the comparison true data (520T) received on the true comparison bit line (521T) does not match the stored true data (518T) stored in the comparison memory cell circuit (514) (e.g., opposite binary polarity). ss It is combined with ). The time for discharging the low match line (512) is the capacitance (C) of the low match line (512). 512 It depends on the current capacity of the true comparison circuit (516T) or the complement comparison circuit (516C). Capacitance (C 512 ) is partially determined by the length of the low match line (512) and the number of loads, such as transistors, to which the low match line (512) is combined or electrically connected.

[0030] The stored true data (518T) is a 1 bit of the binary tag (BT) stored in the row (510). The comparison true data (520T) is a bit of the comparison tag (CT) provided for comparison with the binary tags (BT) stored in the CAM array (500). That is, each of the binary tags (BT) is stored in a plurality of comparison memory cell circuits (514) in the row (510). The number of bits of the binary tag (BT) may correspond to the number of columns (522) of the comparison memory cell circuits (514) of the CAM array (500). The true comparison bit line (521T) receives the comparison true data (520T) for the column (522), and the complement comparison bit line (521C) receives the comparison complement data (520C) that is complementary to the comparison true data (520T).

[0031] The comparison of the comparison tag (CT) and the binary tag (BT) within the row (510) and the generation of a match indication that the comparison tag (CT) matches the binary tag (BT) are performed by a dynamic comparator circuit (524). The dynamic comparator circuit (524) includes a column comparison circuit (526) for each column (522) of the comparison memory cell circuit (514) within each row (510), which generates comparison true data (520T) on a true comparison bit line (521T) and generates comparison complement data (520C) that is complementary to the comparison true data (520T) on a complement comparison bit line (521C). The comparison true data (520T) and the comparison complement data (520C) are generated based on the comparison true bit (528T) and the comparison complement bit (528C), respectively, in response to the activation of the clock signal (CLK). The comparison true bit (528T) and the comparison complement bit (528C) represent bits of the comparison tag (CT).

[0032] As mentioned above, the CAM array (500) includes one decode column (502) for each set (504). The dynamic comparator circuit (524) includes a set clock circuit (530) that generates a set clock signal (532) for addressing the corresponding set (504) (i.e., the set (504) corresponding to the decode column (502)) for each decode column (502). The set clock signal (532) is generated based on the set address signal (506) in response to the clock signal (CLK). The set clock signal (532) controls the matching in the set (504). Specifically, the set clock signal (532) provided to each row (510) of the set (504) is employed to generate a set match signal (508). The dynamic comparator circuit (524) includes a row match circuit (534) that receives a set match signal (508) and a row match line (512). For each row (510), the row match circuit (534) generates a row match signal (536) in response to the set match signal (508) in the row (510) to indicate that the comparison tag (CT) is matched with the binary tag (BT) stored in the row (510). The row match signal (536) corresponds to the hit signal (226) of FIG. 2.

[0033] The low match signal (536) is generated based on the low match line (512) and the set match signal (508). Both the match indication on the low match line (512) and the activation of the set match signal (508) are triggered by the clock signal (CLK). The difference between the delays of each of these signals after the activation of the clock signal (CLK) determines the timing margin. Accordingly, the delays are discussed individually below to explain the reduction in the timing margin in the low match signal (536). The delay from the activation of the clock signal (CLK) to the match indication on the low match line (512) depends on several factors.

[0034] Regarding the first factor, the comparison complement data (520C) is generated by the column comparison circuit (526) based on the comparison complement bit (528C) in response to the clock signal (CLK). The comparison complement data (520C) and the stored true data (518T) are combined in the true comparison circuit (516T) within each row (510). The true comparison circuit (516T) includes a stored data transistor (537T1) controlled by the stored true data (518T), and a comparison data transistor (537T2) controlled by the comparison complement data (520C). When both the stored true data (518T) and the comparison complement data (520C) are at the same voltage (e.g., supply voltage (V) DD If both are in binary "1", indicating a mismatch, the stored data transistor (537T1) and the comparison data transistor (537T2) are both turned on, and the low match line (512) is discharged. Additionally, the complement comparison circuit (516C) includes a stored data transistor (537C1) controlled by the stored complement data (518C) and a comparison data transistor (537C2) controlled by the comparison true data (520T). If both the stored complement data (518C) and the comparison true data (520T) are "1", indicating a mismatch, the complement comparison circuit (516C) is turned on and discharges the low match line (512).

[0035] Regarding the second factor, the propagation time of the comparison true data (520T) is partially determined by the number of rows (510) in the CAM array (500), corresponding to the number of loads on the wire and the wire length. The comparison true data (520T) of each column (522) of the comparison memory cell circuits (514) is coupled to the true comparison circuit (516T) within each row (510). The comparison complement data (520C) has the same number of loads as the comparison true data (520T).

[0036] Regarding the third factor, the time required to discharge the low match line (512) to indicate a mismatch is the capacitance (C 512 The discharge time depends on the length and number of loads on the row match line (512), both of which depend on the number of comparison memory cell circuits (514) within the row (510) (i.e., the number of columns (522) within the row (510)). The discharge time also depends on the number of bits of the binary tag (BT) stored within the row (510) that do not match the corresponding bits of the comparison tag (CT). The number of mismatched bits determines the number of true and complement comparison circuits (516T and 516C) that discharge the row match line (512) in parallel. The discharge time of the row match line (512) decreases with increasing mismatched bits, because more true comparison circuits (516T) or complement comparison circuits (516C) are turned on to discharge the row match line (512) in parallel.

[0037] The decode column (502) improves the synchronization of the set match signal (508) with respect to the match indication on the low match line (512). The three factors described above regarding the delays of the low match line (512) are compared here with the corresponding factors of the set match signal (508).

[0038] First, a set clock signal (532) is generated by a set clock circuit (530) based on a set address signal (506) in response to the activation of a clock signal (CLK). The decode column (502) includes a pull-down circuit (538) corresponding to each row (510) of the CAM array (500). The set clock signal (532) controls the first transistor (540) of the pull-down circuit (538) to be turned on or turned off (e.g., conducting or not conducting) according to the state of the set clock signal (532). The pull-down circuit (538) uses a constant voltage source (e.g., supply voltage (V)) to ensure that the second transistor (542) is always turned on or always turned off. DD) or ground voltage (V ss It includes a second transistor (542) controlled by )).

[0039] Specifically, in the rows (510) of the set (504) corresponding to the decode column (502), the second transistor (542) is supplied with a voltage (V) such that the second transistor (542) is kept turned on (i.e., conducting). DD It is coupled to ). In the rows (510) of sets (504) that do not correspond to the decode column (502), the second transistor (542) is connected to the ground voltage (V) to keep the second transistor (542) turned off (i.e., non-conducting). SS It is coupled to ). Accordingly, the pull-down circuits (538) in the rows (510) in the set (504) corresponding to the decode column (502) are controlled by the set clock signal (532). The pull-down circuits (538) in the rows (510) of the other sets (504) not corresponding to the decode column (502) are always off regardless of the state of the set clock signal (532) coupled to the first transistor (540).

[0040] Second, the propagation time of the set clock signal (532) is partially determined by providing the set clock signal (532) to the load (i.e., the first transistor (540)) within each of the rows (510). When the set clock signal (532) for the set (504) is activated, the set match line (544) for each row (510) within the set (504) is discharged. A set match signal (508) is generated on the set match line (544).

[0041] Third, the time required to discharge the set match line (544) to gate the low match line (512) of the same low (510) depends on the number of decode columns (502), because even if the pull-down circuit (538) within only one decode column (502) discharges the set match line, the set match line (544) is coupled to the pull-down circuit (538) within each decode column, thereby increasing the number of loads on the set match line (544). When comparing the set match line (544) to the low match line (512), the number of loads on the set match line (544) may be less than the number of columns (522) to which the low match line (512) is coupled, but this difference can be offset by the set match line (544) becoming longer than the low match line (512)—which increases the capacitance of the set match line (544).

[0042] The set match line (544) extends along the rows (504) and across the decode columns (502) located at the opposite end of the CAM array (500) from the row match circuit (534). To further increase the delay of the set match line (532), a delay circuit (546) may be included within the row match circuit (534). In another embodiment, the row match line (512) is coupled to the precharge circuit (548), and the set match line (544) is coupled to the precharge circuit (550).

[0043] As presented above, the factors causing delays in the match indications on the low match line (512) and the set match line (544) are very similar due to the addition of decode columns (502). Due to the similarity between the circuits, manufacturing and process variations tend to affect the delays of both to a similar degree. Accordingly, the difference between each delay is reduced, which reduces the timing margin of the low match signal (536).

[0044] The decode column (502) illustrated in FIG. 5 is implemented as a non-comparison memory cell circuit (552) corresponding to a row (510). In a CAM array (500) comprising a plurality of rows (510), the decode column (502) will include a plurality of non-comparison memory cell circuits (552) corresponding to each row (510). A CAM array (500) comprising a plurality of sets (504) will include a decode column (502) corresponding to each set (504), and each of such decode columns (502) will include a non-comparison memory cell circuit (552) corresponding to each row (510). Each decode column (502) will include a set clock circuit (530).

[0045] The non-comparison memory cell circuit (552) is capable of storing stored data (e.g., 1 bit) that can be read by the read bit circuit (554) in response to a read word line (RWL). Typically, information such as process IDs and / or parity bits is stored in the non-comparison memory cell circuit (552) because it is not subject to comparison. The non-comparison memory cell circuit (552) does not include the true and complement comparison circuits (516T and 516C) found in the comparison memory cell circuits (514). Accordingly, the decode column (502) can actually be implemented as the non-comparison memory cell circuits (552) of the CAM array (500). As will be discussed with reference to FIGS. 6 and 7, the decode columns (502) may be integrated into the existing columns of non-comparison memory cell circuits (552) by adding pull-down circuits (538), a set clock signal (532), and a set match line (544). In this way, the decode columns (502) may be implemented in the CAM array (500) to reduce the timing margin of the row match signal (536) without increasing the size (i.e., area).

[0046] The first transistor (540) and the second transistor (542) of each of the pull-down circuits (538) may be, for example, metal oxide semiconductor (MOS) field-effect transistors (FETs) (MOSFETs). A set clock signal (532) is coupled to the gate terminal of the first transistors (540) to control conductivity through the pull-down circuits (538). The set clock circuit (530) can logically AND the set address signal (506) and the clock signal (CLK).

[0047] FIG. 6 is a schematic diagram illustrating details of a non-comparison memory cell circuit (600) in an example comprising a 6T SRAM cell circuit (602). The 6T SRAM cell circuit (602) comprises cross-coupled inverters (604T and 604C) that provide a true storage node (606T) and a complement storage node (606C). The true and complement storage nodes (606T and 606C) are written through pass gates (608). In FIG. 6, the complement storage node (606C) is read through a read bit circuit (610), such as the read bit circuit (554) illustrated in FIG. 5. Further details of the 6T SRAM memory cell circuit (602) are beyond the scope of this disclosure and are not presented herein. When comparing the comparison memory cell circuit (514) with the non-comparison memory cell circuit (600), the read bit circuit (610) occupies the area of ​​the non-comparison memory cell circuit (600) that would be occupied by the complement comparison circuit (516C) in the comparison memory cell circuit (514). The non-comparison memory cell circuit (600) does not include another circuit coupled to the true storage node (606T), and the true comparison circuit (516T) is located within the comparison memory cell circuit (514).

[0048] FIG. 7 is a schematic diagram of a non-comparison memory cell circuit (700) comprising the non-comparison memory cell circuit (600) of FIG. 6 and the pull-down circuit (538) of FIG. 5. In this regard, implementing the decode column (502) shown in FIG. 5 involves simply adding a pull-down circuit (538) to the non-comparison memory cell circuit (600) for a CAM array with reduced timing margin without increasing area.

[0049] FIG. 8 is an example of a decode column (800) comprising a non-comparison memory cell circuit (802) corresponding to a non-comparison memory cell circuit (700) to which pull-down circuits (804A and 804B) coupled to a set match line (806) are added. The set match line (806) corresponds to the set match line (544) of FIG. 5. The pull-down circuits (804A and 804B) load the set match line (806) to match the load of the low match line (512) of FIG. 5. This additional load provides a means to fine-tune the increase in capacitance of the set match line (806), so that the propagation delay of the set match line (806) better corresponds to the propagation delay to the low match line (512), thereby further reducing the timing margin of the low match signal (not shown).

[0050] FIG. 9 is a schematic diagram illustrating a CAM array (900) comprising sets (902A) and sets (902B), wherein each of the sets (902A and 902B) comprises two rows (904). Although not illustrated in FIG. 9, the rows (904) each comprise a plurality of comparison memory cell circuits, such as the comparison memory cell circuits (514) of FIG. 5 for storing bits of a binary tag (BT). The CAM array (900) comprises a decode column (906A) corresponding to set (902A) and a decode column (906B) corresponding to set (902B). A set clock circuit (not illustrated) generates a set clock signal (908A) for set (902A) and generates a set clock signal (909A) for set (902B). The pull-down circuits (910) corresponding to each row (904) in the decode columns (906A and 906B) each receive set match signals (908A and 908B). The pull-down circuits (910) may be included in non-comparison memory cell circuits such as the non-comparison memory cell circuits (552) of FIG. 5 (not shown). Alternatively, the decode columns (906A and 906B) may include only the pull-down circuits (910) within the CAM array (900), separate from the comparison memory cell circuits and non-comparison memory cell circuits not shown.

[0051] The first transistor (912) in each of the pull-down circuits (910) within the decode column (906A) receives a set clock signal (908A) indicating that the set (902A) is being addressed. The first transistor (912) in each of the pull-down circuits (910) within the decode column (906B) receives a set clock signal (908B) indicating that the set (902B) is being addressed. The second transistor (916) in each pull-down circuit (910) is coupled to a fixed voltage source. In the rows (904) of the set (902A), the second transistor (916) in the decode column (906A) is connected to a supply voltage (V DDCombined with ), the pull-down circuit (910) in the rows (904) of the set (902A) is controlled by the set clock signal (908A). Similarly, in the rows (904) of the set (902B), the second transistor (916) in the decode column (906B) is controlled by the supply voltage (V DD Combined with ), the pull-down circuit (910) in the rows (904) of the set (902B) is controlled by the set clock signal (908B).

[0052] However, in the rows (904) of the set (902A), the second transistor (916) in the decode column (906B) is at ground voltage (V SS Combined with ), the pull-down circuit (910) in the rows (904) of the set (902A) in the decode column (906B) is always off. In the rows (904) of the set (902B), the second transistors (916) in the decode column (906A) also maintain the pull-down circuit (910) in the rows (904) of the set (902B) in the decode column (906A) always turned off at the ground voltage (V ssIt is coupled to ). That is, in the decode column (906A), each pull-down circuit (910) corresponding to each row (904) in the set (902A) activates the set match line (918A or 920A) in the row (904) in response to receiving the set clock signal (908A) for the corresponding set (902A). In the decode column (906B), each pull-down circuit (910) corresponding to the row (904) in the set (902B) activates the set match signal (918B or 920B) corresponding to the row (904) in response to receiving the set clock signal (908B) for the corresponding set (902B). In the decode column (906A), each pull-down circuit (910) corresponding to rows (904) in the set (902B) does not activate the set match signal (918A or 918B), and in the decode column (906B), each pull-down circuit (910) in rows (904) in the set (902A) does not activate the set match signal (918B or 920B).

[0053] Even if the set clock signals (908A and 908B) do not control the specific pull-down circuits (910), the first transistors (912) combined with them provide a load that contributes to the capacitance of the set clock signals (908A and 908B), thereby better replicating the loads of the comparison true data (520T) and comparison complement data (520C) of FIG. 5, and helping to reduce the timing margin of the set match signal (508) and low match line (512) of FIG. 5.

[0054] FIG. 10 is a block diagram of an exemplary processor-based system (1000) comprising a processor (1002) (e.g., a microprocessor) comprising an instruction processing circuit (1004). The processor-based system (1000) may be a circuit or circuits contained on an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal information terminal (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system (1000) comprises a processor (1002). The processor (1002) represents one or more general-purpose processing circuits such as a microprocessor, a central processing unit, etc. In particular, the processor (1002) may be an EDGE instruction set microprocessor or another processor implementing an instruction set that supports explicit consumer naming to communicate values ​​produced by the execution of producer instructions. The processor (1002) is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor (1002) includes an instruction cache (1006) for temporary high-speed access memory storage of instructions accessible by the instruction processing circuit (1004). Instructions fetched or prefetched from memory, such as main memory (1008), via the system bus (1010) are stored in the instruction cache (1006). Data may be stored in a cache memory (1012) coupled to the system bus (1010) for low-latency access by the processor (1002). The instruction processing circuit (1004) is configured to process instructions fetched to the instruction cache (1006) and to process instructions for execution.

[0055] The processor (1002) and the main memory (1008) are coupled to a system bus (1010) and can interconnect peripheral devices included within the processor-based system (1000). As is well known, the processor (1000) communicates with these other devices by exchanging address, control, and data information through the system bus (1010). For example, the processor (1002) can communicate bus transaction requests to a memory controller (1014) in the main memory (1008) as an example of a slave device. Although not illustrated in FIG. 10, a plurality of system buses (1010) may be provided, and each system bus constitutes a different fabric. In this example, the memory controller (1014) is configured to provide memory access requests to a memory array (1016) in the main memory (1008). The memory array (1020) is composed of an array of storage bit cells for storing data. The main memory (1008) may be, as non-limiting examples, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM), such as a synchronous DRAM (SDRAM), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0056] Other devices may be connected to the system bus (1010). As illustrated in FIG. 10, these devices may include, as examples, a main memory (1008), one or more input device(s) (1018), one or more output device(s) (1020), a modem (1022), and one or more display controllers (1024). The input device(s) (1018) may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) (1020) may include any type of output device, including but not limited to audio, video, other visual displays, etc. The modem (1022) may be any device configured to allow the exchange of data to and from the network (1026). The network (1026) may be any type of network including, but not limited to, wired or wireless networks, private or public networks, local area networks (LAN), wireless local area networks (WLAN), wide area networks (WAN), Bluetooth™ networks, and the Internet. The modem (1022) may be configured to support any type of communication protocol desired. The processor (1002) may also be configured to access display controller(s) (1024) via the system bus (1010) to control information transmitted to one or more displays (1028). The display(s) (1028) may include any type of display including, but not limited to, cathode ray tubes (CRT), liquid crystal displays (LCD), plasma displays, etc.

[0057] The processor-based system (1000) of FIG. 10 may include a set of instructions (1030) to be executed by a processor (1002) for any desired application according to the instructions. The instructions (1030) may be stored in main memory (1008), the processor (1002), and / or an instruction cache (1006), as examples of non-transient computer-readable media (1032). The instructions (1030) may also reside in main memory (1008) and / or the processor (1002) completely or at least partially during execution. The instructions (1030) may further be transmitted or received through a network (1026) via a modem (1022) such that the network (1026) includes a computer-readable medium (1032).

[0058] Although the computer-readable medium (1036) is depicted as a single medium in exemplary embodiments, the term “computer-readable medium” should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or related caches and servers) that store one or more instruction sets. The term “computer-readable medium” should also be understood to include any medium capable of storing, encoding, or returning an instruction set for execution by a processing device and enabling the processing device to perform any one or more of the methods of the embodiments disclosed herein. Accordingly, the term “computer-readable medium” should be understood to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0059] Any ICs within a processor-based system (1000) may include a CAM array, and the CAM array includes decode columns corresponding to each set, each of which receives a set address signal and generates a set match signal at each row of the set, so that a set match signal and a match indication on the row match line are generated within a reduced timing margin, as shown in FIG. 5.

[0060] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be implemented as machine-executable instructions that can be used to enable a general-purpose or special-purpose processor programmed with instructions to perform the steps, or may be formed by hardware components. Alternatively, the steps may be performed by a combination of hardware and software.

[0061] The embodiments disclosed herein may be provided as a computer program product or software comprising a machine-readable medium (or computer-readable medium) storing instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. The machine-readable medium comprises any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, the machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), magnetic disk storage medium, optical storage medium, flash memory devices, etc.).

[0062] Unless otherwise specifically stated and as is evident from the preceding discussion, it is understood that throughout this description, discussions using terms such as “processing,” “computing,” “decision,” “display,” etc. refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data and memories, expressed as physical (electronic) quantities within the registers of a computer system, into other data similarly expressed as physical quantities within computer system memories or registers or other such information storage, transmission, or display devices.

[0063] The algorithms and displays presented herein are not inherently related to any specific computer or other device. Various systems may be used with programs in accordance with the teachings in this specification, or it may prove convenient to configure more specialized devices to perform the necessary method steps. The structures required for these various systems will become clear from the description above. Furthermore, the embodiments described herein are not described with reference to any specific programming language. It will be understood that various programming languages ​​may be used to implement the teachings of the embodiments as described herein.

[0064] Those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as instructions stored in electronic hardware, memory, or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna systems described herein may be employed, for example, in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be memory of any type and size and may be configured to store any desired type of information. To clearly indicate such interchangeability, the various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each specific application, but such implementation decisions should not be interpreted as taking it outside the scope of the embodiments.

[0065] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed as a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller may be a processor. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors with a DSP core, or any other such configuration).

[0066] The embodiments disclosed herein may be implemented in hardware and in instructions stored in the hardware, and may reside, for example, in RAM, flash memory, ROM-ROM, EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0067] Additionally, it should be noted that the operation steps described in any of the exemplary embodiments in this specification are described for the purpose of providing examples and discussions. The described operations may be performed in a number of different sequences other than those illustrated. Furthermore, operations described as a single operation step may actually be performed in a number of different steps. Also, one or more operation steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals may be represented using any of the various techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the foregoing description may be represented as voltage, current, electromagnetic waves, magnetic fields, or particles, optical fields, or any combination thereof.

[0068] Unless otherwise explicitly stated, any method presented herein is not intended to require that the steps be performed in a specific order. Accordingly, where a method claim does not actually enumerate the order in which the steps are to be followed, or where the claims or description do not specifically state that the steps must be limited to a specific order, any specific order is not intended to be inferred.

[0069] It will be apparent to those skilled in the art that various modifications and variations may be made without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments comprising the spirit and materials of the present invention may come to mind to those skilled in the art, the present invention should be interpreted as including everything within the scope of the appended claims and their equivalents.

Claims

Claim 1 As an array of comparison memory cell circuits, at least one set — each set includes at least one row among a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store a binary tag —; a plurality of columns of the comparison memory cell circuits — each column of the plurality of columns includes a comparison memory cell circuit within each row of the plurality of rows —; at least one decode column — each of the at least one decode column corresponds to a set among the at least one set, and the at least one decode column is configured to: receive a set clock signal for the corresponding set; and to generate a set match signal on a set match line within each row of the corresponding set —; and a dynamic comparator circuit — the dynamic comparator circuit is a set clock circuit configured to generate the set clock signal to address the corresponding set for each of the at least one decode column; A column comparison circuit configured to generate comparison true data representing the comparison true bit of a comparison tag for each of the plurality of columns above;A comparison memory cell circuit array comprising: a row match circuit configured to generate a row match signal indicating that, for each row of the plurality of rows, the comparison tag is matched with the binary tag stored in the row in response to the set match signal generated in the row; wherein each decode column of the at least one decode column comprises a pull-down circuit in each row of the plurality of rows of the comparison memory cell circuits, each pull-down circuit is coupled to the set match line in the corresponding row, and in the decode column corresponding to a set of the at least one set: each pull-down circuit corresponding to a row in the set is configured to activate the set match line in the row in response to receiving the set clock signal for the corresponding set, and each pull-down circuit corresponding to a row in another set of the at least one set is configured not to activate the set match line in the row. Claim 2 A comparison memory cell circuit array according to claim 1, wherein each row of the plurality of rows further includes a row match line, and the row match circuit is also configured to generate the row match signal for the row in response to the row match line indicating that the comparison tag is matched with the binary tag stored in the row. Claim 3 A comparison memory cell circuit array according to paragraph 2, wherein each comparison memory cell circuit is configured to store stored true data corresponding to a comparison true bit of the binary tag, and stored complement data complementary to the stored true data. Claim 4 In paragraph 3, each comparison memory cell circuit comprises: a row match line of the row including the comparison memory cell circuit; and a true comparison circuit coupled to a true comparison bit line configured to receive comparison true data for the column including the comparison memory cell circuit, wherein the true comparison circuit is configured to coupled the row match line to a first voltage to indicate that the comparison true data received on the true comparison bit line does not match the stored true data stored in the comparison memory cell circuit. Claim 5 A comparison memory cell circuit array according to claim 4, wherein the column comparison circuit is also configured to generate comparison complement data for each column of the plurality of columns that is complementary to the comparison true data of the binary tag and represents the comparison complement bit of the comparison tag, and each comparison memory cell circuit further comprises a comparison comparison circuit configured to combine the row match line of the row including the memory cell circuit with the first voltage to indicate that the comparison complement data for the column including the comparison memory cell circuit does not match the stored complement data stored in the comparison memory cell circuit. Claim 6 A comparison memory cell circuit array according to claim 5, wherein the comparison comparison circuit further comprises a third transistor controlled by the stored comparison data stored in the comparison memory cell circuit, and a fourth transistor controlled by the comparison true data for the column including the comparison memory cell circuit. Claim 7 In claim 5, the comparison memory cell circuit array further comprises a first transistor controlled by the stored true data stored in the comparison memory cell circuit, and a second transistor controlled by the comparison complement data for the column including the comparison memory cell circuit. Claim 8 A comparison memory cell circuit array according to paragraph 3, wherein each of the comparison memory cell circuits comprises a static random-access memory (SRAM) cell circuit. Claim 9 A comparison memory cell circuit array according to claim 1, wherein the set clock circuit is also configured to generate the set clock signal in response to a clock signal and a set address signal corresponding to the set for each of the at least one decode column. Claim 10 A comparison memory cell circuit array according to claim 1, wherein the column comparison circuit is also configured to generate comparison true data based on the comparison true bit of the binary tag in response to the clock signal for each column of the plurality of columns. Claim 11 A comparison memory cell circuit array according to claim 1, wherein each decode column is configured to receive the set clock signal for a corresponding set generated by the set clock circuit, and each pull-down circuit comprises a first transistor controlled by the set clock signal and a second transistor coupled to a fixed voltage source. Claim 12 In paragraph 11, in each row within the corresponding set, the voltage source includes the supply voltage (VDD), and in each row not within the corresponding set, the voltage source includes the ground voltage (V ss A comparison memory cell circuit array that includes ). Claim 13 A comparison memory cell circuit array according to claim 11, wherein each decode column further comprises, in each row, a non-comparison memory cell circuit coupled to a read bit line, said non-comparison memory cell circuit comprising: a memory cell circuit; and a read transistor circuit configured to read stored data stored in said non-comparison memory cell circuit in response to activation of a read word signal. Claim 14 An integrated circuit comprising a comparison memory cell circuit array, wherein the comparison memory cell circuit array comprises: at least one set — each set comprises at least one row among a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store a binary tag —; a plurality of columns of the comparison memory cell circuits — each column of the plurality of columns comprises a comparison memory cell circuit within each row of the plurality of rows —; at least one decode column — each of the at least one decode column corresponds to a set among the at least one sets, and the at least one decode column is configured to: receive a set clock signal for the corresponding set; and to generate a set match signal on a set match line within each row of the corresponding set —; and a dynamic comparator circuit — the dynamic comparator circuit comprises: a set clock circuit configured to generate the set clock signal to address the corresponding set for each of the at least one decode column; and a column comparison circuit configured to generate comparison true data representing a comparison true bit of a comparison tag for each column of the plurality of columns.The integrated circuit comprises: a row match circuit configured to generate a row match signal indicating that, for each row of the plurality of rows, the comparison tag is matched with the binary tag stored in the row in response to the set match signal generated in the row; wherein each decode column of the at least one decode column comprises a pull-down circuit in each row of the plurality of rows of the comparison memory cell circuits, and each pull-down circuit is coupled to the set match line in the corresponding row, and in the decode column corresponding to a set of the at least one set: each pull-down circuit corresponding to a row in the set is configured to activate the set match line in the row in response to receiving the set clock signal for the corresponding set, and each pull-down circuit corresponding to a row in another set of the at least one set is configured not to activate the set match line in the row. Claim 15 An integrated circuit according to claim 14, wherein each row of the plurality of rows further comprises a row match line, and the row match circuit is also configured to generate a row match signal for the row in response to the row match line indicating that the comparison tag is matched with the binary tag stored in the row. Claim 16 An integrated circuit according to claim 15, wherein each comparison memory cell circuit is configured to store stored true data corresponding to a comparison true bit of the binary tag, and stored complement data complementary to the stored true data. Claim 17 An integrated circuit according to claim 16, wherein each comparison memory cell circuit comprises: a row match line of the row including the comparison memory cell circuit; and a true comparison circuit coupled to a true comparison bit line configured to receive comparison true data for the column including the comparison memory cell circuit, wherein the true comparison circuit is configured to coupled the row match line to a first voltage to indicate that the comparison true data received on the true comparison bit line does not match the stored true data stored in the comparison memory cell circuit. Claim 18 An integrated circuit according to claim 17, wherein the column comparison circuit is also configured to generate comparison complement data for each column of the plurality of columns that is complementary to the comparison true data of the binary tag and represents the comparison complement bit of the comparison tag, and each comparison memory cell circuit further comprises a comparison comparison circuit configured to combine the row match line of the row including the memory cell circuit with the first voltage to indicate that the comparison complement data for the column including the comparison memory cell circuit does not match the stored complement data stored in the comparison memory cell circuit. Claim 19 An integrated circuit according to claim 18, wherein the true comparison circuit further comprises a first transistor controlled by the stored true data stored in the comparison memory cell circuit, and a second transistor controlled by the comparison complement data for the column including the comparison memory cell circuit. Claim 20 An integrated circuit according to claim 19, wherein the above-mentioned complement comparison circuit further comprises a third transistor controlled by the stored complement data stored in the above-mentioned comparison memory cell circuit, and a fourth transistor controlled by the above-mentioned comparison true data for the column including the above-mentioned comparison memory cell circuit. Claim 21 As an array of comparison memory cell circuits, at least one set — each set includes at least one row among a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store a binary tag —; a plurality of columns of the comparison memory cell circuits — each column of the plurality of columns includes a comparison memory cell circuit within each row of the plurality of rows —; at least one decode column — each of the at least one decode column corresponds to a set among the at least one set, and the at least one decode column is configured to: receive a set clock signal for the corresponding set; and to generate a set match signal on a set match line within each row of the corresponding set —; and a dynamic comparator circuit — the dynamic comparator circuit comprises: a set clock circuit configured to generate the set clock signal to address the corresponding set for each of the at least one decode column; and a column comparison circuit configured to generate comparison true data representing a comparison true bit of a comparison tag for each column of the plurality of columns; A comparison memory cell circuit array comprising: a row match circuit configured to generate a row match signal indicating that, for each row of the plurality of rows, the comparison tag is matched with the binary tag stored in the row in response to the set match signal generated in the row, wherein in each of the at least one decode column: the set clock signal is coupled to a load in each row of each set of the array, and the load in each row of the set corresponding to the decode column includes a circuit that controls the set match signal. Claim 22 A comparison memory cell circuit array according to claim 21, wherein each row of the plurality of rows further includes a row match line, and the row match circuit is also configured to generate the row match signal for the row in response to the row match line indicating that the comparison tag is matched with the binary tag stored in the row. Claim 23 In claim 22, a comparison memory cell circuit array wherein each comparison memory cell circuit is configured to store stored true data corresponding to a comparison true bit of the binary tag, and stored complement data complementary to the stored true data. Claim 24 In claim 23, each comparison memory cell circuit comprises: a row match line of the row including the comparison memory cell circuit; and a true comparison circuit coupled to a true comparison bit line configured to receive comparison true data for the column including the comparison memory cell circuit, wherein the true comparison circuit is configured to coupled the row match line to a first voltage to indicate that the comparison true data received on the true comparison bit line does not match the stored true data stored in the comparison memory cell circuit. Claim 25 A comparison memory cell circuit array according to claim 24, wherein the column comparison circuit is also configured to generate comparison complement data for each column of the plurality of columns that is complementary to the comparison true data of the binary tag and represents the comparison complement bit of the comparison tag, and each comparison memory cell circuit further comprises a comparison comparison circuit configured to combine the row match line of the row including the memory cell circuit with the first voltage to indicate that the comparison complement data for the column including the comparison memory cell circuit does not match the stored complement data stored in the comparison memory cell circuit. Claim 26 A comparison memory cell circuit array according to claim 25, wherein the above-mentioned complement comparison circuit further comprises a third transistor controlled by the stored complement data stored in the comparison memory cell circuit, and a fourth transistor controlled by the comparison true data for the column including the comparison memory cell circuit. Claim 27 In claim 25, the comparison memory cell circuit array further comprises: a first transistor controlled by the stored true data stored in the comparison memory cell circuit; and a second transistor controlled by the comparison complement data for the column including the comparison memory cell circuit. Claim 28 In claim 21, the set clock circuit is also configured to generate the set clock signal in response to a clock signal and a set address signal corresponding to the set for each of the at least one decode column, in a comparison memory cell circuit array. Claim 29 In claim 21, the column comparison circuit is also configured to generate comparison true data based on the comparison true bit of the binary tag in response to the clock signal for each column of the plurality of columns, in a comparison memory cell circuit array. Claim 30 As an array of comparison memory cell circuits, at least one set — each set includes at least one row among a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store a binary tag —; a plurality of columns of the comparison memory cell circuits — each column of the plurality of columns includes a comparison memory cell circuit within each row of the plurality of rows —; at least one decode column — each of the at least one decode column corresponds to a set among the at least one set, and the at least one decode column is configured to: receive a set clock signal for the corresponding set; and to generate a set match signal on a set match line within each row of the corresponding set —; and a dynamic comparator circuit — the dynamic comparator circuit comprises: a set clock circuit configured to generate the set clock signal to address the corresponding set for each of the at least one decode column; and a column comparison circuit configured to generate comparison true data representing a comparison true bit of a comparison tag for each column of the plurality of columns; A comparison memory cell circuit array comprising: a row match circuit including a delay circuit configured to generate a delayed set match signal based on the set match signal generated in the row, wherein for each row of the plurality of rows, the row match circuit is configured to generate a row match signal indicating that the comparison tag is matched with the binary tag stored in the row in response to the delayed set match signal. Claim 31 A comparison memory cell circuit array according to claim 30, wherein each row of the plurality of rows further comprises a row match line, and the row match circuit is also configured to generate the row match signal for the row in response to the row match line indicating that the comparison tag is matched with the binary tag stored in the row. Claim 32 A comparison memory cell circuit array according to claim 31, wherein each comparison memory cell circuit is configured to store stored true data corresponding to a comparison true bit of the binary tag, and stored complement data complementary to the stored true data. Claim 33 In claim 32, each comparison memory cell circuit comprises: a row match line of the row including the comparison memory cell circuit; and a true comparison circuit coupled to a true comparison bit line configured to receive comparison true data for the column including the comparison memory cell circuit, wherein the true comparison circuit is configured to coupled the row match line to a first voltage to indicate that the comparison true data received on the true comparison bit line does not match the stored true data stored in the comparison memory cell circuit. Claim 34 A comparison memory cell circuit array according to claim 33, wherein the column comparison circuit is also configured to generate comparison complement data for each column of the plurality of columns that is complementary to the comparison true data of the binary tag and represents the comparison complement bit of the comparison tag, and each comparison memory cell circuit further comprises a comparison comparison circuit configured to combine the row match line of the row including the memory cell circuit with the first voltage to indicate that the comparison complement data for the column including the comparison memory cell circuit does not match the stored complement data stored in the comparison memory cell circuit. Claim 35 In claim 34, the comparison memory cell circuit array further comprises a third transistor controlled by the stored comparison data stored in the comparison memory cell circuit, and a fourth transistor controlled by the comparison true data for the column including the comparison memory cell circuit. Claim 36 In claim 34, the comparison memory cell circuit array further comprises: a first transistor controlled by the stored true data stored in the comparison memory cell circuit; and a second transistor controlled by the comparison complement data for the column including the comparison memory cell circuit. Claim 37 In paragraph 30, the set clock circuit is also configured to generate the set clock signal in response to a clock signal and a set address signal corresponding to the set for each of the at least one decode column, in a comparison memory cell circuit array. Claim 38 In paragraph 30, the column comparison circuit is also configured to generate comparison true data based on the comparison true bit of the binary tag in response to the clock signal for each column of the plurality of columns, in a comparison memory cell circuit array.

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