Packaging substrate and manufacturing method of the same

Abstract

An embodiment relates to a packaging substrate and a method for manufacturing the same. A packaging substrate according to an embodiment comprises a glass substrate including a first surface and a second surface facing each other, and an upper layer stacked on the first surface or a lower layer stacked under the second surface, wherein the glass substrate may have an edge region. The edge region includes an edge of the glass substrate; and a region of the glass substrate protruding beyond the upper layer or the lower layer. A method for manufacturing the packaging substrate comprises the steps of: preparing a glass substrate including a first surface and a second surface facing each other and forming an upper layer on the first surface; forming a removal line by removing a portion of the upper layer along a cutting line at a location where cutting is scheduled; a filamentation process step of forming a filament on the glass substrate along the removal line; and cutting the glass substrate using the filamentation; thereby manufacturing the packaging substrate according to claim 1. Through this, defects occurring on the surface and cross-section of the substrate can be easily detected.

Description

Technology Field

[0001] The present embodiments relate to a semiconductor packaging substrate and a method for manufacturing a semiconductor packaging substrate, and describe a packaging substrate including a glass substrate and a method for manufacturing the same. Background Technology

[0003] In manufacturing electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process.

[0004] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than by the performance of the semiconductor technology itself.

[0005] While ceramics or resins are currently used as packaging substrate materials, research on applying silicon or glass as high-end packaging substrates is currently underway, and in particular, packaging substrates with a cavity structure using glass substrates have been developed.

[0006] Meanwhile, the Re-Distribution Layer (RDL) in the packaging process refers to a general term for techniques that change the position of pre-formed electrical terminals (e.g., Al Pads) to arbitrary locations using Wafer Level Package (WLP) process technology. This RDL is used as a method to overcome design limitations in semiconductor manufacturing plants through packaging, specifically by being utilized in semiconductor chip stacking.

[0007] Related prior art includes U.S. Patent Publication US 2022 / 0336481 A1 and Korean Patent Publication 10-2020-0133340. The problem to be solved

[0009] The objective of the embodiment is to provide a packaging substrate capable of easily detecting defects that may occur in a glass substrate and a method for manufacturing the same, in a glass substrate and a packaging substrate on which a plurality of devices are mounted.

[0010] In addition, the objective of the embodiment is to provide a packaging substrate capable of simultaneously detecting defects occurring on the surface and cross-section of a glass substrate, and a method for manufacturing the same.

[0011] In addition, the purpose of the embodiment is to reduce time and cost during inspection and quality check of glass substrates. means of solving the problem

[0013] To achieve the above objective, a packaging substrate according to one embodiment comprises: a glass substrate including a first surface and a second surface facing each other; and an upper layer stacked on the first surface or a lower layer stacked under the second surface, wherein the glass substrate may have an edge region. The edge region comprises an edge of the glass substrate; and a region of the glass substrate protruding beyond the upper layer or the lower layer.

[0014] The upper layer may include a first insulating layer laminated on the first surface.

[0015] The edge of the first insulating layer may be positioned inward from the edge of the glass substrate, and the edge region may include the edge of the glass substrate and the edge of the first insulating layer.

[0016] Additionally, the lower layer may also include a second insulating layer laminated under the second surface, the edge of the second insulating layer is positioned inward from the edge of the glass substrate, and the edge region may include the edge of the glass substrate and the edge of the second insulating layer.

[0017] The width from the edge of the first insulating layer to the edge of the glass substrate may be 5 μm to 200 μm.

[0018] The width from the edge of the second insulating layer to the edge of the glass substrate may be 5 μm to 200 μm.

[0019] According to one embodiment, the edge region may be a curved surface.

[0020] The corners of the glass substrate in the above edge region may be curved.

[0021] According to other embodiments, the edge region may be chamfered.

[0022] The corners of the glass substrate in the above edge region may be chamfered.

[0023] The upper layer or the lower layer may each have a tapered shape that thins out in the direction of the edge region.

[0024] The upper layer or the lower layer may each have a tapered shape that becomes thinner in the direction of the cross-section of the glass substrate.

[0025] A semiconductor device can be mounted on the upper part of the above upper layer.

[0026] To achieve the above objective, a method for manufacturing a packaging substrate according to one embodiment may manufacture the packaging substrate described above by including the steps of: preparing a glass substrate having a first surface and a second surface facing each other and forming an upper layer on the first surface; removing a portion of the upper layer along a cutting line at a location where cutting is scheduled to be done to form a removal line; a filamentation process step of forming a filament on the glass substrate along the removal line; and cutting the glass substrate using the filamentation.

[0027] The method for manufacturing the above-described packaging substrate may further include, prior to the filamentation process step, a step of forming a lower layer under the second surface; and a step of removing a portion of the lower layer along the cutting line to form a removal line.

[0028] The width of the above removal line may be 5 μm or more. Also, the width of the above removal line may be 200 μm or less.

[0029] The upper layer and / or the lower layer may each have a tapered shape that thins in the direction of the cross-section of the glass substrate.

[0030] The step of cutting the glass substrate may be a step of separating the glass substrate into two or more parts by applying tensile stress or rotational force to the filamentation and forming a cut surface on the glass substrate.

[0031] The method for manufacturing the above packaging substrate may further include a step of grinding the cut surface of the cut glass substrate after the step of cutting the glass substrate.

[0032] The edge region includes the edge of the glass substrate; and the region of the glass substrate that protrudes beyond the upper layer or the lower layer.

[0033] The method for manufacturing the above packaging substrate may further include the step of detecting a defect in any one selected from the group consisting of the cut surface of the glass substrate, the removal line of the upper layer, the removal line of the lower layer, and a combination thereof. Effects of the invention

[0035] The embodiment can easily detect defects that may occur in a packaging substrate and / or a glass substrate. In addition, the embodiment can simultaneously detect defects that occur on the surface and cross-section of the glass substrate. Furthermore, the embodiment can effectively detect splitting, breakage, cracks, etc. that may occur in the glass substrate at low cost. Brief explanation of the drawing

[0037] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment. FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment. Figures 3 (a) and (b) are conceptual diagrams illustrating a cross-sectional view of a portion of a packaging substrate according to an embodiment, respectively. FIG. 4 is a flowchart illustrating, in cross-section, the process of creating a core distribution layer during the manufacturing process of a packaging substrate according to an embodiment. FIG. 5 is a flowchart illustrating, in cross-section, the process of creating an upper layer during the manufacturing process of a packaging substrate according to an embodiment. FIG. 6 (a) to (c) are drawings for explaining cross-sections of a packaging substrate according to each embodiment. FIG. 7 is a top view of a packaging substrate according to an embodiment, where Gr indicates a glass crack and Gh (glass chipping) indicates glass chipping. Figures 8 (a) to (c) are flowcharts illustrating the manufacturing process of a packaging substrate according to an embodiment in cross-section, where (a) is Laser Ablation, (b) is Laser Filamentation, and (c) is Separation. Figures 9 (a) to (c) are flowcharts illustrating the manufacturing process of a packaging substrate according to another embodiment in cross-section, where (a) is Laser Ablation, (b) is Laser Filamentation, and (c) is Separation. Figures 10 (a) and (b) are photographs of the manufacturing process of a packaging substrate according to an embodiment, where the left side of (a) is a cross-sectional view (Sectional View) and the right side is a top view (Top View). FIG. 11 is a photograph of a cross-section of a ground glass substrate according to an embodiment, where the solid line indicates the cutting line (CL) and the dotted line indicates the edge of the ground glass. FIG. 12 is a top view (a) of a glass substrate according to another embodiment and a photograph (b) of a part thereof. Specific details for implementing the invention

[0038] Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement them. However, embodiments may be implemented in various different forms and are not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals.

[0039] Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components.

[0040] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0041] In this specification, the "~" system may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0042] In this specification, the meaning of B being located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A.

[0043] In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B.

[0044] In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified.

[0046] In the process of developing a semiconductor device capable of high performance with greater integration and thinness, the inventors recognized that the packaging, not just the device itself, is a crucial factor in performance improvement. While conducting research on this, they confirmed that, unlike conventional interposers and organic substrates that use two or more layers of core as packaging substrates on motherboards, the packaging substrate can be made thinner and help improve the electrical characteristics of the semiconductor device by applying a glass core as a single layer and a cavity structure.

[0047] Meanwhile, there is a possibility that cracks or chipping may occur in glass substrates due to internal stress and / or external impact during the manufacturing process, and detecting this requires cross-sectional analysis, which demands high costs. For example, to detect cracks or chipping, inspection using a microscope or similar equipment may be required on all cross-sections of the glass substrate, and such inspection may require significant time and cost. At this time, it was confirmed that the inspection of the core substrate can be easily performed by causing the glass substrate to protrude in the direction of the cross-section relative to the layers stacked on top or bottom. In other words, the invention was completed by confirming that it is possible to rapidly detect defects on the surface and cross-section of the glass substrate without instruments such as a microscope by exposing a portion of the glass substrate.

[0049] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIG. 3 (a) and (b) are conceptual diagrams illustrating a cross-sectional part of a packaging substrate according to an embodiment, respectively.

[0050] To achieve the above objective, a semiconductor device (100) according to an embodiment comprises a semiconductor device section (30) in which one or more semiconductor devices (32, 34, 36) are located, a packaging substrate (20) electrically connected to the semiconductor devices, and a motherboard (10) electrically connected to the packaging substrate (20) and transmitting external electrical signals to the semiconductor devices (32, 34, 36) and connecting them to each other.

[0051] A packaging substrate (20) according to one embodiment includes a core layer (22), an upper layer (26) located on one side of the core layer (22), and a cavity portion (28) in which a cavity element (40) can be located.

[0052] The above semiconductor device part (30) refers to devices mounted on a semiconductor device and is mounted on the packaging substrate (20) by means of connection electrodes, etc. Specifically, the above semiconductor device part (30) may include, for example, a computing device such as a CPU or GPU (first device: 32, second device: 34), a memory device such as a memory chip (third device, 36), etc., but any semiconductor device mounted on a semiconductor device can be applied without limitation.

[0053] The above motherboard (10) may be a printed circuit board, a printed wiring board, etc.

[0054] The above packaging substrate (20) may optionally further include a lower layer (not shown) located below the core layer.

[0055] The core layer (22) may include a glass substrate (21) having a first section (221) having a first thickness (211) and a second section (222) adjacent to the first section (221) having a second thickness (212) thinner than the first thickness; a plurality of core vias (23) penetrating the glass substrate (21) in the thickness direction and a core distribution layer (24) located on the surface of the glass substrate (21) or the core vias (23) and electrically connecting the first surface (213) of the glass substrate (21) and the second surface (214) facing the first surface through the core vias (23). That is, the core layer (22) may refer to a glass structure that is a core via (23), a cavity section (28), or both, on a glass substrate (21) having a first surface (213) and a second surface (214) facing each other.

[0056] The second section (222) of the core layer (22) can function as a cavity structure.

[0057] In the same area, the glass substrate (21) has a first surface (213) and a second surface (214) facing each other, and these two surfaces are generally parallel to each other, so that the glass substrate (21) has a uniform thickness throughout.

[0058] The internal space (281) formed by the difference in thickness between the first zone (221) and the second zone (222) serves to accommodate part or all of the cavity element (40).

[0059] The glass substrate (21) may include a core via (23) penetrating the first surface (213) and the second surface (214). The core via (23) may be formed in both the first zone (221) and the second zone (222) and may be formed with an intended pitch and pattern.

[0060] Conventionally, silicon substrates and organic substrates were applied as packaging substrates for semiconductor devices in a stacked form. Silicon substrates had the disadvantage of relatively high power loss and a risk of parasitic devices occurring when applied to high-speed circuits due to the nature of semiconductors. Furthermore, while organic substrates require large surface areas to form increasingly complex distribution patterns, this does not align with the manufacturing trend of ultra-miniaturized electronic devices. Although pattern miniaturization is practically required to form complex distribution patterns within a fixed size, there were practical limitations to pattern miniaturization due to the characteristics of materials such as polymers applied to organic substrates.

[0061] In an embodiment, a glass substrate (21) is applied as a support for the core layer (22) as a method to solve these problems. Additionally, by applying a core via (23) formed through the glass substrate (21) together with the glass substrate (21), a packaging substrate (20) is provided that has a shorter electrical flow length, is more compact, has a faster response, and has less loss characteristics.

[0062] The above glass substrate (21) is preferably a glass substrate applicable to semiconductors, and for example, a borosilicate glass substrate, an alkali-free glass substrate, etc. may be applied, but is not limited thereto.

[0063] The core via (23) penetrates the glass substrate (21). The core via (23) may be formed by removing a predetermined area of ​​the glass substrate (21), specifically by etching the plate glass by physical and / or chemical methods.

[0064] Specifically, the formation of the core via (23) may be achieved by forming a defect (flaw) on the surface of a glass substrate using a method such as a laser and then chemically etching it, laser etching, etc., but is not limited thereto.

[0065] The above core vias (23) may be located in a number of 100 to 3,000 units based on a unit area (1 cm x 1 cm) of the glass substrate (21), in a number of 100 to 2,500 units, or in a number of 225 to 1,024 units. When these pitch conditions are satisfied, the formation of an electrically conductive layer, etc., and the performance of the packaging substrate can be improved.

[0066] The core distribution layer (24) comprises a core distribution pattern (241), which is an electrically conductive layer that electrically connects the first surface and the second surface of the glass substrate through through-vias, and a core insulation layer (223) that surrounds the core distribution pattern. The core layer (22) has an electrically conductive layer formed inside it through core vias and acts as an electrical pathway across the glass substrate (21), connecting the upper and lower parts of the glass substrate over a relatively short distance, thereby enabling faster electrical signal transmission and low loss characteristics. For example, copper plating layers may be applied to the electrically conductive layers, but are not limited thereto.

[0067] The above cavity (28) is substantially not limited in shape, such as circular, triangular, square, hexagonal, octagonal, or cross-shaped.

[0068] The above cavity element (40) may generally be cylindrical, rectangular, or polygonal in shape.

[0069] The above cavity portion (28) may include a cavity distribution pattern, which is an electrically conductive layer electrically connecting the cavity element (40) and the core distribution layer (24), and an insulating layer surrounding the cavity distribution pattern.

[0070] Meanwhile, according to another embodiment, the cavity portion may be implemented in a form that penetrates the first surface (213) and the second surface (214) of the glass substrate (21). In this case, the cavity portion may be formed according to the same process as the formation process of the core via (23), and the area and shape penetrating the glass substrate (21) may be different from that of the core via (23).

[0071] In this embodiment, an insulating layer can be created after the cavity element (40) is arranged in the cavity portion. That is, an insulating layer can also be created in the cavity portion through the process of creating the core insulating layer (223) described above.

[0072] The core distribution pattern (241) can be formed in such a way that it can be electrically connected to the cavity element (40).

[0073] The above cavity element (40) may include an active element such as a transistor or a power transfer element such as a multilayer ceramic capacitor (MLCC), i.e., a passive element.

[0074] When a component such as a transistor, which plays a role in converting electrical signals between the motherboard and the semiconductor component to an appropriate level is applied to the cavity element (40), the transistor, etc. is applied to the path of the packaging substrate (20), thereby providing a semiconductor device (100) that is more efficient and has a faster speed.

[0075] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive components, are typically applied in at least 200 units in a semiconductor device, and their performance is also affected by the characteristics of the electrically conductive layer surrounding the device in terms of power transfer. In one embodiment, non-circular core vias can be applied in places where a low-resistance electrically conductive layer is required, such as in these power transfer devices.

[0076] Meanwhile, the above cavity element (40) may be applied by individually inserting passive elements such as capacitors, or a group of elements containing multiple passive elements may be formed with electrodes exposed and inserted into the cavity element in a form embedded between insulating layers (cavity element insulating layers). In the latter case, the workability of manufacturing the packaging substrate can be made smoother, and it is more advantageous to position the insulating layer sufficiently and reliably in the space between the complex elements.

[0077] The above glass substrate (21) serves as an intermediate and mediating role connecting the semiconductor device part (30) and the motherboard (10) at the top and bottom, respectively, and the above core via (23) serves as a channel for transmitting their electrical signals, thereby enabling smooth signal transmission. For the purpose of distinguishing it from the core via of the second zone (222) described later, the core via placed in the first zone (221) is called the first zone core via (231).

[0078] An upper layer (26) is located on the first surface (213) above.

[0079] The upper layer (26) includes an upper portion distribution layer (25) and an upper surface connection layer (27) located on the upper portion distribution layer (25), and the uppermost surface of the upper layer (26) can be protected by a cover layer (60) having an opening formed therein that can be directly contacted by a connection electrode of a semiconductor device.

[0080] The upper distribution layer (25) comprises an upper insulating layer (253) located on the first surface; and an upper distribution pattern (251) embedded in the upper insulating layer (253) as an electrically conductive layer having a predetermined pattern and electrically connected to at least a portion thereof with the core distribution layer (24). The upper distribution layers (25) arranged vertically relative to each other may be connected to each other through blind vias (252).

[0081] The upper insulating layer (253) can be applied as an insulating layer to a semiconductor device or a packaging substrate, and for example, an epoxy resin containing a filler can be applied, but is not limited thereto.

[0082] The above insulating layer may be formed by forming and curing a coating layer, or by laminating an insulating film formed in an uncured or semi-cured state onto the core layer (22) and curing it. In this case, if a pressure reduction lamination method is applied, the insulating material can be incorporated into the space inside the core via (23), allowing for an efficient process.

[0083] According to one embodiment, even if multiple insulating layers are laminated and applied, it may be difficult to make substantial distinctions between the insulating layers, and multiple insulating layers are collectively referred to as upper insulating layers. Additionally, the same insulating material may be applied to the core insulating layer (223) and the upper insulating layer (253), and in this case, the boundary may not be substantially distinguishable. Alternatively, according to another embodiment, the boundary of the insulating layers may be created by setting the pressure and temperature for curing the multiple insulating layers differently.

[0084] The upper distribution pattern (251) above refers to an electrically conductive layer located within the upper insulating layer (253) in a preset form, and can be formed, for example, in a build-up layer manner. Specifically, an insulating layer is formed, and after removing an unnecessary part of the insulating layer, an electrically conductive layer is formed by a method such as copper plating. Optionally, after removing an unnecessary part of the electrically conductive layer, an insulating layer is formed again on the electrically conductive layer, and after removing the unnecessary part again, an electrically conductive layer is formed by a method such as plating. By repeating this process, an upper distribution pattern (251) can be formed in which an electrically conductive layer is formed in a vertical or horizontal direction in an intended pattern.

[0085] Since the upper portion distribution pattern (251) is located between the core layer (22) and the semiconductor device portion (30), it is formed to include a fine pattern in at least a part thereof so that the transmission of electrical signals between the semiconductor device portion (30) and the upper portion distribution pattern can proceed smoothly and a complex pattern intended can be sufficiently accommodated. At this time, the fine pattern may have a width and a spacing of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the description of the fine pattern below is the same).

[0086] The upper surface connection layer (27) includes an upper surface connection pattern (272) located on the upper insulating layer (253) and electrically connected to at least a portion of the upper portion distribution pattern (251), and an upper surface connection electrode (271) electrically connecting the semiconductor device portion (30) and the upper surface connection pattern (272). The upper surface connection pattern (272) may be located on one side of the upper insulating layer (253), or at least a portion thereof may be exposed and embedded on the upper insulating layer. For example, if the upper surface connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by a method such as plating, and if the upper surface connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer, etc. may be formed, and then a portion of the insulating layer or electrically conductive layer may be removed by a method such as surface polishing or surface etching.

[0087] The upper surface connection pattern (272) may include a fine pattern in at least a part thereof, similar to the upper portion distribution pattern (251) described above. The upper surface connection pattern (272) including such a fine pattern allows for electrical connection of a larger number of elements even within a narrow area, thereby facilitating smoother electrical signal connection between elements or with the outside, and enabling more integrated packaging.

[0088] The upper surface connection electrode (271) may be directly connected to the semiconductor device part (30) and terminals, etc., or may be connected via a device connection part (51) such as a solder ball.

[0089] The cavity portion (28) is located above and / or below the second zone (222) and includes an internal space (281) in which a cavity distribution layer (282) electrically connected to the core distribution pattern (241) and a cavity element (40) are located. The cavity distribution layer (282) may be formed through the second zone core via (232).

[0090] Specifically, the second zone (222) has a thinner glass substrate (21) compared to the first zone (221), and a cavity element (40) can be located in the internal space (281) formed due to the difference in thickness. Additionally, the core via (23) and the core distribution layer (24) formed on the glass substrate (21) serve as electrical connection structures that connect the cavity element (40) and the external element.

[0091] Additionally, as described above, a cavity portion can be created that penetrates the first area (221), that is, the first surface (213) and the second surface (214) of the glass substrate (1), rather than the second area (222), and a cavity element (40) can be arranged in the cavity portion.

[0092] The above packaging substrate (20) is also connected to the motherboard (10). The motherboard (10) may be directly connected to a core distribution pattern (241) located on at least a portion of the second surface (214) of the core layer (22) and to a terminal of the motherboard (10), or may be electrically connected via a board connection part (52) such as a solder ball. Additionally, the core distribution pattern (241) in contact with the motherboard (10) may be connected to the motherboard (10) via a lower layer (not shown) located below the core layer (22). The component connection part (51) and the board connection part (52) are collectively referred to as the connection part (50).

[0093] According to one example, the packaging substrate (20) located between the semiconductor device part (30) and the motherboard (10) may not substantially have any additional substrate other than the glass substrate (21).

[0094] Previously, an interposer and an organic substrate were stacked and applied together between the device and the motherboard. It is understood that this multi-layered application was adopted for at least two reasons: first, the scaling issue of directly bonding the fine pattern of the device to the motherboard, and second, the potential for wiring damage due to differences in thermal expansion coefficients during the bonding process or the operation of the semiconductor device. In this embodiment, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor device is applied, and a fine pattern having a scale fine enough for device mounting is formed on the first surface of the glass substrate and on its upper layer, thereby resolving these issues.

[0095] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0096] FIGS. 4 and FIGS. 5 are flowcharts illustrating the manufacturing process of a packaging substrate according to an embodiment in cross-section.

[0097] First, as shown in FIG. 4 (a), a glass substrate (21a) having a flat first surface and a second surface is prepared, and a defect (groove, 21b) is formed on the glass surface at a predetermined location for forming a core via. The glass may be a glass substrate applied to a substrate of an electronic device, for example, an alkali-free glass substrate may be used, but is not limited thereto. Commercial products manufactured by manufacturers such as Corning, Schott, and AGC may be used. Methods such as mechanical etching or laser irradiation may be applied to form the defect (groove).

[0098] As shown in FIG. 4(b), a glass substrate (21a) having a defect (groove, 21b) formed therein undergoes an etching step to form a core via (23) through a physical or chemical etching process. During the etching process, the glass substrate forms a via in the defective portion, and at the same time, the surface of the glass substrate (21a) may also be etched. Although a masking film may be applied to prevent such etching of the glass surface, the defective glass substrate itself may be etched considering the inconvenience of the process of applying and removing the masking film, and in this case, the thickness of the glass substrate having the core via may be slightly thinner than the thickness of the original glass substrate.

[0099] Then, the core layer manufacturing step can be performed by forming an electrically conductive layer (21d) on a glass substrate as shown in (c) and (d) of FIG. 4. The electrically conductive layer may be a metal layer including copper metal, but is not limited thereto.

[0100] The surface of the glass (including the surface of the glass substrate and the surface of the core via) and the surface of the copper metal have different properties, so the adhesion strength tends to be poor. In the embodiment, the adhesion strength between the glass surface and the metal can be improved using two methods: a dry method and a wet method.

[0101] The dry method is a method of applying sputtering, that is, a method of forming a seed layer (21c) on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, heterogeneous metals such as titanium, chromium, and nickel can be sputtered together with copper, etc., and in this case, the glass-metal adhesion can be improved by an anchor effect in which the metal particles interact with the surface morphology of the glass.

[0102] The wet method is a method of primer treatment in which a primer layer (21c) is formed by pre-treating with a compound having functional groups such as amines. Depending on the degree of intended adhesion, the primer can be applied with a compound or particle having amine functional groups after pre-treating with a silane coupling agent. As mentioned above, the support substrate of the embodiment requires high performance sufficient to form a fine pattern, and this must be maintained even after primer treatment. Therefore, if such a primer contains nanoparticles, it is preferable to apply nanoparticles having an average diameter of 150 nm or less, and for example, nanoparticles having amine groups are preferable to apply. The above primer layer can be formed by applying an adhesion improver manufactured by MEC's ​​CZ series, for example.

[0103] The above seed layer / primer layer (21c) can selectively form an electrically conductive metal layer with or without removing parts where the formation of the electrically conductive layer is unnecessary. Additionally, the above seed layer / primer layer (21c) can selectively treat parts where the formation of the electrically conductive layer is necessary or unnecessary in a state where it is activated or deactivated for metal plating to proceed with subsequent processes. For example, the activation or deactivation treatment may be applied using light irradiation such as a laser of a specific wavelength, chemical treatment, etc. For the formation of the metal layer, methods such as copper plating applied in semiconductor device manufacturing may be applied, but are not limited thereto.

[0104] As shown in FIG. 4 (e), if a part of the core distribution layer is unnecessary, it may be removed, and after the seed layer is partially removed or deactivated, metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer (21e) of the core distribution layer.

[0105] FIG. 5 illustrates a manufacturing step for forming an insulating layer and an upper distribution pattern according to one embodiment.

[0106] As shown in FIG. 5(a), the core via may undergo an insulating layer formation step in which the empty space is filled with an insulating layer after the formation of the core distribution layer, which is the electrically conductive layer. At this time, the insulating layer applied may be manufactured in the form of a film, and, for example, a method of depressurizing lamination of the film-type insulating layer may be applied. By performing depressurizing lamination in this way, the insulating layer is sufficiently indented into the empty space inside the core via, thereby forming a core insulating layer without void formation.

[0107] Figures 5(b) to 5(e) illustrate the upper layer manufacturing steps.

[0108] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition that forms an insulating layer (23a) or by laminating an insulating film; for simplicity, it is preferable to apply the method of laminating an insulating film. Lamination of the insulating film can be carried out by a process of laminating and curing the insulating film; at this time, if a pressure-reduction lamination method is applied, the insulating resin can be sufficiently incorporated even into layers where an electrically conductive layer is not formed inside the core via. The upper insulating layer also comes into direct contact with the glass substrate at least in part thereof, and thus has sufficient adhesion. Specifically, the glass substrate and the upper insulating layer should have characteristics that satisfy an adhesion test value of 4B or higher according to ASTM D3359.

[0109] The upper distribution pattern can be formed by repeating the process of forming the insulating layer (23a), forming the electrically conductive layer (23c) in a predetermined pattern, and etching the unnecessary parts to form the etched layer (23d) of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with the insulating layer in between, they can be formed by forming a blind via (23b) in the insulating layer and then proceeding with the plating process. For the formation of the blind via, dry etching methods such as laser etching and plasma etching, or wet etching methods using a masking layer and an etching solution can be applied.

[0110] Subsequently, although not shown in the city, an upper surface connection layer and a cover layer may be formed.

[0111] The upper surface connection pattern and the upper surface connection electrode can also be formed through a process similar to the formation of the upper portion distribution layer. Specifically, they can be formed by forming an etched layer of the insulating layer on the insulating layer (23e), forming an electrically conductive layer thereon, and then forming an etched layer of the electrically conductive layer, but they can also be formed by selectively forming only the electrically conductive layer without applying an etching method. The cover layer can be formed such that an opening (not shown) is formed at a position corresponding to the upper surface connection electrode, so that the upper surface connection electrode is exposed and can be directly connected to the device connection part or the terminal of the device.

[0112] Once the upper layer is formed, the process for the lower layer can be carried out by forming a lower connection layer and a cover layer. A lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown), can be formed in a manner similar to the upper connection layer and cover layer formation steps described above.

[0114] According to an embodiment, one or more semiconductor devices may be mounted on a packaging substrate (20). During the manufacturing process of the packaging substrate, multiple packaging substrates may be manufactured simultaneously on a large-area substrate, and the packaging substrate (20) may be cut into a predetermined unit, i.e., a unit, which is an individual packaging substrate. For example, during the manufacturing process of the packaging substrate, there may be a strip substrate in which a plurality of individual products are arranged with a dummy area between them, a quad substrate in which a dummy area is disposed between a plurality of strip substrates, and a panel substrate in which a dummy area is disposed between a plurality of quad substrates, and a glass substrate may be applied as a core in the manufacturing thereof. The glass substrate (core substrate or core layer) may be cut to have a pattern of a certain size and to a state in which an individual semiconductor chip or chip unit is mounted or can be mounted, during or after the placement of the upper layer and / or lower layer. Such cutting, separation, and dividing processes of the substrate may be referred to as dicing or singulation. In the following, depending on the context, the term "packaging substrate" refers to both a packaging substrate before singulation on which individual packaging substrates are arranged and a substrate in a singulated state as a single product.

[0115] In this specification, dicing or singulation may mean dividing a packaging substrate, which includes a glass substrate as a core layer, into multiple units. Additionally, a substrate in which a glass substrate is used as a core layer may be referred to in various ways, such as a core substrate, a glass substrate, or a packaging substrate.

[0116] FIG. 6 (a) to (c) are drawings for explaining cross-sections of a packaging substrate according to each embodiment.

[0117] As described with reference to FIGS. 1 to 5, core vias and cavity portions may be formed in the glass substrate (21). A core distribution layer and a cover layer, etc., may be formed in the upper layer. The lower layer may also have a multilayer structure including an insulating layer and a metal distribution pattern. For convenience of explanation, the packaging substrate (20) including the glass substrate (21), the upper layer (70) formed on the first surface of the glass substrate (21), and the lower layer (80) formed on the second surface is described in a simplified manner in the drawings below, and a detailed description of the remaining detailed configurations is omitted.

[0118] Referring to FIG. 6, an upper layer (70) is disposed on the first surface of the glass substrate (21). Optionally, a lower layer (80) may be disposed on the second surface of the glass substrate (21).

[0119] The upper layer (70) may include an upper distribution layer (71) formed as a multilayer laminated structure including an upper metal pattern (upper distribution pattern) and an upper insulating layer, and a first cover layer (72) formed on the upper distribution layer (71) to protect the substrate. The specific arrangement of the upper distribution pattern and the upper insulating layer within the upper distribution layer is omitted from the drawing.

[0120] The lower layer (80) may also include a lower distribution layer (81) formed as a multilayer structure including a lower metal pattern (lower distribution pattern) and a lower insulating layer, and a second cover layer (82) formed on the upper part of the lower distribution layer (81) to finally flatten and protect the substrate. The arrangement of the lower distribution pattern and the lower insulating layer within the lower distribution layer is omitted from the drawing.

[0121] The first cover layer (72) and / or the second cover layer (82) may be implemented as a solder resist to protect the surface circuit from the external environment. Alternatively, depending on the embodiment, the first cover layer (72) and / or the second cover layer (82) may be implemented as a polyimide film (PI), which is a heat-resistant insulating film having high thermal stability and high mechanical strength.

[0122] A core via, a cavity, and a metal pattern layer are formed on a glass substrate (21), and before a semiconductor device (not shown) is mounted or mounted on the upper layer (70), the packaging substrate can be cut into specific units.

[0123] The packaging substrate can be cut along a cutting line. The cutting line is a predetermined location where cutting is scheduled to take place.

[0124] In an embodiment, a metal pattern layer may not be disposed on a portion of the upper layer (70) and / or a portion of the lower layer (80) corresponding to the cutting line. That is, only an insulating layer or a protective layer may be disposed on a portion of the upper layer (70) and / or a portion of the lower layer (80) that is to be cut and removed.

[0125] The cut packaging substrate (20) generally has a cross-section as shown in (a) of FIG. 6. That is, the cut surface and the first surface or the cut surface and the second surface of the packaging substrate (20) are generally angular in shape, and the corners have a relatively sharp shape.

[0126] In a structure such as (a) of FIG. 6, cracks or breakage originating from the edges or cut surfaces of the glass substrate (21) can easily occur, so according to an embodiment of the present invention, a packaging substrate such as (b) or (c) of FIG. 6 is proposed.

[0127] According to an embodiment, as shown in FIG. 6(b), the cut surface of the glass substrate (21) may have a shape that protrudes beyond the upper layer (70) and / or lower layer (80). That is, the glass substrate (21) may have an edge region (213a) that is an edge protruding beyond the upper layer (70) and / or lower layer (80). The edge region of the first surface and / or the edge region of the second surface (213a) adjacent to the cut surface of the glass substrate (21) may have the upper layer (70) and / or lower layer (80) removed so that the first surface and / or second surface of the glass substrate (21) are exposed to the outside.

[0128] According to an embodiment, as shown in FIG. 6(b), the cut surface of the glass substrate (21) may have a shape that protrudes beyond the upper distribution layer (71) and / or the lower distribution layer (81). That is, the glass substrate (21) may have an edge region (213a) that is an edge protruding beyond the upper distribution layer (71) and / or the lower distribution layer (81). The edge region of the first surface and / or the edge region of the second surface (213a) adjacent to the cut surface of the glass substrate (21) may have the upper distribution layer (71) and / or the lower distribution layer (81) removed so that the first surface and / or the second surface of the glass substrate (21) are exposed to the outside. The upper distribution layer (71) and / or the lower distribution layer (81) may each have two or more layers, three or more layers, four or more layers, or five or more layers arranged in the upper layer (70) and the lower layer (80). In addition, 10 or fewer layers, 8 or fewer layers, or 6 or fewer layers may be arranged.

[0129] According to an embodiment, the upper layer (70) may further include an insulating layer such as a first cover layer (72) laminated on a first surface, the edge of the insulating layer is positioned inward from the edge of the glass substrate (21), and the edge region (213a) may include a region from the edge of the glass substrate (21) to the edge of the insulating layer.

[0130] Additionally, the lower layer (80) may further include an insulating layer such as a second cover layer (82) laminated on the second surface, the edge of the insulating layer is positioned inward from the edge of the glass substrate (21), and the edge region (213a) may include a region from the edge of the glass substrate (21) to the edge of the insulating layer.

[0131] The cutting process may be a process in which the panel substrate is cut into quad substrates.

[0132] The cutting process may be a process in which the quad substrate is cut into a strip substrate.

[0133] The cutting process may be a process in which a strip substrate is cut into individual packaging substrates.

[0134] This is collectively referred to as a process of being cut into unit units.

[0135] In the cutting process of the packaging substrate (20), that is, the cutting process in unit units, the upper layer (70) or the lower layer (80) may be removed, and through this process, after the cutting process, the side of the glass substrate (21) may be formed to protrude in the cutting direction more than the layer stacked on the upper or lower side. The removal may be performed using methods such as laser irradiation, but is not limited thereto.

[0136] The width of the edge region (213a) where the glass substrate (21) is exposed after the upper layer (70) or lower layer (80) is removed can be such that the width from the edge of the insulating layer to the edge of the glass substrate (21) is, for example, 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more, by removing a portion of the upper layer or lower layer. Additionally, the width of the edge region (213a) can be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less, by removing a portion of the upper layer or lower layer. That is, the width of the removed portion (removal line) can be at least twice or 2.2 times the width described above. Also, the width of the removed portion (removal line) can be at least four times or three times.

[0137] As shown in Fig. 6(b), the glass substrate (21) protrudes in the direction of the cut surface, so that the cross-section of the packaging substrate has a thickness reduced in the direction of the glass substrate (21) from the upper layer (70) or the lower layer (80), respectively, and can have an overall tapered shape facing a horizontal "U" shape.

[0138] The edge region (213a) of the protruding glass substrate (21) can be ground so that the corner portion is rounded, as in (c) of FIG. 6. That is, the edge region (213a) placed at the corner of the glass substrate (21) can be a curved surface.

[0139] Alternatively, according to one example, the edge region (213a) placed at the corner of the glass substrate (21) may be chamfered.

[0140] According to one example, the upper layer (70) or lower layer (80) may also be removed or ground to form a tapered shape that becomes thinner in the direction of the cut surface.

[0141] As shown in Fig. 6, when the upper layer is removed from the edge region (213a) of the glass substrate (21), the glass substrate (21) is exposed to the extent of the removed upper layer.

[0142] The width from the edge of the insulating layer to the edge of the glass substrate (21) may, for example, be 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more. Also, the width of the edge region (213a) may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0143] FIG. 7 is a drawing showing a top view of a packaging substrate according to an embodiment.

[0144] As described above, when viewed from above, the packaging substrate cut into units has a first cover layer (72) formed on the first surface of the glass substrate (21), and the upper layer including the first cover layer (72) is removed at the edge region (213a). When the glass substrate (21) is square-shaped, the upper layer can be removed along the four sides of the glass substrate (21). In other words, the edge of the first cover layer (72) is positioned inward from the edge of the glass substrate (21), and the edge region (213a) may refer to the area from the edge of the glass substrate (21) to the edge of the first cover layer (72).

[0145] In the edge region (213a) of the exposed glass substrate (21), glass cracks or chipping can be observed relatively easily, depending on one example.

[0146] As mentioned above, when a glass substrate is used as the core structure of a packaging substrate, there is a high probability that the substrate will break or crack due to internal stress and external impact during the manufacturing process; therefore, analysis of all cross-sections of the cut packaging substrate is required to detect this. Although cross-sectional analysis requires inspection using a microscope or similar equipment on the cut surface of the packaging substrate, this process entails significant time and cost.

[0147] According to the present embodiment, as shown in FIG. 7, defects such as cracks or chipping can be detected quickly and accurately by inspecting only the exposed area (213a) of the glass substrate (21). In other words, by detecting defects in the edge area (213a) of the glass substrate (21) from which the upper or lower layer has been removed and in the cut surface of the glass substrate, there is an advantage of being able to simultaneously perform surface inspection and cross-sectional inspection of the glass substrate without expensive equipment.

[0148] FIG. 8 is a flowchart illustrating the manufacturing process of a packaging substrate according to an embodiment in cross-section.

[0149] According to the embodiment of FIG. 8, an upper layer (70) is formed on the first surface of the glass substrate (21), and a semiconductor device (not shown) can be stacked on the upper layer (70).

[0150] First, as shown in FIG. 8 (a), the upper layer (70) can be removed along the cutting line by a predetermined width using a laser to form a removal line (Laser Ablation).

[0151] An upper layer (70), specifically an insulating layer such as ABF, which is stacked along a cutting line such as a dicing street, can be removed using a green laser or a UV laser.

[0152] At this time, the width of the upper layer (70) being removed, that is, the width of the removal line, may be approximately 10 μm to 600 μm. The width may be 10 μm or more, 14 μm or more, 20 μm or more, 30 μm or more, 40 μm or more, 50 μm or more, 60 μm or more, or 70 μm or more. The width may be 600 μm or less, 550 μm or less, 500 μm or less, 450 μm or less, 400 μm or less, 380 μm or less, 360 μm or less, 340 μm or less, 320 μm or less, 300 μm or less, 280 μm or less, 260 μm or less, 240 μm or less, 220 μm or less, 200 μm or less, or 180 μm or less. The width of the upper layer (70) to be removed can be set to approximately twice or more the width of the edge region of the glass substrate (21) to be protruded.

[0153] Meanwhile, as described, when the upper layer (70) is removed using a laser, no damage is substantially formed on the glass substrate (21).

[0154] Then, as shown in FIG. 8 (b), a filamentation process can be performed to form filaments along the cutting line on the glass substrate (21) from which the upper layer has been removed (Laser Filamentation).

[0155] A method of cutting a substrate using a laser beam, such as an infrared laser (IR laser), involves focusing an ultrashort laser beam into the interior of a glass substrate (21) and irradiating it along a desired cutting path to induce internal filamentation phenomena, thereby forming a cutting groove of a certain depth within the glass substrate (21). By forming filamentation, defects can be formed within the glass substrate (21) along the cutting surface.

[0156] As the ultrashort laser beam passes through the glass substrate (21), some of it is absorbed and transfers energy to the constituent molecules. Due to the high energy density of the ultrashort laser pulse, the energy density absorbed is also high, and plasma is formed instantaneously inside the glass substrate (21). This plasma also affects the optical properties of subsequent pulses when a continuous pulse is introduced. The plasma generated in this way disappears after a certain lifetime. As a result, it may be deformed into a structure different from the surrounding materials, but depending on the cutting processing conditions, a narrow and long empty space may be formed in the thickness direction of the irradiated part of the ultrashort laser beam, which is called 'filamentation'.

[0157] Filamentation is distinct from gaps or cracks caused by thermal expansion; it is a long, narrow gap formed instantaneously when energy is concentrated on the irradiated portion of an ultrashort laser beam because the pulse width is shorter than the reaction time of the molecular bonding structure, rather than affecting surrounding molecules with thermal or vibrational energy.

[0158] When filamentation is formed, as shown in Fig. 8 (c), the glass substrate (21) can be cut using the filamentation, that is, the glass substrate (21) can be separated into units (Separation).

[0159] As described, to cut the glass substrate (21), tensile stress or rotational force (rotational torque) is applied to the filamentation to separate the glass substrate (21) into two or more units.

[0160] In other embodiments, the glass substrate (21) may be separated using a laser or a dicing saw.

[0161] In this way, when the glass substrate (21) is separated into a predetermined unit, as shown in (c) of FIG. 8, the insulating layers of the upper layer (70) are tapered in a shape that becomes thinner in the direction of the cut surface of the glass substrate (21), and the glass substrate (21) has a shape in which the upper layer (70) is exposed and protrudes in the direction of the cut surface.

[0162] According to an embodiment, when a green laser is used to remove the upper layer (70), the laser speed irradiated on the upper layer (70) may be 20 mm / s to 40 mm / s. The laser speed used for filamentation irradiation may be 50 mm / s to 150 mm / s, or 80 mm / s to 120 mm / s.

[0163] FIG. 9 is a flowchart illustrating the manufacturing process of a packaging substrate according to another embodiment in cross-section.

[0164] As shown in FIG. 9 (a), an upper layer (70) is formed on the first surface of the glass substrate (21), and a lower layer (80) is formed on the second surface. That is, in the glass substrate (21) of FIG. 8, the upper layer (70) was formed only on the first surface among the first and second surfaces, so only the upper layer (70) was removed. However, in the case of FIG. 9, since the lower layer (80) including an insulating layer is formed on the second surface of the glass substrate (21), the insulating layer can be removed on both sides.

[0165] The width of the upper layer (70) and the width of the lower layer (80) being removed may have the same range. Specifically, the width of the lower layer (80) being removed may be 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more, based on the width from the edge of the insulating layer to the edge of the glass substrate in the unit glass substrate. Also, the width may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0166] The width of the upper layer (70) and the lower layer (80) to be removed may vary depending on the design of the semiconductor device or motherboard to be mounted. The removal width of the lower layer (80) may be larger than that of the upper layer (70), and specifically, the difference between the upper layer removal width and the lower layer removal width may be 1 μm or more, 3 μm or more, 5 μm or more, or 10 μm or more. The difference may be 20 μm or less.

[0167] The laser irradiation intensity for removing the insulating layer is not greater than the irradiation intensity for forming the filamentation, and even if the laser is used on both sides, damage or defects may not be formed on the glass substrate (21).

[0168] A laser can be irradiated simultaneously or sequentially on both sides where the upper layer (70) and the lower layer (80) are formed to remove the insulating layer. Meanwhile, the laser for removing the upper layer (70) and the lower layer (80) can be applied to both sides, but as shown in FIG. 9 (b), the laser for generating filamentation can be irradiated on only one side (on a single side) of either the first side or the second side.

[0169] The separation of the glass substrate (21) after the filamentation process can be carried out based on tension or rotational torque from an external force, as shown in (c) of Fig. 9.

[0170] Figures 10 (a) and (b) are photographs of the manufacturing process of a packaging substrate according to an embodiment.

[0171] FIG. 10 (a) is a sectional view and top view photograph of a glass substrate (21, before being separated into units) with the upper layer (70) removed, as shown in FIG. 8 (a) or FIG. 9 (a). That is, it is a photograph corresponding to an enlarged view of the dotted rectangular area of ​​FIG. 9 (a), which is part of the substrate.

[0172] As shown in the sectional view of FIG. 10 (a), the upper layer (70) is removed by a predetermined width (w), and it can be seen in the top view that the glass substrate (21) is exposed by the removed width (w). Also, as can be observed in the sectional view, even when the upper layer (70) is removed, no defect is formed in the glass substrate (21). Additionally, the removed upper layer (70) may have a tapered shape that becomes thinner in the direction of the cutting surface.

[0173] FIG. 10(b) is a photograph showing the cut edges after the glass substrate (21) has been cut into units according to FIG. 8(a) and FIG. 9(a). The glass substrate (21) is separated in a manner that is generally close to a straight line, and the upper layer (70) and the lower layer (80) are each positioned inward from the edge of the glass substrate by a certain distance on both sides of the glass substrate.

[0174] As described, the glass substrate (21) can be separated based on the filamentation formed along a predetermined cutting line. This separation reduces the possibility of defects occurring or being inherent in the glass, and even if defects occur, they can be identified quickly and in a relatively simple manner, thereby further improving the efficiency of the semiconductor packaging substrate manufacturing process, including the unitization process of the glass substrate.

[0175] Meanwhile, according to one embodiment, an edge region placed at the corner of the glass substrate (21) can be processed to become a curved surface. That is, the edge region of the glass substrate (21) can be ground. That is, the corner of the glass substrate (21) can be smoothed from a cut sharp state (see example photo in FIG. 11).

[0176] FIG. 11 is a photograph of a cross-section of a ground glass substrate according to an embodiment.

[0177] As described, the cut surface (indicated as "CL" in FIG. 11) of the glass substrate (21) protruding from the upper or lower layer can be rounded when viewed from the cross-section through grinding. The edge of the glass substrate removed through the grinding process may be approximately 10 μm or more, 20 μm or more, 30 μm or more, or 50 μm or more, and may be approximately 100 μm or less.

[0178] Through grinding, the edges of the cut surface can be curved as shown in FIG. 11, and depending on other embodiments, they can be transformed into a C-shape (curved shape) or R-shape (round shape) chamfer.

[0179] When viewed from the side (or cross-section), the packaging substrate (20) having a cut surface may have a side surface corresponding to the thickness ground. For example, the shape of the ground side surface may be a flat edge where the corners where the side surface and the top surface of the packaging substrate meet are chamfered, or a pencil edge where the side surface connecting the top surface and the bottom surface is rounded so that the central part of the side surface protrudes.

[0180] The side (edge) of the packaging substrate (20) may be in the form of a straight line or a broken part of glass immediately after the cutting surface is formed, and can be manufactured into a shape having a constant radius of curvature by grinding. At this time, the radius of curvature is called the radius of curvature of the side surface.

[0181] The radius of curvature of the side surface of the packaging substrate (20) may be 0.05 mm or more, 0.1 mm or more, 0.15 mm or more, or 0.2 mm or more. The radius of curvature of the side surface may be 2.0 mm or less, 1.8 mm or less, 1.6 mm or less, 1.2 mm or less, 1 mm or less, 0.8 mm or less, or 0.6 mm or less. In this case, workability can be improved, such as minimizing the occurrence of breakage of the packaging substrate or glass substrate during manufacturing, transportation, etc.

[0182] For example, when grinding is performed by setting the design angle of the blade to 90˚±1˚ and the cutting amount to 0.08 to 0.14 mm, a packaging substrate with an edge curvature radius of 0.241 mm can be manufactured.

[0183] In addition, for example, when grinding is performed by setting the design angle of the blade to 120˚±1˚ and the cutting amount to 0.05 to 0.12 mm, a packaging substrate with an edge curvature radius of 0.522 mm can be manufactured.

[0184] FIG. 12 is a photograph of a glass substrate according to another embodiment, taken from above and a portion thereof. The glass substrate may be rounded not only in cross-section but also in parts corresponding to the corners of a rectangle when viewed from above. FIG. 12 (a) is a top view of a unit glass substrate, and the first surface (213) and the second surface (214) may also be rounded at the corners as shown.

[0185] A rectangular packaging substrate has four corners when viewed from above, and each corner is rounded to have a predetermined curvature, thereby eliminating sharp edges. This radius of curvature is referred to as the substrate radius of curvature. The substrate radius of curvature may be 0.5 mm or more, 1 mm or more, 1.2 mm or more, or 1.5 mm or more. The substrate radius of curvature may be 8 mm or less, 7 mm or less, 6 mm or less, or 5 mm or less. In such cases, the occurrence of breakage at the corners is minimized, and at the same time, the area where the electrically conductive layer of the upper layer and / or lower layer is placed can be stably secured.

[0186] Meanwhile, according to an embodiment, the vertices of the square-shaped glass substrate (21) can also be curved through grinding. When the vertices are ground, the risk of damage or breakage can be reduced when moving the glass substrate (21) or transporting it on a tray. The curvature of the ground vertices can be derived as an appropriate value by setting the diameter at which the deviation from a predetermined target value occurs is the smallest.

[0187] The cut surface of an unprocessed glass substrate may have uneven right-angle deviations, and hackles may occur at the cut edges, posing a risk of additional damage such as cracks or chipping. By grinding, glass substrates with curved edges or chamfered cut surfaces can significantly reduce the risk of such additional damage. Furthermore, external impacts can be properly dispersed during the movement of glass substrates or packaging substrates, or during transport on trays for additional processes, thereby minimizing defects caused by cracks or chipping.

[0188] According to another embodiment, grinding can be applied not only to the protruding glass substrate (21) but also to the upper layer or lower layer.

[0189] The packaging substrate and the method for manufacturing the same according to the embodiments described above are effective for inspecting defects that may occur in a packaging substrate including a glass structure, and can effectively protect the glass substrate from external impact.

[0190] The present invention described above has been explained with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. That is, the scope of the present invention is not limited to the embodiments described above, and various modifications and improvements by those skilled in the art using the basic concepts of the embodiments defined in the following claims also fall within the scope of the embodiments. Therefore, the true technical scope of protection of the present invention should be determined by the technical concept of the appended claims. Explanation of the symbols

[0192] 100: Semiconductor device 10: Motherboard 30: Semiconductor Device Division 32: First Semiconductor Device 34: Second semiconductor device 36: Third semiconductor device 20: Packaging substrate 21, 21a: Glass substrate 22: Core layer 223: Core insulation layer 213: Page 1 214: Page 2 213a: Edge area 23: Core Via 24: Core Distribution Layer 241: Core distribution pattern 26, 70: Upper layer 25, 71: Upper distribution layer 251: Upper distribution pattern 253: Upper insulation layer 27: Top surface connection layer 271: Top surface connection electrode 272: Top surface connection pattern 28: Cavity section 281: Internal space 282: Cavity distribution layer 40: Cavity element 60: Cover layer 71: First cover layer 80: Lower layer 81: Lower distribution layer 82: Second cover layer

Claims

Claim 1 A packaging substrate comprising: a glass substrate including a first surface and a second surface facing each other; and an upper layer laminated on the first surface or a lower layer laminated under the second surface, wherein the glass substrate has an edge region, the edge region is the edge of the glass substrate; and a region of the glass substrate protruding from the upper layer or the lower layer; wherein the upper layer includes a first insulating layer laminated on the first surface, the edge of the first insulating layer is disposed inwardly from the edge of the glass substrate, the edge region includes the edge of the glass substrate and the edge of the first insulating layer, the width from the edge of the first insulating layer to the edge of the glass substrate is 5 μm or more and 80 μm or less, the edge of the glass substrate disposed in the edge region is a curved surface, the radius of curvature of the curved surface is called the radius of curvature of the side surface, and the radius of curvature of the side surface is 0.05 mm or more and 2.0 mm or less. Claim 2 delete Claim 3 A packaging substrate according to claim 1, wherein the lower layer comprises a second insulating layer laminated under the second surface, the edge of the second insulating layer is disposed inwardly from the edge of the glass substrate, and the edge region comprises the edge of the glass substrate and the edge of the second insulating layer. Claim 4 A packaging substrate according to claim 3, wherein the edge region comprises the edge of the glass substrate, the edge of the first insulating layer, and the edge of the second insulating layer, and the width from the edge of the first insulating layer to the edge of the glass substrate, the width from the edge of the second insulating layer to the edge of the glass substrate, or the width of all of these is independently 5 μm to 200 μm. Claim 5 delete Claim 6 delete Claim 7 A packaging substrate according to claim 1, wherein the upper layer or the lower layer each has a tapered shape that thins in the direction of the edge region. Claim 8 A packaging substrate according to claim 1, wherein a semiconductor device is mounted on the upper layer. Claim 9 A method for manufacturing a packaging substrate, comprising: a step of preparing a glass substrate including a first surface and a second surface facing each other and forming an upper layer on the first surface; a step of forming a removal line by removing a portion of the upper layer using a laser along a cutting line at a position where cutting is scheduled; a filamentation process step of forming a filament on the glass substrate along the removal line; and a step of cutting the glass substrate using the filamentation; wherein the step of cutting the glass substrate is a step of separating the glass substrate into two or more parts by applying tensile stress or rotational force to the filamentation and forming a cut surface on the glass substrate, and further comprising, after the step of cutting the glass substrate, a step of grinding the cut surface of the cut glass substrate; thereby manufacturing a packaging substrate according to claim 1. Claim 10 A method for manufacturing a packaging substrate according to claim 9, further comprising: a step of forming a lower layer under the second surface prior to the filamentation process step; and a step of removing a portion of the lower layer along the cutting line to form a removal line. Claim 11 A method for manufacturing a packaging substrate according to claim 9 or 10, wherein the width of the removal line is 5 μm or more. Claim 12 A method for manufacturing a packaging substrate according to claim 9 or 10, wherein the upper layer or the lower layer each has a tapered shape that becomes thinner in the direction of the cut surface of the glass substrate. Claim 13 delete Claim 14 delete Claim 15 A method for manufacturing a packaging substrate according to claim 9 or 10, wherein the edge region comprises the edge of the glass substrate; and the region of the glass substrate protruding above the upper layer or the lower layer; and further comprising the step of detecting a defect in any one selected from the group consisting of the edge region of the glass substrate, the cut surface of the glass substrate, the removal line of the upper layer, the removal line of the lower layer, and a combination thereof.

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