display device

Abstract

A display device with minimal display non-uniformity is provided. The display device comprises a first layer and a second layer above the first layer. The first layer has a first circuit arranged in m rows and n columns (where m and n are each integers greater than or equal to 1, and the product of m and n is greater than or equal to 2). The second layer has a pixel block arranged in m rows and n columns, and each pixel block has a pixel arranged in a row and b columns (where a and b are each integers greater than or equal to 1). Additionally, the pixel block has a first wire and a second wire electrically connected to the pixel, and the first wire and the second wire of the pixel block in the i-th row and j-th column (where i is an integer greater than or equal to 1 and m, and j is an integer greater than or equal to 1 and n) are each electrically connected to the first circuit in the i-th row and j-th column. The first wire has the function of supplying an input signal from the first circuit to the pixel, and the second wire has the function of supplying an output signal from the pixel to the first circuit.

Description

Technology Field

[0001] One embodiment of the present invention relates to a display device.

[0002] Furthermore, one embodiment of the present invention is not limited to the technical field described above. Examples of the technical field of one embodiment of the present invention disclosed in this specification, etc. include semiconductor devices, display devices, light-emitting devices, capacitor devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving the same, or methods for manufacturing the same. A semiconductor device refers to any device capable of functioning by utilizing semiconductor characteristics. Background Technology

[0003] Oxide semiconductors using metal oxides as semiconductor materials applicable to transistors are attracting attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer that serves as a channel includes indium and gallium, and the ratio of indium is higher than the ratio of gallium, thereby increasing the field-effect mobility (sometimes simply referred to as mobility or μFE).

[0004] Since metal oxides suitable for use in semiconductor layers can be formed using methods such as sputtering, they can be used in the semiconductor layers of transistors that constitute large display devices. Furthermore, equipment investment can be reduced because parts of the production facilities used for transistors made of polycrystalline silicon or amorphous silicon can be modified and utilized. In addition, since transistors using metal oxides possess higher field-effect mobility compared to those using amorphous silicon, it is possible to realize highly functional display devices equipped with driving circuits.

[0005] Wearable and stationary display devices are becoming widely available as display devices for Augmented Reality (AR) or Virtual Reality (VR). Examples of wearable display devices include Head Mounted Displays (HMDs) and glasses-type display devices. Examples of stationary display devices include Head-Up Displays (HUDs).

[0006] In an electronic device having an imaging device such as a digital camera, a viewfinder is used to check the image to be captured before capturing. Additionally, an electronic viewfinder is used as a viewfinder. An electronic viewfinder is provided with a display unit, and an image obtained by an imaging device can be displayed as an image on the display unit. For example, Patent Document 2 discloses an electronic viewfinder that can obtain a good viewing state from the center of the image to the periphery of the image. Prior art literature

[0007] Japanese Patent Publication No. JP 2014-7399 Japanese Patent Publication No. JP 2012-42569 The problem to be solved

[0008] Display devices, such as head-mounted displays (HMDs), where the distance between the display surface and the user is close, may degrade the sense of immersion or presence in AR or VR because users can easily perceive pixels and thus feel a strong sense of graininess. Additionally, electronic viewfinders are provided with an eyepiece, similar to optical viewfinders, and the image displayed on the electronic viewfinder's display is perceived by the user bringing their eyes close to the eyepiece. Consequently, the distance between the electronic viewfinder's display and the user becomes close. As a result, users may perceive a strong sense of graininess because they can easily perceive the pixels provided on the display. For the reasons described above, HMDs and electronic viewfinders require display devices with high-resolution pixels so that pixels are not visible to the user. For example, it is desirable to have a resolution of 1,000 ppi or higher, more desirable to have 2,000 ppi or higher, and even more desirable to have 5,000 ppi or higher. In addition, for example, it is desirable that the display device provided in the electronic viewfinder be able to display images of 4K (pixels: 3840X2160), 5K (pixels: 5120X2880), or higher resolution.

[0009] As the number of pixels in a display device increases, the number of transistors and display elements in the device also increases, which can lead to significant display non-uniformity caused by variations in transistor characteristics and display elements characteristics.

[0010] One embodiment of the present invention has as its objective to provide a display device with minimal display non-uniformity. Alternatively, one embodiment of the present invention has as its objective to provide a display device with a small bezel. Alternatively, one embodiment of the present invention has as its objective to provide a compact display device. Alternatively, one embodiment of the present invention has as its objective to provide a display device with a high degree of layout freedom. Alternatively, one embodiment of the present invention has as its objective to provide a display device with high resolution. Alternatively, one embodiment of the present invention has as its objective to provide a display device capable of displaying high-quality images. Alternatively, one embodiment of the present invention has as its objective to provide a display device capable of displaying images with high realism. Alternatively, one embodiment of the present invention has as its objective to provide a display device capable of displaying high-brightness images. Alternatively, one embodiment of the present invention has as its objective to provide a display device that operates at high speed. Alternatively, one embodiment of the present invention has as its objective to provide a display device with low power consumption. Alternatively, one embodiment of the present invention has as its objective to provide an inexpensive display device. Alternatively, one embodiment of the present invention has as its objective to provide a highly reliable display device. Alternatively, one embodiment of the present invention has as its objective to provide a novel display device. Alternatively, one embodiment of the present invention has as its objective to provide a method of operating the display device. Alternatively, one embodiment of the present invention has as its objective to provide an electronic device having the display device.

[0011] Furthermore, the description of these problems does not interfere with the existence of other problems. Also, one embodiment of the present invention is not required to solve all of these problems. Additionally, problems other than these can be derived from the description in the specification, drawings, claims, etc. means of solving the problem

[0012] One embodiment of the present invention is a display device having a first layer and a second layer above the first layer. The first layer has a first circuit arranged in m rows and n columns (where m and n are each integers greater than or equal to 1, and the product of m and n is greater than or equal to 2). The second layer has a pixel block arranged in m rows and n columns, and each pixel block has a pixel arranged in a row b (where a and b are each integers greater than or equal to 1). Additionally, the pixel block has a first wire and a second wire electrically connected to the pixel, and it is preferable that the first wire and the second wire of the pixel block in the i-th row and j-th column (where i is an integer greater than or equal to 1 and m, and j is an integer greater than or equal to 1 and n) are each electrically connected to the first circuit in the i-th row and j-th column. It is preferable that the first wire has the function of supplying an input signal from the first circuit to the pixel, and the second wire has the function of supplying an output signal from the pixel to the first circuit.

[0013] In the display device described above, the first circuit comprises a correction data generation circuit, a logic circuit, and a source driver circuit. It is preferable that the correction data generation circuit has a function of converting an output signal into correction data. It is preferable that the logic circuit has a function of correcting a video signal input to the first circuit based on the correction data and generating a corrected video signal. It is preferable that the source driver circuit has a function of converting the corrected video signal into an input signal.

[0014] In the display device described above, it is preferable that the pixel block at row i and column j has an area that overlaps with the first circuit at row i and column j.

[0015] In the display device described above, it is preferable that the pixel block at row p and column q (where p is an integer greater than or equal to m and q is an integer greater than or equal to n and 1 and 20 and 30 and 60 and 7

[0016] In the display device described above, it is preferable that the second layer further has m second circuits arranged in a column direction. A pixel block has a third wiring that is electrically connected to a plurality of pixels arranged in a row direction, and it is preferable that the third wiring of the pixel block in the i-th row is electrically connected to the i-th second circuit.

[0017] In the display device described above, it is preferable that the first layer further has m second circuits arranged in a column direction. A pixel block has a third wiring that is electrically connected to a plurality of pixels arranged in a row direction, and it is preferable that the third wiring of the pixel block in the i-th row is electrically connected to the i-th second circuit. In addition, it is preferable that the pixel block in the i-th row and j-th column has an area that overlaps with one or more of the second circuits.

[0018] In the display device described above, it is preferable that the correction data generation circuit has a memory circuit. Additionally, it is preferable that the first layer has a first circuit layer and a second circuit layer above the first circuit layer. The first circuit layer has a logic circuit, and it is preferable that the logic circuit has a transistor having silicon in a channel forming region. The second circuit layer has a memory circuit, and it is preferable that the memory circuit has a transistor having a metal oxide in a channel forming region. Additionally, it is preferable that the metal oxide has In, an element M (M is one or more of Al, Ga, Y, and Sn), and Zn.

[0019] In the display device described above, it is preferable for the pixel to have a transistor having a metal oxide in the channel forming region. Additionally, it is preferable for the metal oxide to have In, an element M (where M is one or more of Al, Ga, Y, and Sn), and Zn.

[0020] In the display device described above, it is preferable that the pixel has a transistor having silicon in the channel forming region. Effects of the invention

[0021] According to one embodiment of the present invention, a display device with minimal display non-uniformity can be provided. Alternatively, according to one embodiment of the present invention, a display device with a small bezel can be provided. Alternatively, according to one embodiment of the present invention, a compact display device can be provided. Alternatively, according to one embodiment of the present invention, a display device with a high degree of layout freedom can be provided. Alternatively, according to one embodiment of the present invention, a display device with high resolution can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of displaying high-quality images can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of displaying images with high realism can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of displaying high-brightness images can be provided. Alternatively, according to one embodiment of the present invention, a display device operating at high speed can be provided. Alternatively, according to one embodiment of the present invention, a display device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, an inexpensive display device can be provided. Alternatively, according to one embodiment of the present invention, a display device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a novel display device can be provided. Alternatively, according to one embodiment of the present invention, a method of operating the above display device can be provided. Alternatively, an electronic device having the display device may be provided according to one embodiment of the present invention.

[0022] Furthermore, the description of these effects does not interfere with the existence of other effects. Also, one embodiment of the present invention does not necessarily have to possess all of these effects. Additionally, effects other than these can be derived from the description in the specification, drawings, claims, etc. Brief explanation of the drawing

[0023] Figure 1 (A) is a schematic diagram showing an example of the configuration of a display device. Figure 1 (B) is a block diagram showing an example of the configuration of a display device. Figure 2 is a block diagram showing an example of the configuration of a display device. Figure 3 is a block diagram showing an example of the configuration of a display device. Figure 4 is a block diagram showing an example of the configuration of a display device. Figure 5 is a block diagram showing an example of the configuration of a display device. Figure 6 is a block diagram showing an example of the configuration of a display device. Figure 7 is a block diagram showing an example of the configuration of a display device. Figure 8 is a block diagram showing an example of the configuration of a display device. FIG. 9 is a block diagram showing an example of the configuration of a display device. FIG. 10 is a block diagram showing an example of the configuration of a display device. FIG. 11 is a block diagram showing an example of the configuration of a display device. Figure 12 (A) is a schematic diagram showing an example of the configuration of a display device. Figure 12 (B) is a block diagram showing an example of the configuration of a display device. FIG. 13 is a block diagram showing an example of the configuration of a display device. FIG. 14 is a block diagram showing an example of the configuration of a display device. FIG. 15 is a block diagram showing an example of the configuration of a display device. FIG. 16 is a block diagram showing an example of the configuration of a display device. FIG. 17 is a block diagram showing an example of the configuration of a display device. Figure 18 is a circuit diagram showing an example of pixel configuration. Figures 19 (A) and (B) are circuit diagrams showing examples of pixel configurations. Figures 20 (A) and (B) are circuit diagrams showing examples of pixel configurations. FIG. 21 is a cross-sectional view showing an example of the configuration of a display device. FIG. 22 is a cross-sectional view showing an example of the configuration of a display device. FIG. 23 is a cross-sectional view showing an example of the configuration of a display device. FIG. 24 is a cross-sectional view showing an example of the configuration of a display device. FIG. 25 is a cross-sectional view showing an example of the configuration of a display device. Figures 26 (A) and (B) are top views showing examples of pixel configurations. FIG. 27 is a top view showing an example of pixel configuration. FIG. 28 is a cross-sectional view showing an example of pixel configuration. Figures (A), (B), (C), (D), and (E) of FIG. 29 are diagrams showing examples of the configuration of a light-emitting element. Figure 30 (A) is a top view showing an example of a transistor configuration. Figures 30 (B) and (C) are cross-sectional views showing examples of a transistor configuration. Figure 31 (A) is a top view showing an example of a transistor configuration. Figures 31 (B) and (C) are cross-sectional views showing examples of a transistor configuration. Figure 32 (A) is a top view showing an example of a transistor configuration. Figures 32 (B) and (C) are cross-sectional views showing examples of a transistor configuration. Figure 33 (A) is a diagram illustrating the classification of the crystal structure of IGZO. Figure 33 (B) is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 33 (C) is a diagram illustrating the ultrafine electron diffraction pattern of the CAAC-IGZO film. Figures 34 (A), (B), (C), (D), and (E) are perspective views showing examples of electronic devices. Figures (A), (B), (C), (D), (E), (F), and (G) of FIG. 35 are perspective views showing examples of electronic devices. Specific details for implementing the invention

[0024] Hereinafter, embodiments are described with reference to the drawings. However, it is readily understood by those skilled in the art that embodiments can be implemented in many different forms and that their forms and details can be varied without departing from the intent and scope thereof. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments described below.

[0025] In addition, in each drawing described in this specification, the size, thickness, or area of ​​each component may be exaggerated for clarity.

[0026] In addition, the ordinal numbers ‘first’, ‘second’, and ‘third’ used in this specification are attached to avoid confusion of components and are not numerically limited.

[0027] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships of the components with reference to the drawings. Additionally, the positional relationships of the components change appropriately depending on the direction in which each component is depicted. Therefore, the terminology described in this specification is not limited to the descriptions provided and can be appropriately changed depending on the context.

[0028] In addition, in this specification and others, the functions of the source and drain of a transistor may change when the polarity of the transistor or the direction of current in circuit operation changes. Therefore, the terms source and drain may be used interchangeably.

[0029] In this specification and other contexts, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Additionally, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wiring," and "terminals" are formed as a single unit. Therefore, for example, an "electrode" may be part of "wiring" or a "terminal," and for example, a "terminal" may be part of "wiring" or an "electrode." Additionally, terms such as "electrode," "wiring," and "terminal" may be substituted with terms such as "region" depending on the context.

[0030] Furthermore, in this specification and others, the term 'resistance' may refer to cases where the resistance value is determined by the length of the wiring. Alternatively, resistance may include cases where a conductor used in the wiring is connected to a different, low-efficiency conductor through a contact. Or, the resistance value may be determined by doping a semiconductor with impurities.

[0031] Furthermore, in this specification and others, "electrically connected" includes cases of direct connection and cases of connection through "some electrical action." Here, "some electrical action" is not subject to any particular limitation as long as it enables the exchange of electrical signals between the connected objects. Therefore, even when expressed as "electrically connected," there may be no physical connection part in the actual circuit, and the wiring may simply be extended. Additionally, even when expressed as "direct connection," cases where wiring is formed through contacts with different conductors are included. Furthermore, regarding the wiring, there are cases where the different conductors contain one or more of the same element, or cases where they contain different elements.

[0032] Additionally, in this specification and others, the terms "film" and "layer" may be interchangeable. For example, the terms "conductive layer" or "insulating layer" may be interchangeable with the terms "conductive film" or "insulating film."

[0033] Furthermore, in this specification and others, off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or cutoff state) unless specifically stated otherwise. The off state refers to the voltage between the gate and source (V) in an n-channel transistor, unless specifically stated otherwise. gs ) is the threshold voltage (V th Lower than ) (in p-channel transistors, V th It refers to a higher state.

[0034] In addition, sizes, layer thicknesses, or areas in drawings may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Furthermore, drawings are schematic representations and are not limited to the shapes or values ​​shown in the drawings. For example, layers or resist masks may be unintentionally reduced during the actual manufacturing process due to treatments such as etching, but this may not be reflected in the drawings to facilitate understanding. Additionally, the same reference numerals are used across different drawings for identical parts or parts having the same function or material, and repetitive descriptions of these parts may be omitted. Furthermore, when referring to the same function or material, the hatch pattern may be identical, and no specific reference numeral may be assigned.

[0035] In this specification and other contexts, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to simply as Oxide Semiconductors or OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be rephrased as a transistor having an oxide or an oxide semiconductor.

[0036] (Embodiment 1)

[0037] In this embodiment, a display device which is one form of the present invention is described.

[0038] One embodiment of the present invention is a display device having a first layer and a second layer above the first layer. The first layer has a first circuit arranged in m rows and n columns (where m and n are each integers greater than or equal to 1, and the product of m and n is greater than or equal to 2). The second layer has a pixel block arranged in m rows and n columns, and each pixel block has a pixel arranged in a row b (where a and b are each integers greater than or equal to 1). Additionally, the pixel block has a first wire and a second wire electrically connected to the pixel, and it is preferable that the first wire and the second wire of the pixel block in the i-th row and j-th column (where i is an integer greater than or equal to 1 and m, and j is an integer greater than or equal to 1 and n) are each electrically connected to the first circuit in the i-th row and j-th column. It is preferable that the first wire has the function of supplying an input signal from the first circuit to the pixel, and the second wire has the function of supplying an output signal from the pixel to the first circuit.

[0039] In the display device described above, the first circuit comprises a correction data generation circuit, a logic circuit, and a source driver circuit. It is preferable that the correction data generation circuit has a function of converting an output signal into correction data. It is preferable that the logic circuit has a function of correcting a video signal input to the first circuit based on the correction data and generating a corrected video signal. It is preferable that the source driver circuit has a function of converting the corrected video signal into an input signal.

[0040] In addition, in the present specification and other documents, the operation of a first circuit correcting a video signal based on an output signal from a pixel and outputting the corrected video signal to a pixel as an input signal may be described as correction or a correction operation. By correcting a signal input to a pixel (input signal) based on a current value (output signal) flowing through a pixel, luminance non-uniformity between pixels can be reduced.

[0041] A display device of one embodiment of the present invention can be made into a display device with minimal display non-uniformity by having a first circuit perform a correction operation. A display device of one embodiment of the present invention has a plurality of first circuits, and the plurality of first circuits can perform a correction operation in parallel. Compared to the case where a correction operation is performed sequentially for each row of the display unit, by having the plurality of first circuits perform the correction operation in parallel, the time required for the correction operation for the entire display unit can be shortened. Accordingly, a display device of one embodiment of the present invention can be made into a display device that operates at high speed. In addition, for example, the time required to record an input signal corresponding to one frame of an image into a pixel can be shortened. Therefore, a display device with a large number of pixels can be made to operate at high speed and can be made into a display device with high resolution. For example, the resolution of a display device of one embodiment of the present invention can be made to 1000 ppi or more, 2000 ppi or more, or 5000 ppi or more.

[0042] It is preferable that the pixel block at row i and column j has an area that overlaps with the first circuit at row i and column j. By having the pixel block have an area that overlaps with the first circuit, the bezel area, which is the area where the pixel block is not provided, can be reduced. Thus, a display device with a narrow bezel can be made. In addition, by narrowing the bezel of the display device, a compact display device can be made. Furthermore, the pixel block at row p and column q (where p is an integer greater than or equal to m and different from i, and q is an integer greater than or equal to n and different from j) may be configured so as not to overlap with the first circuit at row p and column q.

[0043] It is preferable that the second layer has m second circuits arranged in a column direction. A pixel block has a third wiring that is electrically connected to a plurality of pixels arranged in a row direction. It is preferable that the third wiring of the pixel block in the i-th row is electrically connected to the i-th second circuit. Alternatively, the first layer may have m second circuits arranged in a column direction. In addition, it is preferable that the pixel block in the i-th row and j-th column has an area that overlaps with one or more of the second circuits. By having an area that overlaps with the second circuits, the pixel block can be made into a small display device.

[0044] It is preferable that the correction data generation circuit has a memory circuit. Additionally, the first layer has a first circuit layer and a second circuit layer above the first circuit layer. The first circuit layer has a logic circuit, and it is preferable that the logic circuit has a transistor having silicon in a channel forming region. The second circuit layer has a memory circuit, and it is preferable that the memory circuit has a transistor having a metal oxide in a channel forming region. It is preferable that the metal oxide has In, an element M (M is one or more of Al, Ga, Y, and Sn), and Zn. Furthermore, it is more preferable that the element M has either or both of Ga and Sn.

[0045] A display device of one form of the present invention will be described in detail below.

[0046] <Configuration Example 1 of a Display Device>

[0047] A schematic diagram of a display device (10) which is one embodiment of the present invention is shown in FIG. 1 (A). As shown in FIG. 1 (A), the display device (10) has a stacked structure of a first layer (20) and a second layer (30) on top of the first layer (20). FIG. 1 (A) shows a configuration in which the second layer (30) is provided on top of the first layer (20), but one embodiment of the present invention is not limited thereto. The first layer (20) may be provided on top of the second layer (30). One or more of an interlayer insulating layer and a wiring layer may be provided between the first layer (20) and the second layer (30). In addition, the interlayer insulating layer and the wiring layer provided between the first layer (20) and the second layer (30) may each be provided in multiple numbers.

[0048] The first layer (20) has a first circuit (21). The second layer (30) has a second circuit (22) and a display unit (33). The first circuit (21) and the second circuit (22) are circuits for driving the display device (10). Therefore, these circuits can be called driving circuits. The first circuit (21) has the function of generating an input signal that is input to a pixel (34). The second circuit (22) has the function of selecting a pixel (34) where the input signal generated by the first circuit (21) is recorded, and can also be called a gate driver circuit.

[0049] A block diagram showing an example configuration of a display device (10) is shown in (B) of FIG. 1. The first layer (20) has a first circuit (21[1,1] to 22[m,n]) arranged in m rows and n columns. The second layer (30) has a display unit (33), and the display unit (33) has pixel blocks (38[1,1] to 38[m,n]) arranged in m rows and n columns. Each pixel block (38[1,1] to 38[m,n]) has a plurality of pixels (34). In addition, the second layer (30) has m second circuits (22[1] to 22[m]) arranged in a column direction.

[0050] In addition, when the same reference numeral is used for multiple elements in the present specification, etc., particularly when it is necessary to distinguish them, identification symbols such as "[m,n]" or "[m]" may be added to the reference numeral. For example, the pixel block (38) in the first row and first column is described as pixel block (38[1,1]), and the pixel block (38) in the m row and n column is described as pixel block (38[m,n]). For example, the first second circuit (22) is described as second circuit (22[1]), and the m-th second circuit (22) is described as second circuit (22[m]).

[0051] A block diagram showing an example configuration of a display device (10) is shown in FIG. 2. As shown in FIG. 2, each pixel block (38[1,1] to 38[m,n]) has a pixel (34) arranged in row a and column b (where a and b are integers greater than or equal to 1). That is, the display unit (33) has a pixel (34[1,1] to 34[am,bn]) arranged in row am and column bn. In addition, the pixel block (38) has a wiring (32) and a wiring (36) that are electrically connected to the pixel (34). In addition, the pixel block (38) has a wiring (31) that is electrically connected to the pixel (34). The wiring (32) has the function of supplying an input signal from the first circuit (21) to the pixel (34) and can also be called a source line or a signal line. The wiring (36) has the function of supplying an output signal from the pixel (34) to the first circuit (21) and can also be called a monitor line. The wiring (31) has the function of supplying a signal from the second circuit (22) to the pixel (34), and can also be called a gate line or a scan line.

[0052] The connection relationship of each component is explained using FIG. 3, with the pixel block (38[i,j]) in row i and column j as an example.

[0053] The wiring (32[i,b(j-1)+1] to 32[i,bj]) of the pixel block (38[i,j]) is electrically connected to the first circuit (21[i,j]) in the i-th row and j-th column. Each of the wiring (32[i,b(j-1)+1] to 32[i,bj]) is electrically connected to a number of pixels (34) arranged in a column direction in the pixel block (38[i,j]). For example, the wiring (32[i,b(j-1)+1]) is electrically connected to pixels (34[a(i-1)+1,b(j-1)+1] to [ai,b(j-1)+1]).

[0054] The wiring (36[i,b(j-1)+1] to 36[i,bj]) of the pixel block (38[i,j]) is electrically connected to the first circuit (21[i,j]) in the i-th row and j-th column. Each of the wiring (36[i,b(j-1)+1] to 36[i,bj]) is electrically connected to a number of pixels (34) arranged in a column direction in the pixel block (38[i,j]). For example, the wiring (36[i,b(j-1)+1]) is electrically connected to pixels (34[a(i-1)+1,b(j-1)+1] to [ai,b(j-1)+1]).

[0055] The wiring (31[a(i-1)+1] to 31[ai]) of the pixel block (38[i,j]) is electrically connected to the i-th second circuit (22[i]). Each of the wiring (31[a(i-1)+1] to 31[ai]) is electrically connected to bn pixels (34) arranged in a row direction in the display unit (33) (see FIG. 2). For example, wiring (31)[a(i-1)+1] is electrically connected to pixels (34[a(i-1)+1,1] to [a(i-1)+1,bn]) in the display unit (33). Wiring (31[a(i-1)+1]) is electrically connected to pixels (34[a(i-1)+1,b(j-1)+1] to [a(i-1)+1,bj]) in the pixel block (38[i,j]).

[0056] <Example of configuration of the first circuit (21)>

[0057] Each of the first circuits (21[1,1] to 21[m,n]) has a correction data generation circuit (24), a logic circuit (81), and a source driver circuit (26).

[0058] As shown in FIG. 3, the first circuit (21[i,j]) has a correction data generation circuit (24[i,j]), a logic circuit (81[i,j]), and a source driver circuit (26[i,j]).

[0059] The correction data generation circuit (24[i,j]) has the function of converting the output signal from the first circuit (21[i,j]) into correction data. The output signal is supplied from the pixel (34[i,j]) to the first circuit (21[i,j]) through the wiring (36). The wiring (36) functions as a monitor line.

[0060] The logic circuit (81[i,j]) has the function of correcting the video signal input to the first circuit (21[i,j]) based on correction data and generating the corrected video signal.

[0061] The source driver circuit (26[i,j]) has the function of converting a corrected video signal into an input signal. The input signal is supplied from the first circuit (21[i,j]) to the pixel block (38[i,j]) through the wiring (32). The wiring (32) functions as a data line.

[0062] An example of the configuration of the correction data generation circuit (24) is described.

[0063] Each of the correction data generation circuits (24[1,1] to 24[m,n]) has a current-voltage conversion circuit (91), an analog-to-digital conversion circuit (92), and a memory circuit (93).

[0064] As shown in FIG. 3, the correction data generation circuit (24[i,j]) has a current-voltage conversion circuit (91[i,j]), an analog-to-digital conversion circuit (92[i,j]), and a memory circuit (93[i,j]).

[0065] The current-voltage conversion circuit (91) has the function of converting the current value flowing through the wiring (36) into a voltage value and outputting it to the analog-to-digital conversion circuit (92).

[0066] The analog-to-digital conversion circuit (92) has the function of converting the analog voltage value output by the current-voltage conversion circuit (91) into a digital voltage value and outputting it to the memory circuit (93).

[0067] The memory circuit (93) has the function of storing a digital voltage value output by the analog-to-digital conversion circuit (92). Additionally, the voltage value based on the current value flowing (output) from the pixel (34) to the wiring (36) can be used as correction data to correct the current value flowing through the pixel (34). Furthermore, the memory circuit (93) has the function of outputting the stored correction data to the logic circuit (81).

[0068] The logic circuit (81) has the function of correcting the video signal input to the first circuit (21) based on the correction data output by the memory circuit (93) and generating the corrected video signal.

[0069] Additionally, the display device (10) may have a receiving circuit (not shown). The receiving circuit has the function of receiving a video signal that serves as the basis for the corrected video signal generated by the first circuit (21). The video signal may be single-ended digital data. The receiving circuit may have the function of receiving data using a data transmission signal such as LVDS (Low Voltage Differential Signaling), and the function of converting it into an internally processable signal standard.

[0070] An example of the configuration of the source driver circuit (26) is described.

[0071] Each source driver circuit (26[1,1] to 26[m,n]) has a shift register circuit (44), a latch circuit (45), a digital-to-analog conversion circuit (46), and an amplifier circuit (47).

[0072] As shown in FIG. 3, the source driver circuit ([i,j]) has a shift register circuit (44[i,j]), a latch circuit (45), a digital-to-analog conversion circuit (46[i,j]), and an amplifier circuit (47[i,j]).

[0073] The shift register circuit (44) has the function of generating a signal to control the operation of the latch circuit (45).

[0074] The latch circuit (45) has the function of maintaining or outputting correction data output by the logic circuit (81). Whether the latch circuit (45) performs the operation of maintaining or outputting data is selected based on the signal supplied from the shift register circuit (44).

[0075] The digital-to-analog conversion circuit (46) has the function of converting the digital corrected video signal maintained by the latch circuit (45) into an analog corrected video signal.

[0076] The amplifier circuit (47) has the function of amplifying the analog corrected video signal output by the digital-to-analog conversion circuit (46) and outputting it to the wiring (32) as an input signal. By providing the amplifier circuit (47), the corrected video signal represented by the analog signal can be stably supplied to the pixel (34). As the amplifier circuit (47), a voltage follower circuit having an operational amplifier, etc., can be applied. In addition, when using a circuit having a differential input circuit as the amplifier circuit, it is preferable that the offset voltage of the differential input circuit be 0V or a voltage as close to 0V as possible.

[0077] <Example of configuration of the second circuit (22)>

[0078] The second circuit (22), which functions as a gate driver circuit, has the function of selecting a pixel (34) in which a potential corresponding to the image data generated by the first circuit (21) is recorded. For example, the second circuit (22) can generate a selection signal and supply the selection signal to a pixel (34) of a specific row. A potential corresponding to the image data can be recorded in the pixel (34) to which the selection signal is supplied.

[0079] A pixel block (38) has wiring (31) that is electrically connected to a plurality of pixels (34) arranged in a row direction. The wiring (31) of the pixel block (38) of the i-th row is electrically connected to the i-th second circuit (22).

[0080] For example, the second circuit (22[i]) selects the pixel (34) of the first row in the pixel block (38[i,j]), then selects the pixel (34) of the second row, and then sequentially selects up to the pixel (34) of the a-th row, and then selects the pixel (34) of the first row again. That is, the second circuit (22) can be said to have the function of scanning the pixel (34). Also, the selection signal can be supplied to the pixel (34) from the second circuit (22) through the wiring (31). As described above, the wiring (31) can be said to have the function of a scan line. Also, when performing interlaced driving, after selecting the pixel (34) of the first row, the pixel (34) of the second row is not selected, but, for example, the pixel (34) of the third row or the fourth row or later is selected. For example, if m is an even number, pixels (34) in odd-numbered rows can be selected sequentially, and then pixels (34) in even-numbered rows can be selected sequentially.

[0081] The display unit (33) has the function of displaying an image corresponding to the image data supplied to the pixel (34). Specifically, an image is displayed on the display unit (33) by emitting light of a brightness corresponding to the image data from the pixel (34).

[0082] In addition, the color of the light emitted from the pixel (34) can be, for example, red, green, blue, etc. For example, by providing a pixel (34) that emits red light, a pixel (34) that emits green light, and a pixel (34) that emits blue light to the display unit (33), the display device (10) can display full color. In this case, the pixel (34) can be called a subpixel.

[0083] <Example of correction operation of display device (10)>

[0084] An example of a correction operation of a display device (10) is described using FIGS. 4 to 6. In FIGS. 4 to 6, a correction operation is shown using a pixel block (38[i,j]) as an example. The correction operation can be performed in three stages: a reference data recording operation, a correction data acquisition operation, and a display operation.

[0085] An example of a reference data recording operation is shown in Fig. 4.

[0086] The reference data recording operation refers to the operation of recording reference data (hereinafter also referred to as the reference video signal) that serves as the standard for correction into a pixel (34). First, the reference video signal is input into the first circuit (21[i,j]), and the reference video signal is supplied to the source driver circuit (26[i,j]) through the logic circuit (81). In the source driver circuit (26[i,j]), the reference video signal is converted into an input signal, and the input signal is supplied to the pixel block (38[i,j]) through the wiring (32).

[0087] The reference data recording operation can be performed in parallel in a plurality of first circuits (21). For example, all first circuits (21[1,1] to 21[m,n]) of the display device (10) may each perform the reference data recording operation in parallel. By having a plurality of first circuits perform the reference data recording operation in parallel, the time required for the reference data recording operation for the entire display unit (33) can be shortened.

[0088] Additionally, the operation of the correction data generation circuit (24) can be stopped during the period of performing the reference data recording operation. By stopping the operation of the correction data generation circuit (24), the display device (10) can be made to have low power consumption.

[0089] In addition, one or more grayscale values ​​may be used in the reference video signal. For example, one or more of the maximum grayscale value, the minimum grayscale value, and the intermediate grayscale value may be used in the reference video signal. For example, in the case of 8-bit grayscale, the maximum grayscale value 255, the minimum grayscale value 0, the intermediate grayscale value 125, etc. may be used in the reference video signal.

[0090] In a display device with high precision, the size of the pixel (34) is small and the size of the transistor in the pixel (34) is small, so the current flowing through the transistor may be small. Therefore, the precision of the correction operation can be increased by using a reference video signal (e.g., the maximum grayscale value) in which the current flowing through the transistor is large. In addition, multiple grayscale values ​​may be used in the reference video signal. For example, by using three types of reference video signals, such as the maximum grayscale value, the minimum grayscale value, and the intermediate grayscale value, the correction operation can be performed over a wide grayscale range, thereby increasing the precision of the correction operation.

[0091] An example of the correction data acquisition operation is shown in Fig. 5.

[0092] The operation of acquiring correction data refers to the operation of inputting a current value (also called an output signal) from a pixel (34) in which reference data is recorded into a first circuit (21[i,j]) and generating correction data. The output signal from the pixel (34) is supplied to a correction data generation circuit (24[i,j]) through wiring (36). In the correction data generation circuit (24[i,j]), the output current is converted into correction data, and the correction data corresponding to the reference data is maintained in the correction data generation circuit (24[i,j]).

[0093] The correction data acquisition operation can be performed in parallel by a plurality of first circuits (21). For example, all first circuits (21[1,1] to 21[m,n]) of the display device (10) may each perform the correction data acquisition operation in parallel. Compared to the case where the correction data acquisition operation is performed sequentially for each row of the display unit (33), the time required for the correction data acquisition operation for the entire display unit (33) can be shortened by having a plurality of first circuits perform the correction data acquisition operation in parallel.

[0094] Additionally, the operation of the logic circuit (81) and the source driver circuit (26) can be stopped during the period of performing the correction data acquisition operation. By stopping the operation of the logic circuit (81) and the source driver circuit (26), the display device (10) can be made to have low power consumption.

[0095] In addition, if no correction operation is performed, the correction data generation circuit (24) may be stopped. By stopping the correction data generation circuit (24), the display device (10) can be made to have low power consumption.

[0096] An example of the display operation is shown in Fig. 6.

[0097] The display operation refers to the operation of correcting the video signal input to the first circuit (21) and displaying an image on the display unit (33). Specifically, the correction data maintained in the correction data generation circuit (24[i,j]) and the video signal input to the first circuit (21) are supplied to the logic circuit (81). The logic circuit (81) corrects the video signal based on the correction data and generates the corrected video signal. The corrected video signal is converted into an input signal in the source driver circuit (26), and the input signal is supplied to the pixel block (38[i,j]) through the wiring (32).

[0098] By the correction operation described above, a display device (10) of one form of the present invention can be made into a display device with less unevenness in display.

[0099] In addition, the reference data recording operation and the correction data acquisition operation do not need to be performed for every frame. For example, the reference data recording operation and the correction data acquisition operation may be performed only when the display device (10) starts up, and only the display operation may be performed in subsequent frames. For example, if the reference data recording operation and the correction data acquisition operation are performed only when the display device (10) starts up, the correction data acquired at the time of startup is maintained in the correction data generation circuit (24[i,j]), and the display operation can be performed using the correction data in subsequent frames as well.

[0100] A display device of one embodiment of the present invention may have a plurality of first circuits (21) to reduce the number of pixels (34) per one first circuit (21). Additionally, the display device may have a plurality of second circuits (22) to reduce the number of pixels (34) per one second circuit (22). Since the plurality of first circuits (21) can each operate in parallel and the plurality of second circuits (22) can each operate in parallel, the time required to record image data corresponding to one frame of an image into the pixels (34), for example, can be shortened. Therefore, the length of one frame period can be shortened and the display device (10) can be operated at high speed. Furthermore, the number of pixels (34) of the display device (10) can be increased and the resolution of the display device (10) can be increased. For example, the resolution of the display device (10) can be full high vision, 4K2K, 8K4K, 16K8K, or higher than these.

[0101] For example, the resolution of the display device (10) can be set to 1000 ppi or higher, 2000 ppi or higher, or 5000 ppi or higher. Accordingly, high-quality images with low graininess can be displayed on the display device (10), thereby displaying images with high realism. Accordingly, the display device (10) can be used particularly well with devices where the distance between the display surface and the user is close, particularly portable electronic devices, wearable electronic devices, and e-book terminals. It can also be used well with VR devices and AR devices. Furthermore, it can be used well with viewfinders such as electronic viewfinders provided in digital cameras, which are electronic devices having an imaging device.

[0102] Additionally, each pixel block (38) has pixels (34) arranged in rows a and columns b (where a and b are integers greater than or equal to 1). By increasing the number of pixels (34) in one pixel block (38), the number of first circuits (21) provided to the display device (10) is reduced, making it possible to have a display device (10) with low power consumption. Also, by reducing the number of pixels (34) in one pixel block (38), the number of first circuits (21) provided to the display device (10) is increased, making it possible to perform correction efficiently. Therefore, it is possible to have a display device (10) with less display non-uniformity.

[0103] An example of the configuration of the first layer (20) and the second layer (30) shown in (A) of FIG. 1 is shown in FIG. 7. In FIG. 7, the positional relationship between the first layer (20) and the second layer (30) is indicated by white circles and dashed lines, and the white circle of the first layer (20) and the white circle of the second layer (30), connected by dashed lines, overlap. In other drawings, it is indicated in the same way. Also, for clarity of the drawing, wiring (31), wiring (32), and wiring (36) have been omitted in FIG. 7.

[0104] It is preferable that the display device (10) has an area where the first circuit (21) provided on the first layer (20) overlaps with the display portion (33). FIG. 7 shows an example in which pixel blocks (38[1,1] to 38[m,n]) each have an area that overlaps with the first circuit (21[1,1] to 21[m,n]). By stacking the display portion (33) and the first circuit (21) so that they have overlapping areas, the area of ​​the bezel, which is the area where the display portion (33) is not provided, can be reduced. Accordingly, the bezel of the display device (10) can be made narrow. In addition, by making the bezel of the display device (10) narrow, the display device (10) can be miniaturized.

[0105] FIG. 7 illustrates an example in which the pixel block (38) and the first circuit (21) have approximately the same size and each pixel block (38[1,1] to 38[m,n]) has an overlapping area with each of the first circuits (21[1,1] to 21[m,n]), but the scope of the present invention is not limited thereto. The sizes of the pixel block (38) and the first circuit (21) may be different. Also, if the first circuit (21) is larger than the pixel block (38), the bezel of the display device (10) may be wide. Therefore, by making the pixel block (38) and the first circuit (21) approximately the same size, or by making the first circuit (21) smaller than the pixel block (38), the bezel of the display device (10) can be narrowed, thereby allowing the display device (10) to be miniaturized.

[0106] Examples of configurations different from the display device (10) shown in FIG. 7 are shown in FIG. 8 and FIG. 9. The display device (10) shown in FIG. 8 and FIG. 9 differs mainly from the display device (10) shown in FIG. 7 in that the first circuit (21) is smaller than the pixel block (38). Also, in FIG. 9, the pixel block (38) and the second circuit (22) of the second layer (30) shown in FIG. 8 are shown as dashed lines on the first layer (20).

[0107] FIGS. 8 and 9 illustrate an example in which a display device (10) has a pixel block (38) having an area that overlaps with a first circuit (21) that is electrically connected, and a pixel block (38) that does not overlap with the first circuit (21) that is electrically connected. That is, in the display device (10) shown in FIGS. 8 and 9, the pixel block (38[i,j]) in row i and column j has an area that overlaps with the first circuit (21[i,j]) in row i and column j, and the pixel block (38[p,q]) in row p and column q does not overlap with the first circuit (21[p,q]) in row p and column q.

[0108] By configuring the display device (10) as shown in FIGS. 8 and 9, the layout of the first circuit (21) can be used without changing even when the layout of the display unit (33) changes. A common first circuit (21) can be used for multiple types of display devices (10) with different layouts of the display unit (33), thereby increasing the productivity of the display device (10).

[0109] A configuration example different from the display device (10) shown in FIG. 7 is shown in FIG. 10. The display device (10) shown in FIG. 10 is mainly different from the display device (10) shown in FIG. 7 in that the first layer (20) has a second circuit (22). By providing the first circuit (21) and the second circuit (22) in the same layer (first layer (20)), the manufacturing process of the first circuit (21) and the second circuit (22) can be common, thereby increasing productivity.

[0110] A configuration example different from the display device (10) shown in FIGS. 7 to 10 is shown in FIG. 11. FIG. 11 shows an example in which the display device (10) has a pixel block (38) having an area that overlaps with a first circuit (21) that is electrically connected, and a pixel block (38) that does not overlap with the first circuit (21) that is electrically connected, and also the first layer (20) has a second circuit (22).

[0111] In the display device (10) shown in FIG. 11, the pixel block (38) in the i-th row and j-th column preferably has an area that overlaps with one or more of the second circuits (22[1] to 22[m]). By having an area that overlaps with the second circuit (22) and the pixel block (38), the bezel of the display device (10) can be narrowed, thereby allowing the display device (10) to be miniaturized.

[0112] Additionally, FIG. 11 illustrates an example where the first layer (20) is smaller than the second layer (30), but the present invention is not limited thereto. The sizes of the first layer (20) and the second layer (30) may differ. For example, the sizes of the first layer (20) and the second layer (30) may be approximately the same, or the first layer (20) may be larger than the second layer (30).

[0113] After forming the first layer (20), a second layer (30) can be formed on the first layer (20) to manufacture the display device (10). By forming the second layer (30) on the first layer (20), the precision of aligning the positions of the first layer (20) and the second layer (30) can be increased. Therefore, the productivity of the display device (10) can be increased.

[0114] After forming the first layer (20) and the second layer (30) respectively, the first layer (20) and the second layer (30) may be bonded together to produce a display device (10). When producing a display device (10) by bonding the first layer (20) and the second layer (30), the sizes of the first layer (20) and the second layer (30) may be different. Therefore, the first layer (20) and the second layer (30) can be formed without being affected by each other's sizes. For example, a plurality of first layers (20) may be formed on a substrate to be formed for the first layer (20), and after dividing each first layer (20), the second layer (30) may be bonded together to produce a display device (10). Likewise, for the second layer (30), a plurality of second layers (30) may be formed on the substrate to be formed for the second layer (30), and after dividing each second layer (30), the first layer (20) may be bonded to manufacture the display device (10). That is, the productivity of the first layer (20) and the second layer (30) can be increased while increasing the productivity of the display device (10).

[0115] <Configuration Example 2 of a Display Device>

[0116] Examples of configurations different from the display device (10) exemplified in FIGS. 1 (A) and (B) are shown in FIGS. 12 (A) and (B). FIGS. 12 (A) is a schematic diagram of a display device (10A). FIGS. 12 (B) is a block diagram showing an example of a configuration of a display device (10A). The display device (10A) shown in FIGS. 12 (A) and (B) differs mainly from the display device (10) of FIGS. 1 (A) and (B) in that the first layer (20) provided with the first circuit (21) has a stacked structure of a first circuit layer (20a) and a second circuit layer (20b) on the first circuit layer (20a). Also, regarding the second layer (30), a detailed description is omitted as it can be referred to in FIGS. 1 (B). In addition, the stacking order of the first circuit layer (20a), the second circuit layer (20b), and the second layer (30) is not limited to that shown in (A) of FIG. 12. For example, the first circuit layer (20a) may be provided between the second circuit layer (20b) and the second layer (30).

[0117] For example, the first circuit layer (20a) can be a layer having a silicon transistor (Si transistor) in the channel forming region. The second circuit layer (20b) can be a layer having a metal oxide transistor (OS transistor) in the channel forming region.

[0118] When a first circuit (21) is provided in the first layer (20), it is preferable that the second circuit layer (20b) has a memory circuit (93) and the first circuit layer (20a) has components other than the memory circuit (93), such as a logic circuit (81). The OS transistor has a very low leakage current (hereinafter, off current) flowing between the source and the drain when it is off. Therefore, by using a memory circuit (93) having an OS transistor, data that has been recorded can be maintained for a long time. Thus, power consumption can be reduced by lowering the data refresh frequency. In addition, the operating speed can be increased by using a logic circuit (81) having a Si transistor.

[0119] An example of the configuration of the first layer (20) and the second layer (30) is shown in FIG. 13. FIG. 13 shows the connection relationship between the first layer (20) and the second layer (30). Also, for clarity of the drawing, some components and symbols have been omitted in FIG. 13.

[0120] The display device (10) shown in FIG. 13 corresponds to the display device (10) shown in FIG. 7, and the first layer (20) has a first circuit (21), and the second layer (30) has a display part (33) and a second circuit (22).

[0121] The wiring (32) and wiring (36) of the pixel block (38) are electrically connected to the first circuit (21) located below the display unit (33).

[0122] In addition, signal delay may occur due to the resistance of the wiring (32) and the resistance of the wiring (36). As shown in FIG. 13, it is desirable that the length of the wiring (32) and the length of the wiring (36) electrically connected to each pixel (34) be as short as possible. By shortening the length of the wiring (32) and the wiring (36), signal delay can be suppressed.

[0123] FIG. 13 illustrates an example in which the pixel block (38) and the first circuit (21) have approximately the same size and each pixel block (38[1,1] to 38[m,n]) has an overlapping area with each of the first circuits (21[1,1] to 21[m,n]), but the scope of the present invention is not limited thereto. The sizes of the pixel block (38) and the first circuit (21) may be different. An example configuration in which the first circuit (21) is smaller than the pixel block (38) is shown in FIG. 14 and FIG. 15. Additionally, the display device (10) shown in FIG. 15 corresponds to the display device (10) shown in FIG. 9.

[0124] FIGS. 13 to 15 show an example configuration in which the second layer (30) has a second circuit (22), but one embodiment of the present invention is not limited thereto. FIG. 16 shows an example configuration in which the first layer (20) has a second circuit (22). The display device (10) shown in FIG. 16 corresponds to the display device (10) shown in FIG. 10, and the first layer (20) has a first circuit (21) and a second circuit (22), and the second layer (30) has a display part (33).

[0125] The wiring (32) and wiring (36) of the pixel block (38) are electrically connected to a first circuit (21) located below the display unit (33). Additionally, the wiring (31) is electrically connected to a first circuit (21) provided in the first layer (20).

[0126] A different configuration example from the display device (10) shown in FIG. 16 is shown in FIG. 17. Also, the display device (10) shown in FIG. 17 corresponds to the display device (10) shown in FIG. 11. By having the first layer (20) have the second circuit (22) and making the first circuit (21) smaller than the pixel block (38), the bezel of the display device (10) is narrowed, so that the display device (10) can be miniaturized. Additionally, the display device (10) can be miniaturized by having the second circuit (22) have an area that overlaps with any of the pixel blocks (38).

[0127] <Example of composition of pixel (34)>

[0128] An example of the configuration of a pixel (34) is explained using FIGS. 18 to 20.

[0129] The pixel (34) shown in FIG. 18 has a transistor (Tr11), a transistor (Tr12), a transistor (Tr13), a light-emitting element (572), and a capacitance element (C1). In FIG. 18, the transistors (Tr11), (Tr12), and (Tr13) are of the n-channel type, but the present invention is not limited thereto. The transistors (Tr11), (Tr12), and (Tr13) may each be of the p-channel type.

[0130] The gate of the transistor (Tr11) is connected to the wiring (31), one of the source and drain is connected to the gate of the transistor (Tr12) and one electrode of the capacitance element (C1), and the other of the source and drain is connected to the wiring (32). One of the source and drain of the transistor (Tr12) is connected to the other electrode of the capacitance element (C1), one electrode of the light-emitting element (572), and one of the source and drain of the transistor (Tr13), and the other of the source and drain is connected to the wiring (AL) to which the potential (Va) is supplied. The other electrode of the light-emitting element (572) is connected to the wiring (CL) to which the potential (Vc) is supplied. The gate of the transistor (Tr13) is connected to the wiring (31), and the other of the source and drain is connected to the wiring (36). A node connected to one of the source and drain of transistor (Tr11), the gate of transistor (Tr12), and one electrode of capacitance element (C1) is called a node (N1). A node connected to one of the source and drain of transistor (Tr12), one of the source and drain of transistor (Tr13), and the other electrode of capacitance element (C1) is called a node (N2).

[0131] Here, the case in which the potential (Va) supplied to the wiring (AL) is set to a high power potential and the potential (Vc) supplied to the wiring (CL) is set to a low power potential is explained. Additionally, the capacitance element (C1) functions as a holding capacitance element to maintain the potential of the node (N2).

[0132] The transistor (Tr11) has the function of controlling the supply of potential of the wiring (32) to the node (N1). Additionally, the transistor (Tr13) has the function of controlling the supply of potential of the wiring (36) to the node (N2). Specifically, by controlling the potential of the wiring (31) to turn on the transistor (Tr11) and the transistor (Tr13), the potential of the wiring (32) is supplied to the node (N1) and the potential of the wiring (36) is supplied to the node (N2), and the recording of the pixel (34) is performed. Here, the potential of the wiring (32) is a potential corresponding to the image signal. Afterwards, by controlling the potential of the wiring (31) to turn off the transistor (Tr11) and the transistor (Tr13), the potential of the node (N1) and the node (N2) is maintained.

[0133] And, according to the potential between node (N1) and node (N2), the amount of current flowing between the source and drain of the transistor (Tr12) is controlled, and the light-emitting element (572) emits light with brightness according to the amount of current. By this, the gradation of the pixel (34) can be controlled.

[0134] By performing the above operation sequentially for each wire (31), one frame of image can be displayed in the pixel block (38).

[0135] In addition, the selection of the wiring (31) may use a progressive method or an interlaced method. In addition, the supply of video signals from the first circuit (21) to the wiring (32) may be performed using a sequential drive that supplies video signals to the wiring (32) sequentially, or a sequential drive that supplies video signals to all wirings (32) simultaneously. In addition, video signals may be supplied sequentially to each of the multiple wirings (32).

[0136] Then, during the next frame period, the display of the image is performed by the above operation. Accordingly, the image displayed on the display unit (33) is re-recorded. In addition, the frequency of image re-recording is set to a frequency at which it is difficult for an observer of the display unit (33) to identify changes in the image caused by re-recording. When displaying a video on the display unit (33), it is preferable to set the frequency of image re-recording to, for example, 60 times or more per second. By doing so, a smooth video can be displayed.

[0137] Meanwhile, when a still image is displayed on the display unit (33), or when a video is displayed where the image does not change for a certain period or the change is below a certain level, it is preferable to maintain the image of the previous frame without performing re-recording. By doing so, the power consumed for re-recording the image can be reduced.

[0138] When reducing the frequency of image re-recording, it is desirable to maintain the potential of nodes (N1) and (N2) for a long time. Therefore, it is desirable to use OS transistors for transistors (Tr11) and (Tr13). By doing so, the potential of nodes (N1) and (N2) can be maintained over a very long period, and the display state can be maintained even when the frequency of image re-recording is reduced. The frequency of image re-recording can be, for example, at least once a day and less than 0.1 times per second, preferably at least once an hour and less than once per second, and more preferably at least once every 30 seconds and less than once per second.

[0139] Furthermore, maintaining the display state means ensuring that changes in the image do not exceed a certain range. The aforementioned certain range can be set appropriately; for example, it is desirable to set it to a range where, when a user views the image, it can be recognized as the same image.

[0140] In addition, by reducing the frequency of video re-recording, the flickering (also called flicker) when displaying the video can be reduced. This reduces eye fatigue for the observer of the display unit (33).

[0141] In addition, during the period when video re-recording is not performed, the power potential or signal supplied to the first circuit (21) and the second circuit (22) can be stopped. By doing so, the power consumption of the first circuit (21) and the second circuit (22) can be reduced.

[0142] In addition, transistors other than OS transistors may be used for transistors (Tr11) and (Tr13). For example, a transistor in which a channel forming region is formed on a part of a substrate having a single-crystal semiconductor other than a metal oxide may be used. Examples of such substrates include a single-crystal silicon substrate or a single-crystal germanium substrate. Additionally, transistors in which a channel forming region is formed on a film containing a material other than a metal oxide may be used for transistors (Tr11) and (Tr13). Examples of materials other than metal oxides include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphate, gallium nitride, and organic semiconductors. These materials may be single-crystal semiconductors, or non-single-crystal semiconductors such as amorphous semiconductors, microcrystalline semiconductors, and polycrystalline semiconductors.

[0143] In addition, examples of materials that can be used in the channel forming region of the transistor (Tr12) and the transistor described below are the same as those for transistor (Tr11) and transistor (Tr13).

[0144] Examples of configurations different from the pixel (34) shown in FIG. 18 are shown in FIG. 19 and FIG. 20.

[0145] The pixel (34) shown in FIG. 19 differs from FIG. 18 in that transistors (Tr11), transistor (Tr12), and transistor (Tr13) each have a pair of gates. Also, when a transistor has a pair of gates, one gate may be called the first gate, front gate, or simply gate, and the other gate may be called the second gate or back gate.

[0146] The transistors (Tr11), (Tr12), and (Tr13) shown in (A) of FIG. 19 have a back gate, and the back gate is connected to the front gate. In this case, the same potential as the front gate is applied to the back gate, and the on-current of the transistor can be increased. In particular, since the transistor (Tr11) is used for recording video signals or data and the transistor (Tr13) is used for reading data, a pixel (34) capable of high-speed recording and reading can be realized by adopting the structure shown in (A) of FIG. 19.

[0147] The transistors (Tr11), (Tr12), and (Tr13) shown in (B) of FIG. 19 have their back gates connected to a wiring (BGL). The wiring (BGL) is a wiring that has the function of supplying a predetermined potential to the back gate. By controlling the potential of the wiring (BGL), the threshold voltages of the transistors (Tr11), (Tr12), and (Tr13) can be controlled. In particular, since the transistors (Tr11) and (Tr13) are used to maintain the potentials of nodes (N1) and (N2), respectively, the off-current of the transistors (Tr11) and (Tr13) may be reduced by controlling the potential of the wiring (BGL) to shift the threshold voltages of the transistors (Tr11) and (Tr13) in the positive direction. Additionally, the potential supplied to the wiring (BGL) may be a fixed potential or a fluctuating potential.

[0148] The wiring (BGL) may be provided individually for each transistor (Tr11), transistor (Tr12), and transistor (Tr13). Additionally, the wiring (BGL) may be shared among all or some of the pixels (34) of the display device (10).

[0149] In addition, different structures may be adopted for the transistors (Tr11), (Tr12), and (Tr13) depending on the required performance. An example of a pixel (34) configuration in which the structures of the transistor (Tr12) and the transistor (Tr13) are different is shown in (A) of FIG. 20.

[0150] The back gate of transistor (Tr12) is connected to node (N2), and the back gate of transistor (Tr13) is connected to the front gate. When reading data from the pixel (34), it is desirable that the current flowing through transistor (Tr13) be greater than the current flowing through transistor (Tr12). Therefore, transistor (Tr13) uses a structure in which the back gate is connected to the front gate and the ON current can be increased. By doing so, the ON current of transistor (Tr13) can be made greater than the ON current of transistor (Tr12).

[0151] In addition, the relationship between the on-currents of the transistors can be adjusted by configurations other than the back gate. For example, by making the W / L (W is channel width, L is channel length) of transistor (Tr13) larger than the W / L of transistor (Tr12), the on-current of transistor (Tr13) can be made larger than the on-current of transistor (Tr12).

[0152] In addition, the pixel (34) may be configured as shown in (B) of FIG. 20. In (B) of FIG. 20, a selection signal is supplied from the wiring (31) to the back gates of transistors (Tr11) and (Tr13), thereby turning transistors (Tr11) and (Tr13) on, and a predetermined potential is supplied to nodes (N1) and (N2). In addition, the front gates of transistors (Tr11) and (Tr13) are connected to the wiring (36).

[0153] As the light-emitting element (572), for example, an EL element using electroluminescence can be applied. The EL element has a layer (hereinafter also referred to as the EL layer) containing a light-emitting compound between a pair of electrodes. When a potential difference greater than the threshold voltage of the EL element is generated between a pair of electrodes, holes are injected into the EL layer from the positive side and electrons are injected from the negative side. The injected electrons and holes recombine in the EL layer, and the light-emitting material contained in the EL layer emits light.

[0154] In addition, EL devices are distinguished based on whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL device and the latter is called an inorganic EL device.

[0155] In an organic EL device, when a voltage is applied, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, as these carriers (electrons and holes) recombine, the luminescent organic compound forms an excited state, and emits light when the excited state returns to the ground state. Because of this mechanism, the light-emitting device described above is called a current-excited light-emitting device.

[0156] In the present specification, etc., the voltage supplied to a display element such as a light-emitting element or a liquid crystal element refers to the difference between the potential applied to one electrode of the display element and the potential applied to the other electrode of the display element.

[0157] In addition, the EL layer may have, in addition to the emitting compound, a material with high hole injection, a material with high hole transport, a hole blocking material, a material with high electron transport, a material with high electron injection, or a bipolar material (a material with high electron transport and hole transport).

[0158] The EL layer can be formed by methods such as deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0159] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices depending on the device configuration. Dispersed inorganic EL devices have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission utilizing donor and acceptor levels. Thin-film inorganic EL devices have a structure in which a light-emitting layer is sandwiched between dielectric layers and this is sandwiched between electrodes, and the light-emitting mechanism is localized light emission utilizing the inner-shell electron transition of metal ions.

[0160] In order to extract light emission, it is preferable that one of at least one pair of electrodes of the light-emitting element be transparent. Furthermore, a transistor and a light-emitting element are formed on a substrate, and there are light-emitting elements with a top-emission structure that extracts light emission from a side opposite to the substrate, a bottom-emission structure that extracts light emission from a side opposite to the substrate, and a dual-emission structure that extracts light emission from both sides, and any of the light-emitting elements of the injection structure can be applied.

[0161] <Example of Cross-sectional Configuration of Display Device 1>

[0162] A cross-sectional view showing an example configuration of a display device (10) is shown in FIG. 21. The display device (10) has a substrate (701) and a substrate (705), and the substrate (701) and the substrate (705) are joined by a material (712).

[0163] As the substrate (701), a single-crystal semiconductor substrate, such as a single-crystal silicon substrate, may be used. Additionally, as the substrate (701), a semiconductor substrate other than a single-crystal semiconductor substrate may be used.

[0164] A transistor (441) and a transistor (601) are provided on a substrate (701). The transistor (441) and the transistor (601) may be provided on a first layer (20). For example, in the display device (10) shown in FIGS. 7 to 9, the transistor (441) and the transistor (601) may be transistors provided in the first circuit (21). For example, in the display device (10) shown in FIGS. 10 and 11, the transistor (441) and the transistor (601) may be transistors provided in the first circuit (21) or the second circuit (22).

[0165] The transistor (441) has a conductor (443) that functions as a gate electrode, an insulator (445) that functions as a gate insulator, a semiconductor region (447) that is formed as part of the substrate (701) and includes a channel forming region, a low-resistance region (449a) that functions as one of a source region and a drain region, and a low-resistance region (449b) that functions as the other of a source region and a drain region. The transistor (441) may be either a p-channel type or an n-channel type.

[0166] The transistor (441) is electrically isolated from other transistors by the device isolation layer (403). FIG. 21 illustrates a case where the transistor (441) and the transistor (601) are electrically isolated by the device isolation layer (403). The device isolation layer (403) can be formed using the LOCOS (LOCal Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method.

[0167] In the transistor (441) shown in FIG. 21, the semiconductor region (447) has a convex shape. Additionally, the side and top surfaces of the semiconductor region (447) are provided to be covered by a conductor (443) interposed with an insulator (445). Also, FIG. 21 does not show the state in which the conductor (443) covers the side of the semiconductor region (447). Additionally, a material that adjusts the work function can be used for the conductor (443).

[0168] A transistor having a convex shape in a semiconductor region such as the transistor (441) can be called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Additionally, an insulator may be provided that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. Also, although FIG. 21 shows a configuration in which a part of the substrate (701) is processed to form the convex portion, a semiconductor having a convex shape may be formed by processing an SOI substrate.

[0169] In addition, the configuration of the transistor (441) shown in FIG. 21 is an example and is not limited to that configuration; it may be configured appropriately according to the circuit configuration or the method of operation of the circuit. For example, the transistor (441) may be a planar type transistor.

[0170] The transistor (601) can be configured in the same way as the transistor (441).

[0171] On the substrate (701), in addition to the device isolation layer (403), transistor (441), and transistor (601), an insulator (405), an insulator (407), an insulator (409), and an insulator (411) are provided. A conductor (451) is embedded within the insulator (405), within the insulator (407), within the insulator (409), and within the insulator (411). Here, the height of the upper surface of the conductor (451) and the height of the upper surface of the insulator (411) can be made to be about the same.

[0172] An insulator (413) and an insulator (415) are provided on the conductor (451) and on the insulator (411). Additionally, a conductor (457) is embedded within the insulator (413) and within the insulator (415). Here, the height of the upper surface of the conductor (457) and the height of the upper surface of the insulator (415) can be made to be approximately the same.

[0173] An insulator (417) and an insulator (419) are provided on top of a conductor (457) and an insulator (415). Additionally, a conductor (459) is embedded within the insulator (417) and within the insulator (419). Here, the height of the upper surface of the conductor (459) and the height of the upper surface of the insulator (419) can be made to be approximately the same.

[0174] An insulator (421) and an insulator (214) are provided on the conductor (459) and on the insulator (419). A conductor (453) is embedded within the insulator (421) and within the insulator (214). Here, the height of the upper surface of the conductor (453) and the height of the upper surface of the insulator (214) can be made to be about the same.

[0175] An insulator (216) is provided on the conductor (453) and on the insulator (214). The conductor (455) is embedded within the insulator (216). Here, the height of the upper surface of the conductor (455) and the height of the upper surface of the insulator (216) can be made to be about the same.

[0176] Insulators (222), insulators (224), insulators (254), insulators (244), insulators (280), insulators (274), and insulators (281) are provided on the conductor (455) and on the insulator (216). A conductor (305) is embedded within the insulator (222), within the insulator (224), within the insulator (254), within the insulator (244), within the insulator (280), within the insulator (274), and within the insulator (281). Here, the height of the upper surface of the conductor (305) and the height of the upper surface of the insulator (281) can be made to be about the same.

[0177] An insulator (361) is provided on the conductor (305) and on the insulator (281). The conductor (317) and the conductor (337) are embedded within the insulator (361). Here, the height of the upper surface of the conductor (337) and the height of the upper surface of the insulator (361) can be made to be about the same.

[0178] An insulator (363) is provided on top of a conductor (337) and on top of an insulator (361). A conductor (347), a conductor (353), a conductor (355), and a conductor (357) are embedded within the insulator (363). Here, the height of the upper surface of the conductor (353), the conductor (355), and the conductor (357) and the height of the upper surface of the insulator (363) can be made to be approximately the same.

[0179] A connection electrode (760) is provided on the conductor (353), on the conductor (355), on the conductor (357), and on the insulator (363). Additionally, an anisotropic conductor (780) is provided to be electrically connected to the connection electrode (760), and a Flexible Printed Circuit (FPC) (716) is provided to be electrically connected to the anisotropic conductor (780). Through the FPC (716), various signals, etc., are supplied to the display device (10) from outside the display device (10).

[0180] As shown in FIG. 21, a low-resistance region (449b) that functions as the other of the source region and drain region of the transistor (441) is electrically connected to an FPC (716) through a conductor (451), a conductor (457), a conductor (459), a conductor (453), a conductor (455), a conductor (305), a conductor (317), a conductor (337), a conductor (347), a conductor (353), a conductor (355), a conductor (357), a connecting electrode (760), and an anisotropic conductor (780). Here, FIG. 21 shows three conductors, conductor (353), conductor (355), and conductor (357), that function to electrically connect the connecting electrode (760) and the conductor (347), but one embodiment of the present invention is not limited thereto. The conductor having the function of electrically connecting the connecting electrode (760) and the conductor (347) may be one, two, or four or more. By providing multiple conductors having the function of electrically connecting the connecting electrode (760) and the conductor (347), the contact resistance can be lowered.

[0181] A transistor (750) is provided on the insulator (214). The transistor (750) can be provided on the second layer (30). For example, in the display device (10) shown in FIGS. 7 to 11, the transistor (750) can be a transistor provided on the display unit (33). An OS transistor can be used as the transistor (750). An OS transistor has the characteristic of having a very low off-current. Therefore, since the retention time of an image signal, etc., can be extended, the frequency of refresh operations can be reduced. Thus, the power consumption of the display device (10) can be reduced.

[0182] Conductors (301a) and (301b) are embedded within the insulator (254), within the insulator (244), within the insulator (280), within the insulator (274), and within the insulator (281). Conductor (301a) is electrically connected to one of the source and drain of the transistor (750), and conductor (301b) is electrically connected to the other of the source and drain of the transistor (750). Here, the height of the upper surface of the conductor (301a) and conductor (301b) and the height of the upper surface of the insulator (281) can be made to be about the same.

[0183] A conductor (311), a conductor (313), a conductor (331), a capacitive element (790), a conductor (333), and a conductor (335) are embedded within an insulator (361). The conductors (311) and (313) are electrically connected to a transistor (750) and function as wiring. The conductors (333) and (335) are electrically connected to a capacitive element (790). Here, the height of the upper surface of the conductors (331), the conductor (333), and the conductor (335) and the height of the upper surface of the insulator (361) can be approximately the same.

[0184] A conductor (341), a conductor (343), and a conductor (351) are embedded within an insulator (363). Here, the height of the upper surface of the conductor (351) and the height of the upper surface of the insulator (363) can be made to be about the same.

[0185] Insulators (405), insulator (407), insulator (409), insulator (411), insulator (413), insulator (415), insulator (417), insulator (419), insulator (421), insulator (214), insulator (280), insulator (274), insulator (281), insulator (361), and insulator (363) may function as interlayer films and may also function as flattening films that cover the uneven shape of each of the lower surfaces. For example, the upper surface of the insulator (363) may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like to increase flatness.

[0186] As shown in FIG. 21, the capacitance element (790) has a lower electrode (321) and an upper electrode (325). Additionally, an insulator (323) is provided between the lower electrode (321) and the upper electrode (325). That is, the capacitance element (790) has a stacked structure in which an insulator (323) that functions as a dielectric is sandwiched between a pair of electrodes. Also, while FIG. 21 shows an example in which the capacitance element (790) is provided on an insulator (281), the capacitance element (790) may be provided on an insulator other than the insulator (281).

[0187] FIG. 21 illustrates an example in which a conductor (301a), a conductor (301b), and a conductor (305) are formed on the same layer. Also, an example is illustrated in which a conductor (311), a conductor (313), a conductor (317), and a lower electrode (321) are formed on the same layer. Additionally, an example is illustrated in which a conductor (331), a conductor (333), a conductor (335), and a conductor (337) are formed on the same layer. Also, an example is illustrated in which a conductor (341), a conductor (343), and a conductor (347) are formed on the same layer. Additionally, an example is illustrated in which a conductor (351), a conductor (353), a conductor (355), and a conductor (357) are formed on the same layer. By forming a plurality of conductors on the same layer in this manner, the manufacturing process of the display device (10) can be simplified, thereby making the display device (10) inexpensive. In addition, these may each be formed in different layers and may have different types of materials.

[0188] The display device (10) shown in FIG. 21 has a light-emitting element (782). The light-emitting element (782) has a conductor (772), an EL layer (786), and a conductor (788). The EL layer (786) has an organic compound or an inorganic compound such as a quantum dot.

[0189] Materials that can be used for organic compounds include fluorescent materials or phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials.

[0190] The conductor (772) is electrically connected to the other side of the source and drain of the transistor (750) through the conductor (351), conductor (341), conductor (331), conductor (313), and conductor (301b). The conductor (772) is formed on the insulator (363) and functions as a pixel electrode.

[0191] For the conductor (772), a material that is transparent to visible light or reflective can be used. For the transparent material, it is preferable to use an oxide material containing, for example, indium, zinc, tin, etc. For the reflective material, it is preferable to use a material containing, for example, aluminum, silver, etc.

[0192] In addition, although not shown in FIG. 21, the display device (10) may be provided with optical members (optical substrates), such as polarizing members, phase difference members, and anti-reflection members.

[0193] On the substrate (705) side, a light-blocking layer (738) and an insulator (734) in contact with them are provided. The light-blocking layer (738) has the function of blocking light emitted from adjacent areas. Alternatively, the light-blocking layer (738) has the function of blocking external light from reaching the transistor (750), etc.

[0194] In the display device (10) shown in FIG. 21, an insulator (730) is provided on top of an insulator (363). Here, the insulator (730) may be configured to cover a portion of the conductor (772). Additionally, the light-emitting element (782) may have a transparent conductor (788) and may be a top-emission type light-emitting element. Furthermore, the light-emitting element (782) may be a bottom-emission structure that emits light toward the conductor (772), or a dual-emission structure that emits light toward both the conductor (772) and the conductor (788).

[0195] Additionally, the light-blocking layer (738) is provided to have an area that overlaps with the insulator (730). Additionally, the light-blocking layer (738) is covered with the insulator (734). Additionally, the space between the light-emitting element (782) and the insulator (734) is filled with a sealing layer (732).

[0196] Additionally, the structure (778) is provided between the insulator (730) and the EL layer (786). Additionally, the structure (778) is provided between the insulator (730) and the insulator (734).

[0197] FIG. 22 is a modified example of the display device (10) shown in FIG. 21, and differs from the display device (10) shown in FIG. 21 in that it provides a colored layer (736). In addition, the colored layer (736) is provided to have an area that overlaps with the light-emitting element (782). By providing the colored layer (736), the color purity of the light extracted from the light-emitting element (782) can be increased. Thus, a high-quality image can be displayed on the display device (10). In addition, for example, since all light-emitting elements (782) of the display device (10) can be light-emitting elements that emit white light, the EL layer (786) does not need to be formed by individual coating, so the display device (10) can be made high-definition.

[0198] The light-emitting element (782) may have a micro-optical resonator (microcavity) structure. Thus, since light of a predetermined color (e.g., RGB) can be extracted without providing a coloring layer, the display device (10) can display color. By making the configuration without providing a coloring layer, the absorption of light by the coloring layer can be suppressed. Thus, the display device (10) can display high-brightness images and reduce the power consumption of the display device (10). In addition, when the EL layer (786) is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, formed by an individual coating method, the configuration can be made without providing a coloring layer.

[0199] FIGS. 21 and 22 illustrate a configuration in which transistors (441) and transistors (601) are provided such that a channel forming region is formed inside a substrate (701), and an OS transistor is provided by stacking on transistors (441) and transistors (601); however, one embodiment of the present invention is not limited thereto. FIG. 23 is a variation of FIG. 22 and differs from the display device (10) of the configuration shown in FIG. 22 in that transistors (750) are provided by stacking on transistors (602) and transistors (603), which are OS transistors, rather than transistors (441) and transistors (601). That is, the display device (10) of the configuration shown in FIG. 23 is provided with OS transistors stacked thereon.

[0200] An insulator (613) and an insulator (614) are provided on the substrate (701), and a transistor (602) and a transistor (603) are provided on the insulator (614). Additionally, a transistor, etc., may be provided between the substrate (701) and the insulator (613). For example, a transistor with a configuration such as the transistor (441) and transistor (601) shown in FIG. 22 may be provided between the substrate (701) and the insulator (613).

[0201] Transistors (602) and (603) can be provided in the first layer (20). For example, in the display device (10) shown in FIGS. 7 and 9, transistors (602) and (603) can be transistors provided in the first circuit (21). For example, in the display device (10) shown in FIGS. 10 and 11, transistors (602) and (603) can be transistors provided in the first circuit (21) or the second circuit (22).

[0202] The transistors (602) and (603) may be transistors with the same configuration as the transistor (750). Alternatively, the transistors (602) and (603) may be OS transistors with a different configuration from the transistor (750).

[0203] In addition to transistors (602) and (603), insulators (616), insulators (622), insulators (624), insulators (654), insulators (644), insulators (680), insulators (674), and insulators (681) are provided on the insulator (614). A conductor (461) is embedded within the insulator (654), within the insulator (644), within the insulator (680), within the insulator (674), and within the insulator (681). Here, the height of the upper surface of the conductor (461) and the height of the upper surface of the insulator (681) can be made to be about the same.

[0204] An insulator (501) is provided on top of a conductor (461) and on top of an insulator (681). A conductor (463) is embedded within the insulator (501). Here, the height of the upper surface of the conductor (463) and the height of the upper surface of the insulator (501) can be made to be about the same.

[0205] An insulator (503) is provided on top of a conductor (463) and on top of an insulator (501). A conductor (465) is embedded within the insulator (503). Here, the height of the upper surface of the conductor (465) and the height of the upper surface of the insulator (503) can be made to be about the same.

[0206] An insulator (505) is provided on top of a conductor (465) and on top of an insulator (503). Additionally, a conductor (467) is embedded within the insulator (505). Here, the height of the upper surface of the conductor (467) and the height of the upper surface of the insulator (505) can be made to be approximately the same.

[0207] An insulator (507) is provided on top of a conductor (467) and on top of an insulator (505). A conductor (469) is embedded within the insulator (507). Here, the height of the upper surface of the conductor (469) and the height of the upper surface of the insulator (507) can be made to be about the same.

[0208] An insulator (509) is provided on top of a conductor (469) and on top of an insulator (507). Additionally, a conductor (471) is embedded within the insulator (509). Here, the height of the upper surface of the conductor (471) and the height of the upper surface of the insulator (509) can be made to be approximately the same.

[0209] An insulator (421) and an insulator (214) are provided on the conductor (471) and on the insulator (509). A conductor (453) is embedded within the insulator (421) and within the insulator (214). Here, the height of the upper surface of the conductor (453) and the height of the upper surface of the insulator (214) can be made to be about the same.

[0210] As shown in FIG. 23, one of the source and drain of the transistor (602) is electrically connected to the FPC (716) through a conductor (461), a conductor (463), a conductor (465), a conductor (467), a conductor (469), a conductor (471), a conductor (453), a conductor (455), a conductor (305), a conductor (317), a conductor (337), a conductor (347), a conductor (353), a conductor (355), a conductor (357), a connecting electrode (760), and an anisotropic conductor (780).

[0211] Insulators (613), insulator (614), insulator (680), insulator (674), insulator (681), insulator (501), insulator (503), insulator (505), insulator (507), and insulator (509) may function as interlayer films and may also function as flattening films covering the uneven shape of each of the lower surfaces.

[0212] By configuring the display device (10) as shown in FIG. 23, the display device (10) can be made slim-bezel and miniaturized, and all transistors in the display device (10) can be made OS transistors. Thus, for example, the transistor provided in the first layer (20) and the transistor provided in the second layer (30) can be manufactured using the same device. Therefore, the manufacturing cost of the display device (10) can be reduced, making the display device (10) inexpensive.

[0213] <Example of Cross-sectional Configuration of Display Device 2>

[0214] FIG. 24 is a cross-sectional view showing an example configuration of a display device (10A). It differs mainly from the display device (10) shown in FIG. 22 in that it has a layer having a transistor (800) between the layer having a transistor (750) and the layer having a transistor (602) and a transistor (603).

[0215] Transistors (602) and (603) can be provided in the first circuit layer (20a) shown in (A) of FIG. 12, etc. Transistor (800) can be provided in the second circuit layer (20b). For example, in the display device (10A) shown in (A) of FIG. 12, the transistor (800) can be a transistor provided in the memory circuit (93). In addition, transistors (602) and (603) can be transistors provided in components other than the memory circuit (93), such as the logic circuit (81).

[0216] An insulator (821) and an insulator (814) are provided on the conductor (459) and on the insulator (419). A conductor (853) is embedded within the insulator (821) and within the insulator (814). Here, the height of the upper surface of the conductor (853) and the height of the upper surface of the insulator (814) can be made to be about the same.

[0217] An insulator (816) is provided on the conductor (853) and on the insulator (814). The conductor (855) is embedded within the insulator (816). Here, the height of the upper surface of the conductor (855) and the height of the upper surface of the insulator (816) can be made to be about the same.

[0218] Insulators (822), insulators (824), insulators (854), insulators (844), insulators (880), insulators (874), and insulators (881) are provided on top of a conductor (855) and on top of an insulator (816). A conductor (805) is embedded within the insulator (822), within the insulator (824), within the insulator (854), within the insulator (844), within the insulator (880), within the insulator (874), and within the insulator (881). Here, the height of the upper surface of the conductor (805) and the height of the upper surface of the insulator (881) can be made to be approximately the same.

[0219] Insulators (421) and insulators (214) are provided on the conductor (817) and on the insulator (881).

[0220] As shown in FIG. 24, the low-resistance region (449b), which functions as the other of the source region and drain region of the transistor (441), is electrically connected to the FPC (716) through a conductor (451), a conductor (457), a conductor (459), a conductor (853), a conductor (855), a conductor (805), a conductor (817), a conductor (453), a conductor (455), a conductor (305), a conductor (317), a conductor (337), a conductor (347), a conductor (353), a conductor (355), a conductor (357), a connecting electrode (760), and an anisotropic conductor (780).

[0221] A transistor (800) is provided on the insulator (814). The transistor (800) may be provided on the second circuit layer (20b). For example, in the display device (10A) shown in (A) of FIG. 12, the transistor (800) may be a transistor provided on the memory circuit (93). It is preferable that the transistor (800) be an OS transistor.

[0222] Conductors (801a) and (801b) are embedded within the insulator (854), within the insulator (844), within the insulator (880), within the insulator (874), and within the insulator (881). Conductor (801a) is electrically connected to one of the source and drain of the transistor (800), and conductor (801b) is electrically connected to the other of the source and drain of the transistor (800). Here, the height of the upper surface of the conductor (801a) and conductor (801b) and the height of the upper surface of the insulator (881) can be made to be approximately the same.

[0223] A transistor (750) is provided on the insulator (214). The transistor (750) may be provided on the second layer (30). For example, in the display device (10A) shown in (A) of FIG. 12, the transistor (750) may be a transistor provided on the display unit (33). It is preferable that the transistor (750) be an OS transistor.

[0224] The conductor (301a) is electrically connected to one of the source and drain of the transistor (750), and the conductor (301b) is electrically connected to the other of the source and drain of the transistor (750). Here, the height of the upper surface of the conductor (301a) and the conductor (301b) and the height of the upper surface of the insulator (281) can be made to be about the same.

[0225] Additionally, an OS transistor, etc. may be provided between the layer where the transistor (441) and the transistor (601), etc. are provided and the layer where the transistor (800), etc. is provided. Additionally, an OS transistor, etc. may be provided between the layer where the transistor (800), etc. is provided and the layer where the transistor (750), etc. is provided. Additionally, an OS transistor, etc. may be provided on a layer above the layer where the transistor (750), etc. is provided.

[0226] Conductors (311) and (313) are electrically connected to the transistor (750) and function as wiring. Conductors (333) and (335) are electrically connected to the capacitive element (790).

[0227] Insulators (405), insulators (407), insulators (409), insulators (411), insulators (413), insulators (415), insulators (417), insulators (419), insulators (821), insulators (814), insulators (880), insulators (874), insulators (881), insulators (421), insulators (214), insulators (280), insulators (274), insulators (281), insulators (361), and insulators (363) may function as interlayer films and may also function as flattening films covering the uneven shape of each of the lower surfaces.

[0228] As shown in FIG. 24, the capacitance element (790) has a lower electrode (321) and an upper electrode (325). Additionally, an insulator (323) is provided between the lower electrode (321) and the upper electrode (325). That is, the capacitance element (790) has a stacked structure in which an insulator (323) that functions as a dielectric is sandwiched between a pair of electrodes. Also, while FIG. 24 shows an example in which the capacitance element (790) is provided on an insulator (281), the capacitance element (790) may be provided on an insulator other than the insulator (281).

[0229] FIG. 24 illustrates an example in which a conductor (801a), a conductor (801b), and a conductor (805) are formed on the same layer. Also, an example in which a conductor (811), a conductor (813), and a conductor (817) are formed on the same layer is illustrated.

[0230] FIG. 24 illustrates a configuration in which transistors (441) and transistors (601) are provided such that a channel forming region is formed inside a substrate (701), and an OS transistor is provided by stacking on transistors (441) and transistors (601); however, one embodiment of the present invention is not limited thereto. FIG. 25 is a variation of FIG. 24 and differs from the display device (10A) of the configuration shown in FIG. 24 in that transistors (800) and transistor (750) are provided by stacking on transistors (602) and transistors (603), which are OS transistors, rather than transistors (441) and transistors (601). That is, in the display device (10A) of the configuration shown in FIG. 25, OS transistors are provided by stacking three layers.

[0231] An OS transistor, etc. may be provided between the layer where the transistor (602) and the transistor (603), etc. are provided and the layer where the transistor (800), etc. is provided. Additionally, an OS transistor, etc. may be provided between the layer where the transistor (800), etc. is provided and the layer where the transistor (750) or the transistor (750), etc. is provided. Additionally, an OS transistor, etc. may be provided on a layer above the layer where the transistor (750), etc. is provided.

[0232] Transistors (602) and (603) can be provided in the first circuit layer (20a) shown in (A) of FIG. 12, etc. Transistor (800) can be provided in the second circuit layer (20b). For example, in the display device (10A) shown in (A) of FIG. 12, the transistor (800) can be a transistor provided in the memory circuit (93). In addition, transistors (602) and (603) can be transistors provided in components other than the memory circuit (93), such as the logic circuit (81).

[0233] An insulator (821) and an insulator (814) are provided on the conductor (471) and on the insulator (509). A conductor (853) is embedded within the insulator (821) and within the insulator (814). Here, the height of the upper surface of the conductor (853) and the height of the upper surface of the insulator (814) can be made to be about the same.

[0234] As shown in FIG. 25, one of the source and drain of the transistor (602) is electrically connected to the FPC (716) through a conductor (461), a conductor (463), a conductor (465), a conductor (467), a conductor (469), a conductor (471), a conductor (853), a conductor (855), a conductor (805), a conductor (817), a conductor (453), a conductor (455), a conductor (305), a conductor (317), a conductor (337), a conductor (347), a conductor (353), a conductor (355), a conductor (357), a connecting electrode (760), and an anisotropic conductor (780).

[0235] By configuring the display device (10A) as shown in FIG. 25, the display device (10A) can be made slim and compact, and all the transistors in the display device (10A) can be OS transistors. As a result, since there is no need to manufacture different types of transistors, the manufacturing cost of the display device (10A) can be reduced, and the display device (10A) can be made inexpensive.

[0236] <Example of subpixel configuration>

[0237] Figures 26 (A) and (B) are top views showing an example configuration of a subpixel (901) that can be applied to a display device of one form of the present invention. The subpixel (901) can be configured with the circuit shown in Figure 18, etc. Here, the transistor (552) has a back gate in addition to the gate, and the back gate is electrically connected to a wiring (not shown). In addition, the transistor (750) has a back gate in addition to the gate, and the back gate is electrically connected to the other side of the source and drain of the transistor (750), the other electrode of the capacitive element (790), and one electrode of the light-emitting element (572).

[0238] FIG. 26 (A) shows a conductor and a semiconductor constituting a transistor, a capacitive element, and wiring having a subpixel (901). FIG. 26 (B) shows a conductor (772) that functions as one electrode of a light-emitting element (572) in addition to the configuration shown in FIG. 26 (A). Also, in both FIG. 26 (A) and (B), a conductor that functions as the other electrode of a light-emitting element (572) is omitted. Here, one electrode of the light-emitting element (572) functions as a pixel electrode, and the other electrode of the light-emitting element (572) functions as a common electrode.

[0239] As shown in (A) and (B) of FIG. 26, the subpixel (901) has a conductor (911), a conductor (912), a semiconductor (913), a semiconductor (914), a conductor (915a), a conductor (915b), a conductor (916a), a conductor (916b), a conductor (917), a conductor (918), a conductor (919), a conductor (920), a conductor (921), a conductor (922), a conductor (923), a conductor (924), a conductor (925), a conductor (926), a conductor (927), a conductor (928), a conductor (929), a conductor (930), a conductor (931), and a conductor (772).

[0240] Conductors (911) and (912) can be formed in the same process. Semiconductors (913) and (914) are formed in the same process and can be formed in a later process than conductors (911) and (912). Conductors (915a) and (915b), and conductors (916a) and (916b) are formed in the same process and can be formed in a later process than conductors (911) and (912). Conductors (917) and (918) are formed in the same process and can be formed in a later process than semiconductors (913) and (914), and conductors (915a), (915b), (916a), and (916b).

[0241] Conductors (919) to (923) are formed in the same process and may be formed in a later process than conductors (917) and (918). Conductor (924) may be formed in a later process than conductors (919) to (923). Conductors (925) to (928) are formed in the same process and may be formed in a later process than conductor (924). Conductors (929) to (931) are formed in the same process and may be formed in a later process than conductors (925) to (928). Conductor (772) may be formed in a later process than conductors (929) to (931).

[0242] In the present specification, elements formed in the same process may be provided on the same layer. For example, since conductor (911) and conductor (912) can be formed in the same process, conductor (911) and conductor (912) may be provided on the same layer. Additionally, elements formed in a subsequent process may be provided on a layer above the elements formed in a preceding process. For example, since conductors (929) to conductor (931) can be formed in a subsequent process than conductors (925) to conductor (928), conductors (929) to conductor (931) may be provided on a layer above conductors (925) to conductor (928).

[0243] The conductor (911) functions as the back gate electrode of the transistor (552). The semiconductor (913) has a channel forming region of the transistor (552). The conductor (915a) functions as one of the source electrode and drain electrode of the transistor (552). The conductor (915b) functions as the other of the source electrode and drain electrode of the transistor (552). The conductor (917) functions as the gate electrode of the transistor (552).

[0244] The conductor (912) functions as the back gate electrode of the transistor (750). The semiconductor (914) has a channel forming region of the transistor (750). The conductor (916a) functions as one of the source electrode and drain electrode of the transistor (750). The conductor (916b) functions as the other of the source electrode and drain electrode of the transistor (750). The conductor (918) functions as the gate electrode of the transistor (750).

[0245] The conductor (919) functions as one electrode of the capacitance element (790). The conductor (924) functions as the other electrode of the capacitance element (790). The conductor (925) corresponds to the wiring (31) which functions as a scan line. The conductor (929) corresponds to the wiring (32) which functions as a data line. The conductor (930) corresponds to the wiring which functions as a power line. As described above, the conductor (772) functions as one electrode of the light-emitting element (572).

[0246] Conductor (911) is electrically connected to conductor (920). Conductor (912) is electrically connected to conductor (923). Conductor (915a) is electrically connected to conductor (921). Conductor (915b) is electrically connected to conductor (919). Conductor (916a) is electrically connected to conductor (922).

[0247] The conductor (916b) is electrically connected to the conductor (923). That is, the conductor (912) which functions as the back gate electrode of the transistor (750) and the conductor (916b) which functions as the other of the source electrode and drain electrode of the transistor (750) are electrically connected through the conductor (923).

[0248] The conductor (917) is electrically connected to the conductor (920). That is, the conductor (911) which functions as the back gate electrode of the transistor (552) and the conductor (917) which functions as the gate electrode of the transistor (552) are electrically connected through the conductor (920).

[0249] The conductor (920) is electrically connected to the conductor (925). That is, the conductor (917) which functions as the gate electrode of the transistor (552) and the conductor (925) which functions as a scan line are electrically connected through the conductor (920).

[0250] Conductor (917) is electrically connected to conductor (919). Conductor (921) is electrically connected to conductor (926). Conductor (922) is electrically connected to conductor (927). Conductor (923) is electrically connected to conductor (928). Conductor (924) is electrically connected to conductor (928).

[0251] The conductor (926) is electrically connected to the conductor (929). That is, the conductor (915a), which functions as one of the source electrode and drain electrode of the transistor (552), and the conductor (929), which functions as a data line, are electrically connected through the conductor (921) and the conductor (926).

[0252] The conductor (927) is electrically connected to the conductor (930). That is, the conductor (916a), which functions as one of the source electrode and drain electrode of the transistor (750), and the conductor (930), which functions as a power line, are electrically connected through the conductor (922) and the conductor (927).

[0253] The conductor (928) is electrically connected to the conductor (931). The conductor (931) is electrically connected to the conductor (772).

[0254] The semiconductor (913) and the semiconductor (914) may have, for example, a metal oxide. Accordingly, the transistor (552) to the transistor (750) may be an OS transistor.

[0255] FIG. 27 is a top view showing an example of a pixel (902) composed of subpixels (901) of the configuration shown in FIG. 26 (B). In FIG. 27, subpixel (901R) represents a subpixel (901) having the function of emitting red light, subpixel (901G) represents a subpixel (901) having the function of emitting green light, and subpixel (901B) represents a subpixel (901) having the function of emitting blue light. As shown in FIG. 27, the pixel (902) is composed of subpixels (901R), subpixels (901G), and subpixels (901B). Specifically, one pixel (902) is composed of subpixels (901R) and subpixels (901B) provided at the top, and subpixel (901G) provided at the bottom. In addition, one pixel (902) is composed of a subpixel (901G) provided at the top, and subpixels (901R) and subpixels (901B) provided at the bottom.

[0256] In FIG. 27, the subpixels (901R), (901G), and (901B) provided at the top and the subpixels (901R), (901G), and (901B) provided at the bottom each have a configuration in which the left and right sides are reversed. By configuring it this way, subpixels (901) of the same color can be alternately arranged in the direction of extension of the conductor (925) which functions as a scan line. Accordingly, a configuration can be made in which subpixels (901) having the function of emitting light of the same color are electrically connected to a single data line. That is, it is possible to prevent two or more types of subpixels (901) among subpixels (901R), subpixels (901G), and subpixels (901B) from being electrically connected to a single data line.

[0257] FIG. 28 is a cross-sectional view of the portion indicated by the dotted line A1-A2 in FIG. 26 (B). A transistor (552) is provided on an insulator (1021). Additionally, an insulator (1022) is provided on the transistor (552), and an insulator (1023) is provided on the insulator (1022). Additionally, a capacitive element (562) is provided on the insulator (1023). Additionally, a substrate is provided on a layer below the insulator (1021). Furthermore, between the substrate and the insulator (1021), components of the first layer (20) shown in FIG. 1 (A), etc. (first circuit (21), etc.) may be provided.

[0258] As shown in FIG. 28, conductors provided on different layers are electrically connected through a conductor (990) that functions as a plug. For example, a conductor (915a) and a conductor (921) provided on a layer above the conductor (915a) are electrically connected through the conductor (990). The conductor (990) can be configured such as the conductor (853), conductor (805), conductor (453), conductor (305), conductor (337), conductor (353), conductor (355), conductor (357), conductor (301a), conductor (301b), conductor (331), conductor (351), conductor (333), and conductor (335) shown in FIG. 19, etc.

[0259] An insulator (1024) is provided on the conductor (919) to the conductor (923) and on the insulator (1023). A conductor (924) is provided on the insulator (1024). A capacitive element (790) is composed of the conductor (919), the insulator (1024), and the conductor (924).

[0260] An insulator (1025) is provided over the conductor (924) and over the insulator (1024). An insulator (1026) is provided over the conductor (925) to the conductor (928) and over the insulator (1025). An insulator (1027) is provided over the conductor (929) to the conductor (931) and over the insulator (1026).

[0261] A conductor (772) and an insulator (730) are provided on top of an insulator (1027). Here, the insulator (730) may be configured to cover a portion of the conductor (772). A light-emitting element (572) is composed of a conductor (772), an EL layer (786), and a conductor (788).

[0262] An adhesive layer (991) is provided on the conductor (788), and an insulator (992) is provided on the adhesive layer (991). The insulator (992) on the adhesive layer (991) can be formed in the following manner. First, the insulator (992) is formed on a substrate different from the substrate on which the light-emitting element (572), etc., is formed. Next, the conductor (788) and the insulator (992) are bonded together with the adhesive layer (991). After that, the substrate on which the insulator (992) is formed is peeled off. As described above, the insulator (992) can be formed on the conductor (788).

[0263] A colored layer is provided on the insulator (992). Fig. 28 illustrates a colored layer (993a) and a colored layer (993b). A substrate (995) is bonded to the colored layer (993a) and the colored layer (993b) with an adhesive layer (994).

[0264] The coloring layer (993b) has the function of transmitting light of a different color than the coloring layer (993a). For example, if the pixel (902) is composed of a subpixel (901R) that emits red light, a subpixel (901G) that emits green light, and a subpixel (901B) that emits blue light, and the coloring layer (993a) has the function of transmitting red light, the coloring layer (993b) has the function of transmitting green light or blue light.

[0265] By forming a colored layer (993a) and a colored layer (993b) on an insulator (992), the positions of the colored layer (993a) and the colored layer (993b) and the light-emitting element (572) can be easily aligned. This allows for an increase in the precision of a display device of one form of the present invention.

[0266] <Example of configuration of light-emitting element (572)>

[0267] FIGS. 29 (A) to (E) are drawings showing examples of configurations of a light-emitting element (572). FIGS. 29 (A) shows a structure (single structure) in which an EL layer (786) is sandwiched between a conductor (772) and a conductor (788). As described above, the EL layer (786) includes a light-emitting material, and for example, a light-emitting material which is an organic compound.

[0268] Figure 29 (B) is a diagram showing the stacked structure of the EL layer (786). Here, in the light-emitting element (572) of the structure shown in Figure 29 (B), the conductor (772) functions as an anode, and the conductor (788) functions as a cathode.

[0269] The EL layer (786) has a structure in which a hole injection layer (721), a hole transport layer (722), a light-emitting layer (723), an electron transport layer (724), and an electron injection layer (725) are sequentially stacked on a conductor (772). Additionally, if the conductor (772) functions as a negative electrode and the conductor (788) functions as a positive electrode, the stacking order is reversed.

[0270] The light-emitting layer (723) may be configured to appropriately combine a light-emitting material or a plurality of materials to obtain fluorescent light emission or phosphorescent light emission that exhibits a desired light emission color. Additionally, the light-emitting layer (723) may be formed as a stacked structure with different light emission colors. Furthermore, in this case, it is preferable to use different materials as the light-emitting material or other materials used in each stacked light-emitting layer.

[0271] In the light-emitting element (572), for example, the conductor (772) shown in (B) of FIG. 29 is made into a reflective electrode, the conductor (788) is made into a semi-transparent / semi-reflective electrode, and the structure is made into a micro-optical resonator (microcavity), thereby resonating the light emitted from the light-emitting layer (723) included in the EL layer (786) between the two electrodes, so that the light emitted through the conductor (788) can be strengthened.

[0272] In addition, when the conductor (772) of the light-emitting element (572) is a reflective electrode formed by a laminated structure of a reflective conductive material and a transparent conductive material (transparent conductive film), optical adjustment can be performed by controlling the film thickness of the transparent conductive film. Specifically, with respect to the wavelength λ of light obtained from the light-emitting layer (723), it is preferable to adjust the distance between the electrodes of the conductor (772) and the conductor (788) to be around mλ / 2 (where m is a natural number).

[0273] In addition, to amplify the desired light (wavelength: λ) obtained from the light-emitting layer (723), it is preferable to adjust the optical distance from the conductor (772) to the region (light-emitting region) where the desired light is obtained from the light-emitting layer and the optical distance from the conductor (788) to the region (light-emitting region) where the desired light is obtained from the light-emitting layer (723) to be approximately (2m'+1)λ / 4 (where m' is a natural number). Also, the light-emitting region here refers to the recombination region of holes and electrons in the light-emitting layer (723).

[0274] By performing such optical adjustment, the spectrum of a specific monochromatic light obtained from the light-emitting layer (723) can be narrowed, thereby obtaining light emission with good color purity.

[0275] However, in the above-described case, the optical distance between the conductor (772) and the conductor (788) can strictly be described as the total thickness from the reflection area in the conductor (772) to the reflection area in the conductor (788). However, since it is difficult to strictly determine the reflection area in the conductor (772) or the conductor (788), it is assumed that the above-described effect can be sufficiently obtained by assuming an arbitrary location in the conductor (772) and the conductor (788) as the reflection area. In addition, the optical distance between the conductor (772) and the light-emitting layer where the desired light is obtained can strictly be described as the optical distance between the reflection area in the conductor (772) and the light-emitting area in the light-emitting layer where the desired light is obtained. However, since it is difficult to strictly determine the reflection area in the conductor (772) or the light-emitting area in the light-emitting layer where the desired light is obtained, it is assumed that the above-described effect can be sufficiently obtained by assuming an arbitrary location in the conductor (772) as the reflection area and an arbitrary location in the light-emitting layer where the desired light is obtained as the light-emitting area.

[0276] Since the light-emitting element (572) shown in (B) of FIG. 29 has a microcavity structure, it is possible to extract light of different wavelengths (monochromatic light) even with the same EL layer. Therefore, individual coating (e.g., RGB) to obtain different light-emitting colors becomes unnecessary. Thus, it is easy to achieve high precision. It can also be combined with a coloring layer. In addition, since the light-emitting intensity in the frontal direction of a specific wavelength can be increased, low power consumption can be achieved.

[0277] In addition, the light-emitting element (572) shown in (B) of FIG. 29 does not need to have a microcavity structure. In this case, by making the light-emitting layer (723) structured to emit white light and providing a coloring layer, light of a predetermined color (e.g., RGB) can be extracted. Also, when forming the EL layer (786), if it is formed by an individual coating method to obtain different light-emitting colors, light of a predetermined color can be extracted without providing a coloring layer.

[0278] At least one of the conductor (772) and the conductor (788) may be a light-transmitting electrode (transparent electrode, semi-transparent / semi-reflective electrode, etc.). If the light-transmitting electrode is a transparent electrode, the transmittance of visible light of the transparent electrode is 40% or more. In addition, if it is a semi-transparent / semi-reflective electrode, the reflectance of visible light of the semi-transparent / semi-reflective electrode is 20% or more and 80% or less, preferably 40% or more and 70% or less. In addition, the resistivity of these electrodes is 1×10 - 2 It is desirable to have an Ωcm or less.

[0279] When the conductor (772) or the conductor (788) is a reflective electrode (reflective electrode), the reflectance of visible light of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of this electrode is 1×10 - 2 It is desirable to have an Ωcm or less.

[0280] The configuration of the light-emitting element (572) may be as shown in (C) of FIG. 29. FIG. 29 (C) shows a light-emitting element (572) having a stacked structure (tandem structure) in which two layers of EL layers (EL layer (786a) and EL layer (786b)) are provided between a conductor (772) and a conductor (788), and a charge generating layer (792) is provided between the EL layer (786a) and the EL layer (786b). By making the light-emitting element (572) a tandem structure, the current efficiency and external quantum efficiency of the light-emitting element (572) can be increased. Accordingly, a high-brightness image can be displayed on the display device (10). In addition, the power consumption of the display device (10) can be reduced. Here, the EL layer (786a) and the EL layer (786b) can be configured as the same as the EL layer (786) shown in (B) of FIG. 29.

[0281] The charge generation layer (792) has the function of injecting electrons into one of the EL layer (786a) and the EL layer (786b) and injecting holes into the other when voltage is supplied between the conductor (772) and the conductor (788). Therefore, when voltage is supplied such that the potential of the conductor (772) becomes higher than the potential of the conductor (788), electrons are injected from the charge generation layer (792) into the EL layer (786a), and holes are injected from the charge generation layer (792) into the EL layer (786b).

[0282] In addition, the charge generation layer (792) is preferably capable of transmitting visible light (specifically, the transmittance of visible light of the charge generation layer (792) is 40% or more) in terms of light extraction efficiency. Also, the conductivity of the charge generation layer (792) may be lower than the conductivity of the conductor (772) or the conductor (788).

[0283] The configuration of the light-emitting element (572) may be as shown in (D) of FIG. 29. FIG. 29 (D) shows a light-emitting element (572) of a tandem structure having three layers of EL layers (EL layer (786a), EL layer (786b), and EL layer (786c)) provided between the conductor (772) and the conductor (788), and a charge generating layer (792) between the EL layer (786a) and the EL layer (786b) and between the EL layer (786b) and the EL layer (786c). Here, the EL layer (786a), the EL layer (786b), and the EL layer (786c) may be configured as the same as the EL layer (786) shown in (B) of FIG. 29. By configuring the light-emitting element (572) as shown in (D) of FIG. 29, the current efficiency and external quantum efficiency of the light-emitting element (572) can be further increased. Accordingly, an image with higher brightness can be displayed on the display device (10). In addition, the power consumption of the display device (10) can be further reduced.

[0284] The configuration of the light-emitting element (572) may be as shown in (E) of FIG. 29. FIG. 29 (E) shows a light-emitting element (572) of a tandem structure having n layers of EL layers (EL layers (786(1)) to EL layers (786(n))) provided between a conductor (772) and a conductor (788), and a charge generating layer (792) between each EL layer (786). Here, the EL layers (786(1)) to EL layers (786(n)) may be configured as the same as the EL layer (786) shown in (B) of FIG. 29. Also, FIG. 29 (E) shows EL layers (786(1)), EL layers (786(m)), and EL layers (786(n)) among the EL layers (786). Here, m is an integer greater than or equal to 2 and less than n, and n is an integer greater than or equal to m. The larger the value of n, the higher the current efficiency and external quantum efficiency of the light-emitting element (572). Therefore, a high-brightness image can be displayed on the display device (10). In addition, the power consumption of the display device (10) can be reduced.

[0285] <Constituent materials of the light-emitting element (572)>

[0286] Next, the constituent materials that can be used for the light-emitting element (572) will be described.

[0287] [Challenge body (772) and challenge body (788)]

[0288] In the conductor (772) and conductor (788), materials described below may be appropriately combined and used as long as they satisfy the functions of the positive and negative electrodes. For example, metals, alloys, electrically conductive compounds, and mixtures thereof may be appropriately used. Specifically, In-Sn oxide (also called ITO), In-Si-Sn oxide (also called ITSO), In-Zn oxide, and In-W-Zn oxide may be used. In addition, metals such as aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), gallium (Ga), zinc (Zn), indium (In), tin (Sn), molybdenum (Mo), tantalum (Ta), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), yttrium (Y), and neodymium (Nd), and alloys containing appropriate combinations thereof may also be used. In addition, elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium (Li), cesium (Cs), calcium (Ca), strontium (Sr)), rare earth metals such as europium (Eu) and ytterbium (Yb), alloys containing a suitable combination of these, and graphene may be used.

[0289] [Hole injection layer (721) and hole transport layer (722)]

[0290] The hole injection layer (721) is a layer that injects holes into the EL layer (786) from the positive conductor (772) or charge generation layer (792), and is a layer containing a material with high hole injection properties. Here, the EL layer (786) is configured to include EL layer (786a), EL layer (786b), EL layer (786c), and EL layer (786(1)) to EL layer (786(n)).

[0291] Materials with high hole injection properties include transition metal oxides such as molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and manganese oxide. In addition, phthalocyanine compounds such as phthalocyanine (abbreviated: H2Pc) and copper phthalocyanine (abbreviated: CuPc), aromatic amine compounds such as 4,4'-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl (abbreviated: DPAB) and N,N'-bis{4-[bis(3-methylphenyl)amino]phenyl}-N,N'-diphenyl-(1,1'-biphenyl)-4,4'-diamine (abbreviated: DNTPD), or polymers such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (abbreviated: PEDOT / PSS) can be used.

[0292] In addition, as a material with high hole injection properties, a composite material including a hole transport material and an acceptor material (electron accepting material) may be used. In this case, electrons are extracted from the hole transport material by the acceptor material, and holes are generated in the hole injection layer (721), and holes are injected into the light-emitting layer (723) through the hole transport layer (722). In addition, the hole injection layer (721) may be formed as a single layer made of a composite material including a hole transport material and an acceptor material (electron accepting material), but it may also be formed by stacking the hole transport material and the acceptor material (electron accepting material) as separate layers.

[0293] The hole transport layer (722) is a layer that transports holes injected from the conductor (772) by the hole injection layer (721) to the light-emitting layer (723). Additionally, the hole transport layer (722) is a layer containing a hole transportable material. It is particularly preferable to use a hole transportable material that has a HOMO level equal to or close to the HOMO level of the hole injection layer (721) for the hole transport layer (722).

[0294] As an acceptor material used in the hole injection layer (721), oxides of metals belonging to groups 4 to 8 of the periodic table may be used. Specifically, molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide may be used. Among these, molybdenum oxide is particularly preferred because it is stable in the atmosphere, has low hygroscopicity, and is easy to handle. In addition, organic acceptors such as quinodimethane derivatives, chloranyl derivatives, and hexa-azatriphenylene derivatives may be used. Specifically, 7,7,8,8-tetracyano-2,3,5,6-tetrafluoroquinodimethane (abbreviated: F4-TCNQ), chloranyl, 2,3,6,7,10,11-hexacyano-1,4,5,8,9,12-hexaazatriphenylene (abbreviated: HAT-CN), etc. may be used.

[0295] As a hole transportable material used in the hole injection layer (721) and the hole transport layer (722), 10 -6 cm 2 Materials having a hole mobility of / Vs or higher are preferred. Additionally, materials other than these may be used if they have higher hole transport than electron transport.

[0296] As hole-transporting materials, π-electron-excess heteroaromatic compounds (e.g., carbazole derivatives or indole derivatives) or aromatic amine compounds are preferred, and specific examples include 4,4'-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (abbreviated: NPB or α-NPD), N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (abbreviated: TPD), 4,4'-bis[N-(spiro-9,9'-bifluorene-2-yl)-N-phenylamino]biphenyl (abbreviated: BSPB), 4-phenyl-4'-(9-phenylfluorene-9-yl)triphenylamine (abbreviated: BPAFLP), and 4-phenyl-3'-(9-phenylfluorene-9-yl)triphenylamine (abbreviated: mBPAFLP). 4-phenyl-4'-(9-phenyl-9H-carbazole-3-yl)triphenylamine (abbreviated: PCBA1BP), 3-[4-(9-phenanthryl)-phenyl]-9-phenyl-9H-carbazole (abbreviated: PCPPn), N-(4-biphenyl)-N-(9,9-dimethyl-9H-fluorene-2-yl)-9-phenyl-9H-carbazole-3-amine (abbreviated: PCBiF), N-(1,1'-biphenyl-4-yl)-N-[4-(9-phenyl-9H-carbazole-3-yl)phenyl]-9,9-dimethyl-9H-fluorene-2-amine (abbreviated: PCBBiF), 4,4'-diphenyl-4''-(9-phenyl-9H-carbazole-3-yl)triphenylamine (abbreviated: PCBBi1BP), 4-(1-naphthyl)-4'-(9-phenyl-9H-carbazole-3-yl)triphenylamine (abbreviation: PCBANB), 4,4'-di(1-naphthyl)-4''-(9-phenyl-9H-carbazole-3-yl)triphenylamine (abbreviation: PCBNBB), 9,9-dimethyl-N-phenyl-N-[4-(9-phenyl-9H-carbazole-3-yl)phenyl]fluorene-2-amine (abbreviation: PCBAF), N-phenyl-N-[4-(9-phenyl-9H-carbazole-3-yl)phenyl]spiro-9,9'-bifluorene-2-amine (abbreviation: PCBASF), 4,4',4''-tris(carbazole-9-yl)triphenylamine (abbreviation: TCTA), 4,4',4''-Tris(N,N-Diphenylamino)triphenylamine (abbreviation: TDATA), 4,4',Compounds having an aromatic amine backbone such as 4''-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (abbreviation: MTDATA), 1,3-bis(N-carbazolyl)benzene (abbreviation: mCP), 4,4'-di(N-carbazolyl)biphenyl (abbreviation: CBP), 3,6-bis(3,5-diphenylphenyl)-9-phenylcarbazole (abbreviation: CzTP), 3,3'-bis(9-phenyl-9H-carbazole) (abbreviation: PCCP), 3-[N-(9-phenylcarbazole-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA1), 3,6-bis[N-(9-phenylcarbazole-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA2), Compounds having a carbazole backbone such as 3-[N-(1-naphthyl)-N-(9-phenylcarbazole-3-yl)amino]-9-phenylcarbazole (abbreviation: PCzPCN1), 1,3,5-tris[4-(N-carbazolyl)phenyl]benzene (abbreviation: TCPB), and 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 4,4',4''-(benzene-1,3,5-triyl)tri(dibenzothiophen) (abbreviation: DBT3P-II), and 2,8-diphenyl-4-[4-(9-phenyl-9H-fluorene-9-yl)phenyl]dibenzothiophen (abbreviation: DBTFLP-III), Examples include compounds having a thiophene backbone such as 4-[4-(9-phenyl-9H-fluoren-9-yl)phenyl]-6-phenyldibenzothiophene (abbreviation: DBTFLP-IV), and compounds having a furan backbone such as 4,4',4''-(benzene-1,3,5-triyl)tri(dibenzofuran) (abbreviation: DBF3P-II) and 4-{3-[3-(9-phenyl-9H-fluoren-9-yl)phenyl]phenyl}dibenzofuran (abbreviation: mmDBFFLBi-II).

[0297] In addition, polymer compounds such as poly(N-vinylcarbazole) (abbreviated: PVK), poly(4-vinyltriphenylamine) (abbreviated: PVTPA), poly[N-(4-{N'-[4-(4-diphenylamino)phenyl]phenyl-N'-phenylamino}phenyl)methacrylamide] (abbreviated: PTPDMA), and poly[N,N'-bis(4-butylphenyl)-N,N'-bis(phenyl)benzidine] (abbreviated: Poly-TPD) may also be used.

[0298] However, the hole transportable material is not limited to the above, and various known materials may be used as hole transportable materials in the hole injection layer (721) and the hole transport layer (722) by combining one or more types. In addition, the hole transport layer (722) may each be formed into multiple layers. That is, for example, a first hole transport layer and a second hole transport layer may be stacked.

[0299] [Light-emitting layer (723)]

[0300] The light-emitting layer (723) is a layer containing a light-emitting material. Additionally, as the light-emitting material, a material exhibiting a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red is appropriately used. Here, as shown in (C), (D), and (E) of FIG. 29, when the light-emitting element (572) has a plurality of EL layers, by using different light-emitting materials in the light-emitting layer (723) provided to each EL layer, a configuration exhibiting different light-emitting colors (for example, white light obtained by combining light-emitting colors that are in a complementary relationship) can be achieved. For example, when the light-emitting element (572) is configured as shown in (C) of FIG. 29, by making the light-emitting material used in the light-emitting layer (723) provided to the EL layer (786a) and the light-emitting material used in the light-emitting layer (723) provided to the EL layer (786b) different, the light-emitting color exhibited by the EL layer (786a) and the light-emitting color exhibited by the EL layer (786b) can be made different. In addition, a single light-emitting layer may have a stacked structure having different light-emitting materials.

[0301] In addition, the light-emitting layer (723) may have one or more types of organic compounds (host material, assist material) in addition to the light-emitting material (guest material). In addition, as one or both types of organic compounds, one or both of hole transport materials and electron transport materials may be used.

[0302] There are no particular limitations on the light-emitting material that can be used in the light-emitting layer (723), and a light-emitting material that converts singlet excited energy into light emission in the visible light region, or a light-emitting material that converts triplet excited energy into light emission in the visible light region may be used. In addition, the light-emitting material may include, for example, the following:

[0303] Examples of luminescent materials that convert singlet excited energy into luminescence include fluorescent materials (fluorescent materials), such as pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives. In particular, pyrene derivatives are desirable due to their high luminescence quantum yield. Specific examples of pyrene derivatives include N,N'-bis(3-methylphenyl)-N,N'-bis[3-(9-phenyl-9H-fluorene-9-yl)phenyl]pyrene-1,6-diamine (abbreviated: 1,6mMemFLPAPrn), N,N'-diphenyl-N,N'-bis[4-(9-phenyl-9H-fluorene-9-yl)phenyl]pyrene-1,6-diamine (abbreviated: 1,6FLPAPrn), N,N'-bis(dibenzofuran-2-yl)-N,N'-diphenylpyrene-1,6-diamine (abbreviated: 1,6FrAPrn), and N,N'-bis(dibenzothiophen-2-yl)-N,N'-diphenylpyrene-1,6-diamine (abbreviated: 1,6ThAPrn). Examples include N,N'-(pyrene-1,6-diyl)bis[(N-phenylbenzo[b]naphtho[1,2-d]furan)-6-amine] (abbreviated: 1,6BnfAPrn), N,N'-(pyrene-1,6-diyl)bis[(N-phenylbenzo[b]naphtho[1,2-d]furan)-8-amine] (abbreviated: 1,6BnfAPrn-02), N,N'-(pyrene-1,6-diyl)bis[(6,N-diphenylbenzo[b]naphtho[1,2-d]furan)-8-amine] (abbreviated: 1,6BnfAPrn-03), etc. Additionally, pyrene derivatives are a group of compounds useful for achieving a blue color intensity in one embodiment of the present invention.

[0304] In addition, 5,6-bis[4-(10-phenyl-9-anthryl)phenyl]-2,2'-bipyridine (abbreviated: PAP2BPy), 5,6-bis[4'-(10-phenyl-9-anthryl)biphenyl-4-yl]-2,2'-bipyridine (abbreviated: PAPP2BPy), N,N'-bis[4-(9H-carbazole-9-yl)phenyl]-N,N'-diphenylstilbene-4,4'-diamine (abbreviated: YGA2S), 4-(9H-carbazole-9-yl)-4'-(10-phenyl-9-anthryl)triphenylamine (abbreviated: YGAPA), 4-(9H-carbazole-9-yl)-4'-(9,10-diphenyl-2-anthryl)triphenylamine (abbreviated: 2YGAPPA), N,9-Diphenyl-N-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole-3-amine (abbreviation: PCAPA), 4-(10-phenyl-9-anthryl)-4'-(9-phenyl-9H-carbazole-3-yl)triphenylamine (abbreviation: PCBAPA), 4-[4-(10-phenyl-9-anthryl)phenyl]-4'-(9-phenyl-9H-carbazole-3-yl)triphenylamine (abbreviation: PCBAPBA), Perylene, 2,5,8,11-Tetra(tert-butyl)Perylene (abbreviation: TBP), N,N''-(2-tert-butylanthracene-9,10-diyldi-4,1-phenylene)bis[N,N',N'-triphenyl-1,4-phenylenediamine] (abbreviation: DPABPA), N,9-diphenyl-N-[4-(9,10-diphenyl-2-anthryl)phenyl]-9H-carbazole-3-amine (abbreviated: 2PCAPPA), N-[4-(9,10-diphenyl-2-anthryl)phenyl]-N,N',N'-triphenyl-1,4-phenylenediamine (abbreviated: 2DPAPPA), etc. can be used.

[0305] In addition, as luminescent materials that convert triplet excited energy into luminescence, there are, for example, phosphorescent materials (phosphorescent materials) or thermally activated delayed fluorescence (TADF) materials that exhibit thermally activated delayed fluorescence.

[0306] Examples of phosphorescent materials include organometallic complexes, metal complexes (platinum complexes), and rare earth metal complexes. Since these materials exhibit different emission colors (emission peaks), they are appropriately selected and used as needed.

[0307] Phosphorescent materials that exhibit blue or green light and have a peak wavelength of the emission spectrum of 450 nm or more and 570 nm or less include the following materials.

[0308] For example, tris{2-[5-(2-methylphenyl)-4-(2,6-dimethylphenyl)-4H-1,2,4-triazole-3-yl-κN2]phenyl-κC}iridium(III) (abbreviated: [Ir(mpptz-dmp)3]), tris(5-methyl-3,4-diphenyl-4H-1,2,4-triazoleate)iridium(III) (abbreviated: [Ir(Mptz)3]), tris[4-(3-biphenyl)-5-isopropyl-3-phenyl-4H-1,2,4-triazoleate]iridium(III) (abbreviated: [Ir(iPrptz-3b)3]), tris[3-(5-biphenyl)-5-isopropyl-4-phenyl-4H-1,2,4-triazoleate]iridium(III) (abbreviated: Organometallic complexes having a 4H-triazole backbone such as [Ir(iPr5btz)3]), tris[3-methyl-1-(2-methylphenyl)-5-phenyl-1H-1,2,4-triazoleto]iridium(III) (abbreviated: [Ir(Mptz1-mp)3]), organometallic complexes having a 1H-triazole backbone such as tris(1-methyl-5-phenyl-3-propyl-1H-1,2,4-triazoleto)iridium(III) (abbreviated: [Ir(Prptz1-Me)3]), fac-tris[1-(2,6-diisopropylphenyl)-2-phenyl-1H-imidazole]iridium(III) (abbreviated: [Ir(iPrpmi)3]), Organometallic complex having an imidazole backbone such as tris[3-(2,6-dimethylphenyl)-7-methylimidazo[1,2-f]phenantridinato]iridium(III) (abbreviated: [Ir(dmpimpt-Me)3]), bis[2-(4',6'-difluorophenyl)pyridinato-N,C 2']Iridium(III)tetrakis(1-pyrazolyl)borate (abbreviated: FIr6), bis[2-(4',6'-difluorophenyl)pyridinato-N,C 2 ' ]Iridium(III)picolinate (abbreviated: FIrpic), bis[2-(3,5-bistrifluoromethylphenyl)pyridinate-N,C 2 ' ]Iridium(III)picolinate (abbreviation: [Ir(CF3ppy)2(pic)]), bis[2-(4',6'-difluorophenyl)pyridinate-N,C 2' There are organometallic complexes that use a phenylpyridine derivative having an electron-withdrawing group as a ligand, such as iridium(III) acetylacetonate (abbreviated: FIr(acac)).

[0309] The following materials can be cited as phosphorescent materials that exhibit green or yellow color and have a peak wavelength of the emission spectrum between 495 nm and 590 nm.

[0310] For example, tris(4-methyl-6-phenylpyrimidineto)iridium(III) (abbreviated: [Ir(mppm)3]), tris(4-t-butyl-6-phenylpyrimidineto)iridium(III) (abbreviated: [Ir(tBuppm)3]), (acetylacetonato)bis(6-methyl-4-phenylpyrimidineto)iridium(III) (abbreviated: [Ir(mppm)2(acac)]), (acetylacetonato)bis(6-tert-butyl-4-phenylpyrimidineto)iridium(III) (abbreviated: [Ir(tBuppm)2(acac)]), (acetylacetonato)bis[6-(2-norvonyl)-4-phenylpyrimidineto]iridium(III) (abbreviated: Organometallic iridium complexes having a pyrimidine backbone such as [Ir(nbppm)2(acac)]), (acetylacetonato)bis[5-methyl-6-(2-methylphenyl)-4-phenylpyrimidineto]iridium(III) (abbreviated: [Ir(mpmppm)2(acac)]), (acetylacetonato)bis{4,6-dimethyl-2-[6-(2,6-dimethylphenyl)-4-pyrimidinyl-κN3]phenyl-κC}iridium(III) (abbreviated: [Ir(dmppm-dmp)2(acac)]), and (acetylacetonato)bis(4,6-diphenylpyrimidineto)iridium(III) (abbreviated: [Ir(dppm)2(acac)]), Organometallic iridium complexes having a pyrazine backbone such as (acetylacetonato)bis(3,5-dimethyl-2-phenylpyrazineto)iridium(III) (abbreviated: [Ir(mppr-Me)2(acac)]) and (acetylacetonato)bis(5-isopropyl-3-methyl-2-phenylpyrazineto)iridium(III) (abbreviated: [Ir(mppr-iPr)2(acac)]), tris(2-phenylpyridineto-N,C 2' )Iridium(III) (abbreviation: [Ir(ppy)3]), bis(2-phenylpyridinate-N,C 2' )iridium(III)acetylacetonate (abbreviation: [Ir(ppy)2(acac)]), bis(benzo[h]quinolinato)iridium(III)acetylacetonate (abbreviation: [Ir(bzq)2(acac)]), tris(benzo[h]quinolinato)iridium(III) (abbreviation: [Ir(bzq)3]), tris(2-phenylquinolinato-N,C2' )Iridium(III) (abbreviation: [Ir(pq)3]), bis(2-phenylquinolinato-N,C 2' Organometallic iridium complex having a pyridine backbone such as iridium(III) acetylacetonate (abbreviated: [Ir(pq)2(acac)]), bis(2,4-diphenyl-1,3-oxazolato-N,C 2' )Iridium(III)acetylacetonate (abbreviation: [Ir(dpo)2(acac)]), bis{2-[4'-(perfluorophenyl)phenyl]pyridinate-N,C 2 '}Iridium(III)acetylacetonate (abbreviation: [Ir(p-PF-ph)2(acac)]), bis(2-phenylbenzothiazolate-N,C 2' In addition to organometallic complexes such as iridium(III) acetylacetonate (abbreviated: [Ir(bt)2(acac)]), there are rare earth metal complexes such as tris(acetylacetonate)(monophenantroline)terbium(III) (abbreviated: [Tb(acac)3(Phen)]).

[0311] Among the above, organometallic iridium complexes having a pyridine backbone (particularly a phenylpyridine backbone) or a pyrimidine backbone are a group of compounds useful for achieving a green color in one embodiment of the present invention.

[0312] Phosphorescent materials that exhibit yellow or red color and have a peak wavelength of the emission spectrum of 570 nm or more and 750 nm or less include the following materials.

[0313] For example, organometallic complexes having a pyrimidine backbone such as (diisobutyrylmetanato)bis[4,6-bis(3-methylphenyl)pyrimidinato]iridium(III) (abbreviated: [Ir(5mdppm)2(dibm)]), bis[4,6-bis(3-methylphenyl)pyrimidinato](dipivaloylmetanato)iridium(III) (abbreviated: [Ir(5mdppm)2(dpm)]), (dipivaloylmetanato)bis[4,6-di(naphthalene-1-yl)pyrimidinato]iridium(III) (abbreviated: [Ir(d1npm)2(dpm)]), (acetylacetonato)bis(2,3,5-triphenylpyrazinato)iridium(III) (abbreviated: [Ir(tppr)2(acac)]), bis(2,3,5-triphenylpyrazineto)(dipivaloylmetaneto)iridium(III)(abbreviated: [Ir(tppr)2(dpm)]), bis{4,6-dimethyl-2-[3-(3,5-dimethylphenyl)-5-phenyl-2-pyrazinyl-κN]phenyl-κC}(2,6-dimethyl-3,5-heptanedioneto-κ 2 O,O')iridium(III)(abbreviation: [Ir(dmdppr-P)2(dibm)]), bis{4,6-dimethyl-2-[5-(4-cyano-2,6-dimethylphenyl)-3-(3,5-dimethylphenyl)-2-pyrazinyl-κN]phenyl-κC}(2,2,6,6-tetramethyl-3,5-heptaneto-κ 2 O,O')iridium(III)(abbreviation: [Ir(dmdppr-dmCP)2(dpm)]), (acetylacetonato)bis[2-methyl-3-phenylquinoxalineto-N,C 2' ]Iridium(III)(abbreviation: [Ir(mpq)2(acac)]), (acetylacetonato)bis(2,3-diphenylquinoxalineto-N,C 2 ' Organometallic complexes having a pyrazine backbone, such as iridium(III) (abbreviated: [Ir(dpq)2(acac)]) and (acetylacetonato)bis[2,3-bis(4-fluorophenyl)quinoxalinato]iridium(III) (abbreviated: [Ir(Fdpq)2(acac)]), or tris(1-phenylisoquinolinato-N,C 2')Iridium(III) (abbreviation: [Ir(piq)3]), bis(1-phenylisoquinolinato-N,C 2' There are organometallic complexes having a pyridine backbone such as iridium(III) acetylacetonate (abbreviated: [Ir(piq)2(acac)]), platinum complexes such as 2,3,7,8,12,13,17,18-octaethyl-21H,23H-porphyrinplatinum(II) (abbreviated: [PtOEP]), rare earth metal complexes such as tris(1,3-diphenyl-1,3-propanedioto)(monophenanthrolin)europium(III) (abbreviated: [Eu(DBM)3(Phen)]) and tris[1-(2-tenoyl)-3,3,3-trifluoroacetonato](monophenanthrolin)europium(III) (abbreviated: [Eu(TTA)3(Phen)]).

[0314] Among those described above, organometallic iridium complexes having a pyrazine backbone are a group of compounds useful for achieving red coloration in one embodiment of the present invention. In particular, organometallic iridium complexes having a cyano group, such as [Ir(dmdppr-dmCP)2(dpm)], are preferred due to their high stability.

[0315] In addition, as a blue emitting material, it is preferable to use a material having a photoluminescence peak wavelength of 430 nm or more and 470 nm or less, more preferably 430 nm or more and 460 nm or less. In addition, as a green emitting material, it is preferable to use a material having a photoluminescence peak wavelength of 500 nm or more and 540 nm or less, more preferably 500 nm or more and 530 nm or less. As a red emitting material, it is preferable to use a material having a photoluminescence peak wavelength of 610 nm or more and 680 nm or less, more preferably 620 nm or more and 680 nm or less. In addition, photoluminescence may be measured using either a solution or a thin film.

[0316] By combining such a compound with a microcavity effect, the aforementioned color intensity can be achieved more easily. At this time, the film thickness of the semi-transparent / semi-reflective electrode (metal thin film portion) required to obtain the microcavity effect is preferably 20 nm or more and 40 nm or less. More preferably, it is greater than 25 nm and 40 nm or less. In addition, if it exceeds 40 nm, there is a possibility that the efficiency will decrease.

[0317] As for the organic compound (host material, assist material) used in the light-emitting layer (723), it is preferable to select and use one or more types of materials having an energy gap larger than the energy gap of the light-emitting material (guest material). In addition, the hole transport material described above and the electron transport material described below may each be used as a host material or an assist material.

[0318] When the emitting material is a fluorescent material, it is preferable to use an organic compound as the host material that has a large energy level in the singlet excited state and a small energy level in the triplet excited state. For example, it is preferable to use an anthracene derivative or a tetracene derivative. Specifically, 9-phenyl-3-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviated: PCzPA), 3-[4-(1-naphthyl)-phenyl]-9-phenyl-9H-carbazole (abbreviated: PCPN), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviated: CzPA), 7-[4-(10-phenyl-9-anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviated: cgDBCzPA), 6-[3-(9,10-diphenyl-2-anthryl)phenyl]-benzo[b]naphtho[1,2-d]furan (abbreviated: 2mBnfPPA), Examples include 9-phenyl-10-{4-(9-phenyl-9H-fluorene-9-yl)biphenyl-4'-yl}anthracene (abbreviated: FLPPA), 5,12-diphenyltetracene, 5,12-bis(biphenyl-2-yl)tetracene, etc.

[0319] When the emitting material is a phosphorescent material, it is preferable to select an organic compound as the host material that has a triplet excited energy greater than the triplet excited energy of the emitting material (the energy difference between the ground state and the triplet excited state). In addition, in this case, in addition to zinc or aluminum-based metal complexes, oxadiazole derivatives, triazole derivatives, benzimidazole derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, pyrimidine derivatives, triazine derivatives, pyridine derivatives, bipyridine derivatives, phenanthroline derivatives, etc., aromatic amines or carbazole derivatives can be used.

[0320] Specifically, metal complexes such as tris(8-quinolinoleto)aluminum(III) (abbreviated: Alq), tris(4-methyl-8-quinolinoleto)aluminum(III) (abbreviated: Almq3), bis(10-hydroxybenzo[h]quinolinato)beryllium(II) (abbreviated: BeBq2), bis(2-methyl-8-quinolinoleto)(4-phenylphenolato)aluminum(III) (abbreviated: BAlq), bis(8-quinolinoleto)zinc(II) (abbreviated: Znq), bis[2-(2-benzoxazolyl)phenolato]zinc(II) (abbreviated: ZnPBO), and bis[2-(2-benzothiazolyl)phenolato]zinc(II) (abbreviated: ZnBTZ), 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazole-2-yl]benzene (abbreviation: OXD-7), 3-(4-biphenylyl)-4-phenyl-5-(4-tert-butylphenyl)-1,2,4-triazole (abbreviation: TAZ), 2,2',2''-(1,3,5-benzenetriyl)-tris(1-phenyl-1H-benzimidazole) (abbreviation: TPBI), vasofenanthroline (abbreviation: BPhen), vasocuproin (abbreviation: BCP), Examples include heterocyclic compounds such as 2,9-bis(naphthalene-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated: NBphen) and 9-[4-(5-phenyl-1,3,4-oxadiazole-2-yl)phenyl]-9H-carbazole (abbreviated: CO11), and aromatic amine compounds such as NPB, TPD, and BSPB.

[0321] In addition, examples include condensed polycyclic aromatic compounds such as anthracene derivatives, phenanthrene derivatives, pyrene derivatives, chrysene derivatives, and dibenzo[g,p]chrysene derivatives. Specifically, 9,10-diphenylanthracene (abbreviated: DPAnth), N,N-diphenyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole-3-amine (abbreviated: CzA1PA), 4-(10-phenyl-9-anthryl)triphenylamine (abbreviated: DPhPA), YGAPA, PCAPA, N,9-diphenyl-N-{4-[4-(10-phenyl-9-anthryl)phenyl]phenyl}-9H-carbazole-3-amine (abbreviated: PCAPBA), and 9,10-diphenyl-2-[N-phenyl-N-(9-phenyl-9H-carbazole-3-yl)amino]anthracene (abbreviated: 2PCAPA), 6,12-dimethoxy-5,11-diphenylchrysene, N,N,N',N',N'',N'',N''',N'''-octaphenyldibenzo[g,p]chrysene-2,7,10,15-tetraamine (abbreviation: DBC1), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 3,6-diphenyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: DPCzPA), 9,10-bis(3,5-diphenylphenyl)anthracene (abbreviation: DPPA), 9,10-di(2-naphthyl)anthracene (abbreviation: DNA), 2-tert-butyl-9,10-di(2-naphthyl)anthracene (abbreviation: t-BuDNA), 9,9'-bianthrile (abbreviation: BANT), 9,9'-(stilbene-3,3'-diyl)diphenanthrene (abbreviation: DPNS), 9,9'-(stilbene-4,4'-diyl)diphenanthrene (abbreviation: DPNS2), 1,3,5-tri(1-pyrenyl)benzene (abbreviation: TPB3), etc. may be used.

[0322] In addition, when using multiple organic compounds in the light-emitting layer (723), it is preferable to use a compound that forms an excited complex by mixing it with the light-emitting material. In this case, various organic compounds can be appropriately combined and used, but in order to efficiently form the excited complex, it is particularly preferable to combine a compound that readily accepts holes (hole transport material) and a compound that readily accepts electrons (electron transport material). In addition, regarding specific examples of hole transport materials and electron transport materials, the materials shown in this embodiment may be used.

[0323] A TADF material refers to a material capable of upconverting (crossing between inverse terms) from a triplet excited state to a singlet excited state by a small amount of thermal energy, and efficiently exhibiting luminescence (fluorescence) from the singlet excited state. Furthermore, conditions for efficiently obtaining thermally activated delayed fluorescence include an energy difference between the triplet excitation level and the singlet excitation level being 0 eV or more and 0.2 eV or less, preferably 0 eV or more and 0.1 eV or less. Additionally, delayed fluorescence in TADF materials refers to luminescence that has a spectrum similar to general fluorescence but has a significantly longer lifetime. Its lifetime is 10 -6 At least 10 seconds, preferably 10 -3 It is more than a second.

[0324] Examples of TADF materials include fullerene or its derivatives, acridin derivatives such as proflavin, and eosin. In addition, metal-containing porphyrins containing magnesium (Mg), zinc (Zn), cadmium (Cd), tin (Sn), platinum (Pt), indium (In), or palladium (Pd) may be used. Examples of metal-containing porphyrins include protoporphyrin-tin fluoride complex (SnF2(Proto IX)), mesoporphyrin-tin fluoride complex (SnF2(Meso IX)), hematoporphyrin-tin fluoride complex (SnF2(Hemato IX)), coproporphyrin tetramethyl ester-tin fluoride complex (SnF2(Copro III-4Me)), octaethylporphyrin-tin fluoride complex (SnF2(OEP)), ethioporphyrin-tin fluoride complex (SnF2(Etio I)), octaethylporphyrin-platinum chloride complex (PtCl2OEP), etc.

[0325] In addition, 2-(biphenyl-4-yl)-4,6-bis(12-phenylindolo[2,3-a]carbazole-11-yl)-1,3,5-triazine (PIC-TRZ), 2-{4-[3-(N-phenyl-9H-carbazole-3-yl)-9H-carbazole-9-yl]phenyl}-4,6-diphenyl-1,3,5-triazine (PCCzPTzn), 2-[4-(10H-phenoxazine-10-yl)phenyl]-4,6-diphenyl-1,3,5-triazine (PXZ-TRZ), 3-[4-(5-phenyl-5,10-dihydrophenazine-10-yl)phenyl]-4,5-diphenyl-1,2,4-triazine (PPZ-3TPT), Heterocyclic compounds having π-electron-excess heteroaromatic rings and π-electron-deficient heteroaromatic rings, such as 3-(9,9-dimethyl-9H-acridine-10-yl)-9H-xanthen-9-one (ACRXTN), bis[4-(9,9-dimethyl-9,10-dihydroacridine)phenyl]sulfone (DMAC-DPS), and 10-phenyl-10H,10'H-spiro[acridine-9,9'-anthracene]-10'-one (ACRSA), may be used. In addition, materials in which a π-electron-excess heteroaromatic ring and a π-electron-deficient heteroaromatic ring are directly bonded are particularly desirable because both the donor nature of the π-electron-excess heteroaromatic ring and the acceptor nature of the π-electron-deficient heteroaromatic ring are strengthened, thereby reducing the energy difference between the singlet excited state and the triplet excited state.

[0326] In addition, when using TADF materials, they can also be used in combination with other organic compounds.

[0327] [Electron transport layer (724)]

[0328] The electron transport layer (724) is a layer that transports electrons injected from the conductor (788) by the electron injection layer (725) to the light-emitting layer (723). Additionally, the electron transport layer (724) is a layer containing an electron transportable material. The electron transportable material used in the electron transport layer (724) is 1×10 -6 cm 2Materials having an electron mobility of / Vs or higher are preferred. Additionally, materials other than these may be used if they have higher electron transport than hole transport.

[0329] Examples of electron transport materials include metal complexes having quinoline ligands, benzoquinoline ligands, oxazole ligands, or thiazole ligands, oxadiazole derivatives, triazole derivatives, phenanthroline derivatives, pyridine derivatives, bipyridine derivatives, etc. In addition, π-electron deficient heteroaromatic compounds, such as nitrogen-containing heteroaromatic compounds, may be used.

[0330] Specifically, metal complexes such as Alq3, tris(4-methyl-8-quinolinoleate)aluminum (abbreviated: Almq3), bis(10-hydroxybenzo[h]quinolinate)beryllium (abbreviated: BeBq2), BAlq, Zn(BOX)2, and bis[2-(2-hydroxyphenyl)benzothiazolate]zinc (abbreviated: Zn(BTZ)2), 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviated: PBD), and 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazole-2-yl]benzene (abbreviated: OXD-7), Heteroaromatic compounds such as 3-(4'-tert-butylphenyl)-4-phenyl-5-(4''-biphenyl)-1,2,4-triazole (abbreviation: TAZ), 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (abbreviation: p-EtTAZ), vasophenanthroline (abbreviation: Bphen), vasocuproin (abbreviation: BCP), 4,4'-bis(5-methylbenzoxazole-2-yl)stilbene (abbreviation: BzOs), 2-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTPDBq-II), Quinoxaline or dibenzoquinoxaline derivatives such as 2-[3'-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviated: 2mDBTBPDBq-II), 2-[4-(3,6-diphenyl-9H-carbazole-9-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviated: 2CzPDBq-III), 7-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviated: 7mDBTPDBq-II), and 6-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviated: 6mDBTPDBq-II) may be used.

[0331] In addition, polymer compounds such as poly(2,5-pyridinediyl) (abbreviated: PPy), poly[(9,9-dihexylfluorene-2,7-diyl)-co-(pyridine-3,5-diyl)] (abbreviated: PF-Py), and poly[(9,9-dioctylfluorene-2,7-diyl)-co-(2,2'-bipyridine-6,6'-diyl)] (abbreviated: PF-BPy) may also be used.

[0332] In addition, the electron transport layer (724) may have a structure in which two or more layers made of the above material are stacked, not just a single layer.

[0333] [Electron injection layer (725)]

[0334] The electron injection layer (725) is a layer containing a material with high electron injection properties. The electron injection layer (725) contains lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), and lithium oxide (LiO2). x Alkali metals, alkaline earth metals, or compounds thereof such as ) may be used. Rare earth metal compounds such as erbium fluoride (ErF3) may also be used. Additionally, an electride may be used in the electron injection layer (725). Examples of electrides include a material in which electrons are added at a high concentration to a mixed oxide of calcium and aluminum. Additionally, the material constituting the electron transport layer (724) described above may also be used.

[0335] In addition, a composite material formed by mixing an organic compound and an electron donor (donor) may be used in the electron injection layer (725). Since electrons are generated in the organic compound by the electron donor, such a composite material has excellent electron injection and electron transport properties. In this case, it is desirable for the organic compound to be a material that is excellent for transporting the generated electrons, and specifically, for example, an electron transport material (such as a metal complex or a heteroaromatic compound) used in the electron transport layer (724) described above may be used. As for the electron donor, it is desirable to use a material that exhibits electron-donating properties with respect to the organic compound. Specifically, alkali metals, alkaline earth metals, or rare earth metals are preferred, and examples include lithium, cesium, magnesium, calcium, erbium, ytterbium, etc. Also, alkali metal oxides or alkaline earth metal oxides are preferred, and examples include lithium oxide, calcium oxide, barium oxide, etc. Additionally, Lewis bases such as magnesium oxide may be used. Also, organic compounds such as tetrathiafulvalene (abbreviated: TTF) may be used.

[0336] [Charge generating layer (792)]

[0337] The charge generation layer (792) has the function of injecting electrons into the EL layer (786) closer to the conductor (772) and injecting holes into the EL layer (786) closer to the conductor (788) among the two EL layers (786) in contact with the charge generation layer (792) when a voltage is applied between the conductor (772) and the conductor (788). For example, in the light-emitting element (572) with the configuration shown in (C) of FIG. 29, the charge generation layer (792) has the function of injecting electrons into the EL layer (786a) and injecting holes into the EL layer (786b). In addition, the charge generation layer (792) may be configured such that an electron acceptor is added to a hole-transporting material, or may be configured such that an electron donor is added to an electron-transporting material. In addition, both of these configurations may be stacked. In addition, by forming a charge generation layer (792) using the above-described material, the increase in the driving voltage of the display device (10) when the EL layer is stacked can be suppressed.

[0338] In the charge generation layer (792), when the composition is such that an electron acceptor is added to a hole-transporting material, examples of electron acceptors include 7,7,8,8-tetracyano-2,3,5,6-tetrafluoroquinodimethane (abbreviated: F4-TCNQ), chloranyl, etc. Also, oxides of metals belonging to groups 4 to 8 of the periodic table may be used. Specifically, examples include vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, rhenium oxide, etc.

[0339] When the charge generating layer (792) is configured such that an electron donor is added to an electron transportable material, the electron donor may be an alkali metal, an alkaline earth metal, a rare earth metal, or a metal belonging to Group 2 or Group 13 of the periodic table, and its oxide or carbonate. Specifically, it is preferable to use lithium (Li), cesium (Cs), magnesium (Mg), calcium (Ca), ytterbium (Yb), indium (In), lithium oxide, cesium carbonate, etc. Additionally, an organic compound such as tetracyanaptacene may be used as an electron donor.

[0340] In addition, vacuum processes such as deposition methods or solution processes such as spin coating methods or inkjet methods can be used to fabricate the light-emitting element (572). When using a deposition method, physical vapor deposition methods (PVD methods) such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, or chemical vapor deposition methods (CVD methods) can be used. In particular, functional layers (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer) and charge generation layers included in the EL layer of the light-emitting element can be formed by methods such as deposition methods (vacuum deposition methods, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), and printing methods (inkjet, screen printing, offset printing, flexographic printing, gravure, micro-contact method, etc.).

[0341] In addition, each functional layer (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer) and charge generation layer constituting the EL layer of the light-emitting device shown in this embodiment are not limited to the materials described above, and other materials may be used in combination as long as they satisfy the function of each layer. As an example, polymer compounds (oligomers, dendrimers, polymers, etc.), medium-molecular compounds (compounds in the intermediate region between low-molecular and high-molecular weights: molecular weight 400 to 4000), inorganic compounds (quantum dot materials, etc.) may be used. In addition, as quantum dot materials, colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc. may be used.

[0342] The configuration examples and corresponding drawings, etc. exemplified in this embodiment may be implemented by appropriately combining at least a part thereof with other configuration examples or drawings, etc.

[0343] This embodiment may be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0344] (Embodiment 2)

[0345] In this embodiment, a transistor that can be used in a display device, which is one form of the present invention, is described.

[0346] <Transistor Configuration Example 1>

[0347] Figures 30 (A), (B), and (C) are a top view and a cross-sectional view of a transistor (200A) and a periphery of the transistor (200A) that can be used in a display device of one embodiment of the present invention. A transistor (200A) can be applied to a display device of one embodiment of the present invention.

[0348] FIG. 30 (A) is a top view of a transistor (200A). FIG. 30 (B) and (C) are cross-sectional views of a transistor (200A). Here, FIG. 30 (B) is a cross-sectional view of the portion indicated by the dotted line A1-A2 in FIG. 30 (A), and is also a cross-sectional view in the channel length direction of the transistor (200A). FIG. 30 (C) is a cross-sectional view of the portion indicated by the dotted line A3-A4 in FIG. 30 (A), and is also a cross-sectional view in the channel width direction of the transistor (200A). Additionally, in the top view of FIG. 30 (A), some elements have been omitted for clarity of the drawing.

[0349] As shown in FIG. 30, the transistor (200A) comprises a metal oxide (230a) disposed on a substrate (not shown), a metal oxide (230b) disposed on the metal oxide (230a), a conductor (242a) and a conductor (242b) disposed spaced apart from each other on the metal oxide (230b), an insulator (280) disposed on the conductor (242a) and the conductor (242b) with an opening formed between the conductor (242a) and the conductor (242b), a conductor (260) disposed within the opening, an insulator (250) disposed between the metal oxide (230b), the conductor (242a), the conductor (242b), and the insulator (280) and the conductor (260), and the metal oxide (230b), the conductor (242a), the conductor (242b), and the insulator (280). It has a metal oxide (230c) disposed between insulators (250). Here, as shown in (B) and (C) of FIG. 30, it is preferable that the upper surface of the conductor (260) substantially coincides with the upper surface of the insulator (250), insulator (254), metal oxide (230c), and insulator (280). Also, below, the metal oxide (230a), metal oxide (230b), and metal oxide (230c) are collectively referred to as the metal oxide (230). Additionally, the conductor (242a) and conductor (242b) are collectively referred to as the conductor (242).

[0350] The transistor (200A) shown in FIG. 30 has a shape in which the side surface of the conductor (260) of the conductor (242a) and the conductor (242b) is substantially perpendicular. Furthermore, the transistor (200A) shown in FIG. 30 is not limited thereto, and the angle formed by the side surface and the bottom surface of the conductor (242a) and the conductor (242b) may be 10° or more and 80° or less, preferably 30° or more and 60° or less. Additionally, the opposing side surfaces of the conductor (242a) and the conductor (242b) may have multiple surfaces.

[0351] Additionally, as shown in FIG. 30, it is preferable that an insulator (254) be placed between an insulator (224), a metal oxide (230a), a metal oxide (230b), a conductor (242a), a conductor (242b), and a metal oxide (230c) and an insulator (280). Here, as shown in FIG. 30 (B) and (C), it is preferable that the insulator (254) be in contact with the side of the metal oxide (230c), the top and side of the conductor (242a), the top and side of the conductor (242b), the side of the metal oxide (230a) and the metal oxide (230b), and the top of the insulator (224).

[0352] Additionally, although a configuration has been shown in which three layers of metal oxide (230a), metal oxide (230b), and metal oxide (230c) are stacked in the region where a channel is formed in the transistor (200A) (hereinafter also referred to as the channel formation region) and in the vicinity thereof, the present invention is not limited thereto. For example, a configuration may be provided that offers a two-layer structure of metal oxide (230b) and metal oxide (230c), or a stacked structure of four or more layers. Additionally, although the conductor (260) in the transistor (200A) has been shown as a two-layer stacked structure, the present invention is not limited thereto. For example, the conductor (260) may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide (230a), metal oxide (230b), and metal oxide (230c) may have a stacked structure of two or more layers.

[0353] For example, when the metal oxide (230c) has a stacked structure consisting of a first metal oxide and a second metal oxide on top of the first metal oxide, it is preferable that the first metal oxide has the same composition as the metal oxide (230b) and the second metal oxide has the same composition as the metal oxide (230a).

[0354] Here, the conductor (260) functions as the gate electrode of the transistor, and the conductor (242a) and the conductor (242b) each function as the source electrode or the drain electrode. As described above, the conductor (260) is formed to be embedded in the opening of the insulator (280) and in the area fitted between the conductor (242a) and the conductor (242b). Here, the arrangement of the conductor (260), the conductor (242a), and the conductor (242b) is self-aligned with respect to the opening of the insulator (280). That is, in the transistor (200A), the gate electrode can be self-aligned between the source electrode and the drain electrode. Therefore, since the conductor (260) can be formed without a margin of positional alignment, the occupied area of ​​the transistor (200A) can be reduced. This allows for an increase in the precision of the display device. In addition, the display device can be made with a slim bezel.

[0355] Additionally, as shown in FIG. 30, it is preferable that the conductor (260) has a conductor (260a) provided on the inside of the insulator (250) and a conductor (260b) provided to be embedded on the inside of the conductor (260a).

[0356] Additionally, the transistor (200A) preferably has an insulator (214) placed on a substrate (not shown), an insulator (216) placed on the insulator (214), a conductor (205) placed to be embedded in the insulator (216), an insulator (222) placed on the insulator (216) and the conductor (205), and an insulator (224) placed on the insulator (222). It is preferable that a metal oxide (230a) be placed on the insulator (224).

[0357] Additionally, it is preferable that an insulator (274) and an insulator (281) functioning as an interlayer film are disposed on the transistor (200A). Here, it is preferable that the insulator (274) be disposed in contact with the upper surface of the conductor (260), the insulator (250), the insulator (254), the metal oxide (230c), and the insulator (280).

[0358] Insulators (222), insulators (254), and insulators (274) preferably have a function of inhibiting the diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, insulators (222), insulators (254), and insulators (274) preferably have lower hydrogen permeability than insulators (224), insulators (250), and insulators (280). Additionally, insulators (222) and insulators (254) preferably have a function of inhibiting the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, insulators (222) and insulators (254) preferably have lower oxygen permeability than insulators (224), insulators (250), and insulators (280).

[0359] Here, the insulator (224), metal oxide (230), and insulator (250) are separated from the insulator (280) and insulator (281) by the insulator (254) and insulator (274). Therefore, impurities such as hydrogen or excess oxygen contained in the insulator (280) and insulator (281) can be prevented from being mixed into the insulator (224), metal oxide (230a), metal oxide (230b), and insulator (250).

[0360] Additionally, it is preferable to provide a conductor (240) (conductor (240a) and conductor (240b)) that is electrically connected to the transistor (200A) and functions as a plug. Additionally, an insulator (241) (insulator (241a) and insulator (241b)) is provided in contact with the side of the conductor (240) that functions as a plug. That is, an insulator (241) is provided in contact with the inner wall of the opening of the insulator (254), insulator (280), insulator (274), and insulator (281). Furthermore, it may be configured such that a first conductor of the conductor (240) is provided in contact with the side of the insulator (241), and a second conductor of the conductor (240) is provided inside it. Here, the height of the upper surface of the conductor (240) and the height of the upper surface of the insulator (281) can be made to be about the same. In addition, the transistor (200A) shows a configuration in which the first conductor and the second conductor of the conductor (240) are stacked, but the present invention is not limited thereto. For example, the conductor (240) may be provided as a single layer or as a stacked structure of three or more layers. When the structure has a stacked structure, it may be distinguished by assigning an ordinal number in the order of formation.

[0361] In addition, the transistor (200A) preferably uses a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor in a metal oxide (230) (metal oxide (230a), metal oxide (230b), and metal oxide (230c)) that includes a channel forming region. For example, as the metal oxide that becomes the channel forming region of the metal oxide (230), it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more.

[0362] It is preferable that the above metal oxide contains at least indium (In) or zinc (Zn). It is particularly preferable that it contains indium (In) and zinc (Zn). In addition to these, it is preferable that it contains element M. As element M, one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co) may be used. In particular, it is preferable that element M be one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn). Furthermore, it is more preferable that element M have either or both of Ga and Sn.

[0363] Additionally, as shown in (B) of FIG. 30, the film thickness of the metal oxide (230b) in the region that does not overlap with the conductor (242) may be thinner than the film thickness in the region that overlaps with the conductor (242). This is formed by removing a portion of the upper surface of the metal oxide (230b) when forming the conductor (242a) and the conductor (242b). On the upper surface of the metal oxide (230b), when a conductive film that becomes the conductor (242) is formed, a region of low resistance may be formed near the interface with said conductive film. In this way, by removing the region of low resistance located between the conductor (242a) and the conductor (242b) on the upper surface of the metal oxide (230b), it is possible to prevent the formation of a channel in said region.

[0364] According to one embodiment of the present invention, a display device having a small-sized transistor and high precision can be provided. Alternatively, a display device having a transistor with a large on-current and high brightness can be provided. Alternatively, a display device having a transistor with fast operation can be provided. Alternatively, a display device having a transistor with stable electrical characteristics and high reliability can be provided. Alternatively, a display device having a transistor with a small off-current and low power consumption can be provided.

[0365] A detailed configuration of a transistor (200A) that can be used in a display device, which is one form of the present invention, will be described.

[0366] The conductor (205) is positioned to have an overlapping area with the metal oxide (230) and the conductor (260). Additionally, it is preferable that the conductor (205) be provided embedded in the insulator (216). Here, it is desirable to ensure good flatness of the upper surface of the conductor (205). For example, it is preferable to make the average surface roughness (Ra) of the upper surface of the conductor (205) 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. By doing so, the flatness of the insulator (224) formed on the conductor (205) is improved, and the crystallinity of the metal oxide (230b) and the metal oxide (230c) can be enhanced.

[0367] Here, the conductor (260) may function as a first gate (also called a top gate) electrode. Additionally, the conductor (205) may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor (205) is changed independently without being linked to the potential applied to the conductor (260), thereby V of the transistor (200A) th It can be controlled. In particular, by applying a negative potential to the conductor (205), the V of the transistor (200A) thBy making it greater than 0V, the off-current can be reduced. Therefore, when a negative potential is applied to the conductor (205), the drain current when the potential applied to the conductor (260) is 0V can be made smaller than when it is not applied.

[0368] Additionally, it is preferable to provide the conductor (205) larger than the channel-forming region in the metal oxide (230). In particular, as shown in (C) of FIG. 30, it is preferable that the conductor (205) extends outward from the end of the metal oxide (230) that intersects the channel width direction. That is, it is preferable that the conductor (205) and the conductor (260) overlap with an insulator on the outer side of the metal oxide (230) in the channel width direction.

[0369] By having the above configuration, the channel forming region of the metal oxide (230) can be electrically surrounded by the electric field of the conductor (260) which functions as the first gate electrode and the electric field of the conductor (205) which functions as the second gate electrode.

[0370] In addition, as shown in (C) of FIG. 30, the conductor (205) is extended to function as wiring. However, it is not limited to this, and a configuration may be provided that provides a conductor functioning as wiring below the conductor (205).

[0371] In addition, it is preferable to use a conductive material with tungsten, copper, or aluminum as the main component for the conductor (205). Also, although the conductor (205) is shown as a single layer, it may be made of a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material.

[0372] In addition, a conductor having a function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult to permeate the said impurities) may be used below the conductor (205). Alternatively, it is preferable to use a conductor having a function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult to permeate the said oxygen). Furthermore, in this specification, the function of inhibiting the diffusion of impurities or oxygen is defined as a function of inhibiting the diffusion of either or both of the said impurities and the said oxygen.

[0373] By providing a conductor having a function of inhibiting oxygen diffusion below the conductor (205), the conductor (205) can be prevented from oxidizing and the conductivity decreasing. As a conductor having a function of inhibiting oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Accordingly, as the first conductor of the conductor (205), it is preferable to form the above conductive material as a single layer or a stack.

[0374] It is preferable that the insulator (214) functions as a barrier insulating film that suppresses the ingress of impurities, such as water or hydrogen, from the substrate side into the transistor (200A). Accordingly, it is preferable to use an insulating material in the insulator (214) that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult to permeate the said impurities). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (making it difficult to permeate the said oxygen).

[0375] For example, it is preferable to use aluminum oxide or silicon nitride, etc., as the insulator (214). By doing so, the diffusion of impurities such as water or hydrogen from the substrate side to the transistor (200A) side relative to the insulator (214) can be suppressed. Alternatively, the diffusion of oxygen contained in the insulator (224), etc., to the substrate side relative to the insulator (214) can be suppressed.

[0376] In addition, it is preferable that the insulator (216), insulator (280), and insulator (281) functioning as interlayer films have a lower dielectric constant than the insulator (214). By using a material with a lower dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator (216), insulator (280), and insulator (281), silicon oxide, silicon nitride oxide, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide having pores, etc., may be appropriately used.

[0377] The insulator (222) and the insulator (224) function as gate insulators.

[0378] Here, it is preferable that the insulator (224) in contact with the metal oxide (230) has oxygen removed by heating. In this specification, oxygen removed by heating may be referred to as excess oxygen. For example, silicon oxide or silicon nitride, etc., may be appropriately used for the insulator (224). By providing an insulator containing oxygen in contact with the metal oxide (230), the oxygen deficiency within the metal oxide (230) can be reduced, thereby improving the reliability of the transistor (200A).

[0379] Specifically, it is preferable to use an oxide material as an insulator (224) from which some oxygen is released upon heating. An oxide from which oxygen is released upon heating is one in which the amount of oxygen released, converted into oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis, is 1.0 x 10 18 atoms / cm 3 Ideally, 1.0X10 19 atoms / cm 3 Ideally, more preferably 2.0X10 19 atoms / cm 3 Above, or 3.0X10 20 atoms / cm 3 The above is an oxide film. In addition, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0380] Additionally, as shown in (C) of FIG. 30, the film thickness of the region of the insulator (224) that does not overlap with the insulator (254) and does not overlap with the metal oxide (230b) may be thinner than the film thickness of the region other than this. It is preferable that the film thickness of the region of the insulator (224) that does not overlap with the insulator (254) and does not overlap with the metal oxide (230b) be a film thickness that can sufficiently diffuse the oxygen.

[0381] It is preferable that the insulator (222), like the insulator (214), functions as a barrier insulating film to suppress the ingress of impurities such as water or hydrogen from the substrate side into the transistor (200A). For example, it is preferable that the insulator (222) has lower hydrogen permeability than the insulator (224). By surrounding the insulator (224), metal oxide (230), and insulator (250), etc., with the insulator (222), insulator (254), and insulator (274), it is possible to suppress the ingress of impurities such as water or hydrogen from the outside into the transistor (200A).

[0382] Additionally, it is preferable that the insulator (222) has a function of inhibiting the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (making it difficult to permeate the oxygen). For example, it is preferable that the insulator (222) has lower oxygen permeability than the insulator (224). This is preferable because the insulator (222) has a function of inhibiting the diffusion of oxygen or impurities, thereby reducing the diffusion of oxygen from the metal oxide (230) toward the substrate. Additionally, it is possible to inhibit the reaction of the conductor (205) with the oxygen from the insulator (224) or the metal oxide (230).

[0383] For the insulator (222), it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, which are insulating materials. As an insulator containing an oxide of either or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator (222) is formed using such a material, the insulator (222) functions as a layer that suppresses the release of oxygen from the metal oxide (230) or the incorporation of impurities such as hydrogen from the periphery of the transistor (200A) into the metal oxide (230).

[0384] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators, for example. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride oxide, or silicon nitride may be laminated and used with the insulators.

[0385] In addition, as an insulator (222), an insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) may be used in a single layer or stacked manner. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0386] In addition, the insulator (222) and the insulator (224) may have a stacked structure of two or more layers. In that case, the stacked structure is not limited to a stacked structure made of the same material, but may be a stacked structure made of different materials. For example, it may be configured to provide an insulator such as the insulator (224) below the insulator (222).

[0387] The metal oxide (230) has a metal oxide (230a), a metal oxide (230b) above the metal oxide (230a), and a metal oxide (230c) above the metal oxide (230b). By having the metal oxide (230a) below the metal oxide (230b), the diffusion of impurities from a structure formed below the metal oxide (230a) to the metal oxide (230b) can be suppressed. Additionally, by having the metal oxide (230c) above the metal oxide (230b), the diffusion of impurities from a structure formed above the metal oxide (230c) to the metal oxide (230b) can be suppressed.

[0388] Additionally, it is preferable that the metal oxide (230) has a stacked structure consisting of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide (230) contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in the metal oxide (230a) to the total number of atoms of the elements constituting the metal oxide (230a) is higher than the ratio of the number of atoms of element M contained in the metal oxide (230b) to the total number of atoms of the elements constituting the metal oxide (230b). Additionally, it is preferable that the atomic ratio of element M contained in the metal oxide (230a) to In is greater than the atomic ratio of element M contained in the metal oxide (230b) to In. Here, as the metal oxide (230c), a metal oxide that can be used for the metal oxide (230a) or the metal oxide (230b) may be used.

[0389] In addition, it is desirable that the energy at the bottom of the conduction band of the metal oxide (230a) and the metal oxide (230c) be higher than the energy at the bottom of the conduction band of the metal oxide (230b). In other words, it is desirable that the electron affinity of the metal oxide (230a) and the metal oxide (230c) be smaller than the electron affinity of the metal oxide (230b). In this case, it is desirable to use a metal oxide that can be used for the metal oxide (230a) as the metal oxide (230c). Specifically, it is desirable that the ratio of the number of atoms of element M included in the metal oxide (230c) to the total number of atoms of the elements constituting the metal oxide (230c) is higher than the ratio of the number of atoms of element M included in the metal oxide (230b) to the total number of atoms of the elements constituting the metal oxide (230b). In addition, it is desirable that the ratio of the number of atoms of element M included in the metal oxide (230c) to In is greater than the ratio of the number of atoms of element M included in the metal oxide (230b) to In.

[0390] Here, the energy level at the bottom of the conduction band at the junction of the metal oxide (230a), metal oxide (230b), and metal oxide (230c) changes gradually. In other words, the energy level at the bottom of the conduction band at the junction of the metal oxide (230a), metal oxide (230b), and metal oxide (230c) can be said to change continuously or be continuous. To do this, it is preferable to lower the defect level density of the mixed layer formed at the interface between the metal oxide (230a) and the metal oxide (230b) and at the interface between the metal oxide (230b) and the metal oxide (230c).

[0391] Specifically, a mixed layer with a low defect level density can be formed by having a common element other than oxygen (by making it the main component) between the metal oxide (230a) and the metal oxide (230b), and between the metal oxide (230b) and the metal oxide (230c). For example, if the metal oxide (230b) is an In-Ga-Zn oxide, the In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., may be used as the metal oxide (230a) and the metal oxide (230c). Additionally, the metal oxide (230c) may be in a stacked structure. For example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on top of the In-Ga-Zn oxide, or a stacked structure of an In-Ga-Zn oxide and a gallium oxide on top of the In-Ga-Zn oxide may be used. In other words, a stacked structure of an In-Ga-Zn oxide and an oxide that does not contain In may be used as the metal oxide (230c).

[0392] Specifically, as the metal oxide (230a), it is preferable to use a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5. Additionally, as the metal oxide (230b), it is preferable to use a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2. Additionally, as the metal oxide (230c), it is preferable to use a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5. In addition, specific examples of cases where metal oxides (230c) are used as a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0393] At this time, the main path of the carrier is the metal oxide (230b). By configuring the metal oxide (230a) and the metal oxide (230c) as described above, the defect level density at the interface between the metal oxide (230a) and the metal oxide (230b) and at the interface between the metal oxide (230b) and the metal oxide (230c) can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor (200A) can obtain high on-current and high frequency characteristics. In addition, when the metal oxide (230c) is in a stacked structure, in addition to the effect of reducing the defect level density at the interface between the metal oxide (230b) and the metal oxide (230c) described above, it is expected that the diffusion of the constituent elements of the metal oxide (230c) toward the insulator (250) is suppressed. More specifically, the metal oxide (230c) is formed into a stacked structure, and an oxide that does not contain In is placed on top of the stacked structure, thereby suppressing In that can diffuse toward the insulator (250). Since the insulator (250) functions as a gate insulator, if In diffuses, it results in a defect in the transistor's characteristics. Therefore, by forming the metal oxide (230c) into a stacked structure, a highly reliable display device can be provided.

[0394] A conductor (242) (conductor (242a) and conductor (242b)) that functions as a source electrode and a drain electrode is provided on the metal oxide (230b). As the conductor (242), it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy having the above-mentioned metal element as a component or an alloy combining the above-mentioned metal element. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0395] By providing the conductor (242) to come into contact with the metal oxide (230), the oxygen concentration may be reduced in the vicinity of the conductor (242) of the metal oxide (230). Additionally, a metal compound layer containing the metal included in the conductor (242) and the components of the metal oxide (230) may be formed in the vicinity of the conductor (242) of the metal oxide (230). In such cases, the carrier density increases in the region near the conductor (242) of the metal oxide (230), and the region becomes a low-resistance region.

[0396] Here, the region between the conductor (242a) and the conductor (242b) is formed by overlapping the opening of the insulator (280). By doing so, the conductor (260) can be self-aligned between the conductor (242a) and the conductor (242b).

[0397] The insulator (250) functions as a gate insulator. It is preferable that the insulator (250) be placed in contact with the upper surface of the metal oxide (230c). For the insulator (250), silicon oxide, silicon nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide having vacancies may be used. In particular, silicon oxide and silicon nitride are preferred because they are stable against heat.

[0398] It is preferable that the insulator (250), like the insulator (224), has a reduced concentration of impurities such as water or hydrogen within the insulator (250). It is preferable that the film thickness of the insulator (250) be 1 nm or more and 20 nm or less.

[0399] Additionally, a metal oxide may be provided between the insulator (250) and the conductor (260). It is desirable that the metal oxide inhibits the diffusion of oxygen from the insulator (250) to the conductor (260). This prevents oxidation of the conductor (260) caused by oxygen from the insulator (250).

[0400] In addition, the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon nitride is used in the insulator (250), it is preferable to use a metal oxide that is a high-k material with a high dielectric constant for the metal oxide. By making the gate insulator a stacked structure of the insulator (250) and the metal oxide, a stacked structure that is stable against heat and has a high dielectric constant can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness of the gate insulator. In addition, the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

[0401] Specifically, metal oxides containing one or more types selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium may be used. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0402] The conductor (260) is shown as a two-layer structure in FIG. 30, but it may be a single-layer structure or a stacked structure of three or more layers.

[0403] It is preferable to use a conductor (260a) having a function to inhibit the diffusion of impurities such as the aforementioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material having a function to inhibit the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.).

[0404] In addition, since the conductor (260a) has the function of inhibiting the diffusion of oxygen, it is possible to prevent the conductor (260b) from being oxidized and the conductivity from decreasing due to oxygen contained in the insulator (250). As a conductive material having the function of inhibiting the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0405] In addition, it is preferable to use a conductive material with tungsten, copper, or aluminum as the main component for the conductor (260b). Also, since the conductor (260) also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material with tungsten, copper, or aluminum as the main component may be used. In addition, the conductor (260b) may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

[0406] In addition, as shown in (A) and (C) of FIG. 30, the metal oxide (230b) is arranged so that the side of the metal oxide (230) is covered by the conductor (260) in the region that does not overlap with the conductor (242), in other words, in the channel-forming region of the metal oxide (230). This makes it easier to apply the electric field of the conductor (260), which functions as the first gate electrode, to the side of the metal oxide (230). Thus, the on-current of the transistor (200A) can be increased to improve the frequency characteristics.

[0407] It is preferable that the insulator (254), like the insulator (214), functions as a barrier insulating film to suppress the ingress of impurities such as water or hydrogen from the insulator (280) into the transistor (200A). For example, it is preferable that the insulator (254) has lower hydrogen permeability than the insulator (224). In addition, as shown in (B) and (C) of FIG. 30, it is preferable that the insulator (254) is in contact with the side of the metal oxide (230c), the upper and side surfaces of the conductor (242a), the upper and side surfaces of the conductor (242b), the side surfaces of the metal oxide (230a) and the metal oxide (230b), and the upper surface of the insulator (224). By configuring it in this way, hydrogen contained in the insulator (280) can be prevented from penetrating into the metal oxide (230) from the upper or side surface of the conductor (242a), conductor (242b), metal oxide (230a), metal oxide (230b), and insulator (224).

[0408] Additionally, it is preferable that the insulator (254) has the function of inhibiting the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (making it difficult to permeate the oxygen). For example, it is preferable that the insulator (254) has lower oxygen permeability than the insulator (280) or the insulator (224).

[0409] It is preferable that the insulator (254) be formed using a sputtering method. By forming the insulator (254) using a sputtering method in an atmosphere containing oxygen, oxygen can be added to the region in contact with the insulator (254) from the insulator (224). This allows oxygen to be supplied into the metal oxide (230) through the insulator (224) from the said region. Here, the insulator (254) has a function of suppressing the diffusion of oxygen upward, thereby preventing oxygen from diffusing from the metal oxide (230) to the insulator (280). Additionally, the insulator (222) has a function of suppressing the diffusion of oxygen downward, thereby preventing oxygen from diffusing from the metal oxide (230) to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide (230). This reduces the oxygen deficiency of the metal oxide (230), thereby suppressing normalization of the transistor.

[0410] As for the insulator (254), it is preferable to form an insulator containing, for example, an oxide of one or both of aluminum and hafnium. Additionally, as an insulator containing one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0411] By covering the insulator (224), the insulator (250), and the metal oxide (230) with an insulator (254) that has barrier properties against hydrogen, the insulator (280) is separated from the insulator (224), the metal oxide (230), and the insulator (250) by the insulator (254). As a result, since the intrusion of impurities such as hydrogen from the outside of the transistor (200A) can be suppressed, good electrical characteristics and reliability can be imparted to the transistor (200A).

[0412] An insulator (280) is provided over an insulator (224), a metal oxide (230), and a conductor (242) via an insulator (254). For example, as the insulator (280), it is preferable to have silicon oxide, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide having vacancies. In particular, silicon oxide and silicon nitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon nitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0413] It is preferable that the concentration of impurities, such as water or hydrogen, within the insulator (280) be reduced. Additionally, the upper surface of the insulator (280) may be flattened.

[0414] It is preferable that the insulator (274), like the insulator (214), function as a barrier insulating film to prevent impurities such as water or hydrogen from being mixed into the insulator (280) from the top. For the insulator (274), it is preferable to use an insulator that can be used, for example, the insulator (214), the insulator (254), etc.

[0415] In addition, it is desirable to provide an insulator (281) that functions as an interlayer film on the insulator (274). It is desirable that the insulator (281), like the insulator (224), has a reduced concentration of impurities such as water or hydrogen within the film.

[0416] Additionally, a conductor (240a) and a conductor (240b) are placed in an opening formed in the insulator (281), insulator (274), insulator (280), and insulator (254). The conductor (240a) and the conductor (240b) are provided facing each other with the conductor (260) interposed. Additionally, the height of the upper surface of the conductor (240a) and the conductor (240b) may be flat to the upper surface of the insulator (281).

[0417] Additionally, an insulator (241a) is provided in contact with the inner wall of the opening of the insulator (281), insulator (274), insulator (280), and insulator (254), and a first conductor (240a) is formed in contact with the side thereof. A conductor (242a) is located in at least a portion of the bottom of the opening, and the conductor (240a) is in contact with the conductor (242a). Likewise, an insulator (241b) is provided in contact with the inner wall of the opening of the insulator (281), insulator (274), insulator (280), and insulator (254), and a first conductor (240b) is formed in contact with the side thereof. A conductor (242b) is located in at least a portion of the bottom of the opening, and the conductor (240b) is in contact with the conductor (242b).

[0418] It is preferable to use a conductive material with tungsten, copper, or aluminum as the main component for the conductor (240a) and the conductor (240b). Additionally, the conductor (240a) and the conductor (240b) may have a laminated structure.

[0419] In addition, when the conductor (240) is in a laminated structure, it is preferable to use a conductor that has the function of suppressing the diffusion of impurities such as water or hydrogen as described above in the conductor in contact with the metal oxide (230a), metal oxide (230b), conductor (242), insulator (254), insulator (280), insulator (274), and insulator (281). For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. In addition, the conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a laminated structure. By using the above conductive material, it is possible to prevent oxygen added to the insulator (280) from being absorbed by the conductor (240a) and the conductor (240b). In addition, it is possible to prevent impurities such as water or hydrogen from the layer above the insulator (281) from being mixed into the metal oxide (230) through the conductor (240a) and the conductor (240b).

[0420] As for the insulator (241a) and insulator (241b), it is preferable to use an insulator that can be used, for example, insulator (254). Since the insulator (241a) and insulator (241b) are provided in contact with the insulator (254), it is possible to suppress the incorporation of impurities such as water or hydrogen from the insulator (280) into the metal oxide (230) through the conductor (240a) and conductor (240b). In addition, it is possible to prevent oxygen contained in the insulator (280) from being absorbed into the conductor (240a) and conductor (240b).

[0421] Additionally, although not shown, a conductor functioning as wiring may be placed in contact with the upper surface of the conductor (240a) and the upper surface of the conductor (240b). It is preferable to use a conductive material with tungsten, copper, or aluminum as the main component for the conductor functioning as wiring. Furthermore, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductor may be formed to be embedded in an opening provided in the insulator.

[0422] <Transistor Configuration Example 2>

[0423] Figures 31 (A), (B), and (C) are a top view and a cross-sectional view of a transistor (200B) and a portion of the transistor (200B) that can be used in a display device which is one embodiment of the present invention. The transistor (200B) is a modified example of the transistor (200A).

[0424] FIG. 31 (A) is a top view of a transistor (200B). FIG. 31 (B) and (C) are cross-sectional views of the transistor (200B). Here, FIG. 31 (B) is a cross-sectional view of the portion indicated by the dotted line B1-B2 in FIG. 31 (A), and is also a cross-sectional view in the channel length direction of the transistor (200B). FIG. 31 (C) is a cross-sectional view of the portion indicated by the dotted line B3-B4 in FIG. 31 (A), and is also a cross-sectional view in the channel width direction of the transistor (200B). Additionally, in the top view of FIG. 31 (A), some elements have been omitted for clarity of the drawing.

[0425] In the transistor (200B), the conductor (242a) and the conductor (242b) have a region that overlaps with the metal oxide (230c), the insulator (250), and the conductor (260). By doing so, the transistor (200B) can be a transistor with a high on-current. Additionally, the transistor (200B) can be a transistor that is easy to control.

[0426] A conductor (260) functioning as a gate electrode has a conductor (260a) and a conductor (260b) on the conductor (260a). It is preferable to use a conductive material in the conductor (260a) that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0427] By having the conductor (260a) have the function of inhibiting the diffusion of oxygen, the material selectivity of the conductor (260b) can be improved. That is, by having the conductor (260a), the oxidation of the conductor (260b) is inhibited, thereby preventing a decrease in conductivity.

[0428] Additionally, it is preferable to provide an insulator (254) to cover the upper and side surfaces of the conductor (260), the side surface of the insulator (250), and the side surface of the metal oxide (230c). Additionally, it is preferable to use an insulating material for the insulator (254) that has the function of inhibiting the diffusion of impurities such as water or hydrogen and oxygen.

[0429] By providing an insulator (254), oxidation of the conductor (260) can be suppressed. Additionally, by having an insulator (254), impurities such as water and hydrogen in the insulator (280) can be suppressed from diffusing into the transistor (200B).

[0430] <Transistor Configuration Example 3>

[0431] Figures 32 (A), (B), and (C) are a top view and a cross-sectional view of a transistor (200C) and a portion of the transistor (200C) that can be used in a display device which is one form of the present invention. The transistor (200C) is a modified example of the transistor (200A).

[0432] FIG. 32 (A) is a top view of a transistor (200C). FIG. 32 (B) and (C) are cross-sectional views of a transistor (200C). Here, FIG. 32 (B) is a cross-sectional view of the portion indicated by the dotted line C1-C2 in FIG. 32 (A), and is also a cross-sectional view in the channel length direction of the transistor (200C). FIG. 32 (C) is a cross-sectional view of the portion indicated by the dotted line C3-C4 in FIG. 32 (A), and is also a cross-sectional view in the channel width direction of the transistor (200C). Additionally, in the top view of FIG. 32 (A), some elements have been omitted for clarity of the drawing.

[0433] The transistor (200C) has an insulator (250) on a metal oxide (230c) and a metal oxide (252) on the insulator (250). It also has a conductor (260) on the metal oxide (252) and an insulator (270) on the conductor (260). It also has an insulator (271) on the insulator (270).

[0434] It is desirable for the metal oxide (252) to have a function of inhibiting oxygen diffusion. By providing a metal oxide (252) that inhibits the diffusion of oxygen between the insulator (250) and the conductor (260), the diffusion of oxygen into the conductor (260) is inhibited. That is, the reduction in the amount of oxygen supplied to the metal oxide (230) can be inhibited. In addition, oxidation of the conductor (260) due to oxygen can be inhibited.

[0435] Additionally, the metal oxide (252) may function as part of the gate electrode. For example, an oxide semiconductor that can be used as a metal oxide (230) can be used as the metal oxide (252). In this case, the electrical resistance value of the metal oxide (252) can be lowered by depositing the conductor (260) by a sputtering method, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0436] In addition, the metal oxide (252) may function as part of the gate insulator. Therefore, when using silicon oxide or silicon nitride, etc., for the insulator (250), it is preferable to use a metal oxide that is a high-k material with a high dielectric constant for the metal oxide (252). By making the above stacked structure, a stacked structure that is stable against heat and has a high dielectric constant can be made. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness. In addition, the equivalent oxide film thickness (EOT) of the insulating layer functioning as a gate insulator can be reduced.

[0437] Although the metal oxide (252) in the transistor (200C) is shown as a single layer, it may be made into a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulator may be provided by stacking them.

[0438] By having a metal oxide (252), when functioning as a gate electrode, the on-current of the transistor (200C) can be improved without reducing the influence of the electric field from the conductor (260). Alternatively, when functioning as a gate insulator, leakage current between the conductor (260) and the metal oxide (230) can be suppressed by maintaining the distance between the conductor (260) and the metal oxide (230) through the physical thickness of the insulator (250) and the metal oxide (252). Therefore, by providing a stacked structure of the insulator (250) and the metal oxide (252), the physical distance between the conductor (260) and the metal oxide (230) and the electric field strength applied from the conductor (260) to the metal oxide (230) can be easily adjusted.

[0439] Specifically, as a metal oxide (252), a low-resistance oxide semiconductor that can be used for metal oxide (230) may be used. Alternatively, a metal oxide containing one or more types selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium may be used.

[0440] In particular, it is preferable to use an insulating layer containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize during heat treatment in subsequent processes. Also, the metal oxide (252) is not an essential component. It is good to design it appropriately according to the required transistor characteristics.

[0441] It is preferable to use an insulating material for the insulator (270) that has the function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, it is desirable to use aluminum oxide or hafnium oxide. By doing so, the oxidation of the conductor (260) due to oxygen from above the insulator (270) can be suppressed. In addition, it is possible to suppress the ingress of impurities such as water or hydrogen into the metal oxide (230) through the conductor (260) and the insulator (250) from above the insulator (270).

[0442] The insulator (271) functions as a hard mask. By providing the insulator (271), when processing the conductor (260), the side of the conductor (260) can be made substantially vertical, specifically, the angle formed between the side of the conductor (260) and the substrate surface can be made to be 75° or more and 100° or less, preferably 80° or more and 95° or less.

[0443] Additionally, by using an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen and oxygen in the insulator (271), it may also function as a barrier layer. In this case, the insulator (270) does not need to be provided.

[0444] By using an insulator (271) as a hard mask to selectively remove parts of the insulator (270), conductor (260), metal oxide (252), insulator (250), and metal oxide (230c), the sides thereof can be substantially matched and parts of the surface of the metal oxide (230b) can be exposed.

[0445] Additionally, the transistor (200C) has regions (243a) and (243b) on a portion of the surface of the exposed metal oxide (230b). One of the regions (243a) and (243b) functions as a source region, and the other of the regions (243a) and (243b) functions as a drain region.

[0446] The formation of regions (243a) and (243b) can be realized by introducing impurity elements such as phosphorus or boron onto the surface of the exposed metal oxide (230b) using, for example, ion implantation, ion doping, plasma infiltration ion implantation, or plasma treatment. In addition, in this embodiment, "impurity element" refers to an element other than the main component element.

[0447] Additionally, by exposing a portion of the surface of the metal oxide (230b) and then forming a metal film, and subsequently performing a heat treatment, the elements contained in the metal film can be diffused into the metal oxide (230b) to form regions (243a) and (243b).

[0448] The region where impurity elements of the metal oxide (230b) are introduced has a lower electrical resistivity. Therefore, regions (243a) and (243b) are sometimes referred to as 'impurity regions' or 'low-resistance regions'.

[0449] By using an insulator (271) and / or a conductor (260) as a mask, regions (243a) and (243b) can be formed self-aligned. Thus, regions (243a) and / or regions (243b) and the conductor (260) do not overlap, thereby reducing parasitic capacitance. Additionally, no offset region is formed between the channel forming region and the source-drain region (region (243a) or region (243b)). By forming regions (243a) and (243b) self-aligned, an increase in on-current, a reduction in threshold voltage, and an improvement in operating frequency can be realized.

[0450] The transistor (200C) has an insulator (271), an insulator (270), a conductor (260), a metal oxide (252), an insulator (250), and an insulator (272) on the side of the metal oxide (230c). It is preferable that the insulator (272) be an insulator with a low dielectric constant. For example, it is preferable that it be silicon oxide, silicon nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or a resin. In particular, it is preferable to use silicon oxide, silicon nitride, silicon nitride, or silicon oxide with vacancies as the insulator (272) because an excess oxygen region can be easily formed within the insulator (272) in a subsequent process. Also, silicon oxide and silicon nitride are preferable because they are thermally stable. Additionally, it is preferable that the insulator (272) have a function of diffusing oxygen.

[0451] Additionally, to further reduce the off-current, an offset region may be provided between the channel formation region and the source-drain region. An offset region is a region with high electrical resistivity where the introduction of the aforementioned impurity element is not performed. The formation of the offset region can be realized by performing the introduction of the aforementioned impurity element after the formation of the insulator (272). In this case, the insulator (272) also functions as a mask, just like the insulator (271), etc. Therefore, in the region of the metal oxide (230b) that overlaps with the insulator (272), no impurity element is introduced, so the electrical resistivity of the said region can be maintained at a high level.

[0452] Additionally, the transistor (200C) has an insulator (254) on an insulator (272) and a metal oxide (230). It is preferable that the insulator (254) be formed using a sputtering method. By using a sputtering method, an insulator with low impurity content, such as water or hydrogen, can be formed.

[0453] Additionally, an oxide film formed by sputtering may extract hydrogen from the film structure. Therefore, the hydrogen concentration of the metal oxide (230) and the insulator (272) can be reduced by the insulator (254) absorbing hydrogen and water from the metal oxide (230) and the insulator (272).

[0454] <Constituent materials of a transistor>

[0455] This explains the constituent materials that can be used in transistors.

[0456] [Circuit board]

[0457] As a substrate for forming the transistor (200A), transistor (200B), or transistor (200C), it is preferable to use, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Additionally, examples of semiconductor substrates include semiconductor substrates made of silicon, germanium, etc., or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Additionally, there are semiconductor substrates having an insulating region within the semiconductor substrates described above, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or substrates having metal oxides. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, devices provided on these substrates may be used. Devices provided on the substrates include capacitive elements, resistive elements, switching elements, light-emitting elements, memory elements, etc.

[0458] [Insulator]

[0459] Insulators include oxides, nitrides, nitride oxides, nitrate oxides, metal oxides, metal nitride oxides, and metal nitrate oxides that possess insulating properties.

[0460] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may arise due to the thinning of the gate insulator. By using high-k materials for the insulator functioning as the gate insulator, the voltage during transistor operation can be lowered while maintaining the physical film thickness. On the other hand, by using materials with a low relative permittivity for the insulator functioning as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select materials based on the function of the insulator.

[0461] In addition, insulators with high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0462] In addition, insulators with low dielectric constant include silicon oxide, silicon nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide having vacancies, or resins.

[0463] In addition, the electrical characteristics of the transistor can be stabilized by surrounding the transistor using an oxide semiconductor with an insulator (insulator (214), insulator (222), insulator (254), and insulator (274), etc.) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or in a stack. Specifically, as an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon nitride, or silicon nitride can be used.

[0464] Additionally, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by making the silicon oxide or silicon nitride having a region containing oxygen that is released by heating into contact with the metal oxide (230), the oxygen deficiency of the metal oxide (230) can be compensated.

[0465] [Challenge]

[0466] As a conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy having the above-mentioned metal element as a component or an alloy combining the above-mentioned metal element. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0467] In addition, multiple layers of conductors formed from the above materials may be used. For example, a laminated structure may be formed by combining a material containing the metal element described above with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the metal element described above with a conductive material containing nitrogen. Furthermore, a laminated structure may be formed by combining a material containing the metal element described above with a conductive material containing oxygen and a conductive material containing nitrogen.

[0468] In addition, when a metal oxide is used in the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined for the conductor functioning as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material becomes easier to supply to the channel formation region.

[0469] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide where the channel is formed. Additionally, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Additionally, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen included in the metal oxide where the channel is formed. Alternatively, it may be possible to capture hydrogen introduced from an external insulator, etc.

[0470] The configuration examples and corresponding drawings, etc. exemplified in this embodiment may be implemented by appropriately combining at least a part thereof with other configuration examples or drawings, etc.

[0471] This embodiment may be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0472] (Embodiment 3)

[0473] In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used in the OS transistor described in the previous embodiment is described.

[0474] Classification of Crystal Structures

[0475] First, the classification of crystal structures in oxide semiconductors will be explained using Figure 33 (A). Figure 33 (A) is a diagram illustrating the classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0476] As shown in Fig. 33 (A), oxide semiconductors are broadly classified into 'Amorphous', 'Crystalline', and 'Crystal'. The 'Amorphous' category includes completely amorphous. The 'Crystalline' category includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). Additionally, single crystal, polycrystalline, and completely amorphous are excluded from the 'Crystalline' classification. Furthermore, the 'Crystal' category includes single crystal and polycrystalline.

[0477] In addition, the structure within the thick border shown in Fig. 33 (A) is an intermediate state between 'Amorphous' and 'Crystal' and belongs to a new boundary region (New crystalline phase). That is, the structure can be said to be completely different from the energetically unstable 'Amorphous' or 'Crystal'.

[0478] In addition, the crystal structure of the film or substrate can be evaluated using X-ray diffraction (XRD) spectra. Here, the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as 'Crystalline' is shown in Fig. 33 (B). The GIXD method is also known as the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 33 (B) will be referred to simply as the XRD spectrum. Furthermore, the composition of the CAAC-IGZO film shown in Fig. 33 (B) is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 33 (B) is 500 nm.

[0479] As shown in Fig. 33 (B), a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Additionally, as shown in Fig. 33 (B), the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity was detected.

[0480] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 33 (C). Fig. 33 (C) shows the diffraction pattern observed by NBED in which an electron beam is incident parallel to the substrate. In addition, the composition of the CAAC-IGZO film shown in Fig. 33 (C) is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, in nano-beam electron diffraction, electron beam diffraction is performed with a probe diameter of 1 nm.

[0481] As shown in (C) of Fig. 33, multiple spots exhibiting c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0482] [Structure of Oxide Semiconductors]

[0483] In addition, oxide semiconductors may be classified differently from (A) in FIG. 33 when focusing on their crystal structure. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Furthermore, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), amorphous oxide semiconductors, etc.

[0484] Here, the aforementioned CAAC-OS, nc-OS, and a-like OS are explained in detail.

[0485] [CAAC-OS]

[0486] CAAC-OS is an oxide semiconductor having multiple crystal regions, wherein the multiple crystal regions are oriented in a specific direction along the c-axis. Furthermore, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. Additionally, a crystal region is a region that exhibits periodicity in its atomic arrangement. Furthermore, if the atomic arrangement is considered as a lattice arrangement, the crystal region is also a region where the lattice arrangement is aligned. Furthermore, CAAC-OS has a region where multiple crystal regions are connected in the direction of the ab plane, and this region may exhibit deformation. Deformation refers to a part within the region where multiple crystal regions are connected where the direction of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned. In other words, CAAC-OS is an oxide semiconductor that has a c-axis orientation and does not have a clear orientation in the direction of the ab plane.

[0487] In addition, each of the above-mentioned multiple crystal regions is composed of one or more microcrystalline crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of a single microcrystalline crystal, the maximum diameter of the crystal region is less than 10 nm. In addition, when a crystal region is composed of multiple microcrystalline crystals, the size of the crystal region may be approximately tens of nm.

[0488] In addition, in In-M-Zn oxide (where element M is one or more types selected from aluminum, gallium, yttrium, tin, and titanium), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M, Zn) layer) are stacked. In addition, indium and element M can be substituted for each other. Therefore, indium may be included in the (M, Zn) layer. In addition, element M may be included in the In layer. In addition, Zn may be included in the In layer. The above layered structure is observed as a lattice structure, for example, in a high-resolution TEM image.

[0489] For example, when performing structural analysis of a CAAC-OS film using an XRD device, in out-of-plane XRD measurements using θ / 2θ scans, a peak indicating c-axis orientation is detected at 2θ = 31° or nearby. In addition, the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0490] In addition, for example, multiple spots are observed in the electron beam diffraction pattern of a CAAC-OS film. Furthermore, some spots and other spots are observed at point-symmetric positions with the spot of the incident electron beam that has passed through the sample (also called the direct spot) as the center of symmetry.

[0491] When observing the crystal region from the aforementioned specific direction, the lattice arrangement within the crystal region is fundamentally a hexagonal lattice; however, the unit cell is not limited to a regular hexagon but may be non-regular hexagonal. Furthermore, the deformation may result in lattice arrangements such as pentagons or heptagons. Additionally, in CAAC-OS, clear grain boundaries cannot be observed even near deformation. In other words, it can be seen that the formation of grain boundaries is suppressed by the deformation of the lattice arrangement. This is thought to be because CAAC-OS allows for deformation due to factors such as the arrangement of oxygen atoms in the ab plane being less dense, or changes in the bond distance between atoms resulting from the substitution of metal atoms.

[0492] Furthermore, crystal structures in which distinct grain boundaries are observed are referred to as so-called polycrystalline structures. Grain boundaries act as recombination centers, and carrier trapping is highly likely to cause a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which distinct grain boundaries are not observed, is a type of crystalline oxide with a crystal structure suitable for the semiconductor layer of a transistor. Additionally, to construct CAAC-OS, a composition including Zn is desirable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the formation of grain boundaries more effectively than In oxide.

[0493] CAAC-OS is an oxide semiconductor with high crystallinity in which distinct grain boundaries are not observed. Therefore, it can be said that the degradation of electron mobility caused by grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be degraded by the incorporation of impurities or the formation of defects, CAAC-OS can be described as an oxide semiconductor with low levels of impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and highly reliable. Additionally, CAAC-OS remains stable even under high temperatures (so-called thermal budget) during the manufacturing process. Thus, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0494] [nc-OS]

[0495] nc-OS exhibits periodicity in its atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS possesses microcrystalline structures. Furthermore, since the size of these microcrystalline structures is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm, they are also referred to as nanocrystalline structures. Additionally, in nc-OS, no regularity in crystal orientation is observed between different nanocrystalline structures. Consequently, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from α-like OS or amorphous oxide semiconductors. For example, when performing structural analysis of an nc-OS film using an XRD device, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scans. In addition, when electron beam diffraction (also called limited-field electron beam diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also called nano-beam electron beam diffraction) is performed on an nc-OS film using an electron beam with a probe diameter that is close to or smaller than that of a nanocrystal (e.g., 1 nm or more and 30 nm or less), an electron beam diffraction pattern is obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0496] [a-like OS]

[0497] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS possesses voids or low-density regions. In other words, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Additionally, a-like OS has a higher hydrogen concentration within the film compared to nc-OS and CAAC-OS.

[0498] [Composition of Oxide Semiconductors]

[0499] Next, the aforementioned CAC-OS will be explained in detail. Furthermore, CAC-OS concerns the material composition.

[0500] [CAC-OS]

[0501] CAC-OS is a composition of a material in which, for example, elements constituting a metal oxide are localized in sizes ranging from 0.5 nm to 10 nm, preferably from 1 nm to 3 nm, or in the vicinity thereof. Additionally, below, a state in which one or more metal elements are localized in a metal oxide, and regions having said metal elements are mixed in sizes ranging from 0.5 nm to 10 nm, preferably from 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic pattern or a patch pattern.

[0502] In addition, CAC-OS is a composition in which the material is separated into a first region and a second region to form a mosaic pattern, and the first region is distributed within the film (hereinafter also referred to as a cloud phase). That is, CAC-OS is a composite metal oxide having a composition in which the first region and the second region are mixed.

[0503] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in In-Ga-Zn oxide, the first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is greater than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is greater than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0504] Specifically, the first region is a region in which indium oxide, indium zinc oxide, etc. are the main components. Also, the second region is a region in which gallium oxide, gallium zinc oxide, etc. are the main components. That is, the first region can be rephrased as a region in which In is the main component. Also, the second region can be rephrased as a region in which Ga is the main component.

[0505] In addition, there are cases where a clear boundary cannot be observed between the first region and the second region.

[0506] For example, in the CAC-OS of In-Ga-Zn oxide, it can be confirmed from the EDX mapping obtained using Energy Dispersive X-ray Spectroscopy (EDX) that the structure has a localized and mixed region with In as the main component (first region) and a region with Ga as the main component (second region).

[0507] When CAC-OS is used in a transistor, the conductivity attributed to the first region and the insulation attributed to the second region act complementarily, thereby imparting a switching function (On / Off function) to the CAC-OS. In other words, CAC-OS possesses a conductive function in part of the material and an insulating function in another part, while the material as a whole functions as a semiconductor. By separating the conductive and insulating functions, both capabilities can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on It is possible to realize high electric field effect mobility (μ) and good switching operation.

[0508] Oxide semiconductors have various structures, and each has different characteristics. An oxide semiconductor of one form of the present invention may have two or more types among amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0509] Transistor with oxide semiconductor

[0510] Next, the case where the above oxide semiconductor is used in a transistor will be explained.

[0511] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0512] It is desirable to use oxide semiconductors with low carrier concentrations in transistors. For example, the carrier concentration of an oxide semiconductor is 1×10⁻⁶ 17 cm -3 Below, preferably 1X10 15 cm -3 Below, more preferably 1X10 13 cm -3 Below, more preferably 1X10 11 cm -3 Below, more preferably 1X10 10 cm -3 Less than and 1x10 -9 cm -3 That is all. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, it is desirable to lower the impurity concentration within the oxide semiconductor film and lower the defect level density. In this specification and other contexts, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Additionally, an oxide semiconductor with a low carrier concentration may be referred to as high-purity intrinsic or an oxide semiconductor of substantially high-purity intrinsic.

[0513] In addition, since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density, the trap level density may also be low.

[0514] Furthermore, charges trapped in the trap levels of oxide semiconductors take a long time to dissipate, sometimes acting like fixed charges. Therefore, transistors in which channel formation regions are formed within oxide semiconductors with high trap level density may experience unstable electrical characteristics.

[0515] Therefore, to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration within the oxide semiconductor. Furthermore, to reduce the impurity concentration within the oxide semiconductor, it is desirable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0516] Impurities

[0517] Here, the influence of each impurity in the oxide semiconductor is explained.

[0518] When silicon or carbon, which are Group 14 elements, are included in an oxide semiconductor, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by Secondary Ion Mass Spectrometry (SIMS)) are 2×10 18 atoms / cm 3 Below, preferably 2X10 17 atoms / cm 3 The following applies.

[0519] Furthermore, if alkali metals or alkaline earth metals are included in oxide semiconductors, they may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals are prone to exhibiting normaly-on characteristics. Accordingly, the concentration of alkali metals or alkaline earth metals within the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Below, preferably 2X10 16 atoms / cm 3 The following applies.

[0520] Furthermore, when nitrogen is included in an oxide semiconductor, electron carriers are generated, increasing the carrier concentration and making it prone to n-type transformation. Therefore, transistors using oxide semiconductors containing nitrogen are prone to exhibiting normaly-on characteristics. Alternatively, the inclusion of nitrogen in an oxide semiconductor may lead to the formation of trap levels. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration within the oxide semiconductor obtained by SIMS is 5×10 19 atoms / cm 3 Less than, preferably 5X10 18 atoms / cm 3 Below, more preferably 1X10 18 atoms / cm 3 Below, more preferably 5X10 17 atoms / cm 3 The following applies.

[0521] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, which may result in the formation of oxygen vacancies. In some cases, electron carriers are generated as hydrogen enters these oxygen vacancies. Additionally, some of the hydrogen may combine with oxygen bonded to metal atoms to generate electron carriers. Therefore, transistors using oxide semiconductors containing hydrogen are prone to exhibiting normaly-on characteristics. Consequently, it is desirable to reduce the hydrogen content within the oxide semiconductor as much as possible. Specifically, the hydrogen concentration obtained by SIMS in the oxide semiconductor is 1×10 20 atoms / cm 3 Less than, preferably 1X10 19 atoms / cm 3 Less than, more preferably 5X10 18 atoms / cm 3 Less than, more preferably 1X10 18 atoms / cm 3 Make it less than.

[0522] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0523] This embodiment may be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0524] (Embodiment 4)

[0525] In this embodiment, an electronic device having a display device, which is one form of the present invention, is described.

[0526] FIG. 34 (A) is a drawing showing the exterior of a camera (8000) with a finder (8100) mounted. The camera (8000) is provided with an imaging device. The camera (8000) can be, for example, a digital camera. Also, in FIG. 34 (A), the camera (8000) and the finder (8100) are separate electronic devices and configured to be detachable, but a finder having a display device may be built into the housing (8001) of the camera (8000).

[0527] The camera (8000) has a housing (8001), a display (8002), an operation button (8003), a shutter button (8004), etc. Additionally, the camera (8000) is equipped with a detachable lens (8006).

[0528] Here, the camera (8000) is configured so that the lens (8006) can be detached from the housing (8001) and replaced, but the lens (8006) and the housing may be integrated.

[0529] The camera (8000) can take a picture by pressing the shutter button (8004). Additionally, the display unit (8002) functions as a touch panel, and can also take a picture by touching the display unit (8002).

[0530] The housing (8001) of the camera (8000) has a mount having electrodes, and can connect a strobe device, etc., in addition to the finder (8100).

[0531] The finder (8100) has a housing (8101), a display (8102), a button (8103), etc. The finder (8100) can be an electronic viewfinder.

[0532] The housing (8101) has a mount that is coupled to the mount of the camera (8000), and can mount the finder (8100) to the camera (8000). In addition, the mount has an electrode, and can display an image received from the camera (8000) on the display unit (8102) through the electrode.

[0533] The button (8103) functions as a power button. The on / off status of the display unit (8102) can be switched by the button (8103).

[0534] A display device of one form of the present invention can be applied to the display portion (8002) of the camera (8000) and the display portion (8102) of the finder (8100). Since the display device of one form of the present invention has a very high degree of precision, pixels are not visible to the user even if the distance between the display portion (8002) or the display portion (8102) and the user is close, so an image with a higher sense of realism can be displayed on the display portion (8002) or the display portion (8102). In particular, the image displayed on the display portion (8102) provided to the finder (8100) is visible when the user brings their eye close to the eyepiece of the finder (8100), so the distance between the user and the display portion (8102) becomes very close. Therefore, it is particularly desirable to apply a display device of one form of the present invention to the display portion (8102). In addition, when a display device of one form of the present invention is applied to the display unit (8102), the resolution of the image that can be displayed on the display unit (8102) can be 4K, 5K, or higher.

[0535] In addition, it is preferable that the resolution of the image that can be captured by the imaging device provided to the camera (8000) is equal to or greater than the resolution of the image that can be displayed on the display unit (8002) or the display unit (8102). For example, if an image with a resolution of 4K can be displayed on the display unit (8102), it is preferable to provide the camera (8000) with an imaging device capable of capturing an image of 4K or higher. In addition, for example, if an image with a resolution of 5K can be displayed on the display unit (8102), it is preferable to provide the camera (8000) with an imaging device capable of capturing an image of 5K or higher.

[0536] Figure 34 (B) is a drawing showing the appearance of a head-mounted display (8200).

[0537] The head-mounted display (8200) has a mounting part (8201), a lens (8202), a main body (8203), a display part (8204), a cable (8205), etc. Additionally, a battery (8206) is built into the mounting part (8201).

[0538] The cable (8205) supplies power from the battery (8206) to the main body (8203). The main body (8203) has a wireless receiver, etc., and can display an image corresponding to the received image data, etc. on the display unit (8204). In addition, the movement of the user's eyeball or eyelid is detected by a camera provided in the main body (8203), and the coordinates of the user's gaze are calculated based on that information, thereby allowing the user's gaze to be used as an input means.

[0539] Additionally, the mounting portion (8201) may be provided with multiple electrodes at a position in contact with the user. The main body (8203) may have a function of recognizing the user's gaze by detecting the current flowing through the electrodes according to the movement of the user's eyeball. Additionally, it may have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. Furthermore, the mounting portion (8201) may have various sensors such as a temperature sensor, a pressure sensor, and an accelerometer, and may have a function of displaying the user's biometric information on the display portion (8204). Additionally, it may detect the movement of the user's head, etc., and change the image displayed on the display portion (8204) in accordance with that movement.

[0540] A display device of one form of the present invention can be applied to the display unit (8204). By doing so, the head-mounted display (8200) can be made slim bezel-less, and high-quality images can be displayed on the display unit (8204), and images with a high sense of realism can be displayed.

[0541] Figures 34 (C), (D), and (E) are drawings showing the appearance of a head-mounted display (8300). The head-mounted display (8300) has a housing (8301), a display unit (8302), a band-shaped fixture (8304), and a pair of lenses (8305).

[0542] The user can see the display of the display unit (8302) through the lens (8305). Additionally, it is preferable to arrange the display unit (8302) in a curved position. By arranging the display unit (8302) in a curved position, the user can feel a high sense of realism. Furthermore, although the present embodiment exemplifies a configuration providing one display unit (8302), it is not limited thereto, and, for example, a configuration providing two display units (8302) may be used. In this case, if the configuration is such that one display unit is placed for one eye of the user, it becomes possible to perform three-dimensional display using parallax.

[0543] In addition, a display device of one form of the present invention can be applied to the display unit (8302). Since the display device of one form of the present invention has a very high degree of precision, even when magnified using a lens (8305) as in (E) of FIG. 34, pixels are not visible to the user, so an image with a higher sense of realism can be displayed.

[0544] Next, an example of an electronic device different from the electronic devices shown in FIGS. 34 (A) to (E) is shown in FIGS. 35 (A) to (G).

[0545] The electronic device shown in (A) to (G) of FIG. 35 has a housing (9000), a display unit (9001), a speaker (9003), an operation key (9005) (including a power switch or an operation switch), a connection terminal (9006), a sensor (9007) (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, smell, or infrared), a microphone (9008), etc.

[0546] The electronic device shown in FIGS. 35 (A) to (G) has various functions. For example, it may have a function of displaying various information (still images, video, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of performing transmission or reception of various data using the wireless communication function, and a function of reading a program or data recorded on a recording medium and displaying it on a display unit. Furthermore, the functions that the electronic device shown in FIGS. 35 (A) to (G) may have are not limited to these and may have various functions. Also, although not shown in FIGS. 35 (A) to (G), the electronic device may be configured to have a plurality of display units. Additionally, the electronic device may be provided with a camera, etc., and may have a function of capturing still images, a function of capturing video, a function of storing captured images on a recording medium (an external recording medium or a recording medium built into the camera), and a function of displaying captured images on a display unit.

[0547] Detailed information regarding the electronic device shown in (A) to (G) of FIGS. 35 will be explained below.

[0548] FIG. 35 (A) is a perspective view showing a television device (9100). The television device (9100) may be provided with a large screen, for example, a display unit (9001) of 50 inches or more or 100 inches or more.

[0549] A display device of the present invention can be applied to the display unit (9001) of the television device (9100). By doing so, the television device (9100) can have a slim bezel, and high-quality images can be displayed on the display unit (9001), and images with a high sense of realism can be displayed.

[0550] FIG. 35 (B) is a perspective view showing a portable information terminal (9101). The portable information terminal (9101) has one or more functions selected from, for example, a telephone, a notebook, or an information viewing device. Specifically, it can be used as a smartphone. In addition, the portable information terminal (9101) may be provided with a speaker (9003), a connection terminal (9006), a sensor (9007), etc. In addition, the portable information terminal (9101) may display text or images on its multiple surfaces. For example, three operation buttons (9050) (also called operation icons or simply icons) may be displayed on one surface of the display unit (9001). In addition, information (9051) represented by a dashed rectangle may be displayed on the other surface of the display unit (9001). In addition, examples of information (9051) include an indication of incoming email, social networking service (SNS) or phone call, the subject of email or SNS, the sender's name, date and time, battery level, and antenna reception strength. Alternatively, an operation button (9050), etc., may be displayed instead of the information (9051) at the location where the information (9051) is displayed.

[0551] A display device of one form of the present invention can be applied to the display unit (9001) of the portable information terminal (9101). By doing so, the portable information terminal (9101) can be miniaturized, and high-quality images can be displayed on the display unit (9001), and images with a high sense of realism can be displayed.

[0552] FIG. 35 (C) is a perspective view showing a portable information terminal (9102). The portable information terminal (9102) has the function of displaying information on three or more sides of the display unit (9001). Here, an example is shown in which information (9052), information (9053), and information (9054) are displayed on different sides. For example, the user of the portable information terminal (9102) can check the display (here, information (9053)) while the portable information terminal (9102) is stored in the chest pocket of clothing. Specifically, the phone number or name of the caller of an incoming call is displayed in a position that can be observed from the top of the portable information terminal (9102). The user can check the display and decide whether to answer the call without taking the portable information terminal (9102) out of the pocket.

[0553] A display device of one form of the present invention can be applied to the display unit (9001) of the portable information terminal (9102). By doing so, the portable information terminal (9101) is miniaturized, and high-quality images can be displayed on the display unit (9001), and images with a high sense of realism can be displayed.

[0554] FIG. 35 (D) is a perspective view showing a wristwatch-type portable information terminal (9200). The portable information terminal (9200) can execute various applications such as mobile phone, email, text viewing and composition, music playback, internet communication, and computer games. Additionally, the display unit (9001) is provided with a curved display surface and can perform display along the curved display surface. Furthermore, the portable information terminal (9200) can perform short-range wireless communication according to communication standards. For example, hands-free calling can be performed by communicating with a headset capable of wireless communication. Additionally, the portable information terminal (9200) has a connection terminal (9006) and can directly exchange data with another information terminal through a connector. Additionally, charging can be performed through the connection terminal (9006). Furthermore, the charging operation may be performed by wireless power supply without using the connection terminal (9006).

[0555] A display device of the present invention can be applied to the display unit (9001) of the portable information terminal (9200). By doing so, the portable information terminal (9200) can have a slim bezel, display high-quality images on the display unit (9001), and display images with a high sense of realism.

[0556] Figures 35 (E), (F), and (G) are perspective views showing a foldable portable information terminal (9201). Additionally, Figure 35 (E) is a perspective view of the portable information terminal (9201) in an unfolded state, Figure 35 (F) is a perspective view of the portable information terminal (9201) in a state in the middle of changing from one side to the other between the unfolded state and the folded state, and Figure 35 (G) is a perspective view of the portable information terminal (9201) in a folded state. The portable information terminal (9201) has excellent portability when folded, and excellent visibility of the display because it has a wide display area without seams when unfolded. The display unit (9001) of the portable information terminal (9201) is supported by three housings (9000) connected by a hinge (9055). By bending the two housings (9000) through the hinge (9055), the portable information terminal (9201) can be reversibly deformed from an unfolded state to a folded state. For example, the portable information terminal (9201) can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0557] A display device of the present invention can be applied to the display unit (9001) of the portable information terminal (9201). By doing so, the portable information terminal (9201) can have a slim bezel, and high-quality images can be displayed on the display unit (9001), and images with a high sense of realism can be displayed.

[0558] The configuration examples and corresponding drawings, etc. exemplified in this embodiment may be implemented by appropriately combining at least a part thereof with other configuration examples or drawings, etc.

[0559] This embodiment may be implemented by appropriately combining at least a part thereof with other embodiments described in this specification. Explanation of the symbols

[0560] C1: Capacitive element, N1: Node, N2: Node, Tr11: Transistor, Tr12: Transistor, Tr13: Transistor, 10: Display device, 10A: Display device, 20: 1st layer, 20a: 1st circuit layer, 20b: 2nd circuit layer, 21: 1st circuit, 22: 2nd circuit, 24: Correction data generation circuit, 26: Source driver circuit, 30: 2nd layer, 31: Wiring, 32: Wiring, 33: Display unit, 34: Pixel, 36: Wiring, 38: Pixel block, 44: Shift register circuit, 45: Latch circuit, 46: Digital-to-analog conversion circuit, 47: Amplifier circuit, 81: Logic circuit, 91: Current-voltage conversion circuit, 92: Analog-to-digital conversion circuit, 93: Memory circuit, 200A: Transistor, 200B: Transistor, 200C: Transistor, 205: Conductor, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Metal oxide, 230a: Metal oxide, 230b: Metal oxide, 230c: Metal oxide, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor, 243a: Region, 243b: Region, 244: Insulator, 250: Insulator, 252: Metal oxide, 254: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 270: Insulator, 271: Insulator, 272: Insulator, 274: Insulator, 280: Insulator, 281: Insulator, 301a: Conductor, 301b: Conductor, 305: Conductor, 311: Conductor, 313: Conductor, 317: Conductor, 321: Lower electrode, 323: Insulator, 325: Upper electrode, 331: Conductor, 333: Conductor, 335: Conductor, 337: Conductor, 341: Conductor, 343: Conductor, 347: Conductor, 351: Conductor, 353: Conductor, 355: Conductor, 357: Conductor, 361: Insulator, 363: Insulator, 403: Device isolation layer,405: Insulator, 407: Insulator, 409: Insulator, 411: Insulator, 413: Insulator, 415: Insulator, 417: Insulator, 419: Insulator, 421: Insulator, 441: Transistor, 443: Conductor, 445: Insulator, 447: Semiconductor region, 449a: Low resistance region, 449b: Low resistance region, 451: Conductor, 453: Conductor, 455: Conductor, 457: Conductor, 459: Conductor, 461: Conductor, 463: Conductor, 465: Conductor, 467: Conductor, 469: Conductor, 471: Conductor, 501: Insulator, 503: Insulator, 505: Insulator, 507: Insulator, 509: Insulator, 552: Transistor, 562: Capacitive element, 572: Light-emitting element, 601: Transistor, 602: Transistor, 603: Transistor, 613: Insulator, 614: Insulator, 616: Insulator, 622: Insulator, 624: Insulator, 644: Insulator, 654: Insulator, 674: Insulator, 680: Insulator, 681: Insulator, 701: Substrate, 705: Substrate, 712: Material, 716: FPC, 721: Hole injection layer, 722: Hole transport layer, 723: Light-emitting layer, 724: Electron transport layer, 725: Electron injection layer, 730: Insulator, 732: Sealing layer, 734: Insulator, 736: Coloring layer, 738: Light-shielding layer, 750: Transistor, 760: Connecting electrode, 772: Conductor, 778: Structure, 780: Anisotropic conductor, 782: Light-emitting element, 786: EL layer, 786a: EL layer, 786b: EL layer, 786c: EL layer, 788: Conductor, 790: Capacitive element, 792: Charge generation layer, 800: Transistor, 801a: Conductor, 801b: Conductor, 805: Conductor, 811: Conductor, 813: Conductor, 814: Insulator, 816: Insulator, 817: Conductor, 821: Insulator, 822: Insulator, 824: Insulator, 844: Insulator, 853: Conductor, 854: Insulator, 855: Conductor, 874: Insulator, 880: Insulator, 881: Insulator, 901: Subpixel,901B: Subpixel, 901G: Subpixel, 901R: Subpixel, 902: Pixel, 911: Conductor, 912: Conductor, 913: Semiconductor, 914: Semiconductor, 915a: Conductor, 915b: Conductor, 916a: Conductor, 916b: Conductor, 917: Conductor, 918: Conductor, 919: Conductor, 920: Conductor, 921: Conductor, 922: Conductor, 923: Conductor, 924: Conductor, 925: Conductor, 926: Conductor, 927: Conductor, 928: Conductor, 929: Conductor, 930: Conductor, 931: Conductor, 990: Conductor, 991: Adhesive layer, 992: Insulator, 993a: Colored layer, 993b: Colored layer, 994: Adhesive layer, 995: Substrate, 1021: Insulator, 1022: Insulator, 1023: Insulator, 1024: Insulator, 1025: Insulator, 1026: Insulator, 1027: Insulator, 8000: Camera, 8001: Housing, 8002: Display, 8003: Operation button, 8004: Shutter button, 8006: Lens, 8100: Finder, 8101: Housing, 8102: Display, 8103: Button, 8200: Head-mounted display, 8201: Mounting unit, 8202: Lens, 8203: Body, 8204: Display, 8205: Cable, 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8302: Display unit, 8304: Fixture, 8305: Lens, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Operation button, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television unit, 9101: Portable information terminal, 9102: Portable information terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

Claim 1 As a display device, the first layer and a second layer above the first layer, the first layer has a first circuit arranged in m rows and n columns, where m and n are each integers greater than or equal to 1, and the product of m and n is greater than or equal to 2, the second layer has a pixel block arranged in m rows and n columns, the pixel block each has a pixel arranged in a row and b columns, where a and b are each integers greater than or equal to 1, the pixel block has a first wire and a second wire electrically connected to the pixel, the first wire and the second wire having the pixel block in the i-th row and j-th column are each electrically connected to the first circuit in the i-th row and j-th column, i is an integer greater than or equal to 1 and m, and j is an integer greater than or equal to 1 and n, the first wire supplies an input signal from the first circuit to the pixel, and the second wire supplies an output signal from the pixel to the first circuit, and the A display device comprising: a circuit having a correction data generation circuit, a logic circuit, and a source driver circuit, wherein the correction data generation circuit converts the output signal into correction data, the logic circuit converts the video signal input to the first circuit based on the correction data and generates a corrected video signal, and the source driver circuit converts the corrected video signal into the input signal. Claim 2 A display device according to claim 1, wherein the pixel block at row i and column j has an area overlapping with the first circuit at row i and column j. Claim 3 A display device according to claim 1, wherein the pixel block at row p and column q does not overlap with the first circuit at row p and column q, p is an integer greater than or equal to m and different from i, and q is an integer greater than or equal to n and different from j. Claim 4 A display device according to claim 1, wherein the second layer further has m second circuits arranged in a column direction, the pixel block has a third wiring electrically connected to a plurality of the pixels arranged in a row direction, and the third wiring having the pixel block of the i-th row is electrically connected to the i-th second circuit. Claim 5 A display device according to claim 1, wherein the first layer further has m second circuits arranged in a column direction, the pixel block has a third wiring electrically connected to a plurality of the pixels arranged in a row direction, and the third wiring having the pixel block of the i-th row is electrically connected to the i-th second circuit. Claim 6 A display device according to claim 5, wherein the pixel block at row i and column j has an area overlapping with at least one of the second circuits. Claim 7 In claim 1, the correction data generation circuit has a memory circuit, the first layer has a first circuit layer and a second circuit layer above the first circuit layer, the first circuit layer has a logic circuit, the logic circuit has a transistor having silicon in a channel forming region, the second circuit layer has the memory circuit, the memory circuit has a transistor having a metal oxide in a channel forming region, the metal oxide has In, element M, and Zn, and the element M is at least one of Al, Ga, Y, and Sn, a display device. Claim 8 In claim 1, the pixel has a transistor having a metal oxide in a channel forming region, the metal oxide has In, an element M, and Zn, and the element M is at least one of Al, Ga, Y, and Sn, a display device. Claim 9 In claim 1, the pixel is a display device having a transistor having silicon in a channel forming region. Claim 10 A display device having a first layer and a second layer above the first layer, wherein the first layer has a first circuit arranged in m rows and n columns, where m and n are each integers greater than or equal to 1, and the product of m and n is greater than or equal to 2, and the second layer has a pixel block arranged in m rows and n columns, where each pixel block has a pixel arranged in a row and b columns, where a and b are each integers greater than or equal to 1, and the pixel block has a first wire and a second wire electrically connected to the pixel, where the first wire and the second wire included in the pixel block at the i-th row and j-th column are each electrically connected to the first circuit at the i-th row and j-th column, where i is an integer greater than or equal to 1 and m inclusive, and j is an integer greater than or equal to 1 and n inclusive, where the first wire supplies an input signal from the first circuit to the pixel, and the second wire supplies an output signal from the pixel to the first circuit, and i-th row A display device in which the pixel block of the j-th column has an area that overlaps with the first circuit of the i-th row and j-th column.

Images