Semiconductor device testing equipment

Abstract

A semiconductor device testing device comprises a test substrate having a first surface and a second surface facing each other and a plurality of substrate pads provided on the first surface; a plurality of base portions each provided on the plurality of substrate pads and electrically connected to a semiconductor device and in contact with the substrate pads; a plurality of outer tension arms each extending from the base portions to form an arc and forming a closed loop with the outer tension arms; a plurality of inner tension arms each extending from the base portions inside the outer tension arms and forming a closed loop with the outer tension arms; and a plurality of test pins each having a plurality of contact portions connecting the outer tension arms and the inner tension arms to each other and in contact with the semiconductor device.

Description

Technology Field

[0001] The present invention relates to a semiconductor device testing device, and more specifically, to a semiconductor device testing device for testing the reliability of a semiconductor device. Background Technology

[0002] The pogo pin method used in semiconductor inspection processes has a complex structure and a limited current capacity of approximately 2A, as it utilizes an assembly structure that combines multiple micro-components with a coil spring. This presents a fundamental limitation that makes it difficult to respond to the high-power semiconductors or system verification environments that have recently emerged. The press, etching, or laser cutting processes primarily used to manufacture pogo pins inevitably cause surface roughness on the cut surface, which degrades the reliability of fine movements or electrical contacts of the pogo pins and leads to problems such as uneven elastic recovery force or reduced durability during repetitive vertical movements. The problem to be solved

[0003] One objective of the present invention is to provide a semiconductor device inspection device comprising a plurality of test pins capable of stably supporting high current and ensuring excellent elastic recovery force and surface quality. means of solving the problem

[0004] A semiconductor device testing device according to exemplary embodiments for achieving one objective of the present invention comprises: a test substrate having a first surface and a second surface facing each other and a plurality of substrate pads provided on the first surface; a plurality of base portions each provided on the plurality of substrate pads and electrically connected to a semiconductor device and in contact with the substrate pads; a plurality of outer tension arms each extending from the base portions to form an arc and forming a closed loop with the outer tension arms; a plurality of inner tension arms each extending from the base portions inside the outer tension arms and forming a closed loop with the outer tension arms; and a plurality of test pins each having a plurality of contact portions connecting the outer tension arms and the inner tension arms to each other and in contact with the semiconductor device.

[0005] In exemplary embodiments, the plurality of test pins have a cross-section processed by precision numerical control and grinding processes, and have a surface roughness less than or equal to a preset reference value.

[0006] In exemplary embodiments, the first elastic member is further provided on the inner side of the plurality of inner tension arms and reinforces the loss of elasticity during the vertical repetitive movement of the plurality of test pins.

[0007] In exemplary embodiments, a second elastic member is further included, disposed adjacent to one side of the base portions to support and maintain the alignment of the test pins.

[0008] In exemplary embodiments, the contact portions have at least one of an upwardly protruding pointed shape, a flat shape, or a stepped shape that increases contact pressure, corresponding to the terminal shape of the semiconductor device.

[0009] In exemplary embodiments, the closed loop extends from the upper or side surface of each of the base portions to form the arc.

[0010] In exemplary embodiments, each of the outer tension arms and each of the inner tension arms connects the base portion and the contact portion and forms a U-shape.

[0011] In exemplary embodiments, each of the outer tension arms has a first width, each of the inner tension arms has a second width that is thicker than the first width, and the ratio (W2 / W1) of the second width (W2) of each of the inner tension arms to the first width (W1) of each of the outer tension arms is within the range of 1 to 1.1.

[0012] In exemplary embodiments, the thickness of each of the plurality of test pins is within the range of 1.5 to 2.5 times the first width or the second width, and the thickness is within the range of 0.2 mm to 0.25 mm.

[0013] In exemplary embodiments, each of the outer tension arms and each of the inner tension arms extends along the same axis.

[0014] In exemplary embodiments, the plurality of test pins are formed as an integral structure of a heat-treated beryllium copper alloy material and have an allowable current of 3.0A to 4.0A based on the structural elasticity of the closed loop and the electrical properties of the alloy material.

[0015] In exemplary embodiments, each of the test pins has a first signal path passing through the outer tension arm from an input end, which is a point of the base portion in contact with the substrate pad, to an output end, which is a point of the contact portion in contact with the semiconductor device, and a second signal path passing through the inner tension arm from the input end to the output end, wherein the ratio (D1 / D2) of the second distance (D2) of the second signal path to the first distance (D1) of the first signal path is within the range of 0.9 to 1.1. Effects of the invention

[0016] According to exemplary embodiments, a semiconductor device test device may include a test substrate having a first surface and a second surface facing each other and a plurality of substrate pads provided on the first surface; a plurality of base portions each provided on the plurality of substrate pads and electrically connected to a semiconductor device and in contact with the substrate pads; a plurality of outer tension arms each extending from the base portions to form an arc and forming a closed loop with the outer tension arms; a plurality of inner tension arms each extending from the base portions inside the outer tension arms and forming a closed loop with the outer tension arms; and a plurality of test pins each having a plurality of contact portions connecting the outer tension arms and the inner tension arms to each other and in contact with the semiconductor device.

[0017] Accordingly, the semiconductor device testing device has a one-body structure in which the outer tension arms and inner tension arms extending from the base portions of the test pins are connected to each other to form a closed loop, thereby enabling it to independently secure the vertical elastic force required for contact with the semiconductor device without the need for separate complex assembly parts such as coil springs or plungers. This double-arch closed-loop structure distributes the load applied to the test pins to the outside and inside, thereby improving mechanical durability and minimizing structural deformation even during repeated compression and relaxation operations, thus providing stable contact reliability.

[0018] In addition, the semiconductor device inspection device can possess excellent electrical characteristics capable of transmitting high current and high frequency signals up to 3.5A without distortion by overcoming the resistance limitations of the conventional coil spring method through a continuous, integrated metal structure that simplifies the path of electrical signals and secures cross-sectional area. The semiconductor device inspection device can fundamentally prevent contact failure problems caused by internal dust generation or wear by eliminating joints where friction occurs between components, and can precisely implement elastic values ​​optimized for various test environments through the adjustment of the tension arm thickness ratio or precision machining.

[0019] However, the effects of the present invention are not limited to the effects mentioned above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0020] FIG. 1 is a cross-sectional view showing a semiconductor device inspection apparatus according to exemplary embodiments. FIG. 2 is a perspective view showing a plurality of test pins supporting a semiconductor device. Figure 3 is a perspective view showing the test pin of Figure 2. Figure 4 is a diagram showing the electrical signal paths transmitted within the test pin of Figure 3. FIGS. 5 and FIGS. 6 are perspective views showing test pins having modified contact portions, respectively. FIGS. 7 and FIGS. 8 are perspective views showing test pins having modified structures, respectively. Specific details for implementing the invention

[0021] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0022] In each drawing of the present invention, the dimensions of the structures are depicted enlarged compared to the actual dimensions for the clarity of the invention.

[0023] In the present invention, terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0024] The terms used in this invention are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0025] With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are provided merely for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in the text.

[0026] That is, the present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed forms, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0027] FIG. 1 is a cross-sectional view showing a semiconductor device test apparatus according to exemplary embodiments. FIG. 2 is a perspective view showing a plurality of test pins supporting a semiconductor device. FIG. 3 is a perspective view showing the test pins of FIG. 2. FIG. 4 is a diagram showing electrical signal paths transmitted within the test pins of FIG. 3. FIG. 5 and FIG. 6 are perspective views showing test pins each having modified contact portions.

[0028] Referring to FIGS. 1 to 6, a semiconductor device testing device (10) may include a test substrate (100) having a plurality of substrate pads (110) and a plurality of test pins (200) each provided on the plurality of substrate pads (110). The semiconductor device testing device (10) may further include a first elastic member (300) and a second elastic member (310) each extending along the plurality of test pins (200). The semiconductor device testing device (10) may further include a frame (400) for covering the plurality of test pins (200), the first elastic member (300), the second elastic member (310), and the semiconductor device (20) on the test substrate (100).

[0029] In exemplary embodiments, the semiconductor device inspection device (10) may be an interface device that electrically connects the input / output terminals of the semiconductor device to an external test device (Tester) in order to determine whether the semiconductor device (Device Under Test, DUT) or system IC is electrically operating and whether there are performance defects in the latter part of the semiconductor manufacturing process, or whether the semiconductor device is in a wafer state or has been packaged. The semiconductor device inspection device (10) can stably transmit high power and high frequency signals to meet the requirements of high-performance semiconductor devices, and can improve the reliability and yield of the inspection process by minimizing physical wear or elastic degradation even in a repetitive contact inspection environment.

[0030] A semiconductor device testing device (10) can support a semiconductor device (20) through a plurality of test pins (200) and can perform a reliability test on a semiconductor device (20) that is electrically connected to a test substrate (100) through a plurality of test pins (200). The semiconductor device (20) can be placed within a receiving space (410) provided within a frame (400) on the test substrate (100), and the semiconductor device testing device (10) can perform the reliability test.

[0031] In exemplary embodiments, the semiconductor device (20) may be produced through a lead-type packaging process. The semiconductor device (20) may include a high-power, high-performance semiconductor substrate. The semiconductor device (20) may include conductive structures (22) for electrically connecting to external devices.

[0032] For example, the semiconductor device (20) may include DFN (Dual Flat No-lead), QFN (Quad Flat No-lead), SOIC (Small Outline Integrated Circuit), TSSOP (Thin Shrink Small Outline Package), etc. The semiconductor device (20) may include TO-220 (Transistor Outline Package 220), TO-3 (Transistor Outline Package 3), TO-247, TO-92, DIP (Dual In-line Package), SIP (Single In-line Package), etc.

[0033] In exemplary embodiments, the test substrate (100) may have a first surface (102) and a second surface (104) opposite to the first surface (102). The test substrate (100) may include a plurality of substrate pads (110) provided to be exposed from the first surface (102).

[0034] In exemplary embodiments, the test board (100) may include test circuits for performing the reliability test on the semiconductor device (20), and test terminals (120) electrically connected to the test circuits. For example, the test board (100) may be connected to an external device to receive power and exchange data. The test board (100) may refer to an electronic board for testing the reliability of the semiconductor device (20).

[0035] The above test terminals (120) may include transistors, diodes, etc. The above test terminals (120) may constitute circuit elements. Accordingly, the test board (100) may be a semiconductor device having a plurality of circuit elements formed inside.

[0036] For example, the test substrate (100) may include semiconductor materials such as silicon, germanium, silicon-germanium, etc., or group III-V compound semiconductors such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. According to some embodiments, the test substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0037] In exemplary embodiments, the test substrate (100) may include a redistribution layer. The redistribution layer may include a plurality of insulating films and redistributions (130) provided within the insulating films. The redistribution layer may have an upper surface and a lower surface opposite each other. A plurality of substrate pads (110) may be provided so as to be exposed from the upper surface of the redistribution layer. For example, the redistributions (130) may be formed by a plating process, an electroless plating process, a vapor deposition process, etc. The redistributions (130) may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0038] The insulating films may include polymers, dielectric films, etc. The insulating films may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), etc. The insulating films may be formed by a vapor deposition process, a spin coating process, etc. The insulating films may have openings that expose the upper surfaces of the substrate pads (110). For example, the substrate pads (110) may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0039] A plurality of substrate pads (110) can be electrically connected to the redistributions (130) of the redistribution layer and can be electrically connected to test terminals (120) through the redistributions (130). A plurality of substrate pads (110) can electrically connect a semiconductor device (20) placed on a plurality of test pins (200) to the test terminals (120) through the redistributions (130), and the test substrate (100) can perform the reliability test on the semiconductor device (20) through the substrate pads (110) and the plurality of test pins (200).

[0040] In exemplary embodiments, a plurality of test pins (200) may be provided on a test substrate (100). A plurality of test pins (200) may each be provided on substrate pads (110) of the test substrate (100). A plurality of test pins (200) may support a semiconductor device (20) that is the subject of the reliability test on the test substrate (100). A plurality of test pins (200) may be Black Swan pins.

[0041] A plurality of test pins (200) may each be provided on a plurality of substrate pads (110) and electrically connected to a semiconductor device (20). The plurality of test pins (200) may include a conductor and may electrically connect the semiconductor device (20) and the test substrate (100). The plurality of test pins (200) may be provided on the substrate pads (110) of the test substrate (100) to support the semiconductor device (20), and the plurality of test pins (200) may electrically connect the semiconductor device (20) and test terminals (120) together with the substrate pads (110) and the rewiring (130). The plurality of test pins (200) may be produced from silicon, etc. and may include an elastomer having elasticity. Multiple test pins (200) may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti), etc.

[0042] In exemplary embodiments, a plurality of test pins (200) may have a plurality of base portions (210) each contacting substrate pads (110), a plurality of outer tension arms (220) each extending from the base portions (210) in an arc, a plurality of inner tension arms (230) each extending from the base portions (210) inside the outer tension arms (220), and a plurality of contact portions (240) connecting the outer tension arms (220) and the inner tension arms (230) to each other and contacting a semiconductor device (20).

[0043] A plurality of test pins (200) are provided on a test substrate (100) and can serve as a medium for transmitting and receiving electrical signals with a semiconductor device (20). Each of the plurality of test pins (200) may include a plurality of base portions (210) that form a support base by physically and electrically contacting the substrate pads (110). The base portions (210) may have a flat lower surface to make surface contact with the upper surface of the substrate pads (110), thereby providing a structural foundation that can stably support the plurality of test pins (200) without shaking when receiving a vertical load from the semiconductor device (20).

[0044] A plurality of test pins (200) may include a plurality of outer tension arms (220) having an arc shape with a predetermined curvature, extending upward from one side or the other side of the base portions (210). The outer tension arms (220) can define the overall outer shape of the test pins (200) and can provide a primary elastic restoring force against the load generated when the semiconductor device (20) is pressed. The outer tension arms (220) can be extended from the base portions (210) in a smooth curved shape to prevent stress concentration at a specific point and enable flexible bending motion.

[0045] A plurality of test pins (200) may include a plurality of inner tension arms (230) extending from base portions (210) to be disposed in an inner space formed by outer tension arms (220). The inner tension arms (230) may have an arc shape corresponding to the outer tension arms (220) and may be arranged parallel to the outer tension arms (220) at a predetermined distance apart. The plurality of inner tension arms (230) may each form closed loops with the plurality of outer tension arms (220). By forming a closed-loop shape together with the outer tension arms (220), the inner tension arms (230) can effectively distribute the vertical load applied to the test pins (200) inwardly and outwardly, and reinforce the structural rigidity of the pins.

[0046] A plurality of test pins (200) may include a plurality of contact portions (240) that connect the upper ends of the outer tension arms (220) and the upper ends of the inner tension arms (230) to each other and directly contact the terminals of the semiconductor device (20). The contact portions (240) are formed at the point where the outer tension arms (220) and the inner tension arms (230) merge, and may provide a path to transmit electrical signals transmitted from the semiconductor device (20) to the base portions (210) through the outer tension arms (220) and the inner tension arms (230). As a result, the test pins (200) have a one-body structure in which the base parts (210), outer tension arms (220), inner tension arms (230) and contact parts (240) are connected seamlessly, thereby lowering electrical resistance compared to a multi-part assembly method and minimizing heat generation and signal loss during high current transmission.

[0047] The above closed loop may include a first arc section and a second arc section spaced apart from each other at both ends, and the first arc section and the second arc section may each have a center of curvature. A virtual extension line A set to pass through the center of curvature of the first arc section and a virtual extension line B set to pass through the center of curvature of the second arc section may be arranged to be parallel to each other. Here, being parallel to each other may include the extension line A and the extension line B being located on the same straight line, being parallel to each other, or being arranged so that the angle formed between them is less than or equal to a preset reference value. By the extension line A and the extension line B being parallel as described above, the left-right deviation of the elastic restoring force generated during vertical compression is suppressed, and the lateral bending moment is reduced, thereby improving shape stability for repeated driving.

[0048] In exemplary embodiments, each of the outer tension arms (220) and each of the inner tension arms (230) may form a U-shape by connecting the base portion (210) and the contact portion (240). The U-shape formed by the outer tension arms (220) and the inner tension arms (230) may be a geometric structure designed to maximize the effective elastic length of the tension arms within a limited vertical space. The U-shaped structure can prevent stress concentration at a specific point and smoothly distribute the load over the entire curved section when a vertical compressive load is applied from the semiconductor device to the contact portion (240). Through this, the test pins can exhibit excellent elastic recovery force and maintain a stable mechanical life without plastic deformation or breakage even in a long-term, repetitive pressurized environment.

[0049] A first virtual line (L1) passing through a first center of curvature located at one end of the U-shape and a second virtual line (L2) passing through a second center of curvature located at the other end of the U-shape can be formed to be parallel to each other or to be close to parallel within a preset error range. The first virtual line (L1) may be a line penetrating the center of a lower curved section that bends adjacent to the base section (210), and the second virtual line (L2) may be a line penetrating the center of an upper curved section that bends adjacent to the contact section (240). A parallel structure in which the first virtual line (L1) and the second virtual line (L2) are arranged parallel to each other can provide the effect of consistently synchronizing the displacement trajectories of the upper and lower sections during compression and relaxation operations of the pin. This symmetrical and balanced curvature arrangement can effectively suppress the buckling phenomenon in which the tension arms unintentionally twist or bend in the lateral direction when a vertical load is applied.

[0050] The parallelism formed by the first virtual line (L1) and the second virtual line (L2) can serve as a reference indicator for implementing various elastic values ​​by applying slight modifications according to user needs or test environments. By adjusting the parallel structure to be slightly misaligned within a preset error range or by changing the radius of curvature of the U-shape, the designer can finely tune the overall spring constant of the test pins to increase or decrease it. The U-shaped structure having such geometric characteristics can provide optimized mechanical behavior that simultaneously satisfies soft initial contact to prevent damage to the semiconductor device pads and sufficient contact pressure for reliable electrical conduction.

[0051] In exemplary embodiments, the cut surface of a plurality of test pins (200) can be machined by precision numerical control (CNC) and a grinding process. The cut surface of the plurality of test pins (200) can be machined precisely by the precision numerical control and the grinding process, rather than by a general die press or etching method. The precision numerical control may include a machining method that uses a computer to precisely control a tool, thereby enabling the fine and complex closed-loop shape of the plurality of test pins (200) to be precisely realized to approximate the design value. The cutting process using the precision numerical control can improve the structural precision of the plurality of test pins (200) by reducing excessive mechanical stress applied to the material and minimizing deformation of the cut surface.

[0052] The quality of the cut surface of the multiple test pins (200) can be further improved through the grinding process performed after the precision numerical control. The grinding process may include a finishing process to smooth out fine burrs or rough surfaces that may occur during the cutting process. Through the grinding process, the side and curved portions of the multiple test pins (200) can maintain a uniform surface condition, which can contribute to preventing mechanical friction or jamming that may occur during the repetitive vertical movement of the pins.

[0053] Multiple test pins (200) may have a surface roughness of less than or equal to a preset reference value through the precision numerical control and the grinding process. The surface roughness may refer to the arithmetic mean roughness measured by a contact or non-contact surface measuring device. The reference value may be set to a value to suppress local wear and contact resistance fluctuations caused by burrs or micro-protrusions during repetitive compression driving, and for example, the surface roughness may be set to any one of the ranges from 0.05 to 0.5 micrometers or less.

[0054] Multiple test pins (200) may have a surface roughness below a preset reference value through the precision numerical control and grinding process. The preset reference value may refer to a level of smoothness superior to the roughness of a typical cut surface formed during press processing or laser cutting. By having the multiple test pins (200) have a surface roughness below the preset reference value, the surface area through which current flows is substantially increased, thereby improving high-frequency signal transmission characteristics. The surface roughness can reduce the adsorption of foreign substances at the contact area and suppress surface wear even during long-term use, thereby extending the electrical contact reliability and mechanical life of the multiple test pins (200).

[0055] In exemplary embodiments, each of the outer tension arms (220) may have a first width (W1). Each of the outer tension arms (220) may have a first width (W1) to have a predetermined uniform cross-sectional area. The shape and width of the outer tension arms (220) may be designed to provide elastic force capable of supporting a vertical load applied upon contact with a semiconductor device and ensuring smooth movement of the contact portion. Each of the inner tension arms (230) may have a second width (W2). The second width (W2) may be thicker than the first width (W1). Each of the inner tension arms (230) may have a second width (W2) and be arranged parallel to the outer tension arms (220) while spaced apart from them. The width of the inner tension arms (230) can be set independently of the outer tension arms (220) and can be determined by considering structural stability and electrical conductivity.

[0056] The second width (W2) may be thicker than the first width (W1). By forming the inner tension arms (230) to be relatively thicker than the outer tension arms (220), the overall structural rigidity of the test pins can be improved. In particular, the inner tension arms (230) can suppress deformation while acting as a primary support structure against external impact or repetitive compressive loads. The outer tension arms (220), having the relatively thin first width (W1), can induce soft contact with the semiconductor device through flexible elastic deformation and mitigate the impact generated upon contact.

[0057] The inner tension arms (230) primarily support vertical loads applied directly from the terminals of the semiconductor device (20), and accordingly, can be designed to have a relatively thick second width (W2). The sufficient cross-sectional area secured through the second width (W2) can contribute to reinforcing structural rigidity against repetitive compressive loads and preventing fatigue failure due to stress concentration. Alternatively, the outer tension arms (220) are arranged to surround the outer edge of the inner tension arms (230) and can serve as guides to limit lateral flow or twisting that may occur when the pin is compressed. Accordingly, the first width (W1) is formed thinner than the second width (W2) to ensure flexibility, while also performing the function of maintaining the shape of the entire pin and assisting in stable vertical movement.

[0058] The ratio (W2 / W1) of the second width (W2) of each inner tension arm (230) to the first width (W1) of each outer tension arm (220) may be within the range of 1 to 1.1. Within the above ratio range, the width of the inner tension arms (230) is maintained to be greater than or equal to the width of the outer tension arms (220), thereby ensuring that the test pins simultaneously secure balanced elastic restoring force and structural durability. If the above ratio is less than 1, that is, if the inner tension arms (230) are thinner than the outer tension arms (220), stress may be concentrated in structurally weak areas upon repeated application of load, and fatigue failure may occur. Conversely, if the above ratio exceeds 1.1, the stiffness of the inner tension arms (230) increases excessively, reducing the flexibility of the entire pin and causing excessive contact pressure on the terminals of the semiconductor device. Therefore, the above ratio range can serve as an important design factor to ensure the optimized mechanical performance of the test pins.

[0059] In exemplary embodiments, each of the plurality of test pins (200) may have an optimized thickness (T) to minimize interference with adjacent pins when arranged on a test substrate and to correspond to the highly integrated pad pitch of the semiconductor device. The thickness (T) of each of the plurality of test pins (200) may be within the range of 1.5 to 2.5 times the first width (W1) or the second width (W2).

[0060] Thickness (T) refers to the thickness direction dimension of the raw material metal plate forming the plurality of test pins (200), and the first width (W1) and second width (W2) may refer to the width direction dimension of the tension arm patterned on the plate. The ratio range may serve as a structural threshold to maintain stable elastic behavior without buckling or twisting when the plurality of test pins (200) perform repetitive vertical compression operations. If the thickness (T) is less than 1.5 times the first and second widths (W1, W2), the lateral stiffness of the pin is insufficient, and there may be an increased risk of the pin bending sideways or misalignment when a vertical load is applied. Conversely, if the thickness (T) exceeds 2.5 times, the second moment of area of ​​the pin increases excessively, which may cause higher contact pressure than necessary or make it difficult to handle fine pitch.

[0061] The thickness (T) of each of the multiple test pins (200) may be within the range of 0.2 mm to 0.25 mm. This numerical range may be an optimal design value to simultaneously satisfy the pin spacing and allowable current required in recent high-density semiconductor package test environments. If the thickness (T) is excessively thin, less than 0.2 mm, heat generation problems may occur due to increased resistance of the pin itself when high current is applied, or mechanical durability may be reduced, leading to a shortened lifespan. Conversely, if the thickness (T) exceeds 0.25 mm, it may become difficult to accommodate the pad arrangement of semiconductor devices with a narrow pitch due to the increase in the physical volume of the pin, and the risk of electrical short circuits between adjacent pins may increase.

[0062] In exemplary embodiments, each of the outer tension arms (220) and each of the inner tension arms (230) may extend along the same axis (AX). The outer tension arms (220) and the inner tension arms (230) may be spaced apart from each other and extend in a concentric or parallel curved shape. Each of the outer tension arms (220) and each of the inner tension arms (230) may have a geometric shape that extends along the same axis (AX). The same axis (AX) may refer to the central axis of the arc formed by the outer tension arms (220) and the inner tension arms (230), in which case the tension arms may share the same center of curvature. This coaxial arrangement can induce the bending moment generated when the outer tension arms (220) and the inner tension arms (230) are compressed in the vertical direction to be uniformly distributed throughout the entire structure without being concentrated at a specific point.

[0063] The structure extending along the same axis can maintain a constant gap between the outer tension arms (220) and the inner tension arms (230). By maintaining a constant gap, it is possible to prevent the outer tension arms (220) and the inner tension arms (230) from interfering with or coming into contact with each other during compression of the pin, thereby preventing unintended friction or short circuits. The coaxial arrangement provides symmetry to the cross-sectional shape of the pin, thereby minimizing twisting or deformation that may occur during the manufacturing process of the pin, and increasing resistance to buckling when a vertical load is applied, which can improve structural stability. Since the outer tension arms (220) and the inner tension arms (230) share and extend along the same axis (AX), multiple test pins can stably maintain their initial shape even in a repetitive test environment and provide highly reliable electrical contact.

[0064] In exemplary embodiments, each contact portion (240) may be formed to correspond to the terminal shape of the semiconductor device (20). Each contact portion (240) may include a pointed shape protruding upward, a flat shape, or a stepped shape that increases contact pressure. Each contact portion (240) may have an optimized geometric structure to flexibly correspond to various package types and terminal shapes of the semiconductor device (20). The test terminal (120) of the semiconductor device (20) may be various, such as a flat pad, a ball-shaped solder ball, or a lead shape, and each contact portion (240) may be custom-designed to stably adhere to such a terminal to form an electrical conduction path.

[0065] Each of the contact portions (240) may include a shape that protrudes upwardly in a pointed manner. The pointed shape can effectively penetrate oxide films or foreign substances that may be present on the terminal surface of the semiconductor device (20), thereby inducing direct metal-to-metal contact. This can contribute to increasing the reliability of signal transmission by realizing low-resistance contact. Each of the contact portions (240) may include a flat shape. The flat shape can expand the contact area to disperse current density and relieve local pressure applied to the terminal of the semiconductor device (20), thereby preventing damage to the terminal. This can be particularly advantageous when testing a sensitive semiconductor device (20).

[0066] Each of the contact portions (240) may include a stepped shape to increase contact pressure. The stepped shape may be a structure in which a portion of the contact portions (240) is formed higher than another portion, and may provide the effect of lowering contact resistance by concentrating the load on a specific area during initial contact. In addition, the stepped shape may strengthen the structural coupling force that engages with the terminal of the semiconductor device (20), thereby preventing contact failure caused by vibration or shock that may occur during testing. Each of the contact portions (240) including such various shapes may be selectively applied according to the test environment and requirements to achieve optimal electrical and mechanical performance.

[0067] In exemplary embodiments, a plurality of test pins (200) may be formed as an integral structure of a heat-treated beryllium copper (BeCu) alloy material. The beryllium copper is manufactured as a precipitation-hardening alloy by adding a small amount of beryllium to copper, and can secure high tensile strength and fatigue limits through a heat treatment process such as age hardening. The heat-treated beryllium copper material can increase the elastic limit point, allowing the plurality of test pins (200) to be restored to their original shape without plastic deformation even when performing repetitive compression and relaxation operations. The heat treatment conditions for the alloy material may be set to have a hardness value greater than or equal to a preset standard value. The test pins (200) may further include at least one of nickel plating, gold plating, or a similar conductive surface treatment process to reduce electrical contact resistance or improve corrosion resistance. The alloy material maintains excellent copper-based conductivity, thereby effectively suppressing resistance loss and heat generation that may occur during fine signal transmission. Multiple test pins (200) are formed as a one-body structure without separate heterogeneous material parts being combined, thereby fundamentally eliminating instability caused by contact resistance between materials or differences in thermal expansion coefficients.

[0068] A plurality of test pins (200) may have an allowable current of 3.0A to 4.0A based on the structural elasticity of the closed loop and the electrical characteristics of the alloy material. The allowable current may be a rated current that is set such that when current is applied to the test pins (200), the temperature rise, contact resistance, and voltage drop in the contact portion and the tension arms are within a preset allowable limit. For example, the allowable current may be set such that the temperature rise is below a preset limit when current is applied for a preset time, and the contact resistance may be measured using a four-terminal measurement method.

[0069] In contrast to a standard coil spring type pogo pin having a current tolerance limit of about 2A, the multiple test pins (200) of the semiconductor device testing device (10) can smoothly induce current flow through the material properties of the beryllium copper alloy and a continuous integrated current path. The closed-loop structure secures a cross-sectional area through which current can flow by dividing it into an outer tension arm and an inner tension arm, thereby dispersing the current density when high current is applied and preventing local overheating. Accordingly, the multiple test pins (200) maintain a stable electrical connection even in environments requiring high-current testing, such as power semiconductors or high-performance processors, and can provide reliable test results even during long-term burn-in tests or high-speed operation tests.

[0070] In exemplary embodiments, a plurality of test pins (200) may be designed to have structural features similar to a differential signal transmission line to minimize loss and distortion of high frequency signals.

[0071] As illustrated in FIG. 4, a plurality of test pins (200) can divide the path through which an electrical signal is transmitted from an input terminal on a test substrate (100) to an output terminal of a semiconductor device (20) into a first signal path (Signal Path-A, SA) and a second signal path (Signal Path-B, SB). The first signal path (SA) may refer to a current flow formed along the outer tension arm (220), and the second signal path (SB) may refer to a current flow formed along the inner tension arm (230).

[0072] The first signal path (SA) and the second signal path (SB) can form a parallel transmission structure in which they branch off from the input terminal, the substrate pad (110), and rejoin at the output terminal, the conductive structure (22). As the outer tension arm (220) and the inner tension arm (230) are extended in a shape that is parallel to or concentric to each other, the physical length of the first signal path (SA) and the physical length of the second signal path (SB) can have substantially the same or very similar values. By matching the lengths of the two signal paths in this way, problems such as phase difference or skew that may occur when a high-frequency signal passes through a plurality of test pins (200) can be effectively suppressed.

[0073] A first signal path (SA) may be provided, passing through an outer tension arm (220) from the input end of the base part (210) to the output end of the contact part (240). A second signal path (SB) may be provided, passing through an inner tension arm (230) from the input end of the base part (210) to the output end of the contact part (240). The first signal path (SA) may have a first distance (D1), and the second signal path (SB) may have a second distance (D2). The ratio (D1 / D2) of the first distance (D1) and the second distance (D2) may be within the range of 0.9 to 1.1. The first signal path (SA) and the second signal path (SB) may each be physical paths connecting from any point of the base part (210) to any other point of the contact part (240). The first distance (D1) and the second distance (D2) may refer to physical path lengths measured along the centerline of the conductive path from the input end of the base part (210) to the output end of the contact part (240). The length matching of the first signal path (SA) and the second signal path (SB) may be applied as a design condition to suppress phase difference or skew when transmitting high-frequency signals.

[0074] In exemplary embodiments, the test pins (200) may include parallel paths through which electrical signals are transmitted. The test pins (200) may have a first signal path (SA) passing through an outer tension arm (220) from an input end, which is a point on the base portion (210) in contact with the substrate pad (110), to an output end, which is a point on the contact portion (240) in contact with the semiconductor device (20). The test pins (200) may have a second signal path (SB) passing through an inner tension arm (230) from the input end to the output end. The input end may refer to a physical starting point where an electrical signal is first applied from the test substrate, and the output end may refer to a final physical end point where the signal passing through the test pins (200) exits to the semiconductor device (20). The first signal path (SA) and the second signal path (SB) can form a closed-loop electrical transmission structure that branches off from the single input terminal, flows along the outer tension arm (220) and the inner tension arm (230) respectively, and then rejoins at the single output terminal.

[0075] The first signal path (SA) may have a first distance (D1), which is a physical length measured along the shape of the outer tension arm (220) from the input end to the output end. The second signal path (SB) may have a second distance (D2), which is a physical length measured along the shape of the inner tension arm (230) from the input end to the output end. The test pins (200) have a geometric structure in which the outer tension arm (220) and the inner tension arm (230) extend parallel to each other, so that the ratio (D1 / D2) of the first distance (D1) and the second distance (D2) may be within the range of 0.9 to 1.1. The ratio range may mean that the physical length of the first signal path (SA) and the physical length of the second signal path (SB) are designed to be substantially the same or very similar within an error range.

[0076] When the ratio (D1 / D2) of the first distance (D1) and the second distance (D2) is maintained within the range of 0.9 to 1.1, the test pins (200) can exhibit a technical effect of significantly suppressing signal distortion that occurs during signal transmission in the high-frequency band. When high-speed signals of several gigahertz or higher are transmitted, if the lengths of the paths differ, a difference in the time it takes for the branched signals to reach the output terminal, which is the merging point, may occur, which may result in phase shift or skew. However, the test pins (200) can induce the signals passing through the two paths to be fully combined without phase difference at the output terminal by matching the lengths of the first signal path (SA) and the second signal path (SB) to a ratio close to 1:1. This phase matching can minimize timing errors of high-frequency signals and ensure the reliability of data transmission.

[0077] Through the above length matching, the electromagnetic interaction between two signals flowing in parallel can be balanced. The closed-loop structure formed inside the test pins (200) can stably control its own inductance and capacitance components through a constant length ratio, which can contribute to maintaining the characteristic impedance of the entire signal path to match the target value. The matching of the characteristic impedance can fundamentally prevent the phenomenon of signal reflection or loss due to impedance mismatch. Therefore, by satisfying the above ratio range, the test pins (200) can provide optimal electrical performance not only for high-power transmission but also in high-speed interface testing environments of the latest semiconductor devices (20) where signal integrity is strictly required.

[0078] The closed-loop structure formed by the first signal path (SA) and the second signal path (SB) can be advantageous for maintaining a constant characteristic impedance by allowing the interaction of its own inductance and capacitance components. The gap between the outer tension arm (220) and the inner tension arm (230) can function as a transmission line with air as the dielectric, which can result in improved signal integrity by reducing signal reflection or crosstalk. The multiple test pins (200) can ensure precise signal transmission performance without distortion, even in a test environment for high-performance semiconductor devices (20) that handle high-speed digital signals or RF signals above the GHz band, going beyond simple mechanical contact.

[0079] In exemplary embodiments, the first elastic member (300) and the second elastic member (310) can position a plurality of test pins (200) in suitable locations during the process of performing the reliability test. The first elastic member (300) and the second elastic member (310) may include an insulator. The insulator may block current between the plurality of test pins (200). Because the insulator blocks current between the plurality of test pins (200), the plurality of test pins (200) may electrically connect the substrate pads (110) and the conductive structures (22) of the semiconductor device (20) respectively during the process of performing the reliability test. For example, the insulator may include a polymer, a dielectric, etc. The insulator may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), etc.

[0080] In exemplary embodiments, the first elastic member (300) may be provided inside a plurality of inner tension arms (230). The first elastic member (300) may be placed in an inner region of the plurality of inner tension arms (230), which is a space that deforms when a plurality of test pins (200) are compressed in a vertical direction. The inner region may be a space enclosed by the arc shape of the inner tension arms (230), and the first elastic member (300) may be provided in a shape corresponding to the space and placed in close contact with the inner tension arms (230) or at a predetermined distance. The first elastic member (300) may be made of an insulating material with excellent elastic recovery force, such as rubber, silicone, or a polymer. By having the first elastic member (300) provided in the inner region, it can absorb mechanical stress generated when a plurality of test pins (200) perform repetitive compression and relaxation, and act as a stopper to prevent the inner tension arms (230) from being excessively deformed.

[0081] The first elastic member (300) can reinforce the loss of elasticity during the vertical repetitive movement of a plurality of test pins (200). The first elastic member (300) can perform the function of reinforcing the loss of elasticity of the metal material that may occur during the vertical repetitive movement of a plurality of test pins (200). Generally, pins made of metal material tend to gradually lose their initial elasticity due to fatigue accumulation during long-term repetitive use, but the first elastic member (300) can compensate for this phenomenon of elastic degradation by providing additional elastic restoring force. The first elastic member (300) can assist the bending deformation of the inner tension arms (230) to help the plurality of test pins (200) maintain a constant contact pressure when in contact with a semiconductor device. Accordingly, the plurality of test pins (200) including the first elastic member (300) can secure stable mechanical behavior and electrical contact reliability even in tens of thousands of repetitive test cycles, and can extend the replacement cycle of the pins to reduce maintenance costs.

[0082] In exemplary embodiments, the second elastic member (310) may be positioned adjacent to one side of the base portions (210). The second elastic member (310) may be positioned on the side of or in an adjacent space of the plurality of base portions (210) to assist in structural stability. The base portions (210) are located at the bottom of the plurality of test pins (200) on the test substrate and may serve as reference points for physical contact with the substrate pad. By positioning the second elastic member (310) adjacent to one side of the base portions (210), for example, on a side perpendicular to the longitudinal direction of the pin or in the space between the pins, the plurality of base portions (210) may be prevented from moving due to external shock or vibration. The second elastic member (310) may be formed from a flexible material with excellent shape retention, such as silicon rubber, and may have a structure that adheres to or is pressed into the shape of the base portions (210).

[0083] The second elastic member (310) can support the test pins (200) to maintain their alignment. The second elastic member (310) can support the test pins (200) to maintain their alignment precisely by preventing minute positional changes that may occur when the test pins (200) are exposed to repetitive vertical movement or thermal expansion and contraction. As the pad spacing of the semiconductor device becomes finer, alignment errors of the pins can cause critical contact failures, and the second elastic member (310) can serve as a guide to minimize such errors. By elastically wrapping or supporting the multiple base parts (210), the second elastic member (310) can prevent the pins from tilting and guide them to behave correctly in the vertical direction. Accordingly, a semiconductor device inspection device including the second elastic member (310) can reduce the risk of interference between pins or short circuits even in a high-density pin array environment and secure stable test precision over a long period.

[0084] Since the first elastic member (300) and the second elastic member (310) fix the plurality of test pins (200) together, the first elastic member (300) and the second elastic member (310) can improve the restoring force of the plurality of test pins (200). The first elastic member (300) and the second elastic member (310) can increase the usable time of the plurality of test pins (200). The first elastic member (300) and the second elastic member (310) can maintain an even alignment state of the plurality of test pins (200).

[0085] In exemplary embodiments, the semiconductor device test device (10) may further include a frame (400). The frame (400) may cover a plurality of test pins (200), a first elastic member (300), a second elastic member (310), and a semiconductor device (20) on a test substrate (100). The frame (400) may be provided on the test substrate (100).

[0086] The frame (400) may have a receiving space (410) for receiving a plurality of test pins (200), a first elastic member (300), a second elastic member (310), and a semiconductor device (20). During the process of performing the reliability test, the frame (400) may protect the plurality of test pins (200), the first elastic member (300), the second elastic member (310), and the semiconductor device (20) placed within the receiving space (410) from external impact.

[0087] During the process of performing the above reliability test, the frame (400) can press against a plurality of test pins (200). The plurality of test pins (200) can be pressed by the frame (400) to be positioned more stably. The plurality of elastic members are provided between the plurality of test pins (200) and the frame (400) to absorb pressure applied from the frame (400) and to position the plurality of test pins (200) more stably.

[0088] Specifically, the frame (400) can press a plurality of test pins (200) in a vertical direction (Z direction), and the first elastic member (300) and the second elastic member (310) can connect the plurality of test pins (200) to each other to cushion the rotational force generated between the plurality of test pins (200). The frame (400) can press a plurality of test pins (200) in a vertical direction (Z direction), and the second elastic member (310) can provide the elastic force between the plurality of test pins (200) and the test substrate (100) to position the plurality of test pins (200) more stably.

[0089] As described above, the semiconductor device testing device (10) has a one-body structure in which test pins (200) are connected to outer tension arms (220) and inner tension arms (230) extending from base portions (210) to form a closed loop, thereby enabling the device to independently secure the vertical elastic force required for contact with the semiconductor device (20) without the need for separate complex assembly parts such as coil springs or plungers. This double-arch closed-loop structure distributes the load applied to the test pins (200) to the outside and inside, thereby improving mechanical durability and minimizing structural deformation during repeated compression and relaxation operations, thereby providing stable contact reliability.

[0090] In addition, the semiconductor device inspection device (10) can have excellent electrical characteristics that can transmit high current and high frequency signals up to 3.5A without distortion by overcoming the resistance limit of the conventional coil spring method through a continuous, integrated metal structure that simplifies the path of electrical signals and secures the cross-sectional area. The semiconductor device inspection device (10) can fundamentally prevent contact failure problems caused by internal dust generation or wear by having no joints where friction occurs between parts, and can precisely implement elastic values ​​optimized for various test environments through the adjustment of the thickness ratio of the tension arm or precision machining.

[0091] FIGS. 7 and FIGS. 8 are perspective views showing test pins having modified structures, respectively. The test pins are substantially identical or similar to the semiconductor device testing device described with reference to FIGS. 1 through 6, except for the configuration of the base portion, outer tension arm, inner tension arm, and contact portion. Accordingly, identical or similar components are indicated by identical or similar reference numerals, and a repeated description of identical components is omitted.

[0092] Referring to FIGS. 1 to 8, a plurality of test pins (200) may each have a plurality of base portions (210) that contact substrate pads (110), a plurality of outer tension arms (220) that each extend from the base portions (210) in an arc, a plurality of inner tension arms (230) that each extend from the base portions (210) inside the outer tension arms (220), and a plurality of contact portions (240) that connect the outer tension arms (220) and the inner tension arms (230) to each other and contact a semiconductor device (20).

[0093] A plurality of inner tension arms (230) can each form closed loops with a plurality of outer tension arms (220). By forming a closed-loop shape together with the outer tension arms (220), the inner tension arms (230) can effectively distribute the vertical load applied to the test pins (200) inwardly and outwardly, and reinforce the structural rigidity of the pins.

[0094] As illustrated in FIG. 3, the closed loop may extend from the side (212) of each base part (210) to form the arc. As illustrated in FIG. 7, the closed loop may extend from the upper surface (214) of each base part (210) to form the arc. The closed loop may be structurally connected to a plurality of base parts (210) to form an integrated shape, and the specific starting position of the extension may be varied according to design conditions. The outer tension arms and inner tension arms constituting the closed loop are physically connected to the base parts (210) and may extend in an arc shape that bends upward using the base parts (210) as a support point. This arc-shaped extension structure can serve to prevent pin breakage and improve durability by ensuring that when the closed loop receives a vertical compressive force, the stress is not concentrated at a specific point but is evenly distributed across the entire curved section.

[0095] The above closed loop may extend from each side (212) of the base portions (210) to form the arc. In this case, the tension arms may start from the side of the base portions (210), protrude laterally, or curve gently and extend upward. The structure extending from the side (212) can be advantageously applied when the overall height of the pin needs to be designed to be low, or when the effective length of the tension arm needs to be maximized to achieve flexible elasticity. Depending on the required contact pressure and the allowable displacement of the pin, the designer can select the starting point of the extension of the closed loop from the top surface (214) or the side (212) to achieve optimal mechanical properties.

[0096] The effective length of the tension arms may include a mechanical length measured along the arc section of the outer tension arm (220) and the inner tension arm (230) extending from the base portion (210) to the contact portion (240) with respect to the neutral axis. As the effective length increases, the bending stiffness of the tension arms decreases, so the tension value corresponding to the elastic restoring force or contact pressure at the same displacement may be lowered, and as the effective length decreases, the tension value may be higher. Accordingly, by selecting the extension starting point of the closed loop from the upper surface or the side surface, or by adjusting the radius of curvature or the arc length of the arc, the tension value corresponding to the required contact pressure and allowable displacement can be adjusted.

[0097] The above closed loop may extend from the upper surface (214) of each base part (210) to form the arc. In this case, the outer tension arm and the inner tension arm may rise from the upper plane of the base part (210) in a vertical direction or at a predetermined angle of inclination and start a curved section. The structure extending from the upper surface (214) may be advantageous for directly and stably transmitting the vertical load transmitted from the semiconductor device to the central axis of the base part (210), and may contribute to ensuring the straightness of vertical movement by suppressing the buckling phenomenon of the pin.

[0098] In exemplary embodiments, the plurality of test pins (200) may have an asymmetric structure in which inner tension arms (230) and outer tension arms (220) start from different sides and extend from base portions (210).

[0099] As illustrated in FIG. 8, the inner tension arms (230) may extend and start from the upper surface (214) of the base portions (210), and the outer tension arms (220) may extend and start from the side surface (212) of the base portions (210). As the extension starting points are arranged differently on the upper surface and the side surface, the overall closed-loop shape formed by the inner tension arms (230) and the outer tension arms (220) may have a shape tilted to one side with respect to the vertical axis. The tilted closed-loop structure can induce unique elastic behavior by generating a moment in the lateral direction as well as simple vertical displacement when a vertical load is applied to a plurality of test pins (200).

[0100] The contact portions (240) located at the top of the plurality of test pins (200) may also have a shape that is deflected from the central axis or tilted at a predetermined angle in correspondence with the tilted shape of the closed loop. The contact portions (240) may include a protrusion (242) that protrudes in a specific direction to increase contact reliability with the semiconductor device (20). The contact portions (240) may have a nose shape with a pointed or rounded end, and this protruding shape can effectively perform a wiping action that scrapes the terminal surface of the semiconductor device (20) when the pin is pressed, thereby reducing contact resistance. The shape of the protruding portion may be designed to have different shapes, such as being formed sharper or more gently, depending on the terminal shape of the semiconductor device (20) or the required contact area.

[0101] The base portions (210) may have a cut-out shape with some areas removed to ensure mounting efficiency and structural stability for the test board (100). A beveled or rounded cut portion may be formed on the lower corner of the base portions (210) opposite the direction in which the outer tension arms (220) extend. The cut portion may serve to prevent interference between the base portions (210) of adjacent pins when a plurality of test pins (200) are arranged in a dense pitch, or to secure a space for the solder fillet formed during the soldering process on the test board (100).

[0102] Although it has been described above that all components constituting an embodiment of the present invention are combined or operate as a single unit, the present invention is not necessarily limited to such an embodiment. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate.

[0103] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0104] 10: Semiconductor device inspection device 20: Semiconductor device 22: Conductive structure 100: Test board 102: Page 1 104: Page 2 110: Board pad 120: Test terminal 130: Rewiring 200: Multiple test pins 210: Base section 220: Outer tension arm 230: Inner tension arm 240: Contact part 300: First elastic member 310: Second elastic member 400: Frame 410: Accommodation space

Claims

Claim 1 A test substrate having a first surface and a second surface facing each other, and a plurality of substrate pads provided on the first surface; A semiconductor device testing device comprising: a plurality of base portions each provided on a plurality of substrate pads and electrically connected to a semiconductor device and contacting the substrate pads; a plurality of outer tension arms each extending from the base portions to form an arc; a plurality of inner tension arms each extending from the base portions inside the outer tension arms and forming a closed loop with the outer tension arms; and a plurality of test pins each having a plurality of contact portions connecting the outer tension arms and the inner tension arms to each other and contacting the semiconductor device, wherein each of the outer tension arms has a first width, each of the inner tension arms has a second width thicker than the first width, and the ratio (W2 / W1) of the second width (W2) of each of the inner tension arms to the first width (W1) of each of the outer tension arms is within the range of 1 to 1.

1. Claim 2 In claim 1, the plurality of test pins are semiconductor device inspection devices having a surface roughness less than or equal to a preset reference value, wherein the cut surface is processed by a precision numerical control and grinding process. Claim 3 A semiconductor device inspection device according to claim 1, further comprising a first elastic member provided on the inner side of the plurality of inner tension arms and reinforcing the loss of elasticity during the vertical repetitive movement of the plurality of test pins. Claim 4 A semiconductor device inspection device according to claim 1, further comprising a second elastic member disposed adjacent to one side of the base portions to support maintaining the alignment state of the test pins. Claim 5 A semiconductor device inspection device according to claim 1, wherein the contact portions correspond to the terminal shape of the semiconductor device and have at least one of an upwardly protruding pointed shape, a flat shape, or a stepped shape that increases contact pressure. Claim 6 A semiconductor device inspection device according to claim 1, wherein the closed loop extends from the upper surface or side surface of each of the base parts to form the arc. Claim 7 A semiconductor device inspection device according to claim 1, wherein each of the outer tension arms and each of the inner tension arms connects the base portion and the contact portion and forms a U-shape.

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