Display device and method of manufacturing the same

Abstract

A display device is provided. The display device comprises a first pixel electrode disposed in a first light-emitting region on a substrate, a first light-emitting layer disposed on the first pixel electrode, a second pixel electrode disposed in a second light-emitting region on the substrate, a second light-emitting layer disposed on the second pixel electrode, a first bank surrounding the first and second light-emitting regions, a second bank disposed on the first bank and including a tip protruding from the first bank, a first organic pattern disposed on the second bank and including the same material as the first light-emitting layer, a first inorganic layer disposed on the first light-emitting layer and the first organic pattern, a metal pattern surrounding the second light-emitting region on the first inorganic layer, and a second organic pattern surrounding the second light-emitting region on the metal pattern and including the same material as the second light-emitting layer, wherein the side of the metal pattern has an undercut structure that is recessed inward from the side of the second organic pattern.

Description

Technology Field

[0001] The present invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. Display devices may be flat panel display devices, such as Liquid Crystal Display Devices, Field Emission Display Devices, and Organic Light Emitting Display Devices. Among these flat panel display devices, light-emitting display devices include light-emitting elements in which each pixel of the display panel can emit light independently, thereby enabling the display of images without a backlight unit that provides light to the display panel. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device and a method for manufacturing the same, which can prevent the peeling of layers on the organic material and exclude the situation in which the organic material is exposed to the chemical solution of the strip process during the process of forming light-emitting elements separated for each of the plurality of light-emitting regions without performing a mask process.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device of one embodiment for solving the above problem comprises: a first pixel electrode disposed in a first light-emitting region on a substrate; a first light-emitting layer disposed on the first pixel electrode; a second pixel electrode disposed in a second light-emitting region on the substrate; a second light-emitting layer disposed on the second pixel electrode; a first bank surrounding the first and second light-emitting regions; a second bank disposed on the first bank and including a tip protruding from the first bank; a first organic pattern disposed on the second bank and including the same material as the first light-emitting layer; a first inorganic layer disposed on the first light-emitting layer and the first organic pattern; a metal pattern surrounding the second light-emitting region on the first inorganic layer; and a second organic pattern surrounding the second light-emitting region on the metal pattern and including the same material as the second light-emitting layer, wherein the side of the metal pattern has an undercut structure that is recessed inward from the side of the second organic pattern.

[0006] The metal pattern above may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), and ITGZO (Indium Tin Gallium Zinc Oxide).

[0007] The second organic pattern can cover the side of the second bank adjacent to the second light-emitting region, the side of the first organic pattern, the side of the first inorganic layer, and the side of the metal pattern.

[0008] The above display device may further include a first common electrode disposed between the first light-emitting layer and the first inorganic layer, and a second common electrode disposed on the second light-emitting layer.

[0009] The first and second common electrodes are in contact with the side of the first bank and can be electrically connected through the first bank.

[0010] The above display device may further include a second inorganic layer disposed on the second light-emitting layer and the second organic pattern.

[0011] The display device may further include a third pixel electrode disposed in a third light-emitting region on the substrate, a third light-emitting layer disposed on the third pixel electrode, and a third common electrode disposed on the third light-emitting layer.

[0012] The metal pattern may surround the third light-emitting region on the first inorganic layer, and the second organic pattern may surround the third light-emitting region on the metal pattern.

[0013] The display device may further include a third organic pattern disposed on the second inorganic layer and comprising the same material as the third light-emitting layer, and a third inorganic layer disposed on the third light-emitting layer and the third organic pattern.

[0014] The third organic pattern may cover the side of the second bank adjacent to the third light-emitting region, the side of the first organic pattern, the side of the first inorganic layer, the side of the metal pattern, the side of the second organic pattern, and the side of the second inorganic layer.

[0015] A method for manufacturing a display device according to one embodiment for solving the above problem comprises the steps of: forming first to third pixel electrodes on a substrate; sequentially stacking a sacrificial layer, an insulating layer, a first bank, and a second bank on the first to third pixel electrodes; etching the second bank, the first bank, the insulating layer, and the sacrificial layer to expose the first pixel electrode; forming a first light-emitting layer on the first pixel electrode and forming a first organic pattern on the second bank; forming a first inorganic layer on the first light-emitting layer and the first organic pattern; forming a metal pattern on the first inorganic layer and patterning the metal pattern in an area overlapping with the second pixel electrode; and using the metal pattern as a hard mask to etch the second bank, the first bank, the insulating layer, and the sacrificial layer to expose the second pixel electrode.

[0016] The metal pattern above may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), and ITGZO (Indium Tin Gallium Zinc Oxide).

[0017] The step of exposing the first pixel electrode may include the step of etching the side of the first bank more than the side of the second bank to form a protruding tip of the second bank.

[0018] The step of forming the first light-emitting layer and the first organic pattern may include the step of separating the organic material deposited on the substrate by cutting it with the tip of the second bank into the first light-emitting layer and the first organic pattern.

[0019] The method for manufacturing the above display device may further include the steps of forming a second light-emitting layer on the second pixel electrode and forming a second organic pattern on the metal pattern, forming a second inorganic layer on the second light-emitting layer and the second organic pattern, and sequentially stacking a first to third metal mask on the second inorganic layer and patterning the first to third metal mask in an area overlapping with the third pixel electrode.

[0020] A step of etching the second inorganic layer and the second organic pattern using the third metal mask as a hard mask to expose the metal pattern; and

[0021] The method for manufacturing the above-described display device may further include the step of etching the third metal mask and the metal pattern containing the same metal material.

[0022] The method for manufacturing the above display device may further include the step of removing the second metal mask together while etching the first inorganic layer, the first organic pattern, the second bank, and the first bank using the second metal mask as a hard mask, and the step of removing the first metal mask together while etching the insulating layer and the sacrificial layer using the first metal mask as a hard mask.

[0023] The method for manufacturing the above display device may further include the steps of forming a third light-emitting layer on the third pixel electrode and forming a third organic pattern on the second inorganic layer, forming a third inorganic layer on the third light-emitting layer and the third organic pattern, forming a fourth metal mask that overlaps with the third pixel electrode on the third inorganic layer, and etching the third inorganic layer and the third organic pattern using the fourth metal mask as a hard mask.

[0024] The method for manufacturing the above display device may further include the steps of: forming a plurality of fifth metal masks that overlap with the third pixel electrode on the fourth metal mask and overlap with the second pixel electrode on the second inorganic layer; and etching the second inorganic layer and the second organic pattern using the plurality of fifth metal masks as hard masks.

[0025] The method for manufacturing the above display device further includes the step of etching the plurality of fifth masks and the metal pattern, and the step of etching the metal pattern may include the step of leaving the metal pattern in an area surrounding each of the second and third pixel electrodes.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] According to the display device and the method for manufacturing the same according to the embodiments, by performing deposition and etching processes using a metal pattern or a metal mask to form light-emitting elements separated for each of the multiple light-emitting regions, it is possible to exclude the situation in which organic material is exposed during the photoresist stripping process and prevent the peeling of layers on the organic material.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a cross-sectional view showing a display device according to one embodiment. FIG. 3 is a plan view showing a display portion of a display device according to one embodiment. FIG. 4 is a cross-sectional view showing a part of a display device according to one embodiment. Figure 5 is an enlarged view of area A1 in Figure 4. Figure 6 is an enlarged view of area A2 in Figure 4. FIGS. 7 to 36 are cross-sectional views illustrating the manufacturing process of a display device according to one embodiment. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0034] Specific embodiments will be described below with reference to the attached drawings.

[0035] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0036] Referring to FIG. 1, the display device (10) can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs). For example, the display device (10) can be applied to a television, laptop, monitor, billboard, or display unit of the Internet of Things (IOT). As another example, the display device (10) can be applied to wearable devices such as smart watches, watch phones, glasses displays, and head-mounted displays (HMDs).

[0037] The display device (10) may be formed in a planar shape similar to a rectangle. For example, the display device (10) may have a planar shape similar to a rectangle having a short side in the X-axis direction and a long side in the Y-axis direction. The corners where the short side in the X-axis direction and the long side in the Y-axis direction meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses.

[0038] The display device (10) may include a display panel (100), a display driving unit (200), a circuit board (300), and a touch driving unit (400).

[0039] The display panel (100) may include a main area (MA) and a sub-area (SBA).

[0040] The main area (MA) may include a display area (DA) having pixels that display an image, and a non-display area (NDA) disposed around the display area (DA). The display area (DA) may emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel (100) may include a pixel circuit including switching elements, a pixel defining film defining a light-emitting area or an aperture area, and a self-light-emitting element.

[0041] For example, the self-luminous device may include at least one of an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (QLED) including a quantum dot light-emitting layer, an inorganic light-emitting diode (Inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (Micro LED), but is not limited thereto.

[0042] The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be defined as an edge area of ​​the main area (MA) of the display panel (100). The non-display area (NDA) may include a gate driver (not shown) that supplies gate signals to gate lines, and fan-out lines (not shown) connecting the display driver (200) and the display area (DA).

[0043] A sub-region (SBA) may extend from one side of a main region (MA). The sub-region (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region (SBA) is bent, the sub-region (SBA) may overlap with the main region (MA) in the thickness direction (Z-axis direction). The sub-region (SBA) may include a pad portion connected to a display driving unit (200) and a circuit board (300). Optionally, the sub-region (SBA) may be omitted, and the display driving unit (200) and the pad portion may be placed in a non-display area (NDA).

[0044] The display driver (200) can output signals and voltages for driving the display panel (100). The display driver (200) can supply data voltages to data lines. The display driver (200) can supply power voltage to power lines and supply gate control signals to the gate driver. The display driver (200) can be formed as an integrated circuit (IC) and mounted on the display panel (100) using a Chip on Glass (COG) method, a Chip on Plastic (COP) method, or an ultrasonic bonding method. For example, the display driver (200) can be placed in a sub-region (SBA) and can overlap with the main region (MA) in the thickness direction (Z-axis direction) by bending the sub-region (SBA). As another example, the display driver (200) can be mounted on a circuit board (300).

[0045] The circuit board (300) can be attached to the pad portion of the display panel (100) using an anisotropic conductive film (ACF). The lead lines of the circuit board (300) can be electrically connected to the pad portion of the display panel (100). The circuit board (300) may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0046] The touch driving unit (400) may be mounted on the circuit board (300). The touch driving unit (400) may be electrically connected to the touch sensing unit of the display panel (100). The touch driving unit (400) may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driving unit (400) may calculate whether an input has been made and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driving unit (400) may be formed as an integrated circuit (IC).

[0047] FIG. 2 is a cross-sectional view showing a display device according to one embodiment.

[0048] Referring to FIG. 2, the display panel (100) may include a display unit (DU), a touch sensing unit (TSU), and a color filter layer (CFL). The display unit (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light-emitting element layer (EML), and an encapsulation layer (TFEL).

[0049] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate (SUB) may include a glass material or a metal material.

[0050] A thin-film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin-film transistor layer (TFTL) may include a plurality of thin-film transistors that constitute a pixel circuit of pixels. The thin-film transistor layer (TFTL) may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver (200) and the data lines, and lead lines connecting the display driver (200) and the pad portion. Each of the thin-film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if the gate driver is formed on one side of the non-display area (NDA) of the display panel (100), the gate driver may include thin-film transistors.

[0051] The thin-film transistor layer (TFTL) can be placed in a display area (DA), a non-display area (NDA), and a sub-area (SBA). The thin-film transistors, gate lines, data lines, and power lines of each pixel of the thin-film transistor layer (TFTL) can be placed in the display area (DA). The gate control lines and fan-out lines of the thin-film transistor layer (TFTL) can be placed in the non-display area (NDA). The lead lines of the thin-film transistor layer (TFTL) can be placed in the sub-area (SBA).

[0052] A light-emitting element layer (EML) may be disposed on a thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include a plurality of light-emitting elements that emit light by sequentially stacking a pixel electrode, a light-emitting layer, and a common electrode, and a pixel defining film that defines the pixels. The plurality of light-emitting elements of the light-emitting element layer (EML) may be disposed in a display area (DA).

[0053] For example, the light-emitting layer may be an organic light-emitting layer containing an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the pixel electrode receives a predetermined voltage through a thin-film transistor of a thin-film transistor layer (TFTL) and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and combine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode and the common electrode may be a cathode electrode, but is not limited thereto.

[0054] As another example, a plurality of light-emitting elements may include a quantum dot light-emitting diode comprising a quantum dot light-emitting layer, an inorganic light-emitting diode comprising an inorganic semiconductor, or a micro-light-emitting diode.

[0055] The encapsulation layer (TFEL) can cover the upper surface and side surface of the light-emitting element layer (EML) and can protect the light-emitting element layer (EML). The encapsulation layer (TFEL) may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer (EML).

[0056] A touch sensing unit (TSU) may be disposed on an encapsulation layer (TFEL). The touch sensing unit (TSU) may include a plurality of touch electrodes for detecting a user's touch in a capacitive manner, and touch lines connecting the plurality of touch electrodes to a touch driving unit (400). For example, the touch sensing unit (TSU) may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0057] As another example, the touch sensing unit (TSU) may be disposed on a separate substrate placed on the display unit (DU). In this case, the substrate supporting the touch sensing unit (TSU) may be a base member that encapsulates the display unit (DU).

[0058] Multiple touch electrodes of the touch sensing unit (TSU) may be placed in a touch sensor area that overlaps with the display area (DA). Touch lines of the touch sensing unit (TSU) may be placed in a touch peripheral area that overlaps with the non-display area (NDA).

[0059] A color filter layer (CFL) may be disposed on a touch sensing unit (TSU). The color filter layer (CFL) may include a plurality of color filters corresponding to each of a plurality of light-emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer (CFL) may absorb a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light. Therefore, the color filter layer (CFL) can prevent color distortion caused by external light reflection.

[0060] Since the color filter layer (CFL) is placed directly on the touch sensing unit (TSU), the display device (10) may not require a separate substrate for the color filter layer (CFL). Therefore, the thickness of the display device (10) can be relatively reduced.

[0061] A sub-region (SBA) of the display panel (100) may extend from one side of the main region (MA). The sub-region (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region (SBA) is bent, the sub-region (SBA) may overlap with the main region (MA) in the thickness direction (Z-axis direction). The sub-region (SBA) may include a pad portion electrically connected to the display driving unit (200) and the circuit board (300).

[0062] FIG. 3 is a plan view showing a display portion of a display device according to one embodiment.

[0063] Referring to FIG. 3, the display unit (DU) may include a display area (DA) and a non-display area (NDA).

[0064] The display area (DA) is an area for displaying images and can be defined as the central area of ​​the display panel (100). The display area (DA) may include a plurality of pixels (SP), a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of power lines (VL). Each of the plurality of pixels (SP) can be defined as a minimum unit that outputs light.

[0065] A plurality of gate lines (GL) can supply gate signals received from the gate driver (210) to a plurality of pixels (SP). The plurality of gate lines (GL) can be extended in the X-axis direction and can be spaced apart from each other in the Y-axis direction intersecting the X-axis direction.

[0066] A plurality of data lines (DL) can supply data voltage received from a display driving unit (200) to a plurality of pixels (SP). The plurality of data lines (DL) can be extended in the Y-axis direction and can be spaced apart from each other in the X-axis direction.

[0067] A plurality of power lines (VL) can supply power voltage received from a display driving unit (200) to a plurality of pixels (SP). Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. A plurality of power lines (VL) may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0068] A non-display area (NDA) may surround a display area (DA). The non-display area (NDA) may include a gate driver (210), fan-out lines (FOL), and gate control lines (GCL). The gate driver (210) may generate a plurality of gate signals based on a gate control signal and may sequentially supply the plurality of gate signals to a plurality of gate lines (GL) according to a set order.

[0069] Fan-out lines (FOL) can extend from the display driver (200) to the display area (DA). The fan-out lines (FOL) can supply data voltage received from the display driver (200) to a plurality of data lines (DL).

[0070] The gate control line (GCL) can be extended from the display driver (200) to the gate driver (210). The gate control line (GCL) can supply a gate control signal received from the display driver (200) to the gate driver (210).

[0071] The sub-area (SBA) may include a display driving unit (200), a display pad area (DPA), and first and second touch pad areas (TPA1, TPA2).

[0072] The display driver (200) can output signals and voltages to drive the display panel (100) to the fan-out lines (FOL). The display driver (200) can supply a data voltage to the data line (DL) through the fan-out lines (FOL). The data voltage can be supplied to a plurality of pixels (SP) and can determine the brightness of the plurality of pixels (SP). The display driver (200) can supply a gate control signal to the gate driver (210) through the gate control line (GCL).

[0073] The display pad area (DPA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may be placed at the edge of the sub-area (SBA). The display pad area (DPA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may be electrically connected to the circuit board (300) using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste).

[0074] The display pad area (DPA) may include a plurality of display pad sections (DP). The plurality of display pad sections (DP) may be electrically connected to a graphics system through a circuit board (300). The plurality of display pad sections (DP) may be connected to the circuit board (300) to receive digital video data and supply digital video data to a display driving unit (200).

[0075] The first touch pad area (TPA1) may be disposed on one side of the display pad area (DPA) and may include a plurality of first touch pad sections (TP1). The plurality of first touch pad sections (TP1) may be electrically connected to a touch driving section (400) disposed on a circuit board (300). The plurality of first touch pad sections (TP1) may supply touch driving signals to a plurality of driving electrodes through a plurality of driving lines.

[0076] The second touch pad area (TPA2) may be disposed on the other side of the display pad area (DPA) and may include a plurality of second touch pad sections (TP2). The plurality of second touch pad sections (TP2) may be electrically connected to a touch driving unit (400) disposed on the circuit board (300). The touch driving unit (400) may receive a touch sensing signal through a plurality of sensing lines connected to the plurality of second touch pad sections (TP2) and may sense a change in mutual capacitance between a driving electrode and a sensing electrode.

[0077] FIG. 4 is a cross-sectional view showing a part of a display device according to one embodiment, FIG. 5 is an enlarged view of area A1 of FIG. 4, and FIG. 6 is an enlarged view of area A2 of FIG. 4.

[0078] Referring to FIGS. 4 to 6, the display panel (100) may include a display unit (DU), a touch sensing unit (TSU), and a color filter layer (CFL). The display unit (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light-emitting element layer (EML), and an encapsulation layer (TFEL).

[0079] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate (SUB) may include a glass material or a metal material.

[0080] The thin film transistor layer (TFTL) may include a first buffer layer (BF1), a light-blocking layer (BML), a second buffer layer (BF2), a thin film transistor (TFT), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first connecting electrode (CNE1), a first protective layer (PAS1), a second connecting electrode (CNE2), and a second protective layer (PAS2).

[0081] The first buffer layer (BF1) may be disposed on a substrate (SUB). The first buffer layer (BF1) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer (BF1) may include a plurality of inorganic films stacked alternately.

[0082] A light-blocking layer (BML) may be disposed on the first buffer layer (BF1). For example, the light-blocking layer (BML) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. As another example, the light-blocking layer (BML) may be an organic film containing a black pigment.

[0083] The second buffer layer (BF2) may be disposed on the first buffer layer (BF1) and the light-blocking layer (BML). The second buffer layer (BF2) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the second buffer layer (BF2) may include a plurality of inorganic films stacked alternately.

[0084] A thin-film transistor (TFT) can be placed on a second buffer layer (BF2) and can form a pixel circuit for each of a plurality of pixels. For example, the thin-film transistor (TFT) may be a driving transistor or a switching transistor of a pixel circuit. The thin-film transistor (TFT) may include a semiconductor region (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

[0085] A semiconductor region (ACT), a source electrode (SE), and a drain electrode (DE) may be disposed on a second buffer layer (BF2). The semiconductor region (ACT), the source electrode (SE), and the drain electrode (DE) may overlap with a light-blocking layer (BML) in the thickness direction. The semiconductor region (ACT) may overlap with a gate electrode (GE) in the thickness direction and may be insulated from the gate electrode (GE) by a gate insulating film (GI). The source electrode (SE) and the drain electrode (DE) may be provided by making the material of the semiconductor region (ACT) conductive.

[0086] The gate electrode (GE) can be placed on the gate insulating film (GI). The gate electrode (GE) can overlap with the semiconductor region (ACT) with the gate insulating film (GI) in between.

[0087] A gate insulating film (GI) may be disposed on a semiconductor region (ACT), a source electrode (SE), and a drain electrode (DE). For example, the gate insulating film (GI) may cover the semiconductor region (ACT), the source electrode (SE), the drain electrode (DE), and a second buffer layer (BF2), and may insulate the semiconductor region (ACT) from the gate electrode (GE). The gate insulating film (GI) may include a contact hole through which a first connecting electrode (CNE1) passes.

[0088] The first interlayer insulating film (ILD1) may be disposed on the gate electrode (GE) and the gate insulating film (GI). The first interlayer insulating film (ILD1) may include a contact hole through which the first connecting electrode (CNE1) passes. The contact hole of the first interlayer insulating film (ILD1) may be connected to the contact hole of the gate insulating film (GI) and the contact hole of the second interlayer insulating film (ILD2).

[0089] A capacitor electrode (CPE) can be placed on the first interlayer insulating film (ILD1). The capacitor electrode (CPE) can overlap with the gate electrode (GE) in the thickness direction. The capacitor electrode (CPE) and the gate electrode (GE) can form a capacitance.

[0090] The second interlayer insulating film (ILD2) may be disposed on the capacitor electrode (CPE) and the first interlayer insulating film (ILD1). The second interlayer insulating film (ILD2) may include a contact hole through which the first connecting electrode (CNE1) passes. The contact hole of the second interlayer insulating film (ILD2) may be connected to the contact hole of the first interlayer insulating film (ILD1) and the contact hole of the gate insulating film (GI).

[0091] The first connecting electrode (CNE1) may be disposed on the second interlayer insulating film (ILD2). The first connecting electrode (CNE1) may electrically connect the drain electrode (DE) of the thin-film transistor (TFT) and the second connecting electrode (CNE2). The first connecting electrode (CNE1) may be inserted into a contact hole provided in the second interlayer insulating film (ILD2), the first interlayer insulating film (ILD1), and the gate insulating film (GI) to make contact with the drain electrode (DE) of the thin-film transistor (TFT).

[0092] A first protective layer (PAS1) may be disposed on a first connecting electrode (CNE1) and a second interlayer insulating film (ILD2). The first protective layer (PAS1) may protect a thin-film transistor (TFT). The first protective layer (PAS1) may include a contact hole through which the second connecting electrode (CNE2) passes.

[0093] The second connecting electrode (CNE2) may be disposed on the first protective layer (PAS1). The second connecting electrode (CNE2) may electrically connect the first connecting electrode (CNE1) and the first pixel electrode (AE1) of the first light-emitting element (ED1). The second connecting electrode (CNE2) may be inserted into a contact hole provided in the first protective layer (PAS1) and contact the first connecting electrode (CNE1).

[0094] The second protective layer (PAS2) may be disposed on the second connecting electrode (CNE2) and the first protective layer (PAS1). The second protective layer (PAS2) may include a contact hole through which the first pixel electrode (AE1) of the first light-emitting element (ED1) passes.

[0095] A light-emitting element layer (EML) may be disposed on a thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include first to third light-emitting elements (ED1, ED2, ED3), a residual pattern (RP), a first insulating layer (IL1), a capping layer (CAP), a bank (BNK), first to third organic patterns (ELP1, ELP2, ELP3), first to third electrode patterns (CEP1, CEP2, CEP3), first to third capping patterns (CLP1, CLP2, CLP3), first to third inorganic layers (TL1, TL2, TL3), and a metal pattern (MP).

[0096] A display device (10) may include a plurality of pixels arranged along a plurality of rows and columns in a display area (DA). Each of the plurality of pixels may include a first to third light-emitting region (EA1, EA2, EA3) defined by a bank (BNK) or a pixel defining film, and may emit light having a predetermined peak wavelength through the first to third light-emitting regions (EA1, EA2, EA3). Each of the first to third light-emitting regions (EA1, EA2, EA3) may be a region where light generated from a light-emitting element of the display device (10) is emitted to the outside of the display device (10).

[0097] The first to third light-emitting regions (EA1, EA2, EA3) can emit light having a predetermined peak wavelength to the outside of the display device (10). The first light-emitting region (EA1) can emit light of a first color, the second light-emitting region (EA2) can emit light of a second color, and the third light-emitting region (EA3) can emit light of a third color. For example, the first color light may be red light having a peak wavelength in the range of about 610 nm to 650 nm, the second color light may be green light having a peak wavelength in the range of about 510 nm to 550 nm, and the third color light may be blue light having a peak wavelength in the range of about 440 nm to 480 nm, but is not limited thereto.

[0098] For example, the area of ​​the third light-emitting region (EA3) may be larger than the area of ​​the first light-emitting region (EA1), and the area of ​​the first light-emitting region (EA1) may be larger than the area of ​​the second light-emitting region (EA2), but is not limited thereto. As another example, the area of ​​the first light-emitting region (EA1), the area of ​​the second light-emitting region (EA2), and the area of ​​the third light-emitting region (EA3) may be substantially the same.

[0099] A first light-emitting element (ED1) may be placed in a first light-emitting region (EA1) on a thin-film transistor layer (TFTL). The first light-emitting element (ED1) may include a first pixel electrode (AE1), a first light-emitting layer (EL1), and a first common electrode (CE1). A second light-emitting element (ED2) may be placed in a second light-emitting region (EA2) on a thin-film transistor layer (TFTL). The second light-emitting element (ED2) may include a second pixel electrode (AE2), a second light-emitting layer (EL2), and a second common electrode (CE2). A third light-emitting element (ED3) may be placed in a third light-emitting region (EA3) on a thin-film transistor layer (TFTL). The third light-emitting element (ED3) may include a third pixel electrode (AE3), a third light-emitting layer (EL3), and a third common electrode (CE3).

[0100] The first to third pixel electrodes (AE1, AE2, AE3) may be disposed on the second protective layer (PAS2). Each of the first to third pixel electrodes (AE1, AE2, AE3) may be electrically connected to the drain electrode (DE) of the thin-film transistor (TFT) through the first and second connecting electrodes (CNE1, CNE2). The first to third pixel electrodes (AE1, AE2, AE3) may be insulated from each other by the first insulating layer (IL1). For example, the first to third pixel electrodes (AE1, AE2, AE3) may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). As another example, the first to third pixel electrodes (AE1, AE2, AE3) may include materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), etc. As yet another example, the first to third pixel electrodes (AE1, AE2, AE3) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0101] A first insulating layer (IL1) may be disposed on a second protective layer (PAS2) and a residual pattern (RP). The first insulating layer (IL1) may cover the edges of the first to third pixel electrodes (AE1, AE2, AE3) and the residual pattern (RP), and may expose a portion of the upper surface of the first to third pixel electrodes (AE1, AE2, AE3). For example, the first insulating layer (IL1) may expose the first pixel electrode (AE1) in the first light-emitting region (EA1), and the first light-emitting layer (EL1) may be disposed directly on the first pixel electrode (AE1). The first insulating layer (IL1) may include an inorganic insulating material. The first insulating layer (IL1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0102] A residual pattern (RP) may be placed on the edge of each of the first to third pixel electrodes (AE1, AE2, AE3). The first insulating layer (IL1) may not be in direct contact with the upper surface of each of the first to third pixel electrodes (AE1, AE2, AE3) by the residual pattern (RP). The residual pattern (RP) may be formed in the manufacturing process of the display device (10) by removing a sacrificial layer ('SFL' in FIG. 7) placed on the first to third pixel electrodes (AE1, AE2, AE3).

[0103] The first to third light-emitting layers (EL1, EL2, EL3) may be organic light-emitting layers made of organic material and may be formed on the first to third pixel electrodes (AE1, AE2, AE3) through a deposition process. For example, in the deposition process of the first to third light-emitting layers (EL1, EL2, EL3), the organic material may be deposited in a direction inclined from the upper surface of the substrate (SUB).

[0104] A first light-emitting layer (EL1) may be placed directly on a first pixel electrode (AE1) in a first light-emitting region (EA1). A portion of the first light-emitting layer (EL1) may fill the space surrounded by the first pixel electrode (AE1), the residual pattern (RP), and the first insulating layer (IL1), and another portion of the first light-emitting layer (EL1) may cover a portion of the upper surface of the first insulating layer (IL1). A second light-emitting layer (EL2) may be placed directly on a second pixel electrode (AE2) in a second light-emitting region (EA2). A portion of the second light-emitting layer (EL2) may fill the space surrounded by the second pixel electrode (AE2), the residual pattern (RP), and the first insulating layer (IL1), and another portion of the second light-emitting layer (EL2) may cover a portion of the upper surface of the first insulating layer (IL1). A third light-emitting layer (EL3) may be placed directly on a third pixel electrode (AE3) in a third light-emitting region (EA3). A portion of the third light-emitting layer (EL3) may be filled in the space surrounded by the third pixel electrode (AE3), the residual pattern (RP), and the first insulating layer (IL1), and another portion of the third light-emitting layer (EL3) may cover a portion of the upper surface of the first insulating layer (IL1).

[0105] For example, when a thin-film transistor (TFT) applies a predetermined voltage to the first pixel electrode (AE1) of the first light-emitting element (ED1) and the first common electrode (CE1) of the first light-emitting element (ED1) receives a common voltage or a cathode voltage, holes and electrons can each move to the first light-emitting layer (EL1) through the hole transport layer and the electron transport layer, and holes and electrons can combine with each other in the first light-emitting layer (EL1) to emit light.

[0106] A first common electrode (CE1) may be disposed on a first light-emitting layer (EL1), a second common electrode (CE2) may be disposed on a second light-emitting layer (EL2), and a third common electrode (CE3) may be disposed on a third light-emitting layer (EL3). The first to third common electrodes (CE1, CE2, CE3) may include a transparent conductive material and may transmit light generated in the first to third light-emitting layers (EL1, EL2, EL3). The first to third common electrodes (CE1, CE2, CE3) may be in contact with the side of a first bank (BNK1), and the first to third common electrodes (CE1, CE2, CE3) may be electrically connected by the first bank (BNK1). For example, the first common electrode (CE1) may receive a common voltage or a low potential voltage. When the first pixel electrode (AE1) receives a voltage corresponding to the data voltage and the first common electrode (CE1) receives a low potential voltage, a potential difference is formed between the first pixel electrode (AE1) and the first common electrode (CE1), thereby allowing the first light-emitting layer (EL1) to emit light.

[0107] A capping layer (CAP) may be disposed on the first to third common electrodes (CE1, CE2, CE3). The capping layer (CAP) may include an inorganic insulating material and may cover the first to third light-emitting elements (ED1, ED2, ED3). The capping layer (CAP) may prevent the first to third light-emitting elements (ED1, ED2, ED3) from being damaged by the outside air. For example, the capping layer (CAP) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0108] A bank (BNK) may be disposed on a first insulating layer (IL1) to define first to third light-emitting regions (EA1, EA2, EA3). A bank (BNK) may surround the first to third light-emitting regions (EA1, EA2, EA3) on a plane. A bank (BNK) may include first and second banks (BNK1, BNK2).

[0109] A first bank (BNK1) may be disposed on a first insulating layer (IL1), and a second bank (BNK2) may be disposed on the first bank (BNK1). The second bank (BNK2) may include a tip protruding from the first bank (BNK1) toward the first to third light-emitting regions (EA1, EA2, EA3). The side of the first bank (BNK1) may have a shape that is recessed inward from the side of the second bank (BNK2). Accordingly, the lower part of the tip of the second bank (BNK2) may have an undercut structure. The thickness of the first bank (BNK1) may be greater than the thickness of the second bank (BNK2).

[0110] The first and second banks (BNK1, BNK2) may include different metal materials, and the etching rates of the first and second banks (BNK1, BNK2) may differ from each other. For example, the etching rate of the first bank (BNK1) may be faster than the etching rate of the second bank (BNK2), and the first bank (BNK1) may be etched more than the second bank (BNK2) during the formation process of the first to third light-emitting regions (EA1, EA2, EA3). Accordingly, the lateral shape of the first and second banks (BNK1, BNK2) may be determined by the difference in etching rates between the first and second banks (BNK1, BNK2). The first bank (BNK1) may include a metal material with high electrical conductivity, and the second bank (BNK2) may include a material with low reflectivity. For example, the first bank (BNK1) may contain aluminum (Al) and the second bank (BNK2) may contain titanium (Ti), but is not limited thereto.

[0111] A bank (BNK) may include an opening forming first to third light-emitting regions (EA1, EA2, EA3) and may overlap with a light-blocking member (BM) of a color filter layer (CFL). A first bank (BNK1) may electrically connect first to third common electrodes (CE1, CE2, CE3) that are spaced apart from each other. A second bank (BNK) may include a material with low reflectivity to reduce external light reflection.

[0112] Bank (BNK) can form first to third light-emitting regions (EA1, EA2, EA3) through a mask process, and each of the first to third light-emitting layers (EL1, EL2, EL3) can be formed in each of the first to third light-emitting regions (EA1, EA2, EA3). When performing a mask process, a structure for mounting the mask may be required, and an excessively large non-display area (NDA) area may be required to control the dispersion of the mask process. Therefore, when the mask process is minimized, the structure for mounting the mask can be omitted, and the non-display area (NDA) area for dispersion control can be minimized.

[0113] The first to third light-emitting elements (ED1, ED2, ED3) can be formed through deposition and etching processes rather than a mask process. By including first and second banks (BNK1, BNK2) containing different metal materials, the inner wall of the bank (BNK) may have a tip structure, and the display device (10) may individually form different layers in the first to third light-emitting regions (EA1, EA2, EA3) through a deposition process. For example, the first light-emitting layer (EL1) and the first organic pattern (ELP1) may be deposited using the same organic material in a deposition process without using a mask, and may be cut and separated by a tip formed on the inner wall of the bank (BNK). The first light-emitting layer (EL1) can be placed in the first light-emitting region (EA1), and the first organic pattern (ELP1) can be placed on a bank (BNK) between the first to third light-emitting regions (EA1, EA2, EA3).

[0114] An organic material for forming a first light-emitting layer (EL1) can be deposited on the front surface of a display device (10), and the organic material of the first light-emitting layer (EL1) deposited in the second and third light-emitting regions (EA2, EA3) can be removed. An organic material for forming a second light-emitting layer (EL2) can be deposited on the front surface of a display device (10), and the organic material of the second light-emitting layer (EL2) deposited in the first and third light-emitting regions (EA1, EA3) can be removed. An organic material for forming a third light-emitting layer (EL3) can be deposited on the front surface of a display device (10), and the organic material of the third light-emitting layer (EL3) deposited in the first and second light-emitting regions (EA1, EA2) can be removed. Accordingly, the display device (10) can form different organic materials in the first to third light-emitting regions (EA1, EA2, EA3) through deposition and etching processes without using a mask process. The display device (10) can reduce manufacturing costs by omitting unnecessary processes and minimize the area of ​​the non-display area (NDA).

[0115] The first organic pattern (ELP1) contains the same organic material as the first light-emitting layer (EL1) and can be placed on the second bank (BNK2). The first organic pattern (ELP1) can cover the side of the second bank (BNK2) adjacent to the first light-emitting region (EA1). The first light-emitting layer (EL1) and the first organic pattern (ELP1) are deposited in the same process and can be separated by cutting with a tip formed on the inner wall of the bank (BNK). Thus, the first organic pattern (ELP1) can be placed on the second bank (BNK2) in an area excluding the first to third light-emitting regions (EA1, EA2, EA3).

[0116] The first electrode pattern (CEP1) includes the same metallic material as the first common electrode (CE1) and can be placed on the first organic pattern (ELP1). The first electrode pattern (CEP1) can cover the side of the first organic pattern (ELP1) adjacent to the first light-emitting region (EA1). The first common electrode (CE1) and the first electrode pattern (CEP1) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Accordingly, the first electrode pattern (CEP1) can be placed on the first organic pattern (ELP1) in an area excluding the first to third light-emitting regions (EA1, EA2, EA3).

[0117] The first capping pattern (CLP1) comprises the same inorganic material as the capping layer (CAP) and can be disposed on the first electrode pattern (CEP1). The first capping pattern (CLP1) can cover the side of the first electrode pattern (CEP1) adjacent to the first light-emitting region (EA1). The capping layer (CAP) and the first capping pattern (CLP1) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Accordingly, the first capping pattern (CLP1) can be disposed on the first electrode pattern (CEP1) in an area excluding the first to third light-emitting regions (EA1, EA2, EA3).

[0118] The first inorganic layer (TL1) may be disposed on the capping layer (CAP) and the first capping pattern (CLP1) of the first light-emitting region (EA1). The first inorganic layer (TL1) may cover the side of the first bank (BNK1) surrounding the first light-emitting region (EA1). The first inorganic layer (TL1) may include an inorganic material to prevent oxygen or moisture from penetrating into the first light-emitting element (ED1). The first inorganic layer (TL1) may be an inorganic encapsulation layer. For example, the first inorganic layer (TL1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0119] A metal pattern (MP) may be placed on a portion of the first inorganic layer (TL1). The metal pattern (MP) may surround each of the second and third light-emitting regions (EA2, EA3) in a planar manner. The side of the metal pattern (MP) may have a shape that is recessed inward from the side of the second organic pattern (ELP2). The metal pattern (MP) may have an undercut structure that is more etched than the second organic pattern (ELP2) placed on top of the metal pattern (MP).

[0120] The metal pattern (MP) can serve as a mask during the formation process of the second light-emitting region (EA2). For example, when the second light-emitting region (EA2) is formed using a photoresist as a mask, the photoresist can be removed through a stripping process after the second light-emitting region (EA2) is formed. If an exposed organic layer exists during the photoresist stripping process, the chemical solution of the stripping process may penetrate the organic layer and dissolve it, and lifting of the layers placed on the organic layer may occur. The metal pattern (MP) may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), and ITGZO (Indium Tin Gallium Zinc Oxide). For example, the metal pattern (MP) can serve as a hard mask during the formation process of the second light-emitting region (EA2), including ITO (Indium Tin Oxide).

[0121] Accordingly, the display device (10) can form a second light-emitting region (EA2) using a metal pattern (MP), thereby excluding the situation in which the first organic pattern (ELP1) is exposed during the stripping process of the photoresist, and can prevent the first electrode pattern (CEP1), the first capping pattern (CLP1), and the first inorganic layer (TL1) on the first organic pattern (ELP1) from peeling off.

[0122] The second organic pattern (ELP2) may contain the same organic material as the second light-emitting layer (EL2) and may be placed on the metal pattern (MP). The second organic pattern (ELP2) may cover the sides of the second bank (BNK2), the first organic pattern (ELP1), the first electrode pattern (CEP1), the first capping pattern (CLP1), the first inorganic layer (TL1), and the metal pattern (MP) adjacent to the second light-emitting region (EA2). The second light-emitting layer (EL2) and the second organic pattern (ELP2) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the second organic pattern (ELP2) may be placed on the metal pattern (MP) in an area adjacent to the second and third light-emitting regions (EA2, EA3).

[0123] The second electrode pattern (CEP2) includes the same metallic material as the second common electrode (CE2) and can be placed on the second organic pattern (ELP2). The second electrode pattern (CEP2) can cover the side of the second organic pattern (ELP2) adjacent to the second light-emitting region (EA2). The second common electrode (CE2) and the second electrode pattern (CEP2) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Thus, the second electrode pattern (CEP2) can be placed on the second organic pattern (ELP2) in an area adjacent to the second and third light-emitting regions (EA2, EA3).

[0124] The second capping pattern (CLP2) comprises the same inorganic material as the capping layer (CAP) and can be disposed on the second electrode pattern (CEP2). The second capping pattern (CLP2) can cover the side of the second electrode pattern (CEP2) adjacent to the second light-emitting region (EA2). The capping layer (CAP) and the second capping pattern (CLP2) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Thus, the second capping pattern (CLP2) can be disposed on the second electrode pattern (CEP2) in an area adjacent to the second and third light-emitting regions (EA2, EA3).

[0125] The second inorganic layer (TL2) may be disposed on the capping layer (CAP) and the second capping pattern (CLP2) of the second light-emitting region (EA2). The second inorganic layer (TL2) may cover the side of the first bank (BNK1) surrounding the second light-emitting region (EA2). The second inorganic layer (TL2) may include an inorganic material to prevent oxygen or moisture from penetrating into the second light-emitting element (ED2). The second inorganic layer (TL2) may be an inorganic encapsulation layer. For example, the second inorganic layer (TL2) may be made of the material exemplified in the first inorganic layer (TL1).

[0126] The third organic pattern (ELP3) may contain the same organic material as the third light-emitting layer (EL3) and may be disposed on the second inorganic layer (TL2). The third organic pattern (ELP3) may cover the sides of the second bank (BNK2), the first organic pattern (ELP1), the first electrode pattern (CEP1), the first capping pattern (CLP1), the first inorganic layer (TL1), the metal pattern (MP), the second organic pattern (ELP2), the second electrode pattern (CEP2), the second capping pattern (CLP2), and the second inorganic layer (TL2) adjacent to the third light-emitting region (EA3). The third light-emitting layer (EL3) and the third organic pattern (ELP3) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the third organic pattern (ELP3) may be disposed on the second inorganic layer (TL2) in an area adjacent to the third light-emitting region (EA3).

[0127] The third electrode pattern (CEP3) comprises the same metallic material as the third common electrode (CE3) and can be placed on the third organic pattern (ELP3). The third electrode pattern (CEP3) can cover the side of the third organic pattern (ELP3) adjacent to the third light-emitting region (EA3). The third common electrode (CE3) and the third electrode pattern (CEP3) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Thus, the third electrode pattern (CEP3) can be placed on the third organic pattern (ELP3) in an area adjacent to the third light-emitting region (EA3).

[0128] The third capping pattern (CLP3) comprises the same inorganic material as the capping layer (CAP) and can be disposed on the third electrode pattern (CEP3). The third capping pattern (CLP3) can cover the side of the third electrode pattern (CEP3) adjacent to the third light-emitting region (EA3). The capping layer (CAP) and the third capping pattern (CLP3) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Thus, the third capping pattern (CLP3) can be disposed on the third electrode pattern (CEP3) in an area adjacent to the third light-emitting region (EA3).

[0129] The third inorganic layer (TL3) may be disposed on the capping layer (CAP) and the third capping pattern (CLP3) of the third light-emitting region (EA3). The third inorganic layer (TL3) may cover the side of the first bank (BNK1) surrounding the third light-emitting region (EA3). The third inorganic layer (TL3) may include an inorganic material to prevent oxygen or moisture from penetrating into the third light-emitting element (ED3). The third inorganic layer (TL3) may be an inorganic encapsulation layer. For example, the third inorganic layer (TL3) may be made of the material exemplified in the first inorganic layer (TL1).

[0130] The encapsulation layer (TFEL) can be disposed on the first to third inorganic films (TL1, TL2, TL3) to cover the light-emitting element layer (EML). The encapsulation layer (TFEL) may include the first and second encapsulation layers (TFE1, TFE2).

[0131] The first encapsulation layer (TFE1) can be disposed on the first to third inorganic films (TL1, TL2, TL3) to flatten the top surface of the light-emitting element layer (EML). The first encapsulation layer (TFE1) may include an organic material to protect the light-emitting element layer (EML) from foreign substances such as dust. For example, the first encapsulation layer (TFE1) may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first encapsulation layer (TFE1) may be formed by curing a monomer or applying a polymer.

[0132] The second encapsulation layer (TFE2) may be disposed on the first encapsulation layer (TFE1). The second encapsulation layer (TFE2) may include an inorganic material to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML). For example, the second encapsulation layer (TFE2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0133] A touch sensing unit (TSU) may be disposed on an encapsulation layer (TFEL). The touch sensing unit (TSU) may include a third buffer layer (BF3), a bridge electrode (BRG), a second insulating layer (IL2), a touch electrode (TE), and a third insulating layer (IL3).

[0134] A third buffer layer (BF3) may be disposed on the encapsulation layer (TFEL). The third buffer layer (BF3) may have insulating and optical functions. The third buffer layer (BF3) may include at least one inorganic film. Optionally, the third buffer layer (BF3) may be omitted.

[0135] The bridge electrode (BRG) can be placed on the third buffer layer (BF3). The bridge electrode (BRG) can be placed on a different layer from the touch electrode (TE) to electrically connect adjacent touch electrodes (TE).

[0136] The second insulating layer (IL2) may be disposed on the bridge electrode (BRG) and the third buffer layer (BF3). The second insulating layer (IL2) may have insulating and optical functions. For example, the second insulating layer (IL2) may be an inorganic film comprising at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0137] A touch electrode (TE) may be disposed on a second insulating layer (IL2). The touch electrode (TE) may include a driving electrode and a sensing electrode, and may sense a change in mutual capacitance between the driving electrode and the sensing electrode. The touch electrode (TE) may not overlap with the first to third light-emitting regions (EA1, EA2, EA3). The touch electrode (TE) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0138] A third insulating layer (IL3) may be disposed on the touch electrode (TE) and the second insulating layer (IL2). The third insulating layer (IL3) may have insulating and optical functions. The third insulating layer (IL3) may be made of the material exemplified in the second insulating layer (IL2).

[0139] A color filter layer (CFL) may be disposed on a touch sensing unit (TSU). The color filter layer (CFL) may include a light-blocking member (BM), a plurality of color filters (CF), and a flattening layer (OC).

[0140] A light-shielding member (BM) may be disposed on a third insulating layer (IL3) to surround the first to third optical regions (OPT1, OPT2, OPT3). The light-shielding member (BM) may overlap with the touch electrode (TE). The light-shielding member (BM) may include a light-absorbing material to prevent light reflection. For example, the light-shielding member (BM) may include an inorganic black pigment, an organic black pigment, or an organic blue pigment. The inorganic black pigment may be a metal oxide such as carbon black or titanium black, the organic black pigment may include at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be CI pigment blue, but is not limited thereto. The light-blocking member (BM) can improve the color reproduction rate of the display device (10) by preventing visible light from encroaching and mixing between the first to third light-emitting regions (EA1, EA2, EA3).

[0141] A plurality of color filters (CF) may include first to third color filters (CF1, CF2, CF3). Each of the first to third color filters (CF1, CF2, CF3) may be arranged on the third insulating layer (IL3) to correspond to each of the first to third light-emitting regions (EA1, EA2, EA3).

[0142] A first color filter (CF1) may be placed in a first light-emitting region (EA1) on a third insulating layer (IL3). The first color filter (CF1) may be surrounded by a light-blocking member (BM) on a flat surface. The edge of the first color filter (CF1) may cover a portion of the upper surface of the light-blocking member (BM), but is not limited thereto. The first color filter (CF1) may selectively transmit light of a first color (e.g., red light) and block or absorb light of a second color (e.g., green light) and light of a third color (e.g., blue light). For example, the first color filter (CF1) may be a red color filter and may include a red colorant.

[0143] A second color filter (CF2) may be placed in a second light-emitting region (EA2) on a third insulating layer (IL3). The second color filter (CF2) may be surrounded by a light-blocking member (BM) on a flat surface. The edges of the second color filter (CF2) may cover a portion of the upper surface of the light-blocking member (BM), but are not limited thereto. The second color filter (CF2) may selectively transmit light of a second color (e.g., green light) and block or absorb light of a first color (e.g., red light) and light of a third color (e.g., blue light). For example, the second color filter (CF2) may be a green color filter and may include a green colorant.

[0144] A third color filter (CF3) may be placed in a third light-emitting region (EA3) on a third insulating layer (IL3). The third color filter (CF3) may be surrounded by a light-blocking member (BM) on a flat surface. The edges of the third color filter (CF3) may cover a portion of the upper surface of the light-blocking member (BM), but are not limited thereto. The third color filter (CF3) may selectively transmit light of a third color (e.g., blue light) and block or absorb light of a first color (e.g., red light) and light of a second color (e.g., green light). For example, the third color filter (CF3) may be a blue color filter and may include a blue colorant.

[0145] The first to third color filters (CF1, CF2, CF3) can absorb a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light. Accordingly, the first to third color filters (CF1, CF2, CF3) can prevent color distortion caused by external light reflection.

[0146] A flattening layer (OC) may be disposed on a light-blocking member (BM) and first to third color filters (CF1, CF2, CF3). The flattening layer (OC) may flatten the top of the color filter layer (CFL). For example, the flattening layer (OC) may include an organic insulating material.

[0147] FIGS. 7 to 36 are cross-sectional views illustrating the manufacturing process of a display device according to one embodiment.

[0148] In FIG. 7, the first to third pixel electrodes (AE1, AE2, AE3) may be spaced apart from each other on a thin-film transistor layer (TFTL). The first to third pixel electrodes (AE1, AE2, AE3) may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). As another example, the first to third pixel electrodes (AE1, AE2, AE3) may include materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), etc. As yet another example, the first to third pixel electrodes (AE1, AE2, AE3) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0149] A sacrificial layer (SFL) may be disposed on the first to third pixel electrodes (AE1, AE2, AE3). The sacrificial layer (SFL) may be disposed between the upper surface of the first to third pixel electrodes (AE1, AE2, AE3) and the first insulating layer (IL1). The sacrificial layer (SFL) may include an oxide semiconductor. For example, the sacrificial layer (SFL) may include at least one of IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), and IZO (Indium Tin Oxide).

[0150] The first insulating layer (IL1) may be disposed on the thin-film transistor layer (TFTL) and the sacrificial layer (SFL). The first insulating layer (IL1) may include an inorganic insulating material. The first insulating layer (IL1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0151] A first bank (BNK1) may be placed on a first insulating layer (IL1), and a second bank (BNK2) may be placed on the first bank (BNK1). The thickness of the first bank (BNK1) may be greater than the thickness of the second bank (BNK2).

[0152] The photoresist (PR) can be placed on the second bank (BNK2) so as not to overlap with the first pixel electrode (AE1). The photoresist (PR) can be provided excluding the area where the first light-emitting region (EA1) is to be formed.

[0153] In FIG. 8, the second bank (BNK2), the first bank (BNK1), the first insulating layer (IL1), and the sacrificial layer (SFL) can be sequentially etched to form a first hole (HOL1). The first hole (HOL1) can overlap with the first light-emitting region (EA1).

[0154] The first and second banks (BNK1, BNK2) may be etched by performing at least one of a dry etching process and a wet etching process. For example, the first and second banks (BNK1, BNK2) may be etched first through a dry etching process and etched second through a wet etching process, but are not limited thereto. The first and second banks (BNK1, BNK2) may contain different metal materials, and the etching rates of the first and second banks (BNK1, BNK2) may be different from each other. In a wet etching process, the etching rate of the first bank (BNK1) may be faster than the etching rate of the second bank (BNK2), and the first bank (BNK1) may be etched more than the second bank (BNK2). Accordingly, the lateral shape of the first and second banks (BNK1, BNK2) may be determined by the difference in etching rates between the first and second banks (BNK1, BNK2). The second bank (BNK2) may include a tip protruding from the first bank (BNK1) toward the first hole (HOL1). The side of the first bank (BNK1) may have a shape that is recessed inward from the side of the second bank (BNK2). The lower part of the tip of the second bank (BNK2) may have an undercut structure. The thickness of the first bank (BNK1) may be greater than the thickness of the second bank (BNK2).

[0155] The first bank (BNK1) may include a metal material with high electrical conductivity, and the second bank (BNK2) may include a material with low reflectivity. For example, the first bank (BNK1) may include aluminum (Al), and the second bank (BNK2) may include titanium (Ti), but is not limited thereto.

[0156] The first insulating layer (IL1) and the sacrificial layer (SFL) may be etched by performing at least one of a dry etching process and a wet etching process. For example, the first insulating layer (IL1) may be etched through a dry etching process, and the sacrificial layer (SFL) may be etched through a wet etching process, but is not limited thereto. As the first insulating layer (IL1) and the sacrificial layer (SFL) are etched, at least a portion of the upper surface of the first pixel electrode (AE1) may be exposed. In the wet etching process, the sacrificial layer (SFL) may be etched more than the first insulating layer (IL1) on a plane. When the sacrificial layer (SFL) is etched, a residual pattern (RP) may remain between the first insulating layer (IL1) and the first pixel electrode (AE1). Accordingly, the side of the residual pattern (RP) may have a shape that is recessed inward from the side of the first insulating layer (IL1).

[0157] In FIG. 9, the photoresist (PR) can be removed through a stripping process after the first hole (HOL1) is formed.

[0158] In FIG. 10, the first light-emitting layer (EL1) may be placed directly on the first pixel electrode (AE1) in the first light-emitting region (EA1). A portion of the first light-emitting layer (EL1) may be filled in the space surrounded by the first pixel electrode (AE1), the residual pattern (RP), and the first insulating layer (IL1), and another portion of the first light-emitting layer (EL1) may cover a portion of the upper surface of the first insulating layer (IL1).

[0159] An organic material for forming a first light-emitting layer (EL1) and a first organic pattern (ELP1) can be deposited on the front surface of a display device (10). The first organic pattern (ELP1) may contain the same organic material as the first light-emitting layer (EL1) and may be placed on a second bank (BNK2). The first organic pattern (ELP1) may cover the side of the second bank (BNK2) adjacent to the first light-emitting region (EA1). The first light-emitting layer (EL1) and the first organic pattern (ELP1) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the first organic pattern (ELP1) may be placed on the second bank (BNK2) in an area excluding the first light-emitting region (EA1).

[0160] A first common electrode (CE1) may be disposed on a first light-emitting layer (EL1). The first common electrode (CE1) may include a transparent conductive material and may transmit light generated in the first light-emitting layer (EL1). The first common electrode (CE1) may be in contact with the side of a bank (BNK). Thus, a first light-emitting element (ED1) may be formed in a first hole (HOL1) and may emit light through a first light-emitting region (EA1).

[0161] A metal material for forming a first common electrode (CE1) and a first electrode pattern (CEP1) can be deposited on the front surface of a display device (10). The first electrode pattern (CEP1) may contain the same metal material as the first common electrode (CE1) and may be placed on a first organic pattern (ELP1). The first electrode pattern (CEP1) may cover the side of the first organic pattern (ELP1) adjacent to the first light-emitting region (EA1). The first common electrode (CE1) and the first electrode pattern (CEP1) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the first electrode pattern (CEP1) may be placed on the first organic pattern (ELP1) in an area excluding the first light-emitting region (EA1).

[0162] A capping layer (CAP) may be disposed on a first common electrode (CE1). The capping layer (CAP) may include an inorganic insulating material and may cover a first light-emitting element (ED1). The capping layer (CAP) may prevent the first light-emitting element (ED1) from being damaged by the outside air. For example, the capping layer (CAP) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0163] An inorganic material for forming a capping layer (CAP) and a first capping pattern (CLP1) can be deposited on the front surface of a display device (10). The first capping pattern (CLP1) may contain the same inorganic material as the capping layer (CAP) and may be placed on a first electrode pattern (CEP1). The first capping pattern (CLP1) may cover the side of the first electrode pattern (CEP1) adjacent to the first light-emitting region (EA1). The capping layer (CAP) and the first capping pattern (CLP1) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the first capping pattern (CLP1) may be placed on the first electrode pattern (CEP1) in an area excluding the first light-emitting region (EA1).

[0164] The first inorganic layer (TL1) may be disposed on the capping layer (CAP) and the first capping pattern (CLP1) of the first light-emitting region (EA1). The first inorganic layer (TL1) may cover the side of the first bank (BNK1) surrounding the first light-emitting region (EA1). The first inorganic layer (TL1) may include an inorganic material to prevent oxygen or moisture from penetrating into the first light-emitting element (ED1). The first inorganic layer (TL1) may be an inorganic encapsulation layer. For example, the first inorganic layer (TL1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0165] In FIG. 11, a metal pattern (MP) may be disposed on a first inorganic layer (TL1). A metal material for forming the metal pattern (MP) may be deposited on the front surface of a display device (10). The metal pattern (MP) may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), and ITGZO (Indium Tin Gallium Zinc Oxide).

[0166] In FIG. 12, the photoresist (PR) may be positioned on the metal pattern (MP) so as not to overlap with the second pixel electrode (AE2). The photoresist (PR) may be provided excluding the area where the second light-emitting region (EA2) is to be formed.

[0167] In FIG. 13, the metal pattern (MP) can be etched using a photoresist (PR) as a mask. The metal pattern (MP) can be etched by performing a wet etching process. The metal pattern (MP) can be patterned in an area overlapping with the second pixel electrode (AE2). The metal pattern (MP) can be etched in an area where the second hole ('HOL2' in FIG. 15) or the second light-emitting region (EA2) is to be formed.

[0168] In FIG. 14, the photoresist (PR) can be removed through a stripping process after the metal pattern (MP) is etched. The first organic pattern (ELP1) may not be exposed during the stripping process of the photoresist (PR).

[0169] In FIG. 15, the metal pattern (MP) can serve as a mask during the formation process of the second hole (HOL2). For example, the metal pattern (MP) can serve as a hard mask during the formation process of the second hole (HOL2), including ITO (Indium Tin Oxide).

[0170] For example, when a second hole (HOL2) is formed using a photoresist as a mask, the photoresist can be removed through a stripping process after the second hole (HOL2) is formed. If an exposed organic layer exists during the stripping process of the photoresist, the chemical solution of the stripping process may penetrate the organic layer and dissolve it, and lifting of the layers placed on the organic layer may occur. Accordingly, the display device (10) can exclude the situation in which the first organic pattern (ELP1) is exposed during the stripping process of the photoresist by forming the second hole (HOL2) and the second light-emitting region (EA2) using a metal pattern (MP), and can prevent the first electrode pattern (CEP1), the first capping pattern (CLP1), and the first inorganic layer (TL1) on the first organic pattern (ELP1) from peeling off.

[0171] The first inorganic layer (TL1), the first capping pattern (CLP1), the first electrode pattern (CEP1), the first organic pattern (ELP1), the second bank (BNK2), the first bank (BNK1), the first insulating layer (IL1), and the sacrificial layer (SFL) can be sequentially etched to form a second hole (HOL2). The second hole (HOL2) can overlap with the second light-emitting region (EA2). The first inorganic layer (TL1), the first capping pattern (CLP1), the first electrode pattern (CEP1), and the first organic pattern (ELP1) can be etched by performing at least one of a dry etching process and a wet etching process. The process of sequentially etching the second bank (BNK2), the first bank (BNK1), the first insulating layer (IL1), and the sacrificial layer (SFL) may be substantially the same as the process of forming the first hole (HOL1), except that a metal pattern (MP) is used as a hard mask.

[0172] In FIG. 16, the second light-emitting layer (EL2) may be placed directly on the second pixel electrode (AE2) in the second light-emitting region (EA2). A portion of the second light-emitting layer (EL2) may be filled in the space surrounded by the second pixel electrode (AE2), the residual pattern (RP), and the first insulating layer (IL1), and another portion of the second light-emitting layer (EL2) may cover a portion of the upper surface of the first insulating layer (IL1).

[0173] An organic material for forming a second light-emitting layer (EL2) and a second organic pattern (ELP2) can be deposited on the front surface of a display device (10). The second organic pattern (ELP2) may contain the same organic material as the second light-emitting layer (EL2) and may be placed on a metal pattern (MP). The second organic pattern (ELP2) may cover the sides of the second bank (BNK2), the first organic pattern (ELP1), the first electrode pattern (CEP1), the first capping pattern (CLP1), the first inorganic layer (TL1), and the metal pattern (MP) adjacent to the second light-emitting region (EA2). The second light-emitting layer (EL2) and the second organic pattern (ELP2) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the second organic pattern (ELP2) may be placed on the metal pattern (MP) in an area excluding the second light-emitting region (EA2).

[0174] A second common electrode (CE2) may be placed on a second light-emitting layer (EL2). The second common electrode (CE2) may include a transparent conductive material and may transmit light generated in the second light-emitting layer (EL2). The second common electrode (CE2) may be in contact with the side of the bank (BNK). Thus, a second light-emitting element (ED2) may be formed in a second hole (HOL2) and may emit light through a second light-emitting region (EA2).

[0175] A metal material for forming a second common electrode (CE2) and a second electrode pattern (CEP2) can be deposited on the front surface of a display device (10). The second electrode pattern (CEP2) may contain the same metal material as the second common electrode (CE2) and may be placed on a second organic pattern (ELP2). The second electrode pattern (CEP2) may cover the side of the second organic pattern (ELP2) adjacent to the second light-emitting region (EA2). The second common electrode (CE2) and the second electrode pattern (CEP2) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the second electrode pattern (CEP2) may be placed on the second organic pattern (ELP2) in an area excluding the second light-emitting region (EA2).

[0176] A capping layer (CAP) may be placed on the second common electrode (CE2). The capping layer (CAP) may include an inorganic insulating material and may cover the second light-emitting element (ED2). The capping layer (CAP) may prevent the second light-emitting element (ED2) from being damaged by the outside air.

[0177] An inorganic material for forming a capping layer (CAP) and a second capping pattern (CLP2) can be deposited on the front surface of a display device (10). The second capping pattern (CLP2) contains the same inorganic material as the capping layer (CAP) and can be placed on a second electrode pattern (CEP2). The second capping pattern (CLP2) can cover the side of the second electrode pattern (CEP2) adjacent to the second light-emitting region (EA2). The capping layer (CAP) and the second capping pattern (CLP2) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Thus, the second capping pattern (CLP2) can be placed on the second electrode pattern (CEP2) in an area excluding the second light-emitting region (EA2).

[0178] The second inorganic layer (TL2) may be disposed on the capping layer (CAP) and the second capping pattern (CLP2) of the second light-emitting region (EA2). The second inorganic layer (TL2) may cover the side of the second bank (BNK2) surrounding the second light-emitting region (EA2). The second inorganic layer (TL2) may include an inorganic material to prevent oxygen or moisture from penetrating into the second light-emitting element (ED2). The second inorganic layer (TL2) may be an inorganic encapsulation layer. For example, the second inorganic layer (TL2) may be made of the material exemplified in the first inorganic layer (TL1).

[0179] In FIG. 17, the first to third metal masks (MSK1, MSK2, MSK3) may be sequentially disposed on the second inorganic layer (TL2). A metal material for forming the first to third metal masks (MSK1, MSK2, MSK3) may be deposited on the front surface of the display device (10). Each of the first to third metal masks (MSK1, MSK2, MSK3) may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), ITGZO (Indium Tin Gallium Zinc Oxide), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), and lanthanum (La). The first and third metal masks (MSK1, MSK3) may include the same metal material and may include a metal material different from the second metal mask (MSK2). The first and third metal masks (MSK1, MSK3) may include the same metal material as the metal pattern (MP). For example, the first and third metal masks (MSK1, MSK3) may include ITO (Indium Tin Oxide), and the second metal mask (MSK2) may include aluminum (Al), but is not limited thereto.

[0180] In FIG. 18, the photoresist (PR) may be positioned on the metal pattern (MP) so as not to overlap with the third pixel electrode (AE3). The photoresist (PR) may be provided excluding the area where the third light-emitting region (EA3) is to be formed.

[0181] In FIG. 19, the first to third metal masks (MSK1, MSK2, MSK3) can be etched using a photoresist (PR) as a mask. The first to third metal masks (MSK1, MSK2, MSK3) can be etched by performing a wet etching process. The first to third metal masks (MSK1, MSK2, MSK3) can be patterned in an area overlapping with the third pixel electrode (AE3). The first to third metal masks (MSK1, MSK2, MSK3) can be etched in an area where the third hole ('HOL3' in FIG. 23) or the third light-emitting region (EA3) is to be formed.

[0182] In FIG. 20, the photoresist (PR) can be removed through a stripping process after the first to third metal masks (MSK1, MSK2, MSK3) are etched. The first and second organic patterns (ELP1, ELP2) may not be exposed during the stripping process of the photoresist (PR).

[0183] In FIG. 21, the first to third metal masks (MSK1, MSK2, MSK3) can serve as masks during the formation process of the third hole (HOL3). For example, the first and third metal masks (MSK1, MSK3) may include ITO (Indium Tin Oxide), and the second metal mask (MSK2) may include aluminum (Al) to serve as a hard mask during the formation process of the third hole (HOL3).

[0184] Accordingly, the display device (10) can form a third light-emitting region (EA3) using the first to third metal masks (MSK1, MSK2, MSK3), thereby excluding the situation in which the second organic pattern (ELP2) is exposed during the photoresist stripping process and preventing the second electrode pattern (CEP2), the second capping pattern (CLP2), and the second inorganic layer (TL2) on the second organic pattern (ELP2) from peeling off.

[0185] The second inorganic layer (TL2), the second capping pattern (CLP2), the second electrode pattern (CEP2), and the second organic pattern (ELP2) can be etched sequentially. Accordingly, the metal pattern (MP) can be exposed in an area overlapping with the third pixel electrode (AE3), and the third metal mask (MSK) can be exposed in an area not overlapping with the third pixel electrode (AE3). The second inorganic layer (TL2), the second capping pattern (CLP2), the second electrode pattern (CEP2), and the second organic pattern (ELP2) can be etched by performing at least one of a dry etching process and a wet etching process.

[0186] In FIG. 22, the third metal mask (MSK3) and the metal pattern (MP) may contain the same metal material. Accordingly, the third metal mask (MSK3) placed on the front of the display device (10) and the metal pattern (MP) overlapping with the third pixel electrode (AE3) can be etched in the same process, and the second metal mask (MSK2) placed below the third metal mask (MSK3) and the first inorganic film (TL1) placed below the metal pattern (MP) can be exposed.

[0187] In FIG. 23, the first inorganic layer (TL1), the first capping pattern (CLP1), the first electrode pattern (CEP1), the first organic pattern (ELP1), the second bank (BNK2), the first bank (BNK1), the first insulating layer (IL1), and the sacrificial layer (SFL) can be sequentially etched to form a third hole (HOL3).

[0188] The first inorganic layer (TL1), the first capping pattern (CLP1), the first electrode pattern (CEP1), the first organic pattern (ELP1), the second bank (BNK2), and the first bank (BNK1) can be etched using a second metal mask (MSK2) as a hard mask. The etching area of ​​the first bank (BNK1) may be smaller than the etching area of ​​the second bank (BNK2). The second metal mask (MSK2) may be removed together during the etching process of the bank (BNK). The first inorganic layer (TL1), the first capping pattern (CLP1), the first electrode pattern (CEP1), the first organic pattern (ELP1), the second bank (BNK2), and the first bank (BNK1) can be etched by performing at least one of a dry etching process and a wet etching process.

[0189] In FIG. 24, the side of the first bank (BNK1), the first insulating layer (IL1), and the sacrificial layer (SFL) can be etched using the first metal mask (MSK1) as a hard mask. A portion of the first metal mask (MSK1) can be removed together during the etching process of the side of the first bank (BNK1). The side of the first bank (BNK1) may have a shape that is recessed inward from the side of the second bank (BNK2). Accordingly, the second bank (BNK2) may include a tip protruding from the first bank (BNK1) toward the third light-emitting region (EA3), and the lower part of the tip of the second bank (BNK2) may have an undercut structure.

[0190] The remainder of the first metal mask (MSK1) can be completely removed during the etching process of the first insulating layer (IL1) and the sacrificial layer (SFL). As the first insulating layer (IL1) and the sacrificial layer (SFL) are etched, at least a portion of the upper surface of the third pixel electrode (AE3) may be exposed. The sacrificial layer (SFL) may be etched more than the first insulating layer (IL1) on a planar surface. When the sacrificial layer (SFL) is etched, a residual pattern (RP) may remain between the first insulating layer (IL1) and the third pixel electrode (AE3).

[0191] In FIG. 25, the third light-emitting layer (EL3) may be placed directly on the third pixel electrode (AE3) in the third light-emitting region (EA3). A portion of the third light-emitting layer (EL3) may be filled in the space surrounded by the third pixel electrode (AE3), the residual pattern (RP), and the first insulating layer (IL1), and another portion of the third light-emitting layer (EL3) may cover a portion of the upper surface of the first insulating layer (IL1).

[0192] An organic material for forming a third light-emitting layer (EL3) and a third organic pattern (ELP3) can be deposited on the front surface of a display device (10). The third organic pattern (ELP3) may contain the same organic material as the third light-emitting layer (EL3) and may be placed on a second inorganic layer (TL2). The third organic pattern (ELP3) may cover the sides of a second bank (BNK2), a first organic pattern (ELP1), a first electrode pattern (CEP1), a first capping pattern (CLP1), a first inorganic layer (TL1), a metal pattern (MP), a second organic pattern (ELP2), a second electrode pattern (CEP2), a second capping pattern (CLP2), and a second inorganic layer (TL2) adjacent to the third light-emitting region (EA3). The third light-emitting layer (EL3) and the third organic pattern (ELP3) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Accordingly, the third organic pattern (ELP3) can be placed on the second inorganic layer (TL2) in an area excluding the third light-emitting region (EA3).

[0193] A third common electrode (CE3) may be placed on a third light-emitting layer (EL3). The third common electrode (CE3) may include a transparent conductive material and may transmit light generated in the third light-emitting layer (EL3). The third common electrode (CE3) may be in contact with the side of the bank (BNK). Thus, a third light-emitting element (ED3) may be formed in a third hole (HOL3) and may emit light through a third light-emitting region (EA3).

[0194] A metal material for forming a third common electrode (CE3) and a third electrode pattern (CEP3) can be deposited on the front surface of the display device (10). The third electrode pattern (CEP3) may contain the same metal material as the third common electrode (CE3) and may be placed on a third organic pattern (ELP3). The third electrode pattern (CEP3) may cover the side of the third organic pattern (ELP3) adjacent to the third light-emitting region (EA3). The third common electrode (CE3) and the third electrode pattern (CEP3) may be deposited in the same process, but may be cut by a tip formed on the inner wall of the bank (BNK). Thus, the third electrode pattern (CEP3) may be placed on the third organic pattern (ELP3) in an area excluding the third light-emitting region (EA3).

[0195] A capping layer (CAP) may be placed on the third common electrode (CE3). The capping layer (CAP) may include an inorganic insulating material and may cover the third light-emitting element (ED3). The capping layer (CAP) may prevent the third light-emitting element (ED3) from being damaged by the outside air.

[0196] An inorganic material for forming a capping layer (CAP) and a third capping pattern (CLP3) can be deposited on the front surface of the display device (10). The third capping pattern (CLP3) contains the same inorganic material as the capping layer (CAP) and can be placed on the third electrode pattern (CEP3). The third capping pattern (CLP3) can cover the side of the third electrode pattern (CEP3) adjacent to the third light-emitting region (EA3). The capping layer (CAP) and the third capping pattern (CLP3) can be deposited in the same process, but can be cut by a tip formed on the inner wall of the bank (BNK). Thus, the third capping pattern (CLP3) can be placed on the third electrode pattern (CEP3) in an area excluding the third light-emitting region (EA3).

[0197] The third inorganic layer (TL3) may be disposed on the capping layer (CAP) and the third capping pattern (CLP3) of the third light-emitting region (EA3). The third inorganic layer (TL3) may cover the side of the second bank (BNK2) surrounding the third light-emitting region (EA3). The third inorganic layer (TL3) may include an inorganic material to prevent oxygen or moisture from penetrating into the third light-emitting element (ED3). The third inorganic layer (TL3) may be an inorganic encapsulation layer. For example, the third inorganic layer (TL3) may be made of the material exemplified in the first inorganic layer (TL1).

[0198] In FIG. 26, the fourth metal mask (MSK4) may be disposed on the third inorganic layer (TL3). A metal material for forming the fourth metal mask (MSK4) may be deposited on the front surface of the display device (10). The fourth metal mask (MSK4) may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), and lanthanum (La).

[0199] In FIG. 27, the photoresist (PR) can be positioned to overlap the third light-emitting element (ED3) on the fourth metal mask (MSK4). The photoresist (PR) can overlap the third light-emitting region (EA3).

[0200] In FIG. 28, the fourth metal mask (MSK4) can be etched using a photoresist (PR) as a mask. The fourth metal mask (MSK4) can be etched by performing a wet etching process. The side of the fourth metal mask (MSK4) may have a shape that is recessed inward from the side of the photoresist (PR). The fourth metal mask (MSK4) may remain in the area overlapping with the third light-emitting area (EA3) by being etched in the first light-emitting region (EA1) and the adjacent region, and the second light-emitting region (EA2) and the adjacent region.

[0201] In FIG. 29, the photoresist (PR) can be removed through a stripping process after the fourth metal mask (MSK4) is etched. The third organic pattern (ELP3) may not be exposed during the stripping process of the photoresist (PR).

[0202] In FIG. 30, the third inorganic layer (TL3), the third capping pattern (CLP3), the third electrode pattern (CEP3), and the third organic pattern (ELP3) can be etched sequentially. For example, the fourth metal mask (MSK4) may include IZO (Indium Zinc Oxide) and serve as a hard mask during the patterning process of the third organic pattern (ELP3).

[0203] Accordingly, the display device (10) can pattern the third organic pattern (ELP3) using the fourth metal mask (MSK4), thereby excluding the situation in which the third organic pattern (ELP3) is exposed during the photoresist stripping process and preventing the third electrode pattern (CEP3), the third capping pattern (CLP3), and the third inorganic layer (TL3) on the third organic pattern (ELP3) from peeling off.

[0204] The third inorganic layer (TL3), the third capping pattern (CLP3), the third electrode pattern (CEP3), and the third organic pattern (ELP3) can be etched by performing at least one of a dry etching process and a wet etching process. Accordingly, the third inorganic layer (TL3), the third capping pattern (CLP3), the third electrode pattern (CEP3), and the third organic pattern (ELP3) can be etched in the first light-emitting region (EA1) and the region adjacent thereto, the second light-emitting region (EA2) and the region adjacent thereto, and can remain in the region adjacent to the third light-emitting region (EA3).

[0205] In FIG. 31, the fifth metal mask (MSK5) may be disposed on the second inorganic layer (TL2) and the fourth metal mask (MSK4). A metal material for forming the fifth metal mask (MSK5) may be deposited on the front surface of the display device (10). The fifth metal mask (MSK5) may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), and lanthanum (La). The fifth metal mask (MSK5) may include the same metal material as the fourth metal mask (MSK4).

[0206] In FIG. 32, a plurality of photoresists (PR) may be arranged to overlap with second and third light-emitting elements (ED2, ED3) on a plurality of fifth metal masks (MSK5). The photoresists (PR) may overlap with second and third light-emitting regions (EA2, EA3).

[0207] In FIG. 33, the fifth metal mask (MSK5) can be etched using photoresists (PR) as a mask. The fifth metal mask (MSK5) can be etched by performing a wet etching process. The sides of the fifth metal mask (MSK5) may have a shape that is recessed inward from the sides of the photoresists (PR). The fifth metal mask (MSK5) may remain in the area overlapping the second and third light-emitting regions (EA2, EA3) by being etched in the first light-emitting region (EA1) and the adjacent region. The fifth metal mask (MSK5) may cover the sides of the third organic pattern (ELP3), the third electrode pattern (CEP3), the third capping pattern (CLP3), and the third inorganic layer (TL3) in the area adjacent to the third light-emitting region (EA3).

[0208] In FIG. 34, the photoresist (PR) can be removed through a stripping process after the fifth metal mask (MSK5) is etched. The second and third organic patterns (ELP2, ELP3) may not be exposed during the stripping process of the photoresist (PR).

[0209] In FIG. 35, the second inorganic layer (TL2), the second capping pattern (CLP2), the second electrode pattern (CEP2), and the second organic pattern (ELP2) can be etched sequentially. For example, the fifth metal mask (MSK5) may include IZO (Indium Zinc Oxide) and serve as a hard mask during the patterning process of the second organic pattern (ELP2).

[0210] Accordingly, the display device (10) can pattern the second organic pattern (ELP2) using the fifth metal mask (MSK5), thereby excluding the situation in which the second organic pattern (ELP2) is exposed during the stripping process of the photoresist, and can prevent the second electrode pattern (CEP2), the second capping pattern (CLP2), and the second inorganic layer (TL2) on the second organic pattern (ELP2) from peeling off.

[0211] The second inorganic layer (TL2), the second capping pattern (CLP2), the second electrode pattern (CEP2), and the second organic pattern (ELP2) can be etched by performing at least one of a dry etching process and a wet etching process. Accordingly, the second inorganic layer (TL2), the second capping pattern (CLP2), the second electrode pattern (CEP2), and the second organic pattern (ELP2) can be etched in the first light-emitting region (EA1) and the region adjacent thereto, and can remain in the region adjacent to the second and third light-emitting regions (EA2, EA3).

[0212] In FIG. 36, the fifth metal mask (MSK5) and the metal pattern (MP) can be etched by performing at least one of a dry etching process and a wet etching process. For example, the fifth metal mask (MSK5) placed in the second and third light-emitting regions (EA2, EA3) can be completely etched through a wet etching process. The metal pattern (MP) can be etched through a wet etching process and may remain in the region surrounding each of the second and third light-emitting regions (EA2, EA3). The metal pattern (MP) may not be etched by being placed beneath the second inorganic layer (TL2), the second capping pattern (CLP2), the second electrode pattern (CEP2), and the second organic pattern (ELP2) adjacent to the second and third light-emitting regions (EA2, EA3). The etching rate of the metal pattern (MP) may be faster than the etching rate of the second organic pattern (ELP2). Therefore, the side of the metal pattern (MP) may have a shape that is recessed inward from the side of the second organic pattern (ELP2).

[0213] The first encapsulation layer (TFE1) can be disposed on the first to third inorganic films (TL1, TL2, TL3) to flatten the top surface of the light-emitting element layer (EML). The first encapsulation layer (TFE1) may include an organic material to protect the light-emitting element layer (EML) from foreign substances such as dust.

[0214] The second encapsulation layer (TFE2) may be disposed on the first encapsulation layer (TFE1). The second encapsulation layer (TFE2) may contain an inorganic material to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML).

[0215] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0216] 10: Display device 100: Display panel 200: Display driver 210: Gate driver 300: Circuit board 400: Touch driver SUB: Substrate TFTL: Thin-film transistor layer BNK1, BNK2: 1st and 2nd Banks ED1, ED2, ED3: First to third light-emitting elements ELP1, ELP2, ELP3: First to third organic patterns CEP1, CEP2, CEP3: First to third electrode patterns CLP1, CLP2, CLP3: 1st to 3rd capping patterns TL1, TL2, TL3: 1st to 3rd inorganic layers MP: Metal pattern TFEL: Encapsulation layer TSU: Touch Sensing Unit CFL: Color Filter Layer

Claims

Claim 1 A display device comprising: a first pixel electrode disposed in a first light-emitting region on a substrate; a first light-emitting layer disposed on the first pixel electrode; a second pixel electrode disposed in a second light-emitting region on the substrate; a second light-emitting layer disposed on the second pixel electrode; a first bank surrounding the first and second light-emitting regions; a second bank disposed on the first bank and including a tip protruding from the first bank; a first organic pattern disposed on the second bank and including the same material as the first light-emitting layer; a first inorganic layer disposed on the first light-emitting layer and the first organic pattern; a metal pattern surrounding the second light-emitting region on the first inorganic layer; and a second organic pattern surrounding the second light-emitting region on the metal pattern and including the same material as the second light-emitting layer, wherein the side of the metal pattern has an undercut structure that is recessed inward from the side of the second organic pattern. Claim 2 A display device according to claim 1, wherein the metal pattern comprises at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), and ITGZO (Indium Tin Gallium Zinc Oxide). Claim 3 In claim 1, the second organic pattern is a display device covering the side of the second bank adjacent to the second light-emitting region, the side of the first organic pattern, the side of the first inorganic layer, and the side of the metal pattern. Claim 4 A display device according to claim 1, further comprising: a first common electrode disposed between the first light-emitting layer and the first inorganic layer; and a second common electrode disposed on the second light-emitting layer. Claim 5 In claim 4, the first and second common electrodes are in contact with the side of the first bank and are electrically connected through the first bank. Claim 6 A display device according to claim 1, further comprising a second inorganic layer disposed on the second light-emitting layer and the second organic pattern. Claim 7 A display device according to claim 6, further comprising: a third pixel electrode disposed in a third light-emitting region on the substrate; a third light-emitting layer disposed on the third pixel electrode; and a third common electrode disposed on the third light-emitting layer. Claim 8 A display device according to claim 7, wherein the metal pattern surrounds the third light-emitting region on the first inorganic layer, and the second organic pattern surrounds the third light-emitting region on the metal pattern. Claim 9 A display device according to claim 7, further comprising: a third organic pattern disposed on the second inorganic layer and comprising the same material as the third light-emitting layer; and a third inorganic layer disposed on the third light-emitting layer and the third organic pattern. Claim 10 In claim 9, the third organic pattern is a display device covering the side of the second bank adjacent to the third light-emitting region, the side of the first organic pattern, the side of the first inorganic layer, the side of the metal pattern, the side of the second organic pattern, and the side of the second inorganic layer. Claim 11 A method for manufacturing a display device comprising: a step of forming first to third pixel electrodes on a substrate; a step of sequentially stacking a sacrificial layer, an insulating layer, a first bank, and a second bank on the first to third pixel electrodes; a step of etching the second bank, the first bank, the insulating layer, and the sacrificial layer to expose the first pixel electrode; a step of forming a first light-emitting layer on the first pixel electrode and forming a first organic pattern on the second bank; a step of forming a first inorganic layer on the first light-emitting layer and the first organic pattern; a step of forming a metal pattern on the first inorganic layer and patterning the metal pattern in an area overlapping with the second pixel electrode; and a step of using the metal pattern as a hard mask to etch the second bank, the first bank, the insulating layer, and the sacrificial layer to expose the second pixel electrode. Claim 12 A method for manufacturing a display device according to claim 11, wherein the metal pattern comprises at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), ITGO (Indium Tin Gallium Oxide), and ITGZO (Indium Tin Gallium Zinc Oxide). Claim 13 A method for manufacturing a display device according to claim 11, wherein the step of exposing the first pixel electrode comprises the step of etching the side of the first bank more than the side of the second bank to form a protruding tip of the second bank. Claim 14 A method for manufacturing a display device according to claim 13, wherein the step of forming the first light-emitting layer and the first organic pattern comprises the step of separating the organic material deposited on the substrate into the first light-emitting layer and the first organic pattern by cutting it with a tip of the second bank. Claim 15 A method for manufacturing a display device according to claim 11, further comprising the steps of: forming a second light-emitting layer on the second pixel electrode and forming a second organic pattern on the metal pattern; forming a second inorganic layer on the second light-emitting layer and the second organic pattern; and sequentially stacking first to third metal masks on the second inorganic layer and patterning the first to third metal masks in an area overlapping with the third pixel electrode. Claim 16 A method for manufacturing a display device according to claim 15, further comprising the step of etching the second inorganic layer and the second organic pattern using the third metal mask as a hard mask to expose the metal pattern; and the step of etching the third metal mask and the metal pattern comprising the same metal material. Claim 17 A method for manufacturing a display device according to claim 16, further comprising: a step of removing the second metal mask together while etching the first inorganic layer, the first organic pattern, the second bank, and the first bank using the second metal mask as a hard mask; and a step of removing the first metal mask together while etching the insulating layer and the sacrificial layer using the first metal mask as a hard mask. Claim 18 A method for manufacturing a display device according to claim 17, further comprising the steps of: forming a third light-emitting layer on the third pixel electrode and forming a third organic pattern on the second inorganic layer; forming a third inorganic layer on the third light-emitting layer and the third organic pattern; forming a fourth metal mask that overlaps with the third pixel electrode on the third inorganic layer; and etching the third inorganic layer and the third organic pattern using the fourth metal mask as a hard mask. Claim 19 A method for manufacturing a display device according to claim 18, further comprising: a step of forming a plurality of fifth metal masks that overlap with the third pixel electrode on the fourth metal mask and overlap with the second pixel electrode on the second inorganic layer; and a step of etching the second inorganic layer and the second organic pattern using the plurality of fifth metal masks as hard masks. Claim 20 A method for manufacturing a display device according to claim 19, further comprising the step of etching the plurality of fifth masks and the metal pattern, wherein the step of etching the metal pattern comprises the step of leaving the metal pattern in an area surrounding each of the second and third pixel electrodes.

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