Antenna substrate

Abstract

A circuit board according to an embodiment comprises a first substrate layer; a second substrate layer disposed on the first substrate layer; a third substrate layer disposed below the first substrate layer; a first solder resist layer disposed on the second substrate layer; and a second solder resist layer disposed below the third substrate layer, wherein the third substrate layer constitutes an antenna portion, and the second substrate layer constitutes a driving portion that drives the antenna portion, and the thickness of the first solder resist layer is greater than the thickness of the second solder resist layer.

Description

Technology Field

[0001] The embodiments relate to circuit boards, and in particular to circuit boards capable of minimizing warpage and methods for manufacturing the same. Background Technology

[0002] A printed circuit board (PCB) is a circuit board that electrically connects or mechanically fixes certain electronic components and is composed of an insulating layer such as phenolic resin or epoxy resin and a copper foil layer attached to the insulating layer to form a certain wiring pattern.

[0003] These circuit boards are broadly classified according to the number of layers into single-sided circuit boards, in which wiring is formed on only one side of the insulating layer; double-sided circuit boards, in which wiring is formed on both sides of the insulating layer; and multilayer circuit boards, in which wiring is formed in multiple layers.

[0004] During the manufacturing process of such circuit boards, warpage may occur as the circuit board undergoes a heat treatment process. As electronic products become smaller and thinner, circuit boards are also becoming thinner, and as thinning progresses, the defect rate caused by warpage can become a problem. The causes of warpage are diverse, including differences in the coefficient of thermal expansion (CTE) and elastic modulus between the insulating material and the metal circuit.

[0005] In addition, recently, to improve process productivity during substrate package manufacturing, multiple circuit board units are manufactured into a single strip structure, which is commonly referred to as a circuit board strip.

[0006] At this time, circuit board units are arranged in the central area of ​​the circuit board strip, and alignment holes are formed in the outer area for the automation of the strip inspection process or assembly process.

[0007] At this time, if the strip bending phenomenon occurs during the manufacturing of the circuit board strip as described above, there is a problem in that automated processes such as the strip inspection process and assembly process cannot be carried out. The problem to be solved

[0008] In the embodiment, we aim to provide a circuit board and a method for manufacturing the same that can improve reliability by minimizing the occurrence of warpage of the circuit board.

[0009] In addition, the embodiment aims to provide a circuit board and a method for manufacturing the same, which minimizes overall warping of the circuit board by controlling the thickness of a first solder resist layer disposed on the top of the circuit board.

[0010] In addition, the embodiment aims to provide a circuit board and a method for manufacturing the same, which minimizes overall warping of the circuit board by controlling the thickness of a second solder resist layer placed at the bottom of the circuit board.

[0011] In addition, the embodiment aims to provide a circuit board and a method for manufacturing the same, which minimizes overall warping of the circuit board by controlling the thickness of the first outermost circuit pattern layer disposed on the top of the circuit board.

[0012] In addition, in the embodiment, the overall bending of the circuit board can be minimized by adjusting the thickness of the second outer layer circuit pattern placed at the bottom of the circuit board.

[0013] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below. means of solving the problem

[0014] A circuit board according to an embodiment comprises a first substrate layer; a second substrate layer disposed on the first substrate layer; a third substrate layer disposed below the first substrate layer; a first solder resist layer disposed on the second substrate layer; and a second solder resist layer disposed below the third substrate layer, wherein the third substrate layer constitutes an antenna portion, and the second substrate layer constitutes a driving portion that drives the antenna portion, and the thickness of the first solder resist layer is greater than the thickness of the second solder resist layer.

[0015] In addition, the thickness of the first solder resist layer has a range between 130% and 200% of the thickness of the second solder resist layer.

[0016] In addition, the thickness of the first solder resist layer satisfies the range of 16㎛ to 20㎛, and the thickness of the second solder resist layer satisfies the range of 10㎛ to 15㎛.

[0017] Additionally, the second substrate layer includes a first inner circuit pattern layer and a first outermost circuit pattern layer, and the third substrate layer includes a second inner circuit pattern layer and a second outermost circuit pattern layer, and the thickness of the first inner circuit pattern layer is greater than the respective thicknesses of the first inner circuit pattern layer, the second inner circuit pattern layer, and the second outermost circuit pattern layer.

[0018] In addition, the first inner circuit pattern layer is a plurality of times, and the thickness of the first outermost circuit pattern layer is greater than the average value of the thicknesses of the plurality of first inner circuit pattern layers.

[0019] In addition, the thickness of the first outermost circuit pattern layer satisfies a range of 16㎛ to 20㎛.

[0020] In addition, the average value of the respective areas of the first inner circuit pattern layer and the first outermost circuit pattern layer is greater than the average value of the respective areas of the second inner circuit pattern layer and the second outermost circuit pattern layer.

[0021] Additionally, the second substrate layer includes a first inner insulating layer and a first outermost insulating layer, and the third substrate layer includes a second inner insulating layer and a second outermost insulating layer, and the first inner circuit pattern layer is disposed on the first inner insulating layer, the first outermost circuit pattern layer is disposed on the first outermost insulating layer, the second inner circuit pattern layer is disposed below the second inner insulating layer, and the second outermost circuit pattern layer is disposed below the second outermost insulating layer.

[0022] In addition, the average value of the respective thicknesses of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective thicknesses of the second inner insulating layer and the second outermost insulating layer.

[0023] In addition, the average value of the respective thermal expansion coefficients of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective thermal expansion coefficients of the second inner insulating layer and the second outermost insulating layer.

[0024] In addition, the average value of the respective dielectric constants of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective dielectric constants of the second inner insulating layer and the second outermost insulating layer.

[0025] Meanwhile, an antenna substrate according to an embodiment is an antenna substrate comprising a first region and a second region below the first region, wherein the first region of the antenna substrate is a driving unit that drives an antenna portion formed by the second region, and the second region of the antenna substrate operates by the driving of the driving unit and transmits a transmission signal to the outside or receives a signal transmitted from the outside, wherein the first region includes a first solder resist layer and the second region includes a second solder resist layer, and the thickness of the first solder resist layer is greater than the thickness of the second solder resist layer.

[0026] Additionally, the first region comprises a first circuit pattern layer including a first inner circuit pattern layer and a first outermost circuit pattern layer, and the second region comprises a plurality of second circuit pattern layers, and the thickness of the first outermost circuit pattern layer is greater than the thickness of the first inner circuit pattern layer.

[0027] Meanwhile, a method for manufacturing a circuit board according to an embodiment comprises the steps of: forming a first substrate layer; forming a second substrate layer and a third substrate layer on the upper and lower portions of the first substrate layer, respectively; forming a first solder resist layer on the second substrate layer; and forming a second solder resist layer below the third substrate layer, wherein the thickness of the first solder resist layer is greater than the thickness of the second solder resist layer, and the second substrate layer corresponds to a driving unit connected to a transmitting element and a receiving element, which transmits a transmitting signal transmitted from the transmitting element to the third substrate layer or transmits a receiving signal transmitted from the third substrate layer to the receiving element, and the plurality of second inner circuit pattern layers and the second outermost circuit pattern layer correspond to an antenna unit which transmits a transmitting signal transmitted from the second substrate layer to the outside or receives a signal transmitted from the outside and transmits it to the second substrate layer.

[0028] Additionally, the step of forming the first substrate layer comprises the step of preparing a first insulating layer and the step of forming a first and second circuit pattern layer on the upper and lower surfaces, respectively, of the first insulating layer, and the step of forming the second substrate layer and the third substrate layer comprises the step of forming a second substrate layer on the upper part of the first substrate layer, comprising a plurality of first inner insulating layers, a first outermost insulating layer above the plurality of first inner insulating layers, a plurality of first inner circuit pattern layers above the plurality of first inner insulating layers, and a first outermost circuit pattern layer above the first outermost insulating layer, and a third substrate layer on the lower part of the second substrate layer, comprising a plurality of second inner insulating layers, a second outermost insulating layer below the plurality of second inner insulating layers, a plurality of second inner circuit pattern layers below the plurality of second inner insulating layers, and a second outermost circuit pattern layer below the second outermost insulating layer, wherein the first outermost circuit pattern layer comprises the average value of the thickness of each of the plurality of first inner circuit pattern layers and the thickness of each of the plurality of second inner circuit pattern layers It is greater than the average value. Effects of the invention

[0029] The circuit board in the embodiment may be an antenna board. The circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer. The second substrate layer may be an area corresponding to a driving part connected to a transmitting element and a receiving element in the antenna board. And, the third substrate layer may be an area corresponding to an antenna pattern part including an antenna pattern layer for signal transmission and signal reception.

[0030] In this case, the second substrate layer in the embodiment may include a first solder resist layer, and the third substrate layer may include a second solder resist layer. In this case, the thickness of the first solder resist layer may be greater than the thickness of the second solder resist layer. For example, the thickness of the first solder resist layer may have a range between 130% and 200% of the thickness of the second solder resist layer. In the embodiment, the thickness of the first solder resist layer may be increased, and the thickness of the second solder resist layer may be decreased along with the increase in the thickness of the first solder resist layer. Accordingly, in the embodiment, the overall degree of warping of the circuit board can be drastically reduced, and reliability can be improved accordingly.

[0031] In addition, in the embodiment, the thickness of the circuit pattern layer is varied along with the increase in the thickness of the first solder resist layer and the second solder resist layer. For example, the second substrate layer in the embodiment may include a first inner circuit pattern layer and a first outermost circuit pattern layer. And, the third substrate layer may include a second inner circuit pattern layer and a second outermost circuit pattern layer. Here, the thickness of the first outermost circuit pattern layer in the embodiment may be greater than that of the first inner circuit pattern layer and the second inner circuit pattern layer. Specifically, the first inner circuit pattern layer may include a plurality of layers, and the average value of their thicknesses may be smaller than the thickness of the first outermost circuit pattern layer. In addition, the second inner circuit pattern layer may include a plurality of layers, and the average value of their thicknesses may be smaller than the thickness of the second outermost circuit pattern layer. In addition, the thickness of the first outermost circuit pattern layer may be greater than the thickness of the second outermost circuit pattern layer. Accordingly, in the embodiment, the overall degree of warping of the circuit board can be reduced, and reliability can be improved. Brief explanation of the drawing

[0032] Figure 1 is a drawing showing a circuit board according to a comparative example. Figure 2 is a schematic diagram showing the basic materials of a circuit board according to an embodiment. FIG. 3 is a schematic diagram showing a circuit board according to the first embodiment. Figure 4 is a drawing showing the specific configuration of a circuit board according to an embodiment. FIG. 5 is a drawing showing a circuit board according to a second embodiment. FIG. 6 is a drawing showing a circuit board according to a third embodiment. FIG. 7 is a drawing showing a circuit board according to the fourth embodiment. Specific details for implementing the invention

[0033] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably solely for the ease of drafting the specification and do not inherently possess distinct meanings or roles. Furthermore, in describing embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings, and it should be understood that they include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention.

[0034] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0035] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0036] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0037] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0040] FIG. 1 is a drawing showing a circuit board according to a comparative example. In this case, FIG. 1 may be a circuit board including one unit, or may be a part of a circuit board strip including a plurality of units.

[0041] Referring to FIG. 1 (a), the circuit board according to the comparative example includes a first substrate layer (10), a second substrate layer (20), and a third substrate layer (30).

[0042] In the circuit board according to the comparative example, a second substrate layer (20) and a third substrate layer (30) are arranged on the upper and lower sides, respectively, centered around the first substrate layer (10).

[0043] At this time, the circuit board according to the comparative example may have a three-layer structure based on the circuit pattern layer. Accordingly, the first substrate layer (10) is the first circuit pattern layer. And, the second substrate layer (20) is the first insulating layer (21), the second circuit pattern layer (22), and the first solder resist layer (23) arranged above the first circuit pattern layer.

[0044] Additionally, the third substrate layer (30) is a second insulating layer (31), a third circuit pattern layer (32), and a second solder resist layer (33) disposed below the first circuit pattern layer.

[0045] At this time, the second substrate layer (20) and the third substrate layer (30) are respectively positioned above and below the first substrate layer (10). Here, as the first substrate layer (10) is positioned in the center of the circuit board, the influence of the first substrate layer (10) on the second substrate layer (20) and the influence on the third substrate layer (30) may be the same.

[0046] Here, in the comparative example, the insulating layer, the circuit pattern layer, and the solder resist layer were each laminated without considering the thermal expansion coefficients of the second substrate layer (20) and the third substrate layer (30).

[0047] At this time, when the second substrate layer (20) and the third substrate layer (30) positioned above the first substrate layer (10) have a mutually symmetrical structure, the first thermal expansion coefficient (CTE1') of the second substrate layer (20) and the second thermal expansion coefficient (CTE2') of the third substrate layer (30) may be the same.

[0048] However, in a general circuit board, the second substrate layer (20) and the third substrate layer (30) do not have a symmetrical structure centered on the first substrate layer (10). This is because the design of the second circuit pattern layer (22) constituting the second substrate layer (20) and the third circuit pattern layer (32) constituting the third substrate layer (30) are different from each other, and accordingly, the volume occupied by the second circuit pattern layer (22) and the volume occupied by the third circuit pattern layer (32) within the circuit board are different from each other. Furthermore, as the volumes of the second circuit pattern layer (22) and the third circuit pattern layer (32) are different from each other, the volumes of the first insulating layer (21) and the second insulating layer (31) are also different from each other. In addition, as the volumes of the second circuit pattern layer (22) and the third circuit pattern layer (32) are different from each other, the volumes of the first solder resist layer (23) and the second solder resist layer (33) disposed on the second circuit pattern layer (22) and the third circuit pattern layer (32) are also different from each other.

[0049] And, the second substrate layer (20), which includes a first insulating layer (21), a second circuit pattern layer (22), and a first solder resist layer (23) disposed above the first substrate layer (10), has a first thermal expansion coefficient (CTE1'). Additionally, the third substrate layer (30), which includes a second insulating layer (31), a third circuit pattern layer (32), and a second solder resist layer (33) disposed below the first substrate layer (10), has a second thermal expansion coefficient (CTE2').

[0050] In other words, in the comparative example, as the volume of each layer constituting the second substrate layer (20) and the volume of each layer constituting the third substrate layer (30) are different from each other, a difference in the coefficient of thermal expansion between the second substrate layer (20) and the third substrate layer (30) occurs, and a bending phenomenon of the circuit board occurs according to the difference in the coefficient of thermal expansion.

[0051] That is, referring to Fig. 1(b), in the comparative example, as the circuit board is manufactured without considering the difference in the coefficient of thermal expansion between the second substrate layer (20) and the third substrate layer (30), a bending phenomenon occurs in which the other end of the circuit board is lifted by a first height (h1) relative to one end of the circuit board relative to the reference plane. At this time, the first height in the comparative example was 2.6 mm.

[0052] Specifically, warping may occur in the circuit board due to the difference in the coefficient of thermal expansion between the second substrate layer and the third substrate layer as described above. In this case, the first coefficient of thermal expansion (CTE1') of the second substrate layer may be greater than the second coefficient of thermal expansion (CTE2') of the third substrate layer. Accordingly, the circuit board in the comparative example may warp in the upward direction, where the coefficient of thermal expansion is higher.

[0053] At this time, if the circuit board warps, reliability issues arise during the manufacturing process of the circuit board, and consequently, the automation process cannot proceed normally.

[0054] For example, warping of the circuit board can cause problems in processing circuit patterns or via holes in the correct position, and furthermore, can lead to vacuum suction errors or errors in the transfer process.

[0056] Meanwhile, various solutions have been proposed in the past to solve the problem of bending of circuit boards as described above. In this case, solutions have been proposed that consider various variables, such as changing the material of each layer, changing the design of the circuit pattern layer of each layer, changing the thickness of the circuit pattern layer and the epoxy layer, or changing from a three-layer structure to a single-layer or multi-layer structure.

[0057] However, conventionally, the design of the circuit board is determined by considering the material selected by the customer, the dimensional specifications of each layer, the error range, and the design drawings specified by the customer, and accordingly, among the various variables mentioned above, the items that need to be changed to improve bending were relatively limited.

[0058] In addition, conventionally, the problem of warping was solved by changing the design of the insulating layer or circuit pattern layer corresponding to the inner layer of the circuit board, but this not only complicates the manufacturing process of the circuit board and acts as a factor that increases the manufacturing process time, and furthermore, can act as a problem that makes the automation process of the circuit board impossible.

[0060] Therefore, in this embodiment, we intend to present a method that minimizes the occurrence of warping in a circuit board without causing problems during the manufacturing process of the circuit board.

[0062] Figure 2 is a schematic diagram showing the basic materials of a circuit board according to an embodiment.

[0063] Referring to FIG. 2, the base material may be a panel (PNL) in the form of a copper clad laminate (CCL). In this case, the width of the panel (PNL) in the horizontal direction may be 415 to 430 mm. Also, the width of the panel (PNL) in the vertical direction may be 510 to 550 mm. Here, the width of the panel (PNL) in the horizontal direction may be the width in the minor axis direction, and the width in the vertical direction may be the width in the major axis direction.

[0064] At this time, the panel (PNL) may be divided into a plurality of strips (100). The plurality of strips (100) may be spaced apart at regular intervals in the horizontal and vertical directions within the panel (PNL). For example, one panel (PNL) may be divided into 16 strips (100). That is, one panel (PNL) may be divided into two areas in the horizontal direction and eight areas in the vertical direction, and each of the divided areas may constitute a strip (100).

[0065] Accordingly, the base material may include a first area where a plurality of strips (100) are arranged and a second area of ​​an outer area excluding the first area. The second area may be a surrounding area of ​​the first area.

[0066] Additionally, each strip (100) may be divided into multiple units (200). For example, one strip (100) may be divided into 1,275 units (200). In this case, each unit (200) may have a width of 3 mm in the horizontal direction and a width of 2 mm in the vertical direction. Meanwhile, each unit (200) may constitute a single circuit board. In other words, one panel (PNL) may be divided into 16 strips (100) and 20,400 units (200).

[0067] Meanwhile, a plurality of circuit pattern layers, a plurality of insulating layers, and a plurality of via holes (VH) having a certain size may be formed in one unit (200). For example, a plurality of trapezoidal via holes (VH) having an upper width of 80 μm and a lower width of 60 μm may be formed in one unit (200).

[0068] At this time, about 150 via holes (VH) are formed in one unit (200). Accordingly, one panel (PNL) may contain 20,400 units (200) in which about 150 via holes (VH) are formed. In conclusion, more than 3 million via holes (VH) are formed in one panel (PNL).

[0069] In addition, as circuit wiring has recently become more complex and highly integrated, the patterns constituting the circuit pattern layer are becoming finer, and the number of via holes (VH) is also increasing. Accordingly, as at least 3 million via holes (VH) are formed in a single panel (PNL), it is important to maintain the flatness of the panel (PNL) or strip (200) until the formation of the 3 million via holes (VH) is completed. That is, when laser processing is performed to form via holes, heat is applied to the panel (PNL), and consequently, the surface temperature of the panel (PNL) rises up to 700°C. At this time, the panel (PNL) undergoes repeated expansion and contraction phenomena, and consequently, a warping phenomenon occurs in which wrinkles form on the surface of the panel (PNL), and when laser processing is performed in the state where the wrinkles have formed, the position or shape of the via holes (VH) changes. Therefore, it must be possible to maintain the flatness of the panel (PNL) by minimizing problems such as wrinkles occurring on the panel (PNL).

[0070] Accordingly, in the embodiment, the overall degree of bending of the circuit board strip (100) is minimized by changing the thickness of the solder resist layer placed on the outermost side of the circuit board. Furthermore, in the embodiment, the overall degree of bending of the circuit board strip (100) can be minimized by changing the thickness of the outermost circuit pattern along with changing the thickness of the solder resist layer.

[0072] FIG. 3 is a schematic diagram showing a circuit board according to a first embodiment. FIG. 3 may be a circuit board including one unit, or alternatively, may show a portion of a strip of a circuit board including a plurality of units.

[0073] Referring to FIG. 3, the circuit board may have a plurality of layer structures.

[0074] Specifically, the circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer.

[0075] The first substrate layer may be a layer placed in the center of the circuit board.

[0076] The first substrate layer may include an insulating layer and a circuit pattern layer. For example, the first substrate layer may include a first insulating layer (110), a first circuit pattern layer (112), and a second circuit pattern layer (114).

[0077] The first insulating layer (110) may be a core layer positioned in the center of a laminated structure of a circuit board having a plurality of layer structures. The first insulating layer (110) may include prepreg, but is not limited thereto. However, the first insulating layer (110) may be a core layer and may have a structure in which glass fibers are dispersed within a resin.

[0078] The first circuit pattern layer (112) and the second circuit pattern layer (114) may include a plurality of circuit patterns (or wiring, not shown) that are disposed on the upper surface of the first insulating layer (110) and transmit electrical signals. The first circuit pattern layer (112) and the second circuit pattern layer (114) may be formed of a metal material with high electrical conductivity. To this end, the first circuit pattern layer (112) and the second circuit pattern layer (114) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Additionally, the first circuit pattern layer (112) and the second circuit pattern layer (114) may be formed from a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer (112) and the second circuit pattern layer (114) may be formed from copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0079] The first circuit pattern layer (112) and the second circuit pattern layer (114) can be manufactured using conventional circuit board manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed description is omitted here.

[0081] The second substrate layer may be disposed on the upper side of the first substrate layer. For example, the second substrate layer may be disposed on the upper surface of the first substrate layer. Preferably, the second substrate layer may be disposed on the upper surface of the first circuit pattern layer (112) of the first substrate layer.

[0082] The second substrate layer may include an insulating layer and a circuit pattern layer. For example, the second substrate layer may include a plurality of insulating layers and a plurality of circuit pattern layers.

[0083] Specifically, the second substrate layer may include a second insulating layer (120) and a third insulating layer (130). Additionally, the second substrate layer may include a third circuit pattern layer (122) and a fourth circuit pattern layer (132).

[0084] The second insulating layer (120) may be disposed on the first insulating layer (110). Preferably, the second insulating layer (120) may be disposed on the first insulating layer (110) and covering the first circuit pattern layer (112).

[0085] Additionally, the third circuit pattern layer (122) may be disposed on the second insulating layer (120). Preferably, the third circuit pattern layer (122) may be formed protruding over the upper surface of the second insulating layer (120).

[0086] Additionally, the third insulating layer (130) may be disposed on the second insulating layer (120). Preferably, it may be disposed on the second insulating layer (120) while covering the third circuit pattern layer (122). The third insulating layer (130) may be an insulating layer disposed at the uppermost position in the stacked structure of the circuit board. For example, the third insulating layer (130) may be a first outermost insulating layer disposed at the uppermost position in the stacked structure of the circuit board.

[0087] The fourth circuit pattern layer (132) may be disposed on the third insulating layer (130). For example, the fourth circuit pattern layer (132) may be formed protruding above the upper surface of the third insulating layer (130). The fourth circuit pattern layer (132) may be a circuit pattern layer disposed at the uppermost side in the stacked structure of the circuit board. For example, the fourth circuit pattern layer (132) may be a first outermost circuit pattern layer disposed at the uppermost side in the stacked structure of the circuit board.

[0088] At this time, in the drawing, only one second insulating layer (120) is shown disposed between the first insulating layer (110) and the third insulating layer (130), which is the first outermost insulating layer, in the second substrate layer, but it is not limited thereto. For example, the second substrate layer in the embodiment may include a plurality of second insulating layers disposed between the first insulating layer (110) and the third insulating layer (130). In such a case, a circuit pattern layer may be disposed on the upper surface of each of the plurality of second insulating layers.

[0090] A third substrate layer may be disposed below the first substrate layer. For example, the third substrate layer may be disposed below the lower surface of the first substrate layer. Preferably, the third substrate layer may be disposed above the lower surface of the second circuit pattern layer (114) of the first substrate layer.

[0091] The third substrate layer may include an insulating layer and a circuit pattern layer. For example, the third substrate layer may include a plurality of insulating layers and a plurality of circuit pattern layers.

[0092] Specifically, the third substrate layer may include a fourth insulating layer (140) and a fifth insulating layer (150). Additionally, the third substrate layer may include a fifth circuit pattern layer (142) and a sixth circuit pattern layer (152).

[0093] The fourth insulating layer (140) may be disposed below the first insulating layer (110). Preferably, the fourth insulating layer (140) may be disposed below the first insulating layer (110), covering the second circuit pattern layer (114).

[0094] Additionally, the fifth circuit pattern layer (142) may be disposed below the fourth insulating layer (140). Preferably, the fifth circuit pattern layer (142) may be formed protruding below the lower surface of the fourth insulating layer (140).

[0095] Additionally, the fifth insulating layer (150) may be disposed on the fourth insulating layer (140). Preferably, the fifth insulating layer (150) may be disposed below the fourth insulating layer (140), covering the fifth circuit pattern layer (142). The fifth insulating layer (150) may be an insulating layer disposed at the bottom side in the stacked structure of the circuit board. For example, the fifth insulating layer (150) may be a second outermost insulating layer disposed at the bottom side in the stacked structure of the circuit board.

[0096] The sixth circuit pattern layer (152) may be disposed below the fifth insulating layer (150). For example, the sixth circuit pattern layer (152) may be formed protruding below the lower surface of the fifth insulating layer (150). The sixth circuit pattern layer (152) may be a circuit pattern layer disposed at the bottom side in the stacked structure of the circuit board. For example, the sixth circuit pattern layer (152) may be a second outermost circuit pattern layer disposed at the bottom side in the stacked structure of the circuit board.

[0097] At this time, in the drawing, only one layer of the fourth insulating layer (140) is shown disposed between the first insulating layer (110) and the second outermost insulating layer, the fifth insulating layer (150), in the third substrate layer, but it is not limited thereto. For example, the third substrate layer in the embodiment may include a plurality of fourth insulating layers disposed between the first insulating layer (110) and the fifth insulating layer (150). In such a case, a circuit pattern layer may be disposed on the lower surface of each of the plurality of fourth insulating layers.

[0098] Meanwhile, the circuit board in the embodiment may include a first solder resist layer (160) and a second solder resist layer (170).

[0099] The first solder resist layer (160) may be placed on the second substrate layer. Specifically, the first solder resist layer (160) may be placed on the third insulating layer (130), which is the first outermost insulating layer placed at the top of the second substrate layer. For example, the first solder resist layer (160) may be placed on the fourth circuit pattern layer (132), which is the first outermost circuit pattern layer placed at the top of the second substrate layer. The first solder resist layer (160) may function to protect the surfaces of the first outermost insulating layer, the third insulating layer (130), and the fourth circuit pattern layer (132), which are the first outermost circuit pattern layer.

[0100] The second solder resist layer (170) may be disposed below the third substrate layer. Specifically, the second solder resist layer (170) may be disposed below the fifth insulating layer (150), which is the second outermost insulating layer disposed at the bottom of the second substrate layer. For example, the second solder resist layer (170) may be disposed below the sixth circuit pattern layer (152), which is the second outermost circuit pattern layer disposed at the bottom of the second substrate layer. The second solder resist layer (170) may function to protect the surfaces of the fifth insulating layer (150) and the sixth circuit pattern layer (152), which are the second outermost insulating layer and the second outermost circuit pattern layer, respectively.

[0102] The circuit board of the above-described embodiment may be an antenna board. To this end, the circuit board may be provided for feeding and supporting an antenna pattern. The circuit board may include a first region in which a driving unit is disposed to process a signal to be transmitted through an antenna pattern layer or a signal received through an antenna pattern layer, and a second region in which an antenna pattern portion including a conductive antenna pattern layer is disposed to transmit a signal transmitted through the driving unit of the first region to the outside or receive a signal transmitted from the outside.

[0103] For example, in the circuit board above, the first substrate layer may be a layer for distinguishing between a first region where the driving part is placed and a second region where the antenna pattern part is placed.

[0104] And, the second substrate layer may be disposed on the first substrate layer and, accordingly, may be a first region where the driving unit is disposed. Additionally, the third substrate layer may be a second region where the antenna pattern unit is disposed.

[0105] For example, the second substrate layer may include a transmitting element (not shown) that processes a signal to be transmitted through the antenna pattern portion and / or a receiving element (not shown) that processes a signal to be received through the antenna pattern portion. As an example, the transmitting element or the receiving element may be mounted on a third circuit pattern layer (142) disposed on the uppermost side of the second substrate layer. Furthermore, the second insulating layer (120), the third insulating layer (130), the third circuit pattern layer (122), and the fourth circuit pattern layer (132) constituting the second substrate layer are disposed between the antenna pattern portion and the transmitting element / receiving element, so as to transmit a transmitting signal or a receiving signal to the third substrate layer, thereby driving the antenna portion formed by the third substrate layer.

[0107] Additionally, the third substrate layer may be an antenna unit driven by a driving unit configured by the second substrate layer. The third substrate layer may include an antenna pattern unit. For example, the third substrate layer may include a conductive antenna pattern layer for transmitting a transmission signal or receiving a reception signal. The conductive antenna pattern layer may include a fifth circuit pattern layer (142) and a sixth circuit pattern layer (152) constituting the third substrate layer. The conductive antenna pattern layer including the fifth circuit pattern layer (142) and the sixth circuit pattern layer (152) as described above may be an antenna that resonates in a plurality of resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonant antenna that resonates in different resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonant antenna that resonates in a first frequency band of 24.03 GHz to 25.81 GHz and a second frequency band of 27.07 GHz to 28.80 GHz, respectively.

[0108] At this time, the conductive antenna pattern layer including the fifth circuit pattern layer (142) and the sixth circuit pattern layer (152) can resonate in a resonant frequency band corresponding to a predetermined target frequency. To this end, the third substrate layer including the fifth circuit pattern layer (142) and the sixth circuit pattern layer (152) can be designed to resonate in the resonant frequency band. For example, the resonant frequency band of the fifth circuit pattern layer (142) and the sixth circuit pattern layer (152) can be varied according to the dielectric constant or thickness of the fourth insulating layer (140) and the fifth insulating layer (150) constituting the third substrate layer. Accordingly, the dielectric constant or thickness of the fourth insulating layer (140) and the fifth insulating layer (150) can be determined so that the fifth circuit pattern layer (142) and the sixth circuit pattern layer (152) can resonate in the target frequency band.

[0109] Accordingly, the second substrate layer and the third substrate layer in the embodiment may have an asymmetric structure. For example, the circuit board in the embodiment may have an asymmetric structure centered on the first substrate layer, wherein the second substrate layer disposed on the first substrate layer and the third substrate layer disposed below the first substrate layer may have an asymmetric structure. Here, the asymmetric structure may mean that the thickness and dielectric constant of the second substrate layer are different from the thickness and dielectric constant of the third substrate layer.

[0110] The dielectric constant of the fourth insulating layer (140) and the fifth insulating layer (150) constituting the third substrate layer may be greater than the dielectric constant of the second insulating layer (120) and the third insulating layer (130) constituting the second substrate layer. The thickness of the fourth insulating layer (140) and the fifth insulating layer (150) constituting the third substrate layer may be greater than the thickness of the second insulating layer (120) and the third insulating layer (130) constituting the second substrate layer.

[0111] And, as described above, since the second substrate layer and the third substrate layer have a mutually asymmetric structure centered on the first substrate layer, warpage may occur in the circuit board of the embodiment during the manufacturing process.

[0112] At this time, various variables may be considered as a means to resolve the above-mentioned warping. For example, various variables may be considered, such as changing the material of each layer of the second or third substrate layer to a material with resistance to warping, changing the design of the circuit pattern layer of each layer, changing the thickness of the insulating layer, or changing the number of layers of the circuit board. However, typically, the specifications of a circuit board are determined to suit the product. For example, the material, thickness, tolerance range, and pattern design of each layer constituting the circuit board are already determined by the design drawing corresponding to the product specifications, and accordingly, the items that can be changed to resolve the above-mentioned warping are relatively limited. Accordingly, in the embodiment, the occurrence of warping in the circuit board is minimized by changing the dimensions of the circuit pattern layer while maintaining the product specifications corresponding to the design drawing of the circuit board. For example, in the embodiment, the problem of warping as described above is resolved by changing the thickness of the first outermost circuit pattern layer and / or the second outermost circuit pattern layer placed at the outermost side of the circuit board.

[0114] At this time, the numerical values ​​of each layer of the first substrate layer, the second substrate layer, and the third substrate layer in the comparative example are as shown in Table 1 below.

[0115] thickness Copper foil rate CTE First solder resist layer (160) 15㎛ 80% 4th circuit pattern layer (132) 15㎛ 61% Third insulating layer (130) 20㎛ 2% 1.55 ppm / ℃ Third circuit pattern layer (122) 15㎛ 78% second insulating layer (120) 20㎛ 8% 1.41 ppm / ℃ First circuit pattern layer (112) 25㎛ 76% First insulating layer (110) 100㎛ 4% second circuit pattern layer (114) 25㎛ 72% Fourth insulating layer (140) 100㎛ 2% 1.57 ppm / ℃ 5th circuit pattern layer (142) 15㎛ 54% fifth insulating layer (150) 100㎛ 2% 1.57 ppm / ℃ 6th circuit pattern layer (152) 15㎛ 50% second solder resist layer (170) 15㎛ 96%

[0117] Referring to Table 1, the first insulating layer (110) in the comparative example may have a first thickness (T1). The first insulating layer (110) is a core layer and may have a relatively thick thickness accordingly. For example, the first insulating layer (110) may be 100 μm.

[0118] The second insulating layer (120) and the third insulating layer (130) may be formed on the upper side of the first insulating layer (110), each having a second thickness (T2) and a third thickness (T3). For example, the second thickness (T2) and the third thickness (T3) may each be 20 μm.

[0119] The fourth insulating layer (140) and the fifth insulating layer (150) may be formed on the lower side of the first insulating layer (110), each having a fourth thickness (T4) and a fifth thickness (T5). For example, each of the fourth thickness (T4) and the fifth thickness (T5) may be 100 μm.

[0120] Additionally, the first circuit pattern layer (112) and the second circuit pattern layer (114) may be formed on the upper and lower surfaces of the first insulating layer (110), respectively, having a sixth thickness (T6). For example, the sixth thickness (T6) may be 25 μm.

[0121] Additionally, the third circuit pattern layer (122), the fourth circuit pattern layer (132), the fifth circuit pattern layer (142), and the sixth circuit pattern layer (152) may each be formed on the surface of the corresponding insulating layer with a seventh thickness (T7). The seventh thickness (T7) may be 15 μm.

[0122] In addition, the first solder resist layer (160) and the second solder resist layer (170) in the comparative example have the same thickness. For example, the first solder resist layer (160) and the second solder resist layer (170) may be 15 μm.

[0123] In this case, in the comparative example as shown in Table 1 above, the second substrate layer positioned above the first substrate layer and the third substrate layer positioned below the first substrate layer have different thicknesses or dielectric constants of their respective insulating layers, and furthermore, the copper foil ratios of their respective circuit pattern layers are also different. Here, the copper foil ratio may refer to the ratio of the area on which the circuit pattern layer is positioned to the total surface area of ​​the insulating layer.

[0124] Accordingly, in the case of the structure of the comparative example as shown in Table 1 above, bending of the circuit board occurs due to the mutually asymmetric structure of the second substrate layer and the third substrate layer. For example, in the case of the structure of the comparative example as shown in Table 1, bending of the second substrate layer may occur in the direction in which the third substrate layer is arranged. For example, in the structure of the comparative example as shown in Table 1, bending in the shape of a smile (^) occurs in which the edge regions of the first substrate layer, the second substrate layer, and the third substrate layer bend downward.

[0126] At this time, in the embodiment, the bending of the circuit board can be minimized by changing the thickness of the first solder resist layer (160) and the second solder resist layer (170) placed on the outermost side in the structure of the circuit board.

[0127] Here, in order to improve the above-mentioned bending, the degree of bending was checked when the thickness of the second solder resist layer (170) was changed while the thickness of the first solder resist layer (160) was fixed as follows. That is, the degree of bending according to the change in thickness of the second solder resist layer (170) while the thickness of the first solder resist layer (160) is fixed is as shown in Table 2 below. At this time, the thickness of the solder resist layer in the embodiment should generally have a value between 10㎛ and 20㎛. Table 2 shows the degree of bending according to the change in thickness of the second solder resist layer (170) while the thickness of the first solder resist layer (160) is fixed at 15㎛.

[0128] Thickness of the second solder resist layer (170) Degree of bending 10㎛ 0.35241mm 12㎛ 0.37547mm 14㎛ 0.38942mm 16㎛ 0.4095mm 18㎛ 0.4154mm 20㎛ 0.4352mm

[0129] Generally, when the degree of warping is less than 0.4 mm, or even less than 0.3 mm, normal manufacturing can be performed without reliability issues during the manufacturing process of the circuit board.

[0130] However, as shown in Table 2, it was confirmed that when the thickness of the second solder resist layer (170) is changed while the thickness of the first solder resist layer (160) is fixed, it does not significantly affect the degree of warping of the circuit board.

[0132] Next, to improve the above-mentioned bending, the degree of bending was checked when the thickness of the first solder resist layer (160) was changed while the thickness of the second solder resist layer (170) was fixed as follows. That is, the degree of bending according to the change in thickness of the first solder resist layer (160) while the thickness of the second solder resist layer (170) is fixed is as shown in Table 3 below. At this time, the thickness of the solder resist layer in the embodiment must have a value between 10㎛ and 20㎛. Table 3 shows the degree of bending according to the change in thickness of the first solder resist layer (160) while the thickness of the second solder resist layer (170) is fixed at 15㎛.

[0133] Thickness of the first solder resist layer (160) Degree of bending 10㎛ 0.4924mm 12㎛ 0.4752mm 14㎛ 0.4254mm 16㎛ 0.3652mm 18㎛ 0.2592mm 20㎛ 0.2339mm

[0135] As shown in Table 3 above, it was confirmed that when the thickness of the first solder resist layer (160) is reduced while the thickness of the second solder resist layer (170) is fixed, the degree of warping increases. Also, when the thickness of the first solder resist layer (160) is increased while the thickness of the second solder resist layer (170) is fixed, the degree of warping decreases.

[0136] For example, as shown in Table 3, it was confirmed that the smallest degree of warping occurs when the first solder resist layer (160) is formed with the maximum thickness within the thickness range that the first solder resist layer (160) can have. And, it was confirmed that the largest degree of warping occurs when the first solder resist layer (160) is formed with the minimum thickness within the thickness range that the first solder resist layer (160) can have.

[0137] Accordingly, in the embodiment, the thickness of the first solder resist layer (160) is increased so that the degree of bending of the circuit board resulting therefrom can be minimized.

[0138] Furthermore, in the embodiment, it was confirmed that when the thickness of the first solder resist layer (160) is increased and the thickness of the second solder resist layer (170) is decreased within a limited range, the degree of warping of the circuit board is minimized.

[0139] In other words, it was confirmed that the thickness of the first solder resist layer (160) is greater than the thickness of the second solder resist layer (170), and the greater the difference between the thickness of the first solder resist layer (160) and the thickness of the second solder resist layer (170), the less the degree of warping occurs.

[0140] Accordingly, in the embodiment, the thickness of the first solder resist layer (160) is made greater than the thickness of the second solder resist layer (170) so that the degree of warping of the circuit board can be reduced.

[0141] The first solder resist layer (160) of the embodiment may have an eighth thickness (T8). The eighth thickness (T8) may have a value between 16 μm and 20 μm.

[0142] Additionally, the second solder resist layer (170) of the embodiment may have a ninth thickness (T9). The ninth thickness (T9) may be smaller than the eighth thickness (T8). For example, the ninth thickness (T9) may have a value between 10 μm and 15 μm.

[0143] For example, the eighth thickness (T8) of the first solder resist layer (160) in the embodiment may have a value between 130% and 200% of the ninth thickness (T9) of the second solder resist layer (170). If the eighth thickness (T8) is less than 130% of the ninth thickness (T9), the reduction in the degree of warping may be insignificant. Additionally, if the eighth thickness (T8) is greater than 200% of the ninth thickness (T9), the overall thickness of the circuit board may increase due to the increase in the thickness of the first solder resist layer (160).

[0145] That is, in the embodiment, in an antenna substrate including a second substrate layer including a driving part and a third substrate layer including an antenna part, the thickness of the first solder resist layer (160) placed above the driving part is made smaller than the thickness of the second solder resist layer (170) placed below the antenna part so that the overall degree of warping of the circuit board can be drastically reduced.

[0147] Figure 4 is a drawing showing the specific configuration of a circuit board according to an embodiment.

[0148] Referring to FIG. 4, the circuit board may include an insulating layer, a circuit pattern layer, and a solder resist layer corresponding to FIG. 3.

[0149] For example, the circuit board includes a first substrate layer comprising a first insulating layer (210), a first circuit pattern layer (212), and a second circuit pattern layer (214).

[0150] Additionally, the circuit board may include a second substrate layer comprising a second insulating layer (220), a third circuit pattern layer (222), a third insulating layer (230), and a fourth circuit pattern layer (232) disposed on the first substrate layer. Such a second substrate layer may constitute a driving unit in the antenna substrate. For example, the driving unit may drive an antenna unit corresponding to the third substrate layer.

[0151] Additionally, the circuit board may include a third substrate layer below the first substrate layer, comprising a fourth insulating layer (240), a fifth circuit pattern layer (242), a fifth insulating layer (250), and a sixth insulating layer (252). The third substrate layer may form an antenna portion in the antenna substrate.

[0152] In addition, the circuit board may include vias disposed within each insulating layer.

[0153] For example, a first via (V1) may be disposed within the first insulating layer (210). The first via (V1) may electrically connect the first circuit pattern layer (212) and the second circuit pattern layer (214).

[0154] For example, a first via (V2) may be placed within the second insulating layer (220). The second via (V2) may electrically connect the first circuit pattern layer (212) and the third circuit pattern layer (222).

[0155] For example, a third via (V3) may be placed within the third insulating layer (230). The third via (V3) may electrically connect the third circuit pattern layer (222) and the fourth circuit pattern layer (232).

[0156] For example, a fourth via (V4) may be placed within the fourth insulating layer (240). The fourth via (V4) may electrically connect the second circuit pattern layer (214) and the fifth circuit pattern layer (242).

[0157] For example, a fifth via (V5) may be placed within the fifth insulating layer (250). The fifth via (V5) may electrically connect the fifth circuit pattern layer (242) and the sixth circuit pattern layer (252).

[0158] The first to fifth vias (V1, V2, V3, V4, V5) can be formed by filling the inside of the via hole penetrating each insulating layer with a metallic material.

[0159] The above via hole can be formed by a laser processing method. That is, the via hole can be formed by a via hole processing device using a CO2 laser method.

[0160] In addition, the first to fifth vias (V1, V2, V3, V4, V5) can be formed by filling the interior of the via hole with a metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). At this time, the filling of the metal material may be performed using any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0161] Then, a first solder resist layer (160) is disposed on the outermost insulating layer of the second substrate layer. Additionally, a second solder resist layer (170) is disposed below the outermost insulating layer of the third substrate layer. At this time, the thickness of the first solder resist layer (160) is greater than the thickness of the second solder resist layer (170). Accordingly, in the embodiment, the degree of warping that may occur due to the upper and lower asymmetric structure of the circuit board can be reduced, and reliability can be improved accordingly.

[0163] FIG. 5 is a drawing showing a circuit board according to a second embodiment, and FIG. 6 is a drawing showing a circuit board according to a third embodiment.

[0164] Referring to FIGS. 5 and 6, the circuit board according to the second and third embodiments has different thicknesses of the fourth circuit pattern layer (132A) and / or the sixth circuit pattern layer (152A) compared to FIG. 3.

[0165] At this time, the degree of warping occurring according to the thickness change of the first solder resist layer (160), the second solder resist layer (170), the fourth circuit pattern layer (132A), and the sixth circuit pattern layer (152A) is as shown in Table 4 below. The fourth circuit pattern layer (132A) can be referred to as the first outermost circuit pattern layer, and the fifth circuit pattern layer (152A) can be referred to as the second outermost circuit pattern layer.

[0166] 1st outermost circuit pattern layer Thickness (㎛) The second outermost circuit pattern layer Thickness (㎛) 1st solder resist layer Thickness (㎛) 2nd solder resist layer Thickness (㎛) warpage (mm) 14 16 15 15 0.4095 20 10 0.2339 20 15 10 0.2438 20 15 0.3590 20 16 15 10 0.2198 20 15 0.3388 20 15 15 0.3701 20 10 0.1951

[0168] As shown in Table 4 above, among the various variables for improving the occurrence of warping of the circuit board, in the embodiment, the thickness of the first solder resist layer (160) and the thickness of the second solder resist layer (170) are changed first. For example, the occurrence of warping of the circuit board can be improved first by making the thickness of the first solder resist layer (160) greater than the thickness of the second solder resist layer (170). For example, the occurrence of warping of the circuit board can be improved first by increasing the thickness of the first solder resist layer (160) while decreasing the thickness of the second solder resist layer (170).

[0169] Furthermore, in the embodiment, along with the change in thickness of the first solder resist layer (160) and the second solder resist layer (170), the thickness of the first outermost circuit pattern layer and the thickness of the second outermost circuit pattern layer are changed so that the degree of warping can be further improved.

[0170] At this time, the circuit pattern layer in the comparative example has a thickness of about 15㎛.

[0171] Here, as shown in Table 4, it was confirmed that the degree of bending decreases further when the thickness of the first outermost circuit pattern layer and the thickness of the second outermost circuit pattern layer increase.

[0172] Clearly, it was confirmed that the degree of warping is further reduced when the thickness of the first outermost circuit pattern layer increases or the thickness of the second outermost circuit pattern layer increases, along with the change in thickness of the first solder resist layer (160) and the second solder resist layer (170).

[0173] At this time, when only the thickness of the second outermost circuit pattern layer was increased while the thickness of the first outermost circuit pattern layer was maintained at 15㎛, the level of reduction in the degree of bending was insignificant. However, when the thickness of the first outermost circuit pattern layer was increased, it was confirmed that there was a distinct difference in the level of reduction in the degree of bending. In addition, it was confirmed that when the thickness of the second outermost circuit pattern layer was increased along with the increase in the thickness of the first outermost circuit pattern layer, the level of reduction in the degree of bending was optimal.

[0174] Accordingly, in the embodiment, as shown in FIG. 5, the thickness of the second outermost circuit pattern layer is maintained at the seventh thickness (T7), and the thickness of the first outermost circuit pattern layer is increased to the seventh-1 thickness (T7-1), thereby improving the occurrence of warping of the circuit board.

[0175] Furthermore, in the embodiment, as shown in FIG. 6, the thickness of the first outermost circuit pattern layer is increased to the 7-1 thickness (T7-1), and at the same time, the thickness of the second outermost circuit pattern layer is also increased to the 7-1 thickness (T7-1) so that the occurrence of bending of the circuit board can be further reduced.

[0176] At this time, the 7-1 thickness (T7-1) may have a value between 16 μm and 20 μm. For example, the 7-1 thickness (T7-1) may have a value between 107% and 135% of the 7th thickness (T7).

[0177] That is, in the embodiment, in an antenna substrate including a second substrate layer including a driving unit and a third substrate layer including an antenna unit, the thickness of the first outermost circuit pattern layer positioned at the uppermost side among the circuit pattern layers constituting the driving unit is made thicker than other layers, thereby enabling a significant reduction in the overall degree of warping of the circuit board.

[0179] FIG. 7 is a drawing showing a circuit board according to the fourth embodiment.

[0180] Referring to FIG. 7, the circuit board may have a 15-layer stacked structure based on the number of insulating layers. For example, the circuit board may have a 16-layer stacked structure based on the number of circuit pattern layers.

[0181] As shown in FIG. 7, the circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer.

[0182] The first substrate layer may include an insulating layer (310) and a circuit pattern layer (340). The circuit pattern layer (340) may include a first circuit pattern layer (341) disposed on the upper surface of the insulating layer (310) and a second circuit pattern layer (342) disposed on the lower surface of the insulating layer (320).

[0183] The second substrate layer may be disposed on the first substrate layer. The second substrate layer may be a first region in the antenna substrate where a driving part is disposed, centered on the first substrate layer.

[0184] The second substrate layer may include an insulating layer (320) and a circuit pattern layer (350). The insulating layer (320) of the second substrate layer may include a first inner insulating layer (320A) and a first outermost insulating layer (320B).

[0185] Specifically, the first inner insulating layer (320A) may include a first-1 inner insulating layer (321), a first-2 inner insulating layer (322), a first-3 inner insulating layer (323), a first-4 inner insulating layer (324), a first-5 inner insulating layer (325), and a first-6 inner insulating layer (326). Additionally, the first outermost insulating layer (320B) may be placed on the first-6 inner insulating layer (326) which is positioned at the uppermost position among the first inner insulating layers (320A).

[0186] Additionally, the circuit pattern layer (350) of the second substrate layer may include a first inner circuit pattern layer (350A) and a first outermost circuit pattern layer (350B).

[0187] Specifically, the first inner circuit pattern layer (350A) may include a first-1 inner circuit pattern layer (351), a first-2 inner circuit pattern layer (352), a first-3 inner circuit pattern layer (353), a first-4 inner circuit pattern layer (354), a first-5 inner circuit pattern layer (355), and a first-6 inner circuit pattern layer (356).

[0188] The third substrate layer may be disposed below the first substrate layer. The third substrate layer may be a second region in the antenna substrate where the antenna portion is disposed, centered on the first substrate layer.

[0189] The third substrate layer may include an insulating layer (330) and a circuit pattern layer (360). The insulating layer (330) of the third substrate layer may include a second inner insulating layer (330A) and a second outermost insulating layer (330B).

[0190] Specifically, the second inner insulating layer (330A) may include a second-1 inner insulating layer (331), a second-2 inner insulating layer (332), a second-3 inner insulating layer (333), a second-4 inner insulating layer (334), a second-5 inner insulating layer (335), and a second-6 inner insulating layer (336). Additionally, the second outermost insulating layer (330B) may be positioned below the second-6 inner insulating layer (336), which is positioned at the bottom of the second inner insulating layer (330A).

[0191] Additionally, the circuit pattern layer (360) of the third substrate layer may include a second inner circuit pattern layer (360A) and a second outermost circuit pattern layer (360B).

[0192] Specifically, the second inner circuit pattern layer (360A) may include a second-1 inner circuit pattern layer (361), a second-2 inner circuit pattern layer (362), a second-3 inner circuit pattern layer (363), a second-4 inner circuit pattern layer (364), a second-5 inner circuit pattern layer (365), and a second-6 inner circuit pattern layer (366). Additionally, the second outermost circuit pattern layer (360B) may be disposed below the second outermost insulation layer (330B).

[0193] Additionally, the circuit board may include a first solder resist layer (370) disposed on a second substrate layer and a second solder resist layer (380) disposed below a third substrate layer.

[0194] At this time, in the structure of Fig. 7, the thickness of each layer, the copper content, and the coefficient of thermal expansion (CTE) may be as shown in Table 5 below.

[0195] Thickness (㎛) Copper foil ratio (%) CTE(ppm / ℃) First solder resist layer 16~20 80 First outermost circuit pattern layer 16~20 61 First outermost insulation layer 20 2 1.55 1st-6th inner circuit pattern layers 15 76 1st-6th inner insulation layer 20 2 1.55 1st-5th inner circuit pattern 15 78 1st-5th inner insulation layer 20 1 1.55 1st-4th inner circuit pattern 20 76 1st-4th inner insulation layer 20 1 1.55 1st-3rd inner circuit pattern 15 85 1st-3rd inner insulation layer 70 8 1.41 1st-2nd inner circuit pattern 15 75 1st-2nd inner insulation layer 70 8 1.73 Section 1-1 Inner Circuit Pattern 15 86 1-1 inner insulation layer 70 6 1.41 First circuit pattern layer 25 76 First insulating layer 100 4 Second circuit pattern layer 25 72 2-1 Inner insulation layer 70 2 1.73 Section 2-1 Inner circuit pattern layer 15 35 2-2 Inner insulation layer 100 2 1.57 Section 2-2 Inner circuit pattern layer 15 36 2-3 inner insulation layer 100 2 1.57 2-3 Inner circuit pattern layer 15 54 2-4 inner insulation layer 100 2 1.57 2-4 Inner circuit pattern layer 15 52 2-5 inner insulation layer 70 1 1.41 2-5 Inner circuit pattern layer 15 36 2-6 inner insulation layer 100 2 1.57 2-6 Inner circuit pattern layer 15 45 Second outermost insulation layer 100 2 1.57 Second outermost circuit pattern layer 16~20 50 Second solder resist layer 10~15 96

[0197] Summarizing the features of Table 5, in a circuit board, the second substrate layer and the third substrate layer may have a mutually asymmetric structure centered on the first substrate layer. At this time, the asymmetric structure may include at least one of the thickness of the insulating layer constituting the second substrate layer and the third substrate layer, the coefficient of thermal expansion of the insulating layer, and the copper content of the circuit pattern layer.

[0198] Specifically, the average value of the thickness of the plurality of insulating layers (first inner insulating layer and first outermost insulating layer) constituting the second substrate layer may be smaller than the average value of the thickness of the plurality of insulating layers (second inner insulating layer and second outermost insulating layer) constituting the third substrate layer. This is to ensure that the plurality of insulating layers constituting the third substrate layer constitute an antenna portion and have a dielectric constant of a certain level or higher so that the antenna portion can resonate in a specific resonant frequency band. Specifically, the average dielectric constant of the plurality of insulating layers constituting the second substrate layer may be smaller than the average value of the dielectric constant of the plurality of insulating layers constituting the third substrate layer.

[0199] In addition, the average value of the copper foil ratio of a plurality of circuit pattern layers (a first inner circuit pattern layer and a first outermost circuit pattern layer) constituting the second substrate layer may be greater than the average value of the copper foil ratio of a plurality of circuit pattern layers (a second inner circuit pattern layer and a second outermost circuit pattern layer) constituting the third substrate layer.

[0200] In addition, the average value of the thermal expansion coefficients of the plurality of insulating layers (first inner insulating layer and first outermost insulating layer) constituting the second substrate layer may be smaller than the average value of the thermal expansion coefficients of the plurality of insulating layers (second inner insulating layer and second outermost insulating layer) constituting the third substrate layer.

[0201] In the above structure, if the thickness of the first solder resist layer (370) is increased or the thickness of the second solder resist layer (170) is decreased, the degree of warping of the circuit board can be improved in the first place.

[0202] In addition, in the above structure, if the thickness of the outermost circuit pattern layer is increased along with a change in the thickness of the first solder resist layer (160) or the second solder resist layer (170), the overall degree of warping can be further improved.

[0203] For example, when the thickness of the outermost circuit pattern layer (350B) constituting the second substrate layer is increased along with an increase in the thickness of the first solder resist layer (160) or a decrease in the thickness of the second solder resist layer (170), the overall degree of warping of the circuit board can be improved.

[0204] For example, in the comparative example, the thickness of the outermost circuit pattern layer was formed to be the same as the thickness of another circuit pattern layer (e.g., the first inner circuit pattern layer or the second inner circuit pattern layer).

[0205] In contrast, in the embodiment, the thickness of the outermost circuit pattern layer (350B) is formed to be thicker than the thickness of other circuit pattern layers (e.g., the first inner circuit pattern layer or the second inner circuit pattern layer). Accordingly, in the embodiment, the overall degree of warping of the circuit board can be improved, and reliability can be improved accordingly.

[0206] Such a circuit board can be manufactured by the following manufacturing method.

[0207] First, in the embodiment, a process for forming a first substrate layer can be carried out.

[0208] In an embodiment, when the first substrate layer is formed, a process of forming a second substrate layer and a third substrate layer on each side of the first substrate layer can be carried out.

[0209] At this time, the process of forming the second substrate layer and the third substrate layer may include a process of forming the thickness of the outermost circuit pattern layer of the second substrate layer thicker than the thickness of other circuit pattern layers.

[0210] In an embodiment, when the second substrate layer and the third substrate layer are formed, a process can be carried out to form a first solder resist layer on the second substrate layer and a second solder resist layer below the third substrate layer.

[0211] At this time, the thickness of the first solder resist layer (160) is greater than the thickness of the second solder resist layer.

[0213] The circuit board in the embodiment may be an antenna board. The circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer. The second substrate layer may be an area corresponding to a driving part connected to a transmitting element and a receiving element in the antenna board. And, the third substrate layer may be an area corresponding to an antenna pattern part including an antenna pattern layer for signal transmission and signal reception.

[0214] In this case, the second substrate layer in the embodiment may include a first solder resist layer, and the third substrate layer may include a second solder resist layer. In this case, the thickness of the first solder resist layer may be greater than the thickness of the second solder resist layer. For example, the thickness of the first solder resist layer may have a range between 130% and 200% of the thickness of the second solder resist layer. In the embodiment, the thickness of the first solder resist layer may be increased, and the thickness of the second solder resist layer may be decreased along with the increase in the thickness of the first solder resist layer. Accordingly, in the embodiment, the overall degree of warping of the circuit board can be drastically reduced, and reliability can be improved accordingly.

[0215] In addition, in the embodiment, the thickness of the circuit pattern layer is varied along with the increase in the thickness of the first solder resist layer and the second solder resist layer. For example, the second substrate layer in the embodiment may include a first inner circuit pattern layer and a first outermost circuit pattern layer. And, the third substrate layer may include a second inner circuit pattern layer and a second outermost circuit pattern layer. Here, the thickness of the first outermost circuit pattern layer in the embodiment may be greater than that of the first inner circuit pattern layer and the second inner circuit pattern layer. Specifically, the first inner circuit pattern layer may include a plurality of layers, and the average value of their thicknesses may be smaller than the thickness of the first outermost circuit pattern layer. In addition, the second inner circuit pattern layer may include a plurality of layers, and the average value of their thicknesses may be smaller than the thickness of the second outermost circuit pattern layer. In addition, the thickness of the first outermost circuit pattern layer may be greater than the thickness of the second outermost circuit pattern layer. Accordingly, in the embodiment, the overall degree of warping of the circuit board can be reduced, and reliability can be improved.

[0217] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0218] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

Claim 1 A first substrate layer; a second substrate layer disposed on the first substrate layer; a third substrate layer disposed below the first substrate layer; and a first solder resist layer disposed on the second substrate layer. and includes a second solder resist layer disposed below the third substrate layer, wherein the second substrate layer includes a first outermost circuit pattern layer disposed closest to the first solder resist layer, and a first inner circuit pattern layer disposed between the first outermost circuit pattern layer and the first substrate layer, and the third substrate layer includes a second outermost circuit pattern layer disposed closest to the second solder resist layer, and a second inner circuit pattern layer disposed between the second outermost circuit pattern layer and the first substrate layer, wherein the thickness of the first outermost circuit pattern layer is greater than the respective thicknesses of the first inner circuit pattern layer, the second inner circuit pattern layer, and the second outermost circuit pattern layer, and the thickness of the first solder resist layer in a region vertically superimposed with the first outermost circuit pattern layer is greater than the thickness of the second solder resist layer in a region vertically superimposed with the second outermost circuit pattern layer, and the second substrate layer includes a first inner insulating layer and a first An antenna substrate comprising an outermost insulating layer, wherein the third substrate layer comprises a second inner insulating layer and a second outermost insulating layer, wherein the first inner circuit pattern layer is disposed on the first inner insulating layer, wherein the first outermost circuit pattern layer is disposed on the first outermost insulating layer, wherein the second inner circuit pattern layer is disposed below the second inner insulating layer, wherein the second outermost circuit pattern layer is disposed below the second outermost insulating layer, wherein the average value of the respective thicknesses of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective thicknesses of the second inner insulating layer and the second outermost insulating layer, wherein the third substrate layer constitutes an antenna portion, and the second substrate layer constitutes a driving portion that drives the antenna portion. Claim 2 An antenna substrate according to claim 1, wherein the thickness of the first solder resist layer is in the range between 130% and 200% of the thickness of the second solder resist layer. Claim 3 An antenna substrate according to claim 1, wherein the thickness of the first solder resist layer satisfies the range of 16㎛ to 20㎛ and the thickness of the second solder resist layer satisfies the range of 10㎛ to 15㎛. Claim 4 delete Claim 5 An antenna substrate according to claim 1, wherein the first inner circuit pattern layer is a plurality of times, and the thickness of the first outermost circuit pattern layer is greater than the average value of the thicknesses of the plurality of first inner circuit pattern layers. Claim 6 An antenna substrate according to claim 1, wherein the thickness of the first outermost circuit pattern layer satisfies the range of 16㎛ to 20㎛. Claim 7 An antenna substrate according to claim 1, wherein the average value of the respective areas of the first inner circuit pattern layer and the first outermost circuit pattern layer is greater than the average value of the respective areas of the second inner circuit pattern layer and the second outermost circuit pattern layer. Claim 8 delete Claim 9 delete Claim 10 An antenna substrate according to claim 1, wherein the average value of the respective thermal expansion coefficients of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective thermal expansion coefficients of the second inner insulating layer and the second outermost insulating layer. Claim 11 An antenna substrate according to claim 1, wherein the average value of the respective dielectric constants of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective dielectric constants of the second inner insulating layer and the second outermost insulating layer. Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete

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