Semiconductor device

Abstract

A semiconductor device comprises: a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparison circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line extending in the first direction from a first wiring layer on the substrate while being electrically connected to the first and second memory cells; a first power wiring disposed in the first wiring layer and extending in the first direction between the true bit line and the complementary bit line to be electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer different from the first wiring layer on the substrate; first word line pads disposed in the first wiring layer to electrically connect the first memory cell and the first word line; and second word line pads disposed in the first wiring layer to electrically connect the second memory cell and the second word line. and includes a first ground pad disposed in the first wiring layer and electrically connected to the first and second memory cells, and disposed at the same location in the second direction as one of the first wordline pads and one of the second wordline pads.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] Content-addressable memory is a special type of memory used in search applications that require very high speeds. It is commonly abbreviated as CAM and is also known as associative memory.

[0004] Unlike RAM, which returns data at a given address when a user provides a memory address, in CAM, when a user provides a search term, CAM searches its entire memory space and returns the address where the search term is located and, in some cases, data associated with the search term.

[0005] These CAM cells basically consist of an SRAM responsible for storage and a CAM port responsible for comparison to form a single CAM cell, and are generally composed of NOR type CAMs and NAND type CAMs.

[0006] Because the NOR type is faster than the NAND type, it is used relatively widely. A 10T (10 transistors) NOR type CAM is called Binary CAM (BCAM), and a 16T NOR type CAM is called Ternary CAM (TCAM).

[0007] While BCAM can store only 0 or 1 in a single cell, TCAM can store "X" (Don't care) in addition to 0 and 1, providing greater flexibility in searching. For example, if "1" is stored in TCAM, "1" can be entered into the search line of TCAM and "0" can be entered and "0" can be entered. On the other hand, if "X" is stored in TCAM, "1" can be entered into the search line of TCAM and "0" can be entered and "1" can be entered.

[0008] Providing this flexibility requires additional costs, as TCAM requires additional memory to store the "X" state compared to BCAM. The problem to be solved

[0010] The present invention aims to provide a semiconductor device with improved integration density and performance.

[0011] Specifically, the present invention can provide an improved layout of metal wiring formed on the upper part of a TCAM cell area. means of solving the problem

[0013] A semiconductor device according to an embodiment of the present invention comprises: a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparison circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line extending in the first direction from a first wiring layer on the substrate while being electrically connected to the first and second memory cells; a first power wiring disposed in the first wiring layer and extending in the first direction between the true bit line and the complementary bit line to be electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer different from the first wiring layer on the substrate; first word line pads disposed in the first wiring layer to electrically connect the first memory cell and the first word line; and second word line pads disposed in the first wiring layer to electrically connect the second memory cell and the second word line. and may include a first ground pad disposed in the first wiring layer and electrically connected to the first and second memory cells, and disposed at the same location in the second direction as one of the first wordline pads and one of the second wordline pads.

[0015] A semiconductor device according to an embodiment of the present invention comprises: a substrate including a storage region and a comparison region; first to fourth active regions extending in a first direction from the storage region and spaced apart in a second direction intersecting the first direction; a fifth active region extending in the first direction from the comparison region and spaced apart from the fourth active region in the second direction; first and fourth gate structures extending in the second direction and intersecting the first to fourth active regions; second and third gate structures extending in the second direction and intersecting the first to fifth active regions; a fifth gate structure extending in the second direction and intersecting the fifth active region and positioned at the same location as the first gate electrode in the first direction; and a sixth gate structure extending in the second direction and intersecting the fifth active region and positioned at the same location as the fourth gate electrode in the first direction. and active contacts adjacent to the first to sixth gate structures and connected to at least one of the first to fifth active regions, comprising: a first wordline pad connected to the second gate structure; and a second wordline pad disposed at the same position as the first wordline pad in the second direction and connected to the third gate structure; a third wordline pad connected to the first gate structure; a fourth wordline pad disposed at the same position as the third wordline pad in the second direction and connected to the third gate structure; a first ground pad disposed at the same position as the first and second wordline pads in the second direction, connected to the first active region and connected to an active contact adjacent to the first gate structure; and a second ground pad disposed at the same position as the first and second wordline pads in the second direction, connected to the first active region and connected to an active contact adjacent to the fourth gate structure.and may include a third ground pad positioned at the same location as the third and fourth wordline pads in the second direction, connected to the fourth active region, and connected to an active contact shared by the second and third gate structures.;

[0017] A semiconductor device according to an embodiment of the present invention may include: a substrate comprising an active region extending in a first direction, first to fourth gate structures extending in a second direction intersecting the active region, active contacts adjacent to at least one of the first to fourth gate structures, and first and second memory cells respectively connected to the second and third gate electrodes; a first search line extending in the first direction from a first wiring layer on the substrate and connected to the first gate structure; a second search line extending in the first direction from the first wiring layer and connected to the fourth gate structure; and a first ground wiring disposed in the first wiring layer, extending in the first direction between the first and second search lines, and connected to an active contact adjacent to the first gate structure and an active contact adjacent to the fourth gate structure.

[0019] A semiconductor device according to an embodiment of the present invention comprises: a substrate including an active region extending in a first direction, first to fourth gate structures extending in a second direction intersecting the active region, active contacts adjacent to at least one of the first to fourth gate structures, and first and second memory cells respectively connected to the second and third gate structures; a first ground wiring disposed on a first wiring layer on the substrate and connected to an active contact adjacent to the first gate structure and an active contact adjacent to the fourth gate structure; a first search line extending in the first direction from the first wiring layer and connected to the first gate structure; and a second search line extending in the first direction from the first wiring layer and connected to the fourth gate structure. and includes a match line pad connected to an active contact shared by the second and third gate structures in the first wiring layer, wherein the first and second search lines are formed between the first ground wiring and the match line pad, and the first ground wiring is adjacent to the first and second memory cells.

[0021] A semiconductor device according to an embodiment of the present invention comprises: a substrate including an active region extending in a first direction, first to fourth gate structures extending in a second direction intersecting the active region, active contacts adjacent to at least one of the first to fourth gate structures, and first and second memory cells respectively connected to the second and third gate electrodes; a first search line extending in the first direction in a first wiring layer on the substrate and connected to the first gate structure; a second search line extending in the first direction in the first wiring layer and connected to the fourth gate structure; a match line pad connected to an active contact shared by the second and third gate structures in the first wiring layer; a first ground pad connected to an active contact adjacent to the first gate structure in the first wiring layer; and a second ground pad connected to an active contact adjacent to the fourth gate structure in the first wiring layer, wherein the first and second ground pads and the match line pad may be positioned at the same location in the second direction. Effects of the invention

[0023] The present invention can provide a semiconductor device with improved integration density and performance.

[0024] According to an embodiment of the present invention, the layout of metal wiring formed on the upper part of a TCAM cell region can be improved. Specifically, the number of wirings in the lower wiring layer required for a single TCAM cell can be reduced. Furthermore, the electrical characteristics of wiring patterns transmitting complementary signals among the wiring patterns of the lower wiring layer can be matched. Accordingly, the integration density and performance of a semiconductor device including TCAM cells can be improved.

[0025] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0027] Figure 1 is a circuit diagram illustrating a TCAM (Ternary Content-addressable memory). FIG. 2 is a layout diagram for explaining a semiconductor device according to a comparative example different from an embodiment of the present invention. FIG. 3 is a layout diagram for explaining a semiconductor device according to a first embodiment of the present invention. Figure 4 is a layout diagram showing the layout of the front-end process step of the layout diagram of Figure 3. Figure 5 is a layout diagram expressed by adding a first wiring layer to the layout of Figure 4. Figure 6 is a layout diagram showing the first and second wiring layers in the layout diagram of Figure 3. Figure 7 is a cross-sectional view of the layout of Figure 3 cut along I-I'. Figure 8 is a cross-sectional view of the layout of Figure 3 cut along II-II'. FIG. 9 is a layout diagram for explaining a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a layout diagram in which a first wiring layer is added to the layout of the front-end process step in the layout diagram of FIG. 9. FIG. 11 is a layout diagram showing the first and second wiring layers in the layout diagram of FIG. 9. FIG. 12 is a cross-sectional view of the layout of FIG. 9 cut along III-III'. FIG. 13 is a layout diagram for explaining a semiconductor device according to a third embodiment of the present invention. FIG. 14 is a layout diagram in which a first wiring layer is added to the layout of the front-end process step of FIG. 13. FIG. 15 is a layout diagram showing the first to third wiring layers in the layout diagram of FIG. 13. FIG. 16 is a cross-sectional view of the layout of FIG. 13 cut along I-I'. FIG. 17 is a cross-sectional view of the layout of FIG. 13 cut along II-II'. Specific details for implementing the invention

[0028] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

[0030] Figure 1 is a circuit diagram illustrating a TCAM (Ternary Content-addressable memory).

[0031] The TCAM cell area may include a storage area (SR) and a comparison area (CR). The storage area (SR) may include a first cell area (R1) and a second cell area (R2).

[0032] The first cell region (R1) may include first and second inverters (INV1, INV2) connected in parallel between the power terminal (VDD) and the ground terminal (VSS), and first and second pass transistors (PS1, PS2) connected to the output terminals of the first and second inverters (INV1, INV2). The first and second inverters (INV1, INV2) and the first and second pass transistors (PS1, PS2) may provide a first memory cell.

[0033] Each of the first and second pass transistors (PS1, PS2) can be connected to the true bit line (BLT) and the complementary bit line (BLC). The gates of the first and second pass transistors (PS1, PS2) can be connected to the data word line (CWL).

[0034] The first inverter (INV1) may include a first pull-up transistor (PU1) and a first pull-down transistor (PD1) connected in series, and the second inverter may include a second pull-up transistor (PU2) and a second pull-down transistor (PD2) connected in series. The first and second pull-up transistors (PU1, PU2) may be PMOS (P-channel MOS) transistors, and the first and second pull-down transistors (PD1, PD2) may be NMOS (N-channel MOS) transistors.

[0035] The first inverter (INV1) and the second inverter (INV2) can form a single latch circuit. Specifically, the input terminal of the first inverter (INV1) can be connected to the output terminal of the second inverter (INV2), and the input terminal of the second inverter (INV2) can be connected to the output terminal of the first inverter (INV1).

[0036] Similarly, the second cell region (R2) may include third and fourth inverters (INV3, INV4) connected in parallel between the power terminal (VDD) and the ground terminal (VSS), and third and fourth pass transistors (PS3, PS4) connected to the output terminals of the third and fourth inverters (INV3, INV4). The third and fourth inverters (INV3, INV4) and the third and fourth pass transistors (PS3, PS4) may provide a second memory cell.

[0037] The third pass transistor (PS3) and the fourth pass transistor (PS4) can be connected to the true bit line (BLT) and the complementary bit line (BLC), respectively. The gates of the third and fourth pass transistors (PS3, PS4) can be connected to the mask word line (MWL).

[0038] The third inverter (INV3) may include a third pull-up transistor (PU3) and a third pull-down transistor (PD3) connected in series, and the fourth inverter (INV4) may include a fourth pull-up transistor (PU4) and a fourth pull-down transistor (PD4) connected in series. The third and fourth pull-up transistors (PU3, PU4) may be PMOS transistors, and the third and fourth pull-down transistors (PD3, PD4) may be NMOS transistors.

[0039] The third inverter (INV3) and the fourth inverter (INV4) can form a single latch circuit. Specifically, the input terminal of the third inverter (INV3) can be connected to the output terminal of the fourth inverter (INV4), and the input terminal of the fourth inverter (INV4) can be connected to the output terminal of the third inverter (INV3).

[0040] The first cell region (R1) and the second cell region (R2) of a semiconductor device according to an embodiment of the present invention may comprise a data cell and a mask cell. In the example of FIG. 1, the first memory cell of the first cell region (R1) may be a data cell, and the second memory cell of the second cell region (R2) may be a mask cell. However, the present invention is not limited thereto, and it is acceptable for the second memory cell to be a data cell and the first memory cell to be a mask cell.

[0041] To store data in the TCAM, data can be stored in the first cell area (R1) and mask data can be stored in the second cell area (R2) through the true bitline (BLT). For example, if data '1' is to be stored in the TCAM, data '1' can be stored in the first cell area (R1) and data '0' can be stored in the second cell area (R2).

[0042] Specifically, to store data '1' in the first cell region (R1), a voltage is applied to the data word line (CWL) to turn on the first and second pass transistors (PS1, PS2), a voltage corresponding to data '1' is applied to the true bit line (BLT), and a voltage corresponding to data '0' is applied to the complementary bit line (BLC). When data '1' is stored in the first cell region (R1), a voltage corresponding to data '1' is formed at the true data node (CT), which is the output terminal of the first inverter (INV1) and the input terminal of the second inverter (INV2), and a voltage corresponding to data '0' is formed at the complementary data node (CC), which is the output terminal of the second inverter (INV2) and the input terminal of the first inverter (INV1).

[0043] Then, to store data '0' in the second cell region (R2), voltage can be applied to the mask word line (MWL) to turn on the third and fourth pass transistors (PS3, PS4), and a voltage corresponding to data '0' can be applied to the true bit line (BLT) and a voltage corresponding to data '0' can be applied to the complementary bit line (BLC). When data '0' is stored in the second cell region (R2), a voltage corresponding to data '0' is formed at the true mask node (MT), which is the output terminal of the third inverter (INV3) and the input terminal of the fourth inverter (INV4), and a voltage corresponding to data '1' can be formed at the complementary mask node (MC), which is the output terminal of the fourth inverter (INV4) and the input terminal of the third inverter (INV3).

[0044] Meanwhile, if '0' is stored in both the data cell and the mask cell, the data stored in the storage area (SR) may represent 'Don't care' (X). 'Don't care' is a value that includes both '1' and '0'.

[0045] The comparison region (CR) may include first to fourth transistors (T1 - T4). The first transistor (T1) may be connected in series between the ground terminal (VSS) and the second transistor (T2) with the voltage of the true search line (SLT) as the gate voltage. The second transistor (T2) may be connected in series between the first transistor (T1) and the match line (ML) with the voltage of the true mask node (MT) as the gate voltage. The third transistor (T3) may be connected in series between the ground terminal (VSS) and the fourth transistor (T4) with the voltage of the complementary search line (SLC) as the gate voltage. The fourth transistor (T4) may be connected in series between the third transistor (T3) and the match line (ML) with the voltage of the true data node (CT) as the gate voltage.

[0046] The first to fourth transistors (T1 - T4) of the comparison region (CR) can form a comparison circuit. The comparison circuit can compare the signal applied to the search line pair (SLT, SLC) with the voltage formed at the true data node (CT) and the true mask node (MT) and output a '0' or '1' signal to the match line (ML).

[0047] To search for data from TCAM, both the data word line (CWL) and the mask word line (MWL) can be turned off, and the match line (ML) terminal can be precharged. If data '0' is to be searched, the true search line (SLT) can be turned off to '0', and the complementary search line (SLC) can be turned on to '1'. When the true search line (SLT) is turned off to '0', the gate voltage signal of the third transistor (T3) becomes '0', and the third transistor (T3) can be turned off. Then, when the complementary search line (SLC) is turned on to '1', the gate voltage signal of the first transistor (T1) becomes '1', and the first transistor (T1) can be turned on.

[0048] If the data stored in the first cell region (R1) is '0', the gate voltage signal of the second transistor (T2) may be '0'. Since the match line (ML) is floated by the second and third transistors (T2, T3), the precharged match line (ML) terminal maintains a '1' state, which can indicate a match state. If the data stored in the first cell region (R1) is '1', the gate voltage signal of the second transistor (T2) becomes '1', and the second transistor (T2) can be turned on. Since the match line (ML) can be connected to the ground signal (VSS) by the first and second transistors (T1, T2), the terminal of the match line (ML) is discharged, and the terminal value can become '0', which can indicate a no match state.

[0049] Meanwhile, when a don't care value is stored in TCAM, that is, when '0' is stored in the first cell region (R1) and '0' is stored in the second cell region (R2), the gate voltage signals of the second transistor (T2) and the fourth transistor (T4) can both be '0'. In this case, regardless of whether the true search line (SLT) is turned on to '1' or turned off to '0', the match line (ML) can always remain floating and maintain a precharged state. Therefore, the match line (ML) can always indicate a match state.

[0050] A plurality of wiring patterns may be formed on the upper portions of the first cell region (R1), the second cell region (R2), and the comparison region (CR) included in the TCAM. For example, power wiring patterns and ground wiring patterns may be formed on the upper portions of the regions, wiring patterns for providing word line signals, bit line signals, search line signals, etc. may be formed, and wiring patterns for outputting a match line signal from the comparison region may be formed. If the plurality of wiring patterns are not efficiently arranged, the area occupied by the wiring patterns in the semiconductor circuit increases, and thus the integration density of the semiconductor circuit including the TCAM cell may decrease.

[0051] Below, a layout with improved integration density of a semiconductor circuit including a TCAM cell is proposed.

[0053] FIG. 2 is a layout diagram for explaining a semiconductor device according to a comparative example different from an embodiment of the present invention.

[0054] Referring to FIG. 2, a semiconductor device according to a comparative example includes a first cell region (R1), a second cell region (R2), and a comparison region (CR). The first cell region (R1), the second cell region (R2), and the comparison region (CR) correspond to those described with reference to FIG. 1. Referring to FIG. 2, the first cell region (R1) and the second cell region (R2) are adjacent in a first direction, and the comparison region (CR) is adjacent to the first cell region (R1) and the second cell region (R2) in a second direction.

[0055] A semiconductor device according to a comparative example includes active regions (ACT) extending in a first direction and gate structures (GS) extending in a second direction and intersecting the active regions (ACT). The active regions (ACT) and the gate structures (GS) provide a plurality of semiconductor devices.

[0056] For example, one of the gate structures (GS) and active regions (ACT) disposed on both sides thereof provide a single transistor. The active regions (ACT) are connected to active contacts (CNT) adjacent to the gate structures (GS). The transistors included in the semiconductor device are connected to each other to provide the circuit described with reference to FIG. 1. FIG. 2 shows regions in which pass transistors (PS1 - PS4), pull-up transistors (PU1 - PU4), pull-down transistors (PD1 - PD4), and first to fourth transistors (T1 - T4) are formed, respectively, in a first cell region (R1), a second cell region (R2), and a comparison region (CR).

[0057] The semiconductor device includes lower wiring patterns (M1) connected to at least one of gate structures (GS) and active regions (ACT). The lower wiring patterns (M1) are formed of a conductive material such as metal or metal silicide and extend in a first direction as shown in FIG. 2. Some lower wiring patterns (M1) may be positioned at the same location in a second direction and may be insulated from each other. For example, a data wordline pad (CWLP) connecting a data wordline to the gate of a first pass transistor (PS1) and a mask wordline pad (MWLP) connecting a mask wordline to the gate of a second pass transistor (PS2) are positioned at the same location in a second direction and are insulated from each other.

[0058] In FIG. 2, adjacent wiring patterns among the lower wiring patterns (M1) are shown as different patterns (M1_E1, M1_E2). According to the trend of miniaturization of semiconductor processes, it is desirable that the spacing between adjacent lower wiring patterns be formed sufficiently narrow so as not to cause interference with each other. In order to form wiring patterns so that adjacent lower wiring patterns do not cause interference with each other, different processes may be used for the adjacent lower wiring patterns (M1_E1, M1_E2). For example, a process of forming lower wiring patterns (M1_E1) by depositing a metal in a wiring layer, etching the metal, and then depositing an insulator may be performed first, and a process of forming lower wiring patterns (M1_E2) adjacent to the lower wiring patterns (M1_E1) by etching the insulator between the lower wiring patterns (M1_E1) and then depositing a metal may be performed.

[0059] The lower wiring patterns (M1) are connected to at least one of the gate structures (GS) through a gate contact (CB) and provide a signal path for transmitting an input signal to a circuit provided by the semiconductor device. The input signal is input to one of the gate structures (GS) through at least one of the lower wiring patterns (M1), and the output signal is output through at least one of the active regions (ACT).

[0060] According to the comparative example of FIG. 2, the lower wiring patterns (M1) formed on the upper part of the TCAM cell area include three ground wires (M1(VSS)). Of the three ground wires (M1(VSS)), two ground wires provide grounding for the first cell area (R1) and the second cell area (R2), and one ground wire provides grounding for the comparison area (CR). On the upper part of the TCAM cell area, lower wiring patterns (M1) are formed on 11 tracks in the second direction, including three ground wires (M1(VSS)). For example, the lower wiring patterns (M1) are formed on a total of 11 tracks in such a manner that a data wordline pad (CWLP) and a mask wordline pad (MWLP) are placed on the first track (①) and a ground wire (M1(VSS)) is placed on the second track (②). Even if adjacent TCAM cells share lower wiring patterns (M1) at both ends of the TCAM cell, on average, lower wiring (M1) must be formed on 10 tracks in the second direction per TCAM cell. Depending on the number of lower wiring patterns (M1), the length of the TCAM cell area in the second direction may increase, and an increase in the length of the TCAM cell area may cause an increase in the area of ​​the semiconductor device.

[0061] According to embodiments of the present invention, a semiconductor device is proposed in which the number of grounding wires (M1(VSS)) included in the TCAM cell region is reduced, and consequently, the integration density is improved. Hereinafter, a semiconductor device according to embodiments of the present invention is described in detail with reference to FIGS. 3 to 13.

[0063] FIG. 3 is a layout diagram for explaining a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a layout diagram showing the layout of a front-end process step of FIG. 3, FIG. 5 is a layout diagram showing the first wiring layer added to the layout of FIG. 4, and FIG. 6 is a layout diagram showing the first wiring layer and the second wiring layer in the layout of FIG. 3. FIG. 7 is a cross-sectional view taken along I-I' of the layout of FIG. 3, and FIG. 8 is a cross-sectional view taken along II-II' of the layout of FIG. 3.

[0064] Referring to FIGS. 3 to 8, a semiconductor device (200) according to an embodiment of the present invention may include a substrate (201), active regions (ACT), gate structures (GS), active contacts (CNT), and wiring patterns (M1, M2, M3).

[0065] The substrate (201) may be made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Additionally, a silicon-on-insulator (SOI) substrate may be used.

[0066] The substrate (201) may include a first cell region (R1), a second cell region (R2), and a comparison region (CR). The first cell region (R1), the second cell region (R2), and the comparison region (CR) may constitute a TCAM cell region, and each region corresponds to that described with reference to FIG. 1. Referring to FIG. 3, the first cell region (R1) and the second cell region (R2) may be adjacent to each other in a first direction. The comparison region (CR) may be adjacent to the first cell region (R1) and the second cell region (R2) in a second direction.

[0067] Referring to FIG. 3, the boundary line between the first cell region (R1) and the second cell region (R2) is extended in the second direction, and the boundary line between the first cell region (R1) and the comparison region (CR) can be extended in the first direction. The boundary line between the second cell region (R2) and the comparison region (CR) can also be extended in the first direction.

[0068] The first direction and the second direction may be directions perpendicular to each other. However, the present invention is not limited thereto. The third direction may be a direction perpendicular to both the first direction and the second direction.

[0069] The first cell region (R1) and the second cell region (R2) may be storage regions (SR). A first memory cell and a second memory cell as described with reference to FIG. 1 may be formed in the first cell region (R1) and the second cell region (R2).

[0070] The comparison region (CR) can compare the signals of the first cell region (R1) and the second cell region (R2) with the signal input to the true search line (SLT). A semiconductor device (200) according to an embodiment of the present invention can form a TCAM cell including the first cell region (R1), the second cell region (R2), and the comparison region (CR).

[0071] Referring to FIG. 4, the semiconductor device (200) may include active regions (ACT1 - ACT5) that extend in a first direction and are spaced apart in a second direction. Among the active regions (ACT1 - ACT5), the first, fourth, and fifth active regions (ACT1, ACT4, ACT5) may be N-type doped regions, and the second and third active regions (ACT2, ACT3) may be P-type doped regions.

[0072] And, the semiconductor device (200) may include gate structures (GS1 - GS6) that extend in a second direction and are spaced apart in a first direction. Among the gate structures (GS1 - GS6), the second gate structure (GS2) may extend across the first cell region (R1) and the comparison region (CR), and the third gate structure (GS3) may extend across the second cell region (R2) and the comparison region (CR). The first and fifth gate structures (GS1, GS5) may be positioned at the same location in the first direction and may be insulated between the first cell region (R1) and the comparison region (CR). And, the fourth and sixth gate structures (GS4, GS6) may be positioned at the same location in the first direction and may be insulated between the second cell region (R2) and the comparison region (CR).

[0073] Active contacts (CNT1 - CNT10) can be extended in a second direction between gate structures (GS1 - GS6). The active contacts (CNT1 - CNT10) can connect active regions (ACT1 - ACT5) with wiring patterns.

[0074] A gate cut (CT) for insulation between adjacent transistors sharing the gate structure may be formed in each of the gate structures (GS1 - GS4). Additionally, an active cut (CX) for insulation between adjacent transistors sharing the active contact may be formed in each of the active contacts (CNT1 - CNT5). Meanwhile, although the gate cuts in FIG. 4 and others are depicted as being placed on a single gate structure, this is for convenience of illustration and the present invention is not limited thereto. For example, a single gate cut (CT) may be placed across the second and third gate structures (GS2, GS3), and both the second and third gate structures (GS2, GS3) may be cut. Furthermore, it is understood that the position, shape, size, etc., of the gate cut (CT) and the active cut (CX) may be adjusted within a range that does not impair the spirit of the present invention.

[0075] One of the gate structures (GS1 - GS6) and active regions (ACTs) disposed on both sides thereof can provide a single transistor. The active regions (ACTs) can be connected to active contacts (CNTs) adjacent to the gate structures (GS). The transistors included in the semiconductor device can be connected to each other to provide the circuit described with reference to FIG. 1. FIG. 4 shows regions in which pass transistors (PS1 - PS4), pull-up transistors (PU1 - PU4), pull-down transistors (PD1 - PD4), and first to fourth transistors (T1 - T4) are formed, respectively.

[0076] Specifically, a second gate structure (GS2) and a first active region (ACT1) disposed on both sides thereof may form a first pass transistor (PS1), and a first gate structure (GS1) and a fourth active region (ACT4) disposed on both sides thereof may form a second pass transistor (PS2). Additionally, a third gate structure (GS3) and a first active region (ACT1) disposed on both sides thereof may form a third pass transistor (PS3), and a fourth gate structure (GS4) and a fourth active region (ACT4) disposed on both sides thereof may form a fourth pass transistor (PS4).

[0077] A first gate structure (GS1) and a first active region (ACT1) disposed on both sides thereof can form a first pull-down transistor (PD1), and a first gate structure (GS1) and a second active region (ACT2) disposed on both sides thereof can form a first pull-up transistor (PU1). That is, the first pull-down transistor (PD1) and the first pull-up transistor (PU1) can share the first gate structure (GS1). Similarly, a second pull-down transistor (PD2) and a second pull-up transistor (PU2) can be formed by sharing the second gate structure (GS2), a third pull-down transistor (PD3) and a third pull-up transistor (PU3) can be formed by sharing the fourth gate structure (GS4), and a fourth pull-down transistor (PD4) and a fourth pull-up transistor (PU4) can be formed by sharing the third gate structure (GS3).

[0078] The input and output terminals of the inverters can be connected through gate contacts (CB). Specifically, a first gate structure (GS1) shared by a first pull-up transistor (PU1) and a first pull-down transistor (PD1) can be connected to a second active contact (CNT2) shared by a second pull-up transistor (PU2) and a second pull-down transistor (PD2) through the gate contact (CB). Additionally, a second gate structure (GS2) shared by a second pull-up transistor (PU2) and a second pull-down transistor (PD2) can be connected to a second active contact (CNT2) shared by a first pull-up transistor (PU1) and a first pull-down transistor (PD1) through the gate contact (CB).

[0079] Likewise, the fourth gate structure (GS4) shared by the third pull-up transistor (PU3) and the third pull-down transistor (PD3) can be connected to the fourth active contact (CNT4) shared by the fourth pull-up transistor (PU4) and the fourth pull-down transistor (PD4) through the gate contact (CB). And, the third gate structure (GS3) shared by the fourth pull-up transistor (PU4) and the fourth pull-down transistor (PD4) can be connected to the fourth active contact (CNT4) shared by the third pull-up transistor (PU3) and the third pull-down transistor (PD3) through the gate contact (CB).

[0080] A fifth gate structure (GS5) and a fifth active region (ACT5) can form a first transistor (T1), a second gate structure (GS2) and a fifth active region (ACT5) can form a second transistor (T2), a sixth gate structure (GS6) and a fifth active region (ACT5) can form a third transistor (T3), and a third gate structure (GS3) and a fifth active region (ACT5) can form a fourth transistor (T4).

[0081] Referring to FIG. 5, a first wiring layer including lower wiring patterns (M1) may be formed on the upper part of the TCAM cell region of FIG. 4. The lower wiring patterns (M1) may extend in a first direction and may be spaced apart in a second direction. Some of the lower wiring patterns (M1) may be placed at the same location in the second direction and may be insulated from each other.

[0082] Referring to FIG. 6, a second wiring layer including intermediate wiring patterns (M2) may be formed on top of a first wiring layer. The intermediate wiring patterns (M2) may extend in a second direction and may be spaced apart in a first direction. Some of the intermediate wiring patterns (M2) may be placed at the same location in the first direction and may be insulated from each other.

[0083] Referring to FIGS. 4 through 6, a second gate structure (GS2) forming a first pass transistor (PS1) can be connected to a data wordline pad (CWLP) through a gate contact (CB). The data wordline pad (CWLP) can be connected to a data wordline (CWL) through a lower via (V1). Similarly, a first gate structure (GS1) forming a second pass transistor (PS2) can also be connected to a data wordline (CWL) through a data wordline pad (CWLP). Furthermore, a fourth gate structure (GS4) forming a third pass transistor (PS3) can be connected to a mask wordline (MWL) through a mask wordline pad (MWLP), and a third gate structure (GS3) forming a fourth pass transistor (PS4) can also be connected to a mask wordline (MWL) through a mask wordline pad (MWLP).

[0084] A third active contact (CNT3) between the first active region (ACT1) shared by the first and third pass transistors (PS1, PS3) can be connected to a true bitline (M1(BLT)) through an active via (VA). Additionally, a first active contact (CNT1) connected to a fourth active region (ACT4) adjacent to the second pass transistor (PS2) can be connected to a complementary bitline (M1(BLC)) through an active via (VA), and a fifth active contact (CNT5) connected to a fourth active region (ACT4) adjacent to the fourth pass transistor (PS4) can be connected to a complementary bitline (M1(BLC)) through an active via (VA).

[0085] The eighth active contact (CNT8) between the fifth active region (ACT5) shared by the second and fourth transistors (T2, T4) can be connected to a match line pad (MLP) through an active via (VA). The match line pad (MLP) can be connected to a match line (ML) through a lower via (V1).

[0086] The first to fourth pull-up transistors (PU1 - PU4) can be connected to a power line (M1(VDD)) connected to the first, third, and fifth active contacts (CNT1, CNT3, CNT5) through an active via (VA). The first to fourth pull-up transistors (PU1 - PU4) can receive an external power supply (VDD) through the power line (M1(VDD)).

[0087] According to the first embodiment of the present invention, ground wiring (M1(VSS)) can be removed from the first wiring layer on the first cell region (R1) and the second cell region (R2). Additionally, ground can be provided to the first to fourth pull-down transistors (PD1 - PD4) through the ground wiring (M1(VSS)) on the comparison region (CR).

[0088] Specifically, referring to FIG. 5, the ground wiring (M1(VSS)) on the comparison region (CR) can be connected to an external ground. The ground wiring (M1(VSS)) on the comparison region (CR) can be connected to a sixth active contact (CNT6) adjacent to the first transistor (T1) through an active via (VA), and can be connected to a tenth active contact (CNT10) adjacent to the third transistor (T3) through an active via (VA).

[0089] And, referring to FIG. 6, the ground wire (M1(VSS)) on the comparison area (CR) can be connected to the ground wires (M2(VSS)) formed in the second wiring layer through the lower via (V1). The ground wires (M2(VSS)) can be connected to the ground pads (VSSP) of the first wiring layer through the lower via (V1).

[0090] Referring again to FIG. 5, the first active contact (CNT1) adjacent to the first pull-down transistor (PD1) can be connected to the ground pad (VSSP) through an active via (VA). Similarly, the third active contact (CNT3) shared by the second and third pull-down transistors (PD2, PD3) can be connected to the ground pad (VSSP) through an active via (VA), and the fifth active contact (CNT5) adjacent to the fourth pull-down transistor (PD4) can be connected to the ground pad (VSSP) through an active via (VA).

[0091] In short, a ground wire (M1(VSS)) formed on the first wiring layer in the comparison region (CR) can not only provide ground (VSS) for the first and third transistors (T1, T3), but also provide ground (VSS) for the first to fourth pull-down transistors (PD1 - PD4).

[0092] In the comparative example described with reference to FIG. 2, three ground wires (M1(VSS)) are formed in the first wiring layer above the TCAM cell region to provide ground to the transistors of the TCAM cell. On the other hand, according to the first embodiment of the present invention, ground to the transistors of the TCAM cell can be provided using one ground wire (M1(VSS)) formed in the first wiring layer above the TCAM cell region. Ground pads (VSSP) formed for ground (VSS) of the first to fourth pull-down transistors (PD1 - PD4) can be placed at the same location in the second direction as the data wordline pad (CWLP) and the mask wordline pad (MWLP). That is, the ground pads (VSSP), the data wordline pad (CWLP), and the mask wordline pad (MWLP) can be placed on a single track. Accordingly, the number of tracks on which the lower wiring patterns (M1) are placed in the TCAM cell is reduced, and the length of the TCAM cell in the second direction can be reduced. As a result, the integration density of semiconductor circuits including TCAM cells can be improved.

[0094] In addition, according to the first embodiment of the present invention, the grounding wiring (M1(VSS)) formed on the comparison area (CR) may be formed between the true search line (M1(SLT)) and the complementary search line (M1(SLC)).

[0095] In the comparative example described with reference to FIG. 2, the true search line (M1(SLT)) and the complementary search line (M1(SLC)) are adjacent. When adjacent wiring patterns are formed in different processes, the true search line (M1(SLT)) and the complementary search line (M1(SLC)) transmitting the complementary signal may have different electrical properties. On the other hand, according to the first embodiment of the present invention, the true search line (M1(SLT)) and the complementary search line (M1(SLC)) are not adjacent to each other. The true search line (M1(SLT)) and the complementary search line (M1(SLC)) may be formed in the same process. Therefore, according to the first embodiment of the present invention, the true search line (M1(SLT)) and the complementary search line (M1(SLC)) have the same electrical properties, thereby improving the complementary signal transmission performance. As a result, the data retrieval performance of the TCAM cell can be improved.

[0097] Referring to FIGS. 7 and 8, a semiconductor device (200) according to a first embodiment of the present invention may include active regions (ACTs) formed on a substrate (201), gate structures (GS) disposed between the active regions (ACTs), and active contacts (CNTs) connected to the active regions (ACTs). A channel region (203) is defined between active regions (ACTs) adjacent to each other in a first direction, and at least one of the gate structures (GS) may be disposed on the channel region (203). The gate structures (GS) may extend in a second direction.

[0098] In the embodiment described with reference to FIGS. 7 and 8, the channel region (203) included in the semiconductor device (200) is assumed to be provided by fin structures, but alternatively, it may be implemented by nanowires, nanosheets, etc. formed on the substrate (201) and surrounded by gate structures (GS). When the channel region (203) is implemented by nanowires, nanosheets, etc., the channel region (203) may be separated from the substrate (201) in a third direction. Alternatively, the channel region (203) may not protrude in a third direction, and the upper surface of the active regions (ACT) may form a co-plane with the upper surface of the channel region (203). In other words, each of the semiconductor devices may be implemented as a general horizontal transistor.

[0099] Referring to FIG. 7, each of the gate structures (GS) may include a gate spacer (211), a gate insulating layer (212), a gate conductive layer (213), and a capping layer (214), etc. However, depending on the embodiments, the structure of each of the gate structures (GS) may be varied. For example, the thickness and / or material of the gate insulating layer (212) may be different, or the material and / or stacking structure of the gate conductive layer (213) may be different, depending on the threshold voltage of each of the semiconductor devices.

[0100] The channel region (203) may be provided by fin structures formed in a third direction perpendicular to the upper surface of the substrate (201), and among the gate structures (GS), the gate insulating layer (212) may have a shape that extends over the fin structures. In other words, both the side and upper surfaces of the fin structures may come into contact with the gate insulating layer (212). The gate insulating layer (212) comes into contact with the side and upper surfaces of the fin structures, and a gate conductive layer (213) and a capping layer (214) may be formed on the gate insulating layer (212).

[0101] Meanwhile, the semiconductor device (200) may include an interlayer insulating layer (270), and the interlayer insulating layer (270) may include a plurality of interlayer insulating layers (271-277). For example, the first interlayer insulating layer (271) may be placed at the same height as the gate structures (GS) and active contacts (CNT), and the second interlayer insulating layer (272) may be placed at the same height as the gate contact (CB) and active via (VA). The third interlayer insulating layer (273) may be placed at the same height as the first wiring layer, and the fourth interlayer insulating layer (274) may be placed at the same height as the lower via (V1). The fifth interlayer insulation layer (275) may be placed at the same height as the second wiring layer, the sixth interlayer insulation layer (276) may be placed at the same height as the intermediate via (V2), and the seventh interlayer insulation layer (277) may be placed at the same height as the third wiring layer. The interlayer insulation layer (270) may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0102] The gate contact (CB) can be connected to the gate conductive layer (213) and, for example, can penetrate the first and second interlayer insulating layers (271, 272). The lower surface of the gate contact (CB) is in contact with the gate conductive layer (213), and the upper surface of the gate contact (CB) can be positioned higher than the upper surface of the active contacts (CNT). For example, the upper surface of the gate contact (CB) can be positioned at the same height as the upper surface of the interlayer insulating layer (272).

[0103] Active regions (ACTs) can be connected to the channel region (203) in a first direction. For example, active regions (ACTs) can be formed by applying a selective epitaxial growth process to the substrate (201). Active regions (ACTs) are connected to active contacts (CNTs), for example, active contacts (CNTs) can be formed in a shape that recesses a portion of the active regions (ACTs). Active regions (ACTs) that are physically separated from each other in a second direction can be electrically connected by each of the active contacts (CNTs).

[0104] Referring to FIG. 7, the lower surface of the active via (VA) is positioned at the same height as the upper surface of the first interlayer insulating layer (271) and can come into contact with the active via (VA). Thus, the lower surface of the active via (VA) can be located between the upper surface of the gate structures (GS) and the upper surface of the gate contact (CB) in a third direction. However, this is only one embodiment, and in other embodiments, the arrangement shape and height of the active via (VA), gate structures (GS), and gate contact (CB), etc., can be varied in various ways.

[0105] Active contacts (CNTs) are adjacent to gate structures (GS) in a first direction and can be connected to active regions (ACTs). The active regions (ACTs) may be formed of metal, metal silicide, polysilicon, etc., and may include two or more layers formed of different materials. For example, each active contact (CNT) may include a metal silicide layer and a metal layer, etc., and in one embodiment, may include a metal silicide layer in direct contact with the active regions (ACTs) and a metal layer disposed on the metal silicide layer.

[0106] At least one of the active contacts (CNT) can be connected to one of the lower wiring patterns (M1) through an active via (VA) disposed thereon. The active via (VA) and the lower wiring patterns (M1) may also include a plurality of layers, for example, a barrier metal layer and a fill metal layer. According to embodiments, the lower wiring patterns (M1) and the active via (VA) may be formed in a single process, in which case the barrier metal layer of the lower wiring patterns (M1) and the active via (VA) may be connected as one, and the fill metal layer may also be connected as one.

[0107] The lower wiring pattern (M1) can be connected to the intermediate wiring pattern (M2) through the lower via (V1). For example, the layer where the lower wiring patterns (M1) are placed can be defined as the first wiring layer, and the layer where the intermediate wiring patterns (M2) are placed can be defined as the second wiring layer.

[0108] Although omitted in the layout diagrams of FIGS. 3 to 6, the semiconductor device (200) according to the first embodiment of the present invention may further include a third wiring layer. Referring to FIGS. 7 and 8, an intermediate wiring pattern (M2) may be connected to an upper wiring pattern (M3) through an intermediate via (V2). The layer on which the upper wiring patterns (M3) are placed may be defined as the third wiring layer. The upper wiring patterns (M3) may extend in a second direction parallel to the intermediate wiring patterns (M2). And, the upper wiring patterns (M3) may overlap with the intermediate wiring patterns (M2) in a third direction. The upper wiring pattern (M3) may transmit the same signal as the overlapping intermediate wiring pattern (M2). For example, a ground wire (M3(VSS)) may be formed on top of a ground wire (M2(VSS)), a data word line (M3(CWL)) may be formed on top of a data word line (M2(CWL)), and a mask word line (M3(MWL)) may be formed on top of a mask word line (M2(MWL)). According to the first embodiment of the present invention, two wiring patterns, namely an intermediate wiring pattern (M2) and an upper wiring pattern (M3), may be used to transmit the same signal, so that the resistance of the ground line, data word line, and mask word line is reduced and the operating performance of the TCAM can be improved.

[0110] Referring to FIG. 8, semiconductor devices within a semiconductor device can be separated from each other by a device isolation film (202) formed on a substrate (201). For example, semiconductor devices disposed on both sides of the device isolation film (202) in a second direction may be PMOS devices and NMOS devices, respectively.

[0111] According to the first embodiment of the present invention, lower wiring patterns (M1) can be formed on nine tracks (① - ⑨) in the second direction. If adjacent TCAM cells share the lower wiring patterns (M1) at both ends, lower wiring patterns (M1) can be formed on an average of eight tracks in the second direction per TCAM cell. Comparing the first embodiment of the present invention with the comparative example described with reference to FIG. 2, the number of tracks on which lower wiring patterns (M1) are arranged per TCAM cell can be reduced by two, and the length of the TCAM cell in the second direction can be reduced. Accordingly, the integration density of the semiconductor device can be improved.

[0113] FIG. 9 is a layout diagram for explaining a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a layout diagram in which a first wiring layer is added to the layout of the front-end process step in FIG. 9, and FIG. 11 is a layout diagram in which the first and second wiring layers are shown in FIG. 9. FIG. 12 is a cross-sectional view of FIG. 9 cut along III-III'.

[0114] Referring to FIGS. 9 to 12, a semiconductor device (300) according to a second embodiment of the present invention may include a substrate (301), active regions (ACT), gate structures (GS), active contacts (CNT), and wiring patterns (M1, M2, M3).

[0115] The substrate (301) may be made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Additionally, a silicon-on-insulator (SOI) substrate may be used.

[0116] The substrate (301) may include a first cell region (R1), a second cell region (R2), and a comparison region (CR). The first cell region (R1), the second cell region (R2), and the comparison region (CR) may constitute a TCAM cell region, and each region may correspond to that described with reference to FIG. 1. The first cell region (R1), the second cell region (R2), and the comparison region (CR) may be arranged similarly to the first embodiment of the present invention described with reference to FIG. 3 to FIG. 8.

[0117] Referring to FIGS. 9 and 10, the semiconductor device (300) may include active regions (ACTs) that extend in a first direction and are spaced apart in a second direction. The semiconductor device (300) may also include gate structures (GS) that extend in a second direction and are spaced apart in the first direction. Active contacts (CNTs) may extend in the second direction between the gate structures (GS). The active contacts (CNTs) may connect the active regions (ACTs) with wiring patterns.

[0118] One of the gate structures (GS) and the active regions (ACT) disposed on both sides thereof may provide a single transistor. The transistors included in the semiconductor device (300) may be connected to each other to provide a circuit described with reference to FIG. 1. That is, the semiconductor device (300) may provide a circuit comprising pass transistors (PS1 - PS4), pull-up transistors (PU1 - PU4), pull-down transistors (PD1 - PD4), and first to fourth transistors (T1 - T4). In the first cell region (R1), the second cell region (R2), and the comparison region (CR), the transistors may be arranged in the same manner as described with reference to FIG. 4.

[0119] Referring to FIG. 10, a first wiring layer including lower wiring patterns (M1) may be formed on top of transistors arranged in the same manner as described with reference to FIG. 4. The lower wiring patterns (M1) may extend in a first direction and may be spaced apart in a second direction. Some of the lower wiring patterns (M1) may be arranged at the same location in the second direction and may be insulated from each other.

[0120] Referring to FIG. 11, a second wiring layer including intermediate wiring patterns (M2) may be included on top of a first wiring layer. The intermediate wiring patterns (M2) may extend in a second direction and may be spaced apart in a first direction. Some of the intermediate wiring patterns (M2) may be placed at the same location in the first direction and may be insulated from each other.

[0121] Referring to FIGS. 10 and 11, pass transistors (PS1-PS4) can be connected to the data word line (CWL) and mask word line (MWL) in a manner similar to that described with reference to FIGS. 4 through 6, and the second and fourth transistors (T2, T4) can be connected to the match line (ML) in a manner similar to that described with reference to FIGS. 4 through 6. Additionally, pull-up transistors (PU1-PU4) can be connected to the power wiring (M1(VDD)) in a manner similar to that described with reference to FIGS. 4 through 6 to receive an external power supply (VDD).

[0122] Referring to FIG. 11, a ground wire (M1(VSS)) on a comparison area (CR) can be connected to ground wires (M2(VSS)) formed in a second wiring layer through a lower via (V1). A match line (ML) can be formed in the second wiring layer, and one of the ground wires (M2(VSS)) can be positioned at the same location as the match line (ML) in a first direction.

[0123] According to a second embodiment of the present invention, ground wires (M1(VSS)) may be removed from the first wiring layer on the first cell region (R1) and the second cell region (R2), and the first wiring layer on the comparison region (CR) may include ground wires (M1(VSS)). Similar to what is described with reference to FIGS. 5 and 6, the ground wires (M1(VSS)) on the comparison region (CR) may be connected to an external ground and may provide ground to the first to fourth pull-down transistors (PD1 - PD4) and the first to fourth transistors (T1 - T4).

[0124] Referring to FIG. 12, a semiconductor device (300) according to a second embodiment of the present invention may include active regions (ACT) formed on a substrate (301), gate structures (GS) disposed between the active regions (ACT), and active contacts (CNT) connected to the active regions (ACT). Additionally, semiconductor devices within the semiconductor device may be separated from each other by a device isolation film (302) formed on the substrate (301) of the semiconductor device (300). Furthermore, the semiconductor device (300) may further include an interlayer insulating layer (370) comprising a plurality of interlayer insulating layers (371-377). The structure and arrangement of the gate structures (GS), active regions (ACT), active contacts (CNT), device isolation film (302), etc. of the semiconductor device (300) may be similar to that described with reference to FIGS. 7 and 8, and the interlayer insulating layer (370) may be similar to the interlayer insulating layer (270) described with reference to FIGS. 7 and 8.

[0125] Similar to the first embodiment of the present invention described with reference to FIGS. 3 to 8, the number of lower wiring patterns (M1) required per TCAM cell can be eight on average. When comparing the comparative example described with reference to FIG. 2 with the second embodiment of the present invention, the number of lower wiring patterns (M1) required per TCAM cell can be reduced by two. Thus, the integration density of the semiconductor device can be improved.

[0126] Additionally, according to the second embodiment of the present invention, the ground wiring (M1(VSS)) on the comparison area (CR) may be formed adjacent to the storage area (SR). A complementary search line (M1(SLC)) and a true search line (M1(SLT)) may be formed between the ground wiring (M1(VSS)) and the match line pad (MLP). That is, the ground wiring (M1(VSS)) formed in the first wiring layer and the match line pad (MLP) may be sufficiently spaced apart, and the ground wiring (M2(VSS)) formed in the second wiring layer and the match line (ML) may also be sufficiently spaced apart. Since the ground wiring (M2(VSS)) and the match line (ML) may be spaced apart, interference between signals may be mitigated.

[0128] FIG. 13 is a layout diagram for explaining a semiconductor device according to a third embodiment of the present invention. FIG. 14 is a layout diagram in which a first wiring layer is added to the layout of the front-end process step in FIG. 13, and FIG. 15 is a layout diagram in which the first to third wiring layers are expressed in FIG. 13. FIG. 16 is a cross-sectional view taken along I-I' of the layout of FIG. 13, and FIG. 17 is a cross-sectional view taken along II-II' of the layout of FIG. 13.

[0129] Referring to FIGS. 13 to 17, a semiconductor device (400) according to a second embodiment of the present invention may include a substrate (401), active regions (ACT), gate structures (GS), active contacts (CNT), and wiring patterns (M1, M2, M3).

[0130] The substrate (401) may be made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Additionally, a silicon-on-insulator (SOI) substrate may be used.

[0131] The substrate (401) may include a first cell region (R1), a second cell region (R2), and a comparison region (CR). The first cell region (R1), the second cell region (R2), and the comparison region (CR) may constitute a TCAM cell region, and each region may correspond to that described with reference to FIG. 1. The first cell region (R1), the second cell region (R2), and the comparison region (CR) may be arranged similarly to the first and second embodiments of the present invention described with reference to FIG. 3 to FIG. 12.

[0132] Referring to FIGS. 13 and 14, the semiconductor device (400) may include active regions (ACTs) that extend in a first direction and are spaced apart in a second direction. The semiconductor device (400) may also include gate structures (GS) that extend in a second direction and are spaced apart in the first direction. Active contacts (CNTs) may extend in the second direction between the gate structures (GS). The active contacts (CNTs) may connect the active regions (ACTs) with wiring patterns.

[0133] One of the gate structures (GS) and the active regions (ACT) disposed on both sides thereof may provide a single transistor. The transistors included in the semiconductor device (300) may be connected to each other to provide a circuit described with reference to FIG. 1. That is, the semiconductor device (400) may provide a circuit comprising pass transistors (PS1 - PS4), pull-up transistors (PU1 - PU4), pull-down transistors (PD1 - PD4), and first to fourth transistors (T1 - T4). In the first cell region (R1), the second cell region (R2), and the comparison region (CR), the transistors may be arranged in the same manner as described with reference to FIG. 4.

[0134] Referring to FIG. 14, a first wiring layer including lower wiring patterns (M1) may be formed on top of transistors arranged in the same manner as described with reference to FIG. 4. The lower wiring patterns (M1) may extend in a first direction and may be spaced apart in a second direction. Some of the lower wiring patterns (M1) may be arranged at the same location in the second direction and may be insulated from each other.

[0135] Referring to FIG. 15, a second wiring layer including intermediate wiring patterns (M2) may be included on top of a first wiring layer. The intermediate wiring patterns (M2) may extend in a second direction and may be spaced apart in a first direction. Some of the intermediate wiring patterns (M2) may be placed at the same location in the first direction and may be insulated from each other. Additionally, a third wiring layer including an upper wiring pattern (M3) may be further included on top of the second wiring layer.

[0136] Referring to FIGS. 14 and 15, pass transistors (PS1 - PS4) can be connected to the data word line (CWL) and mask word line (MWL) in a manner similar to that described with reference to FIGS. 4 through 6, and the second and fourth transistors (T2, T4) can be connected to the match line (ML) in a manner similar to that described with reference to FIGS. 4 through 6. Additionally, pull-up transistors (PU1 - PU4) can be connected to the power wiring (M1(VDD)) in a manner similar to that described with reference to FIGS. 4 through 6 to receive an external power supply (VDD).

[0137] According to the third embodiment of the present invention, ground wires (M1(VSS)) in the first wiring layer on the first cell region (R1) and the second cell region (R2) may be removed. Additionally, ground wires (M1(VSS)) included in the first wiring layer on the comparison region (CR) may also be removed. According to the second embodiment of the present invention, the third wiring layer above the TCAM cell region may include ground wires (M3(VSS)) connected to an external ground. Furthermore, the first to fourth pull-down transistors (PD1 - PD4) and the first to fourth transistors (T1 - T4) may be connected to an external ground through the ground wires (M3(VSS)) formed in the third wiring layer.

[0138] Specifically, referring to FIG. 15, the ground wire (M3(VSS)) of the third wiring layer can be connected to the ground wires (M2(VSS)) formed in the second wiring layer through an intermediate via (V2). The ground wires (M2(VSS)) can be connected to the ground pads (VSSP) of the first wiring layer through a lower via (V1).

[0139] Referring to FIG. 14, an active contact (CNT) adjacent to the first pull-down transistor (PD1) can be connected to the ground pad (VSSP) through an active via (VA). Similarly, an active contact (CNT) shared by the second and third pull-down transistors (PD2, PD3) can be connected to the ground pad (VSSP) through an active via (VA), and an active contact (CNT) adjacent to the fourth pull-down transistor (PD4) can be connected to the ground pad (VSSP) through an active via (VA). Additionally, an active contact (CNT) adjacent to the first transistor (T1) and an active contact (CNT) adjacent to the third transistor (T3) can each be connected to the ground pad (VSSP) through an active via (VA).

[0140] In the comparative example described with reference to FIG. 2, three ground wires (M1(VSS)) are formed in the first wiring layer above the TCAM cell region to provide ground to the transistors of the TCAM cell. On the other hand, according to the third embodiment of the present invention, the three ground wires (M1(VSS)) formed in the first wiring layer are removed, and ground can be provided to the transistors of the TCAM cell using one ground wire (M3(VSS)) formed in the third wiring layer.

[0141] Depending on the implementation, the ground wiring (M3(VSS)) of the third wiring layer may overlap with the power wiring (M1(VDD)) of the first wiring layer in the third direction. Additionally, the ground pads (VSSP) may be positioned in the same location in the second direction as the data wordline pad (CWLP), mask wordline pad (MWLP), or matchline pad (MLP). Accordingly, the number of tracks in which the lower wiring patterns (M1) are positioned in the second direction in the TCAM cell is reduced, and the length of the TCAM cell in the second direction may be reduced. Consequently, the integration density of the semiconductor circuit containing the TCAM cells may be improved.

[0142] Referring to FIGS. 16 and 17, a semiconductor device (400) according to a third embodiment of the present invention may include active regions (ACT) formed on a substrate (401), gate structures (GS) disposed between the active regions (ACT), and active contacts (CNT) connected to the active regions (ACT). Additionally, semiconductor devices within the semiconductor device may be separated from each other by a device isolation film (402) formed on the substrate (401) of the semiconductor device (400). Furthermore, the semiconductor device (400) may further include an interlayer insulating layer (470) comprising a plurality of interlayer insulating layers (471-477). The structure and arrangement of the gate structures (GS), active regions (ACT), active contacts (CNT), device isolation film (402), etc. of the semiconductor device (400) may be similar to that described with reference to FIGS. 7 and 8, and the interlayer insulating layer (470) may be similar to the interlayer insulating layer (270) described with reference to FIGS. 7 and 8.

[0143] Referring to FIG. 16, the semiconductor device (400) may include a ground wire (M3(VSS)) formed in a third wiring layer that overlaps in a third direction with a power wire (M1(VDD)) formed in a first wiring layer. The ground wire (M3(VSS)) of the third wiring layer may be connected to an external ground and may be connected to the ground wire (M2(VSS)) of the second wiring layer through an intermediate via (V2) to provide ground to the transistor elements of the TCAM cell.

[0144] Referring to FIG. 17, according to the third embodiment of the present invention, lower wiring patterns (M1) can be formed on eight tracks (① - ⑧) in a second direction on a TCAM cell area. If adjacent TCAM cells share the lower wiring patterns (M1) at both ends, lower wiring patterns (M1) can be arranged on an average of seven tracks per TCAM cell. Comparing the comparative example described with reference to FIG. 2 with the second embodiment of the present invention, the number of tracks on which lower wiring patterns (M1) are arranged per TCAM cell can be reduced by three, and the length of the second direction of the TCAM cell can be reduced. Accordingly, the integration density of the semiconductor device can be improved.

[0146] According to embodiments of the present invention described with reference to FIGS. 3 to 17, ground wiring (M1(VSS)) included in the first wiring layer above the first cell region (R1) and the second cell region (R2) can be removed, so the area of ​​the TCAM cell is reduced and the integration density of the semiconductor device can be improved.

[0147] In particular, according to the first embodiment of the present invention, a ground wire (M1(VSS)) formed in a first wiring layer above a comparison region (CR) and providing ground to the transistors of the TCAM cell region can be placed between the true search line (SLT) and the complementary search line (SLC). Placing the ground wire (M1(VSS)) between the true search line (SLT) and the complementary search line (SLC) allows the true search line (SLT) and the complementary search line (SLC), which transmit complementary signals, to have the same electrical characteristics, thereby further improving the performance of the TCAM cell.

[0148] In addition, according to the first embodiment of the present invention, by forming wiring patterns that transmit the same signal as the wiring patterns formed in the second wiring layer in the third wiring layer, the resistance of the signal lines can be reduced and the performance of the TCAM cell can be further improved.

[0149] According to a second embodiment of the present invention, a grounding wire (M1(VSS)) formed in a first wiring layer may be positioned adjacent to a storage area (SR). The grounding wire (M1(VSS)) may be spaced apart from a match line pad (MLP). Accordingly, a grounding wire (M2(VSS)) positioned at the same location as the match line (ML) in the first direction in the second wiring layer may be sufficiently spaced apart from the match line (ML). Since the match line (ML) and the grounding wire (M2(VSS)) transmitting different signals can be sufficiently spaced apart, interference between the signals is prevented, thereby further improving the performance of the TCAM cell.

[0150] Meanwhile, according to the third embodiment of the present invention, a ground wiring (M3(VSS)) connected to an external ground and providing ground to the transistors of the TCAM cell region may be disposed in the third wiring layer. According to the second embodiment of the present invention, the ground wiring (M1(VSS)) above the comparison region (CR) may also be removed, thereby further improving the integration density of the semiconductor device.

[0152] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0154] 200, 300, 400: Semiconductor device 201, 301, 401: Substrate R1, R2: Cell area CR: Comparison Area ACT: Active area GS: Gate structure CNT: Active contact M1: Lower wiring pattern M2: Intermediate wiring pattern M3: Upper wiring pattern BLT, BLC: Bitline CWL, MWL: Wordline SLT, SLC: Searchline

Claims

Claim 1 A substrate comprising: a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparison circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line extending in the first direction from a first wiring layer on the substrate while being electrically connected to the first and second memory cells; a first power wiring disposed in the first wiring layer and extending in the first direction between the true bit line and the complementary bit line to be electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer different from the first wiring layer on the substrate; first word line pads disposed in the first wiring layer to electrically connect the first memory cell and the first word line; and second word line pads disposed in the first wiring layer to electrically connect the second memory cell and the second word line. A semiconductor device comprising a first ground pad disposed in the first wiring layer and electrically connected to the first and second memory cells, and disposed at the same location in the second direction as one of the first wordline pads and one of the second wordline pads. Claim 2 A semiconductor device according to claim 1, further comprising: a first grounding wire disposed in the first wiring layer and electrically connected to the comparison circuit and external ground; and a second grounding wire disposed in the second wiring layer and electrically connected to the first grounding pad and the first grounding wire. Claim 3 A semiconductor device according to paragraph 2, further comprising a true search line and a complementary search line extending in the first direction from the first wiring layer and electrically connected to the comparison circuit, wherein the first ground wiring extends in the first direction between the true search line and the complementary search line. Claim 4 In paragraph 2, the second grounding wiring is a semiconductor device extending in the second direction between the first and second word lines. Claim 5 A semiconductor device according to claim 1, further comprising: a first ground wire extending in the first direction from the first wiring layer and electrically connected to the comparison circuit and external ground; a true search line and a complementary search line extending in the first direction from the first wiring layer and electrically connected to the comparison circuit; and a match line pad electrically connected to the comparison circuit from the first wiring layer, wherein the true search line and the complementary search line are formed between the first ground wire and the match line pad. Claim 6 A semiconductor device according to claim 5, further comprising: a second grounding wire extending in the second direction from the second wiring layer and electrically connected to the first grounding wire; and a match line extending in the second direction from the second wiring layer and electrically connected to the match line pad, wherein the second grounding wire and the match line are positioned at the same location in the first direction. Claim 7 A semiconductor device according to claim 1, further comprising: a first match line extending in the second direction from the second wiring layer; a match line pad disposed in the first wiring layer and electrically connecting the match line and the comparison circuit; and a second ground pad disposed in the first wiring layer and electrically connected to the comparison circuit, and disposed at the same location as the match line pad in the second direction. Claim 8 A semiconductor device according to claim 7, further comprising: a fourth grounding wire disposed on a third wiring layer different from the first and second wiring layers on the substrate and electrically connected to an external ground; and fifth grounding wires disposed on the second wiring layer and electrically connecting the first grounding pad and the second grounding pad to the fourth grounding wire, respectively. Claim 9 A substrate comprising an active region extending in a first direction, first to fourth gate structures extending in a second direction intersecting the active region, active contacts adjacent to at least one of the first to fourth gate structures, and first and second memory cells respectively connected to the second and third gate structures; a first ground wiring disposed on a first wiring layer on the substrate and connected to an active contact adjacent to the first gate structure and an active contact adjacent to the fourth gate structure; a first search line extending in the first direction from the first wiring layer and connected to the first gate structure; and a second search line extending in the first direction from the first wiring layer and connected to the fourth gate structure. A semiconductor device comprising: a match line pad connected to an active contact shared by the second and third gate structures in the first wiring layer, wherein the first and second search lines are formed between the first ground wiring and the match line pad, the first ground wiring is adjacent to the first and second memory cells, and extends in the second direction from the first wiring layer and other second wiring layer on the substrate and is electrically connected to the match line pad; and further comprising a second ground wiring extending in the second direction from the second wiring layer and is electrically connected to the first ground wiring, wherein the match line and the second ground wiring are positioned at the same location in the first direction. Claim 10 delete

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