Semiconductor devices

Abstract

A semiconductor device according to an embodiment of the present invention comprises: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region and comprising silicon germanium (SiGe); a gate structure extending in a second direction that intersects the active region and the plurality of channel layers on the substrate and surrounds each of the plurality of channel layers; a source / drain region disposed on the active region at least on one side of the gate structure and in contact with the plurality of channel layers; and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region comprises a first layer, and the first layer may be in contact with the side of the gate structure, the sides of the plurality of channel layers, and the upper surface of the substrate insulating layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration of semiconductor devices, it is required to implement patterns with fine widths or fine spacing. In addition, efforts are being made to develop semiconductor devices including FinFETs with three-dimensional channel structures to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs). The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region and comprising silicon germanium (SiGe); a gate structure extending in a second direction on the substrate, intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers; a source / drain region disposed on the active region at least on one side of the gate structure and in contact with the plurality of channel layers; and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region comprises a first layer, and the first layer may be in contact with the side of the gate structure, the sides of the plurality of channel layers and the upper surface of the substrate insulating layer.

[0008] A semiconductor device according to exemplary embodiments comprises: an active region extending in a first direction on a substrate; a plurality of channel layers including silicon germanium (SiGe) spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region; a gate structure extending in a second direction that intersects the active region and the plurality of channel layers and surrounds each of the plurality of channel layers on the substrate; a source / drain region disposed on the active region at least on one side of the gate structure and in contact with the plurality of channel layers; and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region includes an epitaxial layer and protective layers, the epitaxial layer contacts the substrate insulating layer, the protective layers contact at least some of the gate structure and the plurality of channel layers, and the protective layers may be spaced apart from each other in the first direction by the epitaxial layer.

[0009] A semiconductor device according to exemplary embodiments comprises: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region and comprising silicon germanium (SiGe); a gate structure extending in a second direction on the substrate, intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers; a source / drain region disposed on the active region at at least one side of the gate structure and in contact with the plurality of channel layers; and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region comprises an epitaxial layer in contact with the sides of the plurality of channel layers and the upper surface of the substrate insulating layer, at least a portion of the sides of the epitaxial layer forms a surface perpendicular to the upper surface of the substrate, and the lower surface of the epitaxial layer forms a flat surface, and the lower surface of the gate dielectric layer surrounding the lowest gate electrode of the gate structure may be in contact with the upper surface of the substrate insulating layer. Effects of the invention

[0011] A semiconductor device with improved electrical characteristics can be provided by using silicon germanium (SiGe) in the channel layer, controlling the structure of the source / drain regions, and using a Silicon On Insulator (SOI) structure.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 2a is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 2b is a partial enlarged view illustrating a part of a semiconductor device according to exemplary embodiments. FIG. 2c illustrates the distribution of germanium (Ge) concentration in a blocking layer and a channel layer in a semiconductor device according to exemplary embodiments. FIG. 3a is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 3b is a partial enlarged view illustrating a part of a semiconductor device according to exemplary embodiments. FIG. 4a is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 4b is a partial enlarged view illustrating a part of a semiconductor device according to exemplary embodiments. FIG. 5a is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 5b is a partial enlarged view illustrating a part of a semiconductor device according to exemplary embodiments. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 7 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 8 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 9a to 9j are cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments.

[0018] FIG. 2a is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments.

[0019] FIG. 2b is a partial enlarged view illustrating a part of a semiconductor device according to exemplary embodiments. FIG. 2b illustrates an enlarged view of region A of FIG. 2a.

[0020] FIG. 2c illustrates the distribution of germanium (Ge) concentration in a blocking layer and a channel layer in a semiconductor device according to exemplary embodiments.

[0021] For convenience of explanation, only the major components of the semiconductor device are shown in FIGS. 1 to 2c.

[0023] Referring to FIGS. 1 to 2c, a semiconductor device (100) may include a substrate (101), an active region (105) on the substrate (101), a substrate insulating layer (111) on the active region (105), a channel structure (140) comprising a plurality of channel layers (141, 142, 143) spaced apart perpendicularly from each other on the substrate insulating layer (111), a source / drain region (150) in contact with the plurality of channel layers (141, 142, 143), a gate structure (160) extending across the active region (105), and a contact plug (180) connected to the source / drain region (150). The semiconductor device (100) may further include device isolation layers (110) and an interlayer insulating layer (190). The gate structure (160) may include a spacer layer (161), a gate dielectric layer (162), a gate electrode layer (163), and a gate capping layer (164).

[0024] In the semiconductor device (100), the active region (105) has a fin structure, and the gate electrode layer (163) may be disposed between the active region (105) and the channel structure (140), between a plurality of channel layers (141, 142, 143) of the channel structures (140), and on top of the channel structure (140). Accordingly, the semiconductor device (100) is a Gate-All-Around type field-effect transistor, i.e., MBCFET, formed by the channel structure (140), the source / drain region (150), and the gate structure (160).TM It may include a (Multi-Bridge Channel FET). The transistor may be, for example, NMOS transistors.

[0026] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may have an SOI structure including a substrate insulating layer (111) and a lowermost layer among the sacrificial layers (120). The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, an SOI (Silicon On Insulator) layer, or a SeOI (Semiconductor On Insulator) layer, etc. For example, the substrate (101) may be provided as an SOI substrate together with the substrate insulating layer (111).

[0028] The device isolation layer (110) can define an active region (105) on the substrate (101). The device isolation layer (110) can be formed, for example, by a shallow trench isolation (STI) process. According to embodiments, the device isolation layer (110) may further include a region that extends deeper and has a step below the substrate (101). The device isolation layer (110) may expose the substrate insulating layer (111) and partially expose the upper portion of the active region (105). According to embodiments, the device isolation layer (110) may have a curved upper surface having a higher level as it is adjacent to the active region (105). The device isolation layer (110) may be made of an insulating material. The device isolation layer (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0030] The active region (105) is defined by the device isolation layer (110) within the substrate (101) and may be positioned to extend in a first direction (X). The active region (105) may have a structure protruding from the substrate (101). The top of the active region (105) may be positioned to protrude to a predetermined height from the upper surface of the substrate insulating layer (111). The active region (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). However, on both sides of the gate structure (160), the active region (105) on the substrate (101) may be partially recessed, and a source / drain region (150) may be positioned on the recessed active region (105). The active region (105) may include impurities or doping regions containing impurities.

[0032] The substrate insulating layer (111) can be laid flat on the active region (105). The substrate insulating layer (111) may be made of, for example, a silicon oxide film (SiO2), a silicon nitride film (Si3N4), or a combination thereof. Although the substrate insulating layer (111) is shown as being made of a single layer, the substrate insulating layer (111) may be composed of multiple layers as needed. According to one embodiment, the thickness of the substrate insulating layer (111) may satisfy a range of about 500 nm to about 2000 nm.

[0034] The channel structure (140) may include first to third channel layers (141, 142, 143), which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active region (105), for example, in the z-direction, on the active region (105). The first to third channel layers (141, 142, 143) may be spaced apart from the upper surface of the active region (105) while being connected to the source / drain region (150). The first to third channel layers (141, 142, 143) may have a width equal to or similar to that of the active region (105) in the y-direction and a width equal to or similar to that of the gate structure (160) in the x-direction. However, according to the embodiments, the first to third channel layers (141, 142, 143) may have a reduced width such that their sides are located at the bottom of the gate structure (160) in the x direction.

[0035] The first to third channel layers (141, 142, 143) may be made of a semiconductor material and may include, for example, silicon germanium (SiGe). The number and shape of the channel layers (141, 142, 143) forming a channel structure (140) may vary in the embodiments. For example, according to the embodiments, the channel structure (140) may further include a channel layer disposed on the upper surface of the active region (105).

[0037] A source / drain region (150) may be disposed on recessed regions where an active region (105) is recessed, at least on one side of a gate structure (160). The recessed region may extend along the x-direction between gate structures (160) and may have inner walls located at both ends along the x-direction and a bottom surface between the inner walls. The source / drain region (150) may be provided as a source region or a drain region of transistors. The upper surface of the source / drain region (150) may be located at a height level similar to or higher than the lower surface of the gate structures (160), as shown in FIG. 2a. However, the relative height between the source / drain region (150) and the gate structures (160) may vary depending on the embodiments. For example, the source / drain regions (150) may have an elevated source / drain shape in which the upper surface is positioned higher than the lower surface of the gate structures (160), particularly the gate electrodes (163).

[0038] The source / drain region (150) may have a cross-section along the y-direction that is pentagonal, hexagonal, or similar in shape, as shown in FIG. 2a. However, in the embodiments, the source / drain region (150) may have various shapes, for example, any one of polygonal, circular, elliptical, and rectangular shapes. Additionally, the source / drain region (150) may have a generally flat upper surface in a cross-section along the x-direction, as shown in FIG. 2a. The source / drain region (150) may have a substantially flat lower surface because it may come into contact with the upper surface of the substrate insulating layer (111).

[0040] The source / drain region (150) may include an epitaxial layer (156) and protective layers (155).

[0041] The protective layers (155) are in contact with the substrate insulating layer (111), and each of the protective layers (155) may be spaced apart from each other in the X direction by an epitaxial layer (156). The protective layers (155) may be in contact with a lower portion (160B) of a gate structure (160) disposed below each of the channel layers (141, 142, 143). According to one embodiment, the surface where the protective layers (155) and the epitaxial layer (156) are in contact may form a surface perpendicular to the upper surface of the substrate (101).

[0042] Each of the protective layers (155) may include protrusions that protrude in the X direction toward the gate structure (160) at the same level as the lower portion (160B) of the gate structure (160). According to embodiments, the side along the first direction (X) of the lower portion (160B) of the gate structure (160) may be recessed to a predetermined depth and have an inwardly concave shape. The protrusions of the protective layers (155) may be placed within the recessed areas of the lower portion (160B) of the gate structure (160). The width of the protective layers (155) along the first direction (X) at the level of the gate structure (160) may be greater than the width of the protective layers (155) along the first direction (X) at the levels of the first to third channel layers (141, 142, 143).

[0043] According to one embodiment, the horizontal widths (D1, D2, D3) of the protrusions may become smaller as they get closer to the substrate insulating layer (111). For example, the horizontal width (D3) of the lowest portion of the recessed area (160B) of the gate structure (160) may be smaller than the horizontal width (D2) between the lowest portion and the highest portion, and the horizontal width (D2) between the lowest portion and the highest portion may be smaller than the horizontal width (D1) of the highest portion. The horizontal widths (D1, D2, D3) of the protrusions are not limited to this relationship and may vary depending on the embodiments.

[0044] The surface of the protective layers (155) that contacts the plurality of channel layers (141, 142, 143) and the lower portion (160B) of the gate structure (160) may have a wavy shape along the protrusions, but is not limited thereto. The shape of the protective layers (155) may be changed according to the shape of the channel structure (140), the shape of the gate structure (160), etc. For example, if the semiconductor device further includes an outer spacer on the outer side of the gate electrode layer (163) of the lower portion (160B), the outer surface of the protective layers (155) may have a gentle curved shape. The protective layers (155) may include silicon germanium (SiGe) doped with a group 3 element. According to an embodiment, the protective layers (155) may include any one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).

[0045] The epitaxial layer (156) may be positioned to completely fill the recess region. The epitaxial layer (156) may be spaced apart from the gate structure (160) and the plurality of channel layers (141, 142, 143) by a protective layer (155). The epitaxial layer (156) may contain silicon (Si) and may contain impurities of different elements and / or concentrations, and the upper part of the epitaxial layer (156) may contain impurities at a higher concentration than the lower part of the epitaxial layer (156). The epitaxial layer (156) may have an n-type conductivity type and may be an epitaxially grown layer. For example, the epitaxial layer (156) may contain either phosphorus (P) or arsenic (As) as a doping element.

[0047] FIG. 2c illustrates the germanium (Ge) concentration profile of the protective layer (155) and the plurality of channel layers (141, 142, 143) of the source / drain region (150) along the vertical line IV-IV' along the Z direction in FIG. 2b. The horizontal axis of the graph in FIG. 2c represents the depth from IV to IV', and the vertical axis represents the germanium (Ge) concentration. The impurity concentration in the region corresponding to each of the protective layer (155) and the plurality of channel layers (141, 142, 143) may have a substantially constant value. The germanium (Ge) concentration in the region corresponding to each of the plurality of channel layers (141, 142, 143) may be relatively higher than the germanium (Ge) concentration in the region corresponding to the protective layer (155). According to one embodiment, the germanium (Ge) concentration of the plurality of channel layers (141, 142, 143) satisfies a range of about 15 at% to about 40 at%, and the germanium (Ge) concentration of the protective layer (155) may be about 10 at% or less. As a result, germanium (Ge) may diffuse at the boundary portion between the plurality of channel layers (141, 142, 143) and the protective layer (155). In this specification, the term "constant" for the concentration may mean not only a case where it is completely constant, but also a case where a slight difference occurs due to process errors, etc., even though the same process is performed.

[0049] A semiconductor device (100) according to an embodiment of the present invention can satisfy low power and high performance through a plurality of channel layers (141, 142, 143) made of silicon germanium (SiGe) and a source / drain region (150) of the above-described structure.

[0050] In order to improve the performance of a semiconductor device, a channel layer made of silicon germanium (SiGe) is used in a FinFET structure. Through this, the semiconductor device can satisfy low power consumption and high performance. Accordingly, the source / drain region (150) according to the embodiment of the present invention has the structural features described above, thereby improving the performance of the semiconductor device even in an MBCFET structure. In particular, by using a channel layer made of silicon germanium (SiGe) and arranging a substrate insulating layer (111) and a protective layer (155), the performance of the semiconductor device (100) can be improved by protecting the substrate (101) and the epitaxial layer (156) in the process of removing the sacrificial layer (120) made of silicon (Si) described with reference to FIG. X.

[0052] A gate structure (160) may be positioned to extend in one direction, e.g., in the y-direction, intersecting the active region (105) and channel structures (140) on top of the active region (105) and channel structures (140). A channel region of transistors may be formed in the active region (105) and channel structures (140) intersecting the gate structure (160). The gate structure (160) may include a gate electrode layer (163), a gate dielectric layer (162) between the gate electrode layer (163) and a plurality of channel layers (141, 142, 143), spacer layers (161) on the sides of the gate electrode layer (163), and a gate capping layer (164) on the upper surface of the gate electrode layer (163). The gate structure (160) may include an upper portion disposed above the uppermost channel layer among the plurality of channel layers (141, 142, 143) and a lower portion (160B) disposed below each of the plurality of channel layers (141, 142, 143). The lowest portion of the lower portion (160B) of the gate structure (160) may be in contact with the substrate insulating layer (111).

[0053] The gate dielectric layer (162) may be positioned between the active region (105) and the gate electrode layer (163) and between the channel structure (140) and the gate electrode layer (163), and may be positioned to cover at least some of the faces of the gate electrode layer (163). For example, the gate dielectric layer (162) may be positioned to surround all faces except the top face of the gate electrode layer (163). The gate dielectric layer (162) may extend between the gate electrode layer (163) and the spacer layers (161), but is not limited thereto. The lower surface of the gate dielectric layer (162) surrounding the gate electrode at the bottom of the gate structure (160) may be in contact with the upper surface of the substrate insulating layer (111). The gate dielectric layer (162) may comprise an oxide, a nitride, or a high-k dielectric material. The above high dielectric constant material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The above high dielectric constant material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi2). x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It can be any one of ), and praseodymium oxide (Pr2O3).

[0054] The gate electrode layer (163) may be disposed extending above the channel structure (140) and filling the space between the plurality of channel layers (141, 142, 143) on the upper part of the substrate insulating layer (111). The gate electrode layer (163) may be spaced apart from the plurality of channel layers (141, 142, 143) by a gate dielectric layer (162). The gate electrode layer (163) may include a conductive material. For example, it may include at least one of a metal nitride (e.g., at least one of titanium nitride film (TiN), tantalum nitride film (TaN), and tungsten nitride film (WN)), a metal material (e.g., at least one of aluminum (Al), tungsten (W), and molybdenum (Mo)), and silicon (e.g., doped polysilicon).

[0055] The gate electrode layer (163) may be composed of two or more multilayers. Spacer layers (161) may be disposed on both sides of the gate electrode layer (163). The gate spacer layers (161) may insulate the source / drain region (150) from the gate electrode layer (163). The spacer layers (161) may be formed into a multilayer structure according to the embodiments. The spacer layers (161) may include at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0056] The gate capping layer (164) can be placed on top of the gate electrode layer (163), and the lower surface can be surrounded by the gate electrode layer (163) and the spacer layers (161).

[0058] The interlayer insulating layer (190) may be disposed to cover the source / drain region (150), the gate structure (160), and the device isolation layer (110). The interlayer insulating layer (190) may include, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0060] A contact plug (180) can be connected to a source / drain region (150) by penetrating an interlayer insulating layer (190) and can apply an electrical signal to the source / drain region (150). The contact plug (180) can be placed on the source / drain region (150) and, depending on the embodiments, may be placed to have a longer length along the y-direction than the source / drain region (150). The contact plug (180) may have a slanted side such that the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but is not limited thereto. The contact plug (180) may be placed to recess the source / drain region (150) to a predetermined depth. The contact plugs (180) may include a metal-semiconductor compound layer (182) located at the bottom, a barrier layer (184) placed along the sidewalls, and a plug conductive layer (186). The metal-semiconductor compound layer (182) may be, for example, a metal silicide layer. The barrier layer (184) may include a metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The plug conductive layer (186) may include a metallic material, for example, aluminum (Al), tungsten (W), or molybdenum (Mo). In an exemplary embodiment, the contact plug (180) may be positioned to penetrate at least a portion of the source / drain region (150).

[0062] FIGS. 3a, FIGS. 4a, FIGS. 5a and FIGS. 6 to 7 are cross-sectional views illustrating a semiconductor device according to exemplary embodiments.

[0063] FIGS. 3b, FIGS. 4b, and FIGS. 5b are partial enlarged views illustrating parts of a semiconductor device according to exemplary embodiments. FIG. 3b shows an enlarged view of region B of FIG. 3a, FIG. 4b shows an enlarged view of region C of FIG. 4a, and FIG. 5b shows an enlarged view of region D of FIG. 5a.

[0065] In FIGS. 3a to 7, the same drawing numbers as in FIG. 2a indicate corresponding configurations, and descriptions that overlap with the above are omitted.

[0066] Referring to FIGS. 3a and 3b, the horizontal widths (D1', D2', D3') of the protrusions of the protective layers (155) may be substantially the same. For example, the horizontal width (D3') of the lowest part of the recessed area (160B) of the gate structure (160), the horizontal width (D2') between the lowest part and the highest part, and the horizontal width (D1') of the highest part may be substantially the same. These shapes are not limited and may vary depending on the embodiment. In this specification, the phrase "substantially" identical in concentration and thickness, etc., means not only cases where they are completely identical, but also cases where, despite being formed together through the same process, there are actually slight differences due to process errors, etc., and can be interpreted in the same sense even when the expression "substantially" is omitted.

[0068] Referring to FIGS. 4a and 4b, the protective layer (155) may come into contact with a plurality of channel layers (141, 142, 143) and a lower portion (160B) of a gate structure (160), and the contact surface may form a surface perpendicular to the upper surface of the substrate (101). According to one embodiment, since the protective layers (155) are made of silicon germanium (SiGe), they may have etch selectivity with respect to a sacrificial layer (120) made of silicon (Si). As a result, the protective layers (155) can protect the epitaxial layers (150) during the process of removing the sacrificial layer (120).

[0070] Referring to FIGS. 5a and 5b, unlike the embodiment of FIG. 2a, the surface where the protective layers (155) and the epitaxial layer (156) come into contact may not form a surface perpendicular to the upper surface of the substrate (101). Specifically, the surface where the epitaxial layer (156) and the protective layers (155) come into contact may have a shape that is inwardly concave by being recessed to a predetermined depth along the first direction (X) of the lower part (160B) of the gate structure (160). The epitaxial layer (156) may be disposed within the recessed area of ​​the protective layers (155). The protective layers (155) of this embodiment may have a relatively thin thickness compared to the embodiment of FIG. 2a, but are not limited thereto.

[0072] Referring to FIG. 6, unlike the embodiment of FIG. 2a above, internal spacer layers (130) may be included without protective layers (155). The internal spacer layers (130) may be arranged parallel to the gate electrode layer (163) between the channel structures (140). Below the third channel layer (143), the gate electrode layer (163) may be electrically separated from the source / drain regions (150) by the internal spacer layers (130). The internal spacer layers (130) may have a shape in which the side facing the gate electrode layer (163) is rounded inwardly convex toward the gate electrode layer (163), but is not limited thereto. The internal spacer layers (130) may be made of oxide, nitride, and oxynitride, and in particular may be made of a low dielectric constant film.

[0073] Internal spacer layers (130) can be formed in the area where the sacrificial layers (120) have been removed before forming the epitaxial layer (156) (see FIG. 9d). Internal spacer layers (130) can be formed by burying an insulating material in the area where the sacrificial layers (120) have been removed and removing the insulating material deposited on the outside of the channel structures (140). Internal spacer layers (130) can be formed from the same material as the spacer layers (161), but are not limited thereto. For example, internal spacer layers (130) may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0074] The internal spacer layers (130) can also be applied to other embodiments.

[0076] Referring to FIG. 7, the source / drain region (150) may include a plurality of epitaxial layers, for example, first to fourth epitaxial layers (151, 152, 153, 154). In this specification, the first to fourth layers of the claim may be referred to as the first to fourth epitaxial layers (151, 152, 153, 154).

[0077] The first epitaxial layer (151) is disposed on the active region (105) and may be extended to contact a plurality of channel layers (141, 142, 143). The first epitaxial layer (151) may contact a lower portion (160B) of a gate structure (160) disposed below each of the channel layers (141, 142, 143). The lower portion (160B) of the gate structure (160) and the sides of the plurality of channel layers (141, 142, 143) may form a coplanar in a direction perpendicular to the upper surface of the substrate (101). The lowest surface of the source / drain region (150) may be in contact with the substrate insulating layer (111) to form a flat surface, and the source / drain region (150) may be separated from the substrate (101) by the substrate insulating layer (111).

[0078] Among the plurality of epitaxial layers (151, 152, 153, 154), the first epitaxial layer (151) may cover the side of the plurality of channel layers (141, 142, 143), the side of the lower part (160B) of the gate structure (160), and the upper surface of the substrate insulating layer (111). The first epitaxial layer (151) may have a recessed shape. The first epitaxial layer (151) may have an approximately U-shaped shape.

[0079] The first epitaxial layer (151) may include silicon germanium (SiGe) doped with a group 3 element and may have a p-type conductivity. For example, the first epitaxial layer (151) may include any one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl) as a doping element. The germanium (Ge) concentration of the first epitaxial layer (151) may be lower than that of the sacrificial layer (120) before the gate structure (160) is substituted. The first epitaxial layer (151) may have a lower etch selectivity than the sacrificial layer (120) under specific etching conditions during the manufacturing process. Due to this difference in etching selectivity, in the sacrificial layer (120) removal process, the sacrificial layer (120) is selectively removed, and the source / drain region (150) surrounded by the first epitaxial layer (151) may remain.

[0080] The second epitaxial layer (152) may be disposed on the first epitaxial layer (151). The second epitaxial layer may have a roughly U-shaped rounded form, but is not limited thereto.

[0081] The third epitaxial layer (153) may be placed on the second epitaxial layer (152). The third epitaxial layer (153) may be placed to completely fill the recess area of ​​the source / drain region (150).

[0083] The first to third epitaxial layers (151, 152, 153) may have different germanium (Ge) concentrations. The germanium (Ge) concentration may increase in the order of the first epitaxial layer (151), the second epitaxial layer (152), and the third epitaxial layer (153). For example, the first epitaxial layer (151) may include first silicon germanium (SiGe) containing germanium (Ge) of a first concentration, the second epitaxial layer (152) may include second silicon germanium (SiGe) containing germanium (Ge) of a second concentration higher than the first concentration, and the third epitaxial layer (153) may include third silicon germanium (SiGe) containing germanium (Ge) of a third concentration higher than the second concentration.

[0084] The fourth epitaxial layer (154) may comprise silicon (Si) doped with a group 3 element. For example, the fourth epitaxial layer (154) may comprise any one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). In an exemplary embodiment, the fourth epitaxial layer (154) may comprise silicon (Si) doped with boron (B), and the fourth epitaxial layer (154) may not substantially contain germanium (Ge). The fourth epitaxial layer (154) may be a protective layer capping the first to third epitaxial layers (151, 152, 153). At least a portion of the fourth epitaxial layer (154) may be formed at a level higher than the upper surface of the top channel layer (143), but is not limited thereto.

[0085] The first to fourth epitaxial layers (151, 152, 153, 154) have different material compositions (e.g., concentration of Ge), so they can be substantially distinguished through analysis such as TEM-EDS (Transmission Electron Microscopy Energy-Dispersive X-ray spectroscopy).

[0087] According to one embodiment, the semiconductor device (100e) may further include the internal spacer layers (130) of FIG. 6.

[0089] FIG. 8 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments.

[0090] Referring to FIG. 8, the semiconductor device (100f) may include a first region (E) and a second region (F). The first region (E) may be, for example, a region where NMOS transistors are placed, and the second region (F) may be, for example, a region where PMOS transistors are placed. The first region (E) and the second region (F) may be placed adjacent to each other or spaced apart.

[0091] The above description with reference to FIG. X can be applied in the same way to the transistor of the first region (E), and the above description with reference to FIG. X can be applied in the same way to the transistor of the second region (F).

[0093] FIGS. 9a through 9k are cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 9a through 9k illustrate an example of a method for manufacturing a semiconductor device of FIGS. 1 through 2c and illustrate cross-sections corresponding to FIG. 2a.

[0094] Referring to FIG. 9a, a substrate insulating layer (111) is disposed on a substrate (101), and sacrificial layers (120) and channel layers (141, 142, 143) can be alternately stacked on the substrate insulating layer (111).

[0095] The substrate insulating layer (111) can be formed on the substrate (101) through high-temperature annealing after an ion implantation process. For example, oxygen ions can be implanted.

[0096] The sacrificial layers (120) may be layers that are replaced by the gate dielectric layer (162) and the gate electrode layer (163) as in FIG. 2A through a subsequent process. The sacrificial layers (120) may be made of a material having etch selectivity with respect to the channel layers (141, 142, 143). The channel layers (141, 142, 143) may include a material different from the sacrificial layers (120). In an exemplary embodiment, the channel layers (141, 142, 142) may include silicon (SiGe), and the sacrificial layers (120) may include silicon (Si).

[0097] The sacrificial layers (120) and channel layers (141, 142, 143) can be formed by performing an epitaxial growth process using the lowest layer of the sacrificial layers (120) as a seed. Each of the sacrificial layers (120) and channel layers (141, 142, 143) is approximately 1 It may have a thickness in the range of 100 nm. The number of channel layers (141, 142, 143) alternately stacked with the sacrificial layer (120) may vary in the embodiments.

[0099] Referring to FIG. 9b, active structures can be formed by removing a portion of the stacked structure of sacrificial layers (120) and channel layers (141, 142, 143), the substrate insulating layer (111), and the substrate (101).

[0100] The active structure may include sacrificial layers (120) and channel layers (141, 142, 143) that are alternately stacked, and may further include an active region (105) formed so as to protrude onto the upper surface of the substrate (101) by removing a portion of the substrate insulating layer (111) and the substrate (101). The active structures may be formed in a line shape extending in one direction, for example, in the x-direction, and may be spaced apart from each other in the y-direction.

[0101] In the area where a portion of the substrate insulating layer (111) and the substrate (101) has been removed, an insulating material is buried, and then a recess is formed so that an active region (105) protrudes, thereby forming device isolation layers (110). The upper surface of the device isolation layers (110) may be formed lower than the upper surface of the active region (105).

[0103] Referring to FIG. 9c, sacrificial gate structures (170) and spacer layers (161) can be formed on the active structures.

[0105] The sacrificial gate structures (170) may be sacrificial structures formed in a region where a gate dielectric layer (162) and a gate electrode layer (163) are disposed on top of a channel structure (140) through a subsequent process as in FIG. 2a. The sacrificial gate structures (170) may include first and second sacrificial gate layers (172, 175) and a mask pattern layer (176) that are sequentially stacked. The first and second sacrificial gate layers (172, 175) may be patterned using the mask pattern layer (176). The first and second sacrificial gate layers (172, 175) may each be an insulating layer and a conductive layer. For example, the first sacrificial gate layer (172) may include silicon oxide, and the second sacrificial gate layer (175) may include polysilicon. The mask pattern layer (176) may include silicon nitride. The sacrifice gate structures (170) may have a line shape extending in one direction intersecting the active structures. The sacrifice gate structures (170) may extend in the y direction, for example, and be spaced apart from each other in the x direction.

[0106] Spacer layers (161) can be formed on both side walls of the sacrificial gate structures (170). The spacer layers (161) can be formed by forming a film of uniform thickness along the top and side surfaces of the sacrificial gate structures (170) and the active structures, and then performing anisotropic etching. The spacer layers (161) can be made of a low dielectric constant material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0108] Referring to FIG. 9d, channel structures (140) can be formed by removing exposed sacrificial layers (120) and channel layers (141, 142, 143) between sacrificial gate structures (170) to form a recess region (RC).

[0109] The active region (105) can be recessed to a predetermined depth from the upper surface to form a recessed region (RC). The recessed process can be formed by sequentially applying, for example, a dry etching process and a wet etching process. First, the recessed region (RC) can be formed in the vertical direction through the dry etching process. Next, the recessed region (RC) can be formed in the horizontal direction through the wet etching process.

[0110] At this time, since the plurality of channel layers (141, 142, 143) made of silicon germanium (SiGe) have a smaller etching selectivity than the sacrificial layers (120) made of silicon (Si), the depth at which the recess region (RC) is recessed along the first direction (X) below the sacrificial gate structures (170) may differ. For example, in the recess region (RC), the width along the first direction (X) at the level of the sacrificial layers (120) may be greater than the width along the first direction (X) at the level of the first to third channel layers (141, 142, 143). The remaining sacrificial layers (120) may be removed to a predetermined depth from the side along the x direction and may have inwardly concave sides. The remaining channel layers (141, 142, 143) may have the side along the x direction etched and may have outwardly convex sides.

[0111] Next, as the degree to which the sacrificial layer (120) is etched becomes smaller as it approaches the substrate insulating layer (111), the width of the recess region (RC) along the first direction (X) at the level of the sacrificial layers (120) can become smaller as it approaches the substrate insulating layer (111).

[0112] However, the shape of the sides of the sacrificial layers (120) and channel layers (141, 142, 143) and the width along the first direction (X) at the level of the sacrificial layers (120) are not limited to those illustrated. The sides of the sacrificial layers (120) and channel layers (141, 142, 143) may be formed to form a co-plane in a direction perpendicular to the upper surface of the substrate (101).

[0114] Referring to FIG. 9e, protective layers (155) can be formed within the recess area (RC).

[0115] The protective layers (155) may be extended to contact the channel layers (141, 142, 143) and the sacrificial layers (120) within the recess region (RC). As a result, the protective layers (155) may partially expose the substrate insulating layer (111), and the side of the protective layers (155) facing the recess region (RC) may include a region extending perpendicularly to the upper surface of the substrate (101). The side of the protective layers (155) that contacts the channel layers (141, 142, 143) and the sacrificial layers (120) may have a wavy shape.

[0116] The protective layers (155) may comprise silicon germanium (SiGe) doped with a group 3 element. According to an embodiment, the protective layers (155) may comprise any one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The protective layers (155) may be formed by supplying silicon (Si) and germanium (Ge) source gases under the supply of a carrier gas. In an exemplary embodiment, the carrier gas is hydrogen (H2) gas, the silicon (Si) source gas is, for example, silane (SiH4), dichlorosilane (SiH2Cl2; DCS) or chlorosilane (SiH3Cl; MCS), and the germanium (Ge) source gas may be, for example, germanium tetrahydrogenate (GeH4). The epitaxial layer (156) described below may also be formed in a similar manner.

[0117] The protective layers (155) may contain germanium (Ge) at a lower concentration than the plurality of channel layers (141, 142, 143). In an exemplary embodiment, the protective layers (155) may contain germanium (Ge) at a concentration greater than about 0 at% and less than or equal to about 10 at%, and the plurality of channel layers (141, 142, 143) may contain germanium (Ge) at a concentration of about 15 at% to about 40 at%. Accordingly, during the subsequent process described with reference to FIG. 9g, the epitaxial layer (156) can be protected by the protective layers (155) during the sacrificial layer (120) removal process.

[0119] Referring to FIG. 9f, a source / drain region (150) can be formed to fill the recess region (RC).

[0120] In the source / drain region (150), the epitaxial layer (156) can be formed by performing an epitaxial growth process using the protective layers (155) as seeds. Therefore, in the finally formed source / drain region (150), the boundary between the epitaxial layer (156) and the protective layers (155) may not be identifiable in an electron microscope image. However, even in this case, since the epitaxial layer (156) and the protective layers (155) have different material compositions, they can be substantially distinguished by analyzing the impurity concentration through analysis such as TEM-EDX (Transmission Electron Microscopy Energy-Dispersive X-ray spectroscopy).

[0122] Referring to FIG. 9g, an interlayer insulating layer (190) can be formed, and the sacrificial layers (120) and sacrificial gate structures (170) can be removed.

[0123] The interlayer insulating layer (190) can be formed by forming an insulating film covering the sacrificial gate structures (170) and the source / drain region (150) and performing a flattening process.

[0124] The sacrificial layers (120) and sacrificial gate structures (170) can be selectively removed with respect to the spacer layers (161), the interlayer insulating layer (190), and the plurality of channel layers (141, 142, 143). First, the sacrificial gate structures (170) can be removed to form upper gap regions (UR), and then the sacrificial layers (120) exposed through the upper gap regions (UR) can be removed to form lower gap regions (LR). For example, if the sacrificial layers (120) contain silicon germanium (SiGe) and the plurality of channel layers (141, 142, 143) contain silicon (Si), the sacrificial layers (120) can be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the above removal process, protective layers (155) made of silicon germanium (SiGe) can protect the epitaxial layer (156) by selectively etching the sacrificial layers (120) made of silicon (Si).

[0126] Referring to FIG. 9h, a gate structure (160) can be formed within the upper gap regions (UR) and the lower gap regions (LR).

[0127] The gate dielectric layer (162) can be formed to conformally cover the inner surfaces of the upper gap regions (UR) and lower gap regions (LR). The gate electrode layer (163) can be formed to completely fill the upper gap regions (UR) and lower gap regions (LR). The gate electrode layer (163) and the spacer layers (161) can be removed from the upper gap regions (UR) to a predetermined depth from the top. A gate capping layer (164) can be formed in the area where the gate electrode layer (163) and the spacer layers (161) have been removed from the upper gap regions (UR). By this, a gate structure (160) comprising the gate dielectric layer (162), the gate electrode layer (163), the spacer layers (161), and the gate capping layer (164) can be formed.

[0129] Referring to FIGS. 9i and FIGS. 9j, a contact plug (180) can be formed.

[0130] First, as illustrated in FIG. 9i, contact holes (CH) that expose source / drain regions (150) can be formed. The lower surface of the contact holes (CH) can be recessed into the source / drain regions (150).

[0131] Next, as illustrated in FIG. 9j, after depositing a material forming a barrier layer (184), a process such as a silicide process can be performed to form a metal-semiconductor compound layer (182) on the bottom surfaces of the contact holes (CH).

[0132] Next, referring together with FIG. 2a, a conductive material can be deposited to fill the contact holes (CH) to form a plug conductive layer (186). By this step, contact plugs (180) comprising a metal-semiconductor compound layer (182), a barrier layer (184), and a plug conductive layer (186) can be formed.

[0133] According to one embodiment, the contact plug (180) may be formed to penetrate at least a portion of the source / drain region (150). In this case, the metal-semiconductor compound layer (182) of the contact plug (180) may be in contact with a portion of the epitaxial layers (156), and the bottom of the metal-semiconductor compound layer (182) may be located at a lower level than the top of the plurality of channel layers (141, 142, 143). However, the shape and arrangement of the contact plug (180) are not limited thereto and may be varied.

[0135] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0137] 100: Semiconductor device 101: Substrate 105: Active region 110: Device isolation layer 111: Substrate insulating layer 120: Sacrificial layer 130: Internal spacer layer 140: Channel structure 141, 142, 143: Channel layer 150: Source / drain region 151: First epitaxial layer 152: Second epitaxial layer 153: Third epitaxial layer 154: Fourth epitaxial layer 155: Protective layer 156: Epitaxial layer 160: Gate structure 161: Spacer layer 162: Gate dielectric layer 163: Gate electrode 164: Gate capping layer 170: Sacrifice gate structure 180: Contact plug 190: Interlayer insulation layer

Claims

Claim 1 A semiconductor device comprising: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region and comprising silicon germanium (SiGe); a gate structure extending in a second direction on the substrate, intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers; a source / drain region disposed on the active region at least on one side of the gate structure and in contact with the plurality of channel layers; and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region comprises a first layer, the first layer contacts the side of the gate structure, the sides of the plurality of channel layers, and a first upper surface of the substrate insulating layer, and the first upper surface of the substrate insulating layer in contact with the source / drain region is located at the same level as the second upper surface of the substrate insulating layer in contact with the gate structure. Claim 2 In claim 1, the source / drain region is a semiconductor device spaced apart from the substrate by the substrate insulating layer. Claim 3 A semiconductor device according to claim 1, wherein the source / drain region comprises: a second layer disposed on the first layer and having a composition different from that of the first layer; and a third layer on the second layer, wherein the first layer comprises a first silicon germanium (SiGe) comprising a first concentration of germanium (Ge), the second layer comprises a second silicon germanium (SiGe) comprising a second concentration of germanium (Ge) higher than the first concentration, and the third layer comprises a third silicon germanium (SiGe) comprising a third concentration of germanium (Ge) higher than the second concentration. Claim 4 A semiconductor device according to claim 1, wherein the germanium (Ge) concentration of the plurality of channel layers is 15 at% to 40 at%. Claim 5 An active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region and comprising silicon germanium (SiGe); a gate structure extending in a second direction on the substrate, intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers; and a source / drain region disposed on the active region at least on one side of the gate structure and in contact with the plurality of channel layers. A semiconductor device comprising a source / drain region and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region comprises an epitaxial layer and protective layers, the epitaxial layer is in contact with the substrate insulating layer, the protective layers are in contact with at least some of the gate structure and the plurality of channel layers, the protective layers are spaced apart from each other in the first direction by the epitaxial layer, and the first upper surface of the substrate insulating layer in contact with the source / drain region is located at the same level as the second upper surface of the substrate insulating layer in contact with the gate structure. Claim 6 A semiconductor device according to claim 5, wherein the protective layers contain impurities, and the concentration of the impurities is greater than 0 at% and less than or equal to 10 at%. Claim 7 A semiconductor device according to claim 5, wherein the gate structure comprises an upper portion disposed above the uppermost channel layer among the plurality of channel layers and a lower portion disposed below each of the plurality of channel layers, and each of the protective layers comprises protrusions protruding toward the gate structure at the same level as the lower portion of the gate structure. Claim 8 A semiconductor device according to claim 7, wherein the width of the protrusions in the first direction becomes smaller as they approach the substrate insulating layer. Claim 9 A semiconductor device according to claim 7, wherein the side of the epitaxial layer in contact with the protective layers includes a portion protruding toward the protective layers at the same level as the lower portion of the gate structure. Claim 10 An active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active region and comprising silicon germanium (SiGe); a gate structure extending in a second direction on the substrate, intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers; and a source / drain region disposed on the active region at least on one side of the gate structure and in contact with the plurality of channel layers. A semiconductor device comprising a source / drain region and a substrate insulating layer disposed between the source / drain region and the substrate, wherein the source / drain region comprises an epitaxial layer in contact with the side surface of the plurality of channel layers and a first upper surface of the substrate insulating layer, at least a portion of the side surface of the epitaxial layer forms a surface perpendicular to the upper surface of the substrate, the lower surface of the epitaxial layer forms a flat surface, the lower surface of the gate dielectric layer surrounding the lowest gate electrode of the gate structure contacts a second upper surface of the substrate insulating layer, and the first upper surface of the substrate insulating layer in contact with the source / drain region is located at the same level as the second upper surface of the substrate insulating layer in contact with the gate structure.

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