Manufacturing method of power semiconductor device and power semiconductor device manufactured by the method

Abstract

A method for manufacturing a power semiconductor device and a power semiconductor device manufactured by this method are disclosed. A high electron mobility transistor (HEMT) structure may be applied to the power semiconductor device. The disclosed high electron mobility transistor (HEMT) may include a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer and inducing a 2-dimensional electron gas (2DEG) in the first semiconductor layer, a depletion forming layer disposed on the second semiconductor layer and forming a depletion region in the 2DEG, a void region defined below the depletion forming layer and formed such that at least a portion of the second semiconductor layer is recessed and extends into the second semiconductor layer, a mask pattern disposed between the depletion forming layer and the void region and including an insulating mask layer, a gate disposed on the depletion forming layer, and a source and a drain electrically connected to at least one of the first and second semiconductor layers. The above mask pattern may have a multilayer structure further comprising a metal mask layer disposed between the insulating mask layer and the void region.

Description

Technology Field

[0001] The present invention relates to a transistor, a method for manufacturing the same, and a device including a transistor, and more specifically, to a high electron mobility transistor, a method for manufacturing the same, and an electronic device including a high electron mobility transistor. Background Technology

[0002] Various power conversion systems require power devices, which are components that control the flow of current through ON / OFF switching. In power conversion systems, the efficiency of the power device can determine the overall system efficiency.

[0003] Most existing power devices have been silicon (Si)-based power MOSFETs (metal-oxide-semiconductor field-effect transistors) or IGBTs (insulated gate bipolar transistors). However, due to limitations in silicon's physical properties and manufacturing processes, it has become difficult to increase the efficiency of silicon-based power devices. To overcome these problems, research has been conducted to improve conversion efficiency by applying III-V compound semiconductors to power devices. In this regard, high electron mobility transistors (HEMTs), which utilize the heterojunction structure of compound semiconductors, are attracting attention.

[0004] HEMTs contain semiconductors with different electrical polarization characteristics. In a HEMT, a semiconductor layer with a relatively large polarization rate can induce a two-dimensional electron gas (hereinafter, 2DEG) in another semiconductor layer bonded to it. The 2DEG can have very high electron mobility and can be used as a channel in the HEMT. However, in order to utilize HEMTs effectively in various electronic devices, it is necessary to appropriately adjust or improve their characteristics. In particular, it is necessary to adjust or improve the threshold voltage and ON-current level of the HEMT.

[0005] Conventional methods for implementing normally-off devices by adjusting the threshold voltage of HEMTs include applying a recessed gate structure, applying a p-type gallium nitride layer under the gate electrode, or combining the two methods to apply a p-type gallium nitride layer within the recess region. However, conventional recess formation methods form the recess region in the semiconductor layer (barrier layer) using a dry etching method, which causes etching damage to the semiconductor layer and the device. Furthermore, if the barrier layer is thin, the carrier concentration decreases, leading to a significant reduction in ON-current. Meanwhile, in the case of the method applying a p-type gallium nitride layer, the semiconductor layer (barrier layer) must be formed thinly to remove 2DEG from the channel layer under the gate electrode. If the barrier layer is thin, the carrier concentration in 2DEG decreases, which can lead to a decrease in ON-current. Furthermore, from a process perspective, a p-type gallium nitride layer is formed on the front surface of the barrier layer and then patterned using a dry etching method to leave a gate-shaped p-type gallium nitride layer; however, since it is difficult to precisely stop the etching at the upper surface of the barrier layer, there are issues with the reproducibility and reliability of the etching process. The problem to be solved

[0006] The technical problem to be solved by the present invention is to provide a high electron mobility transistor (HEMT) having normally-off characteristics that can be manufactured to have excellent physical properties without etching damage caused by dry etching, and a method for manufacturing the same.

[0007] Furthermore, the technical objective of the present invention is to provide a high electron mobility transistor (HEMT) and a method for manufacturing the same, which can prevent reproducibility and reliability issues of the etching process, has a relatively high threshold voltage, and possesses stable normally-off characteristics.

[0008] Furthermore, the technical objective of the present invention is to provide a high electron mobility transistor (HEMT) and a method for manufacturing the same, which enables the application of a relatively thicker barrier layer (channel supply layer) than conventional methods and thereby secures a higher ON-current.

[0009] In addition, the technical problem that the present invention aims to solve is to provide an electronic device (e.g., a power device) comprising the high electron mobility transistor (HEMT).

[0010] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be understood by those skilled in the art from the description below. means of solving the problem

[0011] According to one embodiment of the present invention, a high electron mobility transistor (HEMT) is provided, comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer and inducing a 2-dimensional electron gas (2DEG) in the first semiconductor layer; a depletion forming layer disposed on the second semiconductor layer and forming a depletion region in the 2DEG; a void region defined below the depletion forming layer, formed such that at least a portion of the second semiconductor layer is recessed and extends into the second semiconductor layer, having a structure extending into the depletion forming layer, wherein the thickness of the portion extending into the depletion forming layer is in the range of 5 to 1000 nm; a gate disposed on the depletion forming layer; and a source and a drain spaced apart from the gate and electrically connected to at least one of the first and second semiconductor layers.

[0012] The above-mentioned depletion forming layer may have a width greater than that of the void region and may have a structure extended in both directions of the void region.

[0013] The upper region of the void region may be disposed within the depletion forming layer, and the depletion forming layer may be disposed to cover the upper surface and both sides of the upper region.

[0014] The HEMT may further include an insulating passivation layer disposed on the second semiconductor layer region between the depletion forming layer and the source and between the depletion forming layer and the drain.

[0015] The first semiconductor layer may include a gallium nitride-based material.

[0016] The second semiconductor layer may have a single layer or multilayer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B.

[0017] The above depletion forming layer may include a p-type semiconductor.

[0018] According to another embodiment of the present invention, a high electron mobility transistor (HEMT) is provided, comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer and inducing a 2-dimensional electron gas (2DEG) in the first semiconductor layer; a depletion forming layer disposed on the second semiconductor layer and forming a depletion region in the 2DEG; a void region defined below the depletion forming layer and formed such that at least a portion of the second semiconductor layer is recessed and extends into the second semiconductor layer; a mask pattern disposed between the depletion forming layer and the void region and comprising an insulating mask layer; a gate disposed on the depletion forming layer; and a source and a drain spaced apart from the gate and electrically connected to at least one of the first and second semiconductor layers.

[0019] The above mask pattern can be embedded into the above depletion forming layer.

[0020] The above depletion forming layer may have a width greater than the mask pattern and may be positioned to cover the upper surface and both sides of the mask pattern.

[0021] The above mask pattern may have a multilayer structure further comprising a metal mask layer disposed between the insulating mask layer and the void region.

[0022] The above metal mask layer may include a metal having a melting point of about 1000°C or higher.

[0023] The metal mask layer may have a single-layer or multi-layer structure comprising at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), and palladium (Pd).

[0024] The HEMT may further include an insulating passivation layer disposed on the second semiconductor layer region between the depletion forming layer and the source and between the depletion forming layer and the drain.

[0025] The first semiconductor layer may include a gallium nitride-based material.

[0026] The second semiconductor layer may have a single layer or multilayer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B.

[0027] The above depletion forming layer may include a p-type semiconductor.

[0028] According to another embodiment of the present invention, a power device comprising the aforementioned HEMT is provided.

[0029] According to another embodiment of the present invention, a method for manufacturing a high electron mobility transistor (HEMT) is provided, comprising: forming a first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer that causes a 2DEG within the first semiconductor layer; defining a state in which a mask pattern having a multilayer structure including a metal mask layer and an insulating mask layer sequentially disposed on a part of the second semiconductor layer is disposed, and an insulating mask material layer having an opening that exposes the second semiconductor layer region on both sides of the mask pattern is disposed on the second semiconductor layer; forming a void region by recessing the portion of the second semiconductor layer below the metal mask layer while forming a depletion forming layer that grows to cover the mask pattern from the second semiconductor layer region exposed on both sides of the mask pattern and forms a depletion region in the 2DEG; forming a gate on the depletion forming layer; and forming a source and a drain that are spaced apart from the gate and are electrically connected to at least one of the first and second semiconductor layers.

[0030] The step of forming the void region while forming the depletion forming layer can be performed under a temperature condition of about 1000°C or higher in a gas atmosphere containing hydrogen, and the second semiconductor layer portion below the metal mask layer can be etched by a hydrogen radical reaction to form the void region.

[0031] The above metal mask layer may include a metal having a melting point of about 1000°C or higher.

[0032] The metal mask layer may have a single-layer or multi-layer structure comprising at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), and palladium (Pd).

[0033] After the step of forming the void region while forming the depletion forming layer, the step of removing the insulating mask material layer may be further performed.

[0034] After the step of forming the void region while forming the depletion forming layer, a further step of removing the region where the source and drain are to be formed in the insulating mask material layer may be performed, and the remaining insulating mask material layer may be used as an insulating passivation layer.

[0035] Before forming the gate, source, and drain, a step of removing the metal mask layer or a step of removing the insulating mask layer and the metal mask layer may be further performed.

[0036] The first semiconductor layer may include a gallium nitride-based material.

[0037] The second semiconductor layer may have a single layer or multilayer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B.

[0038] The above depletion forming layer may include a p-type semiconductor. Effects of the invention

[0039] According to embodiments of the present invention, a HEMT having normally-off characteristics and a method for manufacturing the same can be realized, which can be manufactured to have excellent physical properties without etching damage caused by dry etching. Furthermore, according to embodiments of the present invention, the invention provides a HEMT having stable normally-off characteristics with a relatively high threshold voltage, which can prevent problems regarding the reproducibility and reliability of the etching process, and a method for manufacturing the same. Additionally, according to embodiments of the present invention, the invention provides a HEMT and a method for manufacturing the same that can secure a higher ON-current by applying a barrier layer (channel supply layer) that is relatively thicker than in conventional methods.

[0040] According to one embodiment, by using a growth (re-growth) technique for a compound semiconductor (depletion formation layer) using a metal mask to decompose the portion of the lower semiconductor layer in contact with the metal mask, a void region formed by recesses can be formed during the thin film growth process without a separate etching process (dry etching process), and a HEMT having normally-off characteristics can be manufactured without etching damage. Therefore, the problem of plasma damage occurring during dry etching can be prevented.

[0041] According to one embodiment, since a depletion forming layer (e.g., a p-type semiconductor layer) can be formed in a growth (re-growth) manner only in a desired area without a patterning process using etching, problems regarding the reproducibility and reliability of the etching process can be prevented and the ease of the process can be improved.

[0042] According to one embodiment, by utilizing the void formation effect caused by the recess of the semiconductor layer, a relatively thicker barrier layer (channel supply layer) can be applied compared to the conventional method of applying a p-type gallium nitride layer, and an ON-current improvement effect can be obtained accordingly.

[0043] According to one embodiment, by applying a void region formed by a recess and a depletion forming layer (e.g., a p-type semiconductor layer) together, a HEMT device having a high threshold voltage and stable normally-off characteristics can be reproducibly implemented.

[0044] According to one embodiment, by using a multilayer mask comprising a metal mask layer and an insulating mask layer, the film quality of the growing depletion forming layer (e.g., a p-type semiconductor layer) can be improved and the depletion forming layer can be formed stably, thereby enabling the improvement of HEMT performance and processability.

[0045] By applying the HEMT according to the embodiments of the present invention, various electronic devices (e.g., power devices) having excellent performance can be realized.

[0046] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0047] FIG. 1 is a cross-sectional view showing a high electron mobility transistor (HEMT) according to one embodiment of the present invention. FIG. 2 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. FIG. 3 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. FIG. 4 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. FIG. 5 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. FIGS. 7a to 7g are cross-sectional views showing a method for manufacturing HEMT according to one embodiment of the present invention. FIG. 8 is a scanning electron microscope (SEM) cross-sectional image showing a structure manufactured according to a process similar to an embodiment of the present invention. FIGS. 9a to 9c are cross-sectional views showing a method for manufacturing HEMT according to another embodiment of the present invention. FIGS. 10a to 10c are cross-sectional views showing a method for manufacturing HEMT according to another embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing HEMT according to another embodiment of the present invention. FIGS. 12a to 12e are cross-sectional views showing a method for manufacturing HEMT according to another embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a method for manufacturing HEMT according to another embodiment of the present invention. Specific details for implementing the invention

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0049] The embodiments of the present invention described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments may be modified in various other forms.

[0050] The terms used herein are for describing specific embodiments and are not intended to limit the invention. Terms used herein in the singular form may include plural forms unless the context clearly indicates otherwise. Additionally, the terms “comprise” and / or “comprising” used herein specify the presence of the mentioned features, steps, numbers, actions, components, elements, and / or groups thereof, and do not exclude the presence or addition of one or more other features, steps, numbers, actions, components, elements, and / or groups thereof. Furthermore, the term “connected” used herein means not only that components are directly connected, but also includes the concept of indirectly connecting components through the interposition of additional components between them.

[0051] Furthermore, when a component is described in this specification as being located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components. The term "and / or" as used in this specification includes any one of the listed items and all combinations of one or more thereof. Additionally, terms of degree such as "about" and "substantially" as used in this specification are used to mean a range of numerical values ​​or degrees or approximate values, taking into account inherent manufacturing and material tolerances, and are used to prevent an infringer from unfairly exploiting the disclosures in which precise or absolute figures provided to aid in understanding this specification are mentioned.

[0052] Embodiments of the present invention will be described in detail below with reference to the attached drawings. The sizes or thicknesses of the areas or parts depicted in the attached drawings may be slightly exaggerated for the clarity of the specification and convenience of explanation. Throughout the detailed description, the same reference numerals indicate the same components.

[0053] FIG. 1 is a cross-sectional view showing a high electron mobility transistor (HEMT) according to one embodiment of the present invention.

[0054] Referring to FIG. 1, a first semiconductor layer (SL10) may be disposed on a substrate (SUB10). The substrate (SUB10) may be composed of, for example, sapphire, Si, SiC, GaN, etc. However, the type of substrate (SUB10) is not limited to the above and may vary in various ways. The first semiconductor layer (SL10) may be a channel layer. The first semiconductor layer (SL10) may include a compound semiconductor of the III-V group. For example, the first semiconductor layer (SL10) may include a GaN-based material (e.g., GaN). In this case, the first semiconductor layer (SL10) may be an undoped GaN layer, but in some cases, it may be a GaN layer doped with a predetermined impurity.

[0055] Although not illustrated, a buffer layer may be provided between the substrate (SUB10) and the first semiconductor layer (SL10). The buffer layer can eliminate leakage current to the lower part of the 2DEG through high resistance characteristics and enable a high off-state breakdown voltage and a sharp pinch-off. Additionally, the buffer layer may be provided to prevent a decrease in the crystallinity of the first semiconductor layer (SL10) by mitigating the difference in lattice constant and coefficient of thermal expansion between the substrate (SUB10) and the first semiconductor layer (SL10). The buffer layer may have a single-layer or multi-layer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B. As a specific example, the buffer layer may have a single-layer or multi-layer structure comprising at least one of various materials such as AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN, etc. In some cases, a predetermined seed layer (not shown) may be further provided between the substrate (SUB10) and the buffer layer. The seed layer may be a base layer for the growth of the buffer layer.

[0056] A second semiconductor layer (SL20) may be disposed on a first semiconductor layer (SL10). The second semiconductor layer (SL20) may be referred to as a barrier layer or a channel supply layer. Here, the term 'barrier layer' may be related to the role of the second semiconductor layer (SL20) in terms of energy band structure. The second semiconductor layer (SL20) may be a semiconductor layer different from the first semiconductor layer (SL10).

[0057] The second semiconductor layer (SL20) may be a layer that induces a two-dimensional electron gas (hereinafter, 2DEG) in the first semiconductor layer (SL10). The 2DEG may be formed in the portion of the first semiconductor layer (SL10) below the interface between the first semiconductor layer (SL10) and the second semiconductor layer (SL20). The second semiconductor layer (SL20) may include a material (semiconductor) that has different polarization characteristics and / or an energy bandgap and / or a lattice constant from the first semiconductor layer (SL10). The second semiconductor layer (SL20) may include a material (semiconductor) that has a larger polarization rate and / or energy bandgap than the first semiconductor layer (SL10).

[0058] For example, the second semiconductor layer (SL20) may have a single-layer or multi-layer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B. As a specific example, the second semiconductor layer (SL20) may have a single-layer or multi-layer structure comprising at least one of various materials such as AlGaN, AlInN, InGaN, AlN, AlInGaN, etc. The second semiconductor layer (SL20) may be an undoped layer, but may also be a layer doped with a predetermined impurity.

[0059] A depletion formation layer (P10) that forms a depletion region in the 2DEG may be disposed on the second semiconductor layer (SL20). The depletion formation layer (P10) may be grown and formed on a portion of the second semiconductor layer (SL20). The 2DEG region corresponding to the area of ​​the second semiconductor layer (SL20) in contact with the depletion formation layer (P10) may be depleted.

[0060] The energy bandgap of the second semiconductor layer (SL20) in contact with it can be increased by the depletion forming layer (P10), and as a result, a depletion region can be formed in the 2DEG of the first semiconductor layer (SL10) corresponding to the region of the second semiconductor layer (SL20) in contact with the depletion forming layer (P10). Accordingly, the 2DEG region corresponding to the region of the second semiconductor layer (SL20) in contact with the depletion forming layer (P10) may be broken or have characteristics (electron concentration, etc.) different from the remaining region. The region where the 2DEG is broken can be called a 'broken region'.

[0061] The depletion forming layer (P10) may be a p-type semiconductor layer or a layer doped with p-type impurities (i.e., a p-doped layer). Additionally, the depletion forming layer (P10) may include a nitride semiconductor of the III-V series. For example, the depletion forming layer (P10) may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with p-type impurities such as Mg. As a specific example, the depletion forming layer (P10) may be a p-GaN layer or a p-AlGaN layer. The depletion forming layer (P10) may include a compound semiconductor, and the compound semiconductor may be a p-type semiconductor, for example, Al x Ga 1-x N (0<x≤1), In x Al 1-x N (0 < x ≤ 1) and In x Al y Ga 1-x-y N may include any one selected from [0<x≤1, 0<y≤1, 0<(x+y)≤1]. As the energy bandgap of the second semiconductor layer (SL20) in contact with it is raised by this depletion forming layer (P10), a 'disconnected region' (depletion region) may be formed in 2DEG.

[0062] A void region (V1) may be defined (formed) below the depletion forming layer (P10). The void region (V1) may be an air-void region as an empty region. The void region (V1) may be formed such that at least a part of the second semiconductor layer (SL20) is recessed and extends into the second semiconductor layer (SL20). The void region (V1) may be a type of recess region, and said recess region may be an empty space.

[0063] At least a portion of the void region (V1) may be formed in the semiconductor layer (SL20). At least a portion of the void region (V1) may be an area formed by recessing a portion of the second semiconductor layer (SL20) to a predetermined depth. The void region (V1) may be formed at a depth shallower than the interface between the first semiconductor layer (SL10) and the second semiconductor layer (SL20). For example, the void region (V1) may have a depth of at least 1 / 3 or at least 1 / 2 of the thickness of the second semiconductor layer (SL20) from the interface between the second semiconductor layer (SL20) and the depletion forming layer (P10). A discontinuous region may be formed in the 2DEG at the interface between the first semiconductor layer (SL10) and the second semiconductor layer (SL20) by the void region (V1). The portion of the 2DEG corresponding to the void region (V1) may be broken or have different characteristics (such as electron concentration) from the remaining region. The thickness of the second semiconductor layer (SL20) in the void region (V1) may be, for example, tens of nm or less, about 20 nm or less, or about 10 nm or less. The depth from the interface between the second semiconductor layer (SL20) and the depletion forming layer (P10) to the bottom surface of the void region (V1) may be several nm or more, and the width of the void region (V1) may be several nm or more and thousands of nm or less.

[0064] The void region (V1) may be formed such that at least a portion of the second semiconductor layer (SL20) is recessed and extends into the second semiconductor layer (SL20), and may also have a structure that extends (extends) into the depletion forming layer (P10). The upper portion of the void region (V1) may be inserted (i.e., embedded) into the depletion forming layer (P10). Accordingly, the depletion forming layer (P10) may cover the upper surface and both sides of the upper portion. Here, the two sides may be the two sides along the width direction of the void region (V1). The thickness (t1) of the portion extending from the void region (V1) into the depletion forming layer (P10) may be in the range of about 5 to 1000 nm or about 10 to 500 nm. Additionally, the depletion forming layer (P10) may have a width greater than that of the void region (V1) and may have a structure extended in both directions of the void region (V1). The depletion forming layer (P10) may be in contact with the upper surface area of ​​the second semiconductor layer (SL20) on both sides of the void region (V1).

[0065] Since the void region (V1) may be formed through a decomposition reaction rather than a dry etching method, etching damage problems such as plasma damage may not occur when forming the void region (V1). In some cases, the void region (V1) may be formed through a decomposition reaction and wet etching.

[0066] A gate electrode (G10) may be disposed on a depletion forming layer (P10). The gate electrode (G10) may be formed from various metals or metal compounds. The width of the gate electrode (G10) may be smaller than or equal to the width of the depletion forming layer (P10). However, in some cases, the gate electrode (G10) may have a width greater than that of the depletion forming layer (P10). When an insulating layer is provided on the second semiconductor layer (SL20) on both sides of the depletion forming layer (P10), the gate electrode (G10) may be formed to extend onto the insulating layer.

[0067] A source electrode (S10) and a drain electrode (D10) may be provided, which are spaced apart from the gate electrode (G10) and are electrically connected to at least one of the first and second semiconductor layers (SL10, SL20). The source electrode (S10) and the drain electrode (D10) may be provided on the second semiconductor layer (SL20) on both sides of the gate electrode (G10). The source electrode (S10) and the drain electrode (D10) may be electrically connected to the 2DEG. The source electrode (S10) and the drain electrode (D10) may make an ohmic contact with the second semiconductor layer (SL20). In some cases, an ohmic contact layer (not shown) may be further provided between the source electrode (S10) and the second semiconductor layer (SL20) and between the drain electrode (D10) and the second semiconductor layer (SL20).

[0068] The source electrode (S10) and drain electrode (D10) may have a structure inserted into the interior of the second semiconductor layer (SL20) or the interior of the first semiconductor layer (SL10). For example, after etching (recessing) a portion of the second semiconductor layer (SL20) and the first semiconductor layer (SL10), the source electrode (S10) and drain electrode (D10) may be formed in the etched area (recessed area). At this time, the depth of the etched area (recessed area) may be deeper than the depth of the 2DEG. Therefore, the source electrode (S10) and drain electrode (D10) may come into direct contact with the side of the 2DEG. Alternatively, the source / drain electrodes (S10, D10) may be formed after etching only a portion of the second semiconductor layer (SL20) to a predetermined depth. That is, after etching (recessing) a portion of the second semiconductor layer (SL20) to the interface between the first semiconductor layer (SL10) and the second semiconductor layer (SL20) or to a shallower depth, source / drain electrodes (S10, D10) can be formed in the etched region (recessed region). In addition, the configuration of the source electrode (S10) and the drain electrode (D10) can be varied in various ways.

[0069] A HEMT according to an embodiment of the present invention may have normally-off characteristics due to a void region (V1) and a depletion forming layer (P10). That is, the HEMT according to the embodiment may be a normally-off device. The HEMT may have a positive (+) threshold voltage. By applying a void region (V1) and a depletion forming layer (P10) together through a recess, a HEMT device having a high threshold voltage and stable normally-off characteristics can be reproducibly implemented.

[0070] In addition, according to an embodiment of the present invention, since a decomposition reaction rather than dry etching is used to form the void region (V1), the problem of damage to the thin film and device caused by dry etching can be prevented. According to an embodiment of the present invention, since the depletion forming layer (P10) can be formed in a growth (re-growth) manner only in the desired area without a patterning process using etching, problems regarding the reproducibility and reliability of the etching process can be prevented, and the ease of the process can be improved. According to an embodiment of the present invention, by utilizing the void formation effect caused by the recess of the second semiconductor layer (SL20), a relatively thicker second semiconductor layer (SL20) can be applied compared to the conventional method, and an improvement in ON-current can be obtained accordingly.

[0071] FIG. 2 is a cross-sectional view showing a HEMT according to another embodiment of the present invention.

[0072] Referring to FIG. 2, the HEMT according to the present embodiment may further include an insulating passivation layer (NP10). The insulating passivation layer (NP10) may be disposed on a second semiconductor layer (SL20) region between the depletion forming layer (P10) and the source electrode (S10) and between the depletion forming layer (P10) and the drain electrode (D10). The insulating passivation layer (NP10) may include, for example, at least one of silicon oxide, silicon nitride, silicon nitrate, and a high-dielectric constant (high-k) material. The high-dielectric constant material may be a material having a dielectric constant higher than that of silicon nitride, and may include, as a non-limiting example, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), etc. In FIG. 2, the remaining configuration excluding the insulating passivation layer (NP10) may be the same as described in FIG. 1.

[0073] FIG. 3 is a cross-sectional view showing a HEMT according to another embodiment of the present invention.

[0074] Referring to FIG. 3, the HEMT according to the present embodiment may include a first semiconductor layer (SL10) disposed on a substrate (SUB10), a second semiconductor layer (SL20) disposed on the first semiconductor layer (SL10) to induce a 2DEG in the first semiconductor layer (SL10), and a depletion forming layer (P10) disposed on the second semiconductor layer (SL20) to form a depletion region in the 2DEG. The HEMT may include a void region (V1) defined (formed) below the depletion forming layer (P10), and the void region (V1) may be formed such that at least a portion of the second semiconductor layer (SL20) is recessed and extends into the second semiconductor layer (SL20). As a non-limiting example, the void region (V1) may be disposed below the central part or approximately the central part of the depletion forming layer (P10).

[0075] The above HEMT may further include a mask pattern (MP1) disposed between the depletion forming layer (P10) and the void region (V1). The mask pattern (MP1) may include an insulating mask layer (N10). Additionally, the mask pattern (MP1) may further include a metal mask layer (M10) disposed between the insulating mask layer (N10) and the void region (V1). The mask pattern (MP1) may have a multilayer structure comprising a metal mask layer (M10) and an insulating mask layer (N10). An insulating mask layer (N10) may be in contact with the upper surface of the metal mask layer (M10), and a depletion forming layer (P10) may be in contact with the upper surface of the insulating mask layer (N10). The mask pattern (MP1) may be embedded within the depletion forming layer (P10). Both the insulating mask layer (N10) and the metal mask layer (M10) can be embedded and disposed within the depletion forming layer (P10).

[0076] The depletion forming layer (P10) may have a width greater than that of the mask pattern (MP1) and may be positioned to cover the upper surface and both sides of the mask pattern (MP1). The two sides may be the sides along the width direction of the mask pattern (MP1). The depletion forming layer (P10) may have a structure that extends to both sides of the insulating mask layer (N10) and the metal mask layer (M10) while covering them. The insulating mask layer (N10) and the metal mask layer (M10) may have the same width, but in some cases, they may have different widths.

[0077] The metal mask layer (M10) can serve as a mask for growing (regrowing) the depletion forming layer (P10). Additionally, the metal mask layer (M10) can play a specific role in forming a void region (V1) during the growth process of the depletion forming layer (P10). The void region (V1) may not be a region formed by a dry etching method. The void region (V1) may be a region formed as the portion of the second semiconductor layer (SL20) in contact with the metal mask layer (M10) is decomposed and recessed during the growth process of the depletion forming layer (P10). Therefore, in forming the void region (V1), etching damage issues such as plasma damage may not occur.

[0078] The depletion forming layer (P10) may have a width greater than that of the void region (V1) and may have a structure extended in both directions of the void region (V1). The void region (V1) may be formed directly below the metal mask layer (M10), and the widths of the void region (V1) and the metal mask layer (M10) may be the same or similar.

[0079] According to one embodiment, the metal mask layer (M10) may be composed of or include a metal having a melting point of about 1000°C or higher. The melting point of the metal may be, for example, about 1000°C to 4000°C. Since the process temperature in the growth of the depletion forming layer (P10) and the formation of the void region (V1) may be about 1000°C or higher, it may be advantageous to apply a metal having a melting point of about 1000°C or higher to the metal mask layer (M10). As a specific example, the metal mask layer (M10) may have a single-layer or multi-layer structure comprising at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), and palladium (Pd). Melting points (T) of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), palladium (Pd), etc. m The thermal conductivity [W / (cm·K)] and work function (eV) are summarized as shown in Table 1 below.

[0080] substance T m (℃) Thermal conductivity [W / (cm·K)] Work function (eV) W 3422 1.740 4.55 Re 3186 0.479 4.72 Os 3033 0.876 5.93 Ta 3017 0.575 4.25 Mo 2623 1.380 4.50∼4.95 Nb 2477 0.537 3.95∼4.87 Hf 2233 0.230 3.90 Rh 1966 1.5 4.98 Cr 1907 0.937 4.50 Zr 1855 0.227 4.05 Ti 1668 0.219 4.33 Pd 1555 0.718 5.22 Sapphire 2027 0.32∼0.35 GaN 2500 1.3

[0081] According to one embodiment, the thickness of the metal mask layer (M10) may be about 0.1 to 100 nm or about 1 to 50 nm, but is not limited thereto. In some cases, the thickness of the metal mask layer (M10) may be about 100 nm or more.

[0082] An insulating mask layer (N10) is placed on a metal mask layer (M10) and can serve to enable the depletion forming layer (P10) to grow more stably during the growth process of the depletion forming layer (P10). Stable growth of the depletion forming layer (P10) can be enabled by the insulating mask layer (N10), and the film quality of the depletion forming layer (P10) can be improved.

[0083] According to one embodiment, the insulating mask layer (N10) may comprise at least one of, for example, silicon oxide, silicon nitride, silicon nitrate, and a high-k dielectric material. The high-k dielectric material may be a material having a dielectric constant higher than that of silicon nitride, and may include, as a non-limiting example, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), etc. The thickness of the insulating mask layer (N10) may be, for example, several nm to several hundred nm.

[0084] The HEMT according to the present embodiment may include a gate electrode (G10), a source electrode (S10), and a drain electrode (D10). The configuration and characteristics of the gate electrode (G10), the source electrode (S10), and the drain electrode (D10) may be the same as described in FIG. 1. Additionally, the HEMT may further include an insulating passivation layer (NP10). The configuration and characteristics of the insulating passivation layer (NP10) may be the same as described in FIG. 2.

[0085] In the embodiment of FIG. 3, the metal mask layer (M10) may be excluded. An example thereof is shown in FIG. 4.

[0086] FIG. 4 is a cross-sectional view showing a HEMT according to another embodiment of the present invention.

[0087] Referring to FIG. 4, as the metal mask layer (M10 in FIG. 3) is removed, the void region (V1) may have a structure that extends (expands) into the depletion forming layer (P10). The upper region of the void region (V1) may be inserted (i.e. embedded) into the depletion forming layer (P10). In this embodiment, the insulating mask layer (N10) itself may be a 'mask pattern'. That is, the mask pattern may be composed of the insulating mask layer (N10).

[0088] As in the embodiment of FIG. 4, when the metal mask layer (M10) is excluded, the channel control characteristics by the gate electrode (G10) may be further improved. However, even when the metal mask layer (M10) is present, the channel control characteristics of the gate electrode (G10) may be relatively excellent. The structure in FIG. 4 in which the insulating mask layer (N10) is excluded may correspond to the structure of FIG. 2. In addition, the structure in FIG. 4 in which the insulating mask layer (N10) and the insulating passivation layer (NP10) are excluded may correspond to the structure of FIG. 1.

[0089] FIG. 5 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. This embodiment has a structure in which a part of FIG. 3 is modified.

[0090] Referring to FIG. 5, the mask pattern (MP1) may have a multilayer structure including a metal mask layer (M10) and an insulating mask layer (N10), and the insulating mask layer (N10) may have a wider width than the metal mask layer (M10). The insulating mask layer (N10) may be positioned to cover the upper surface and both sides of the metal mask layer (M10). In this case, since the insulating mask layer (N10) can act as an insulating barrier on the upper surface and both sides of the metal mask layer (M10), the depletion forming layer (P10) can grow more stably and the film quality can be improved.

[0091] FIG. 6 is a cross-sectional view showing a HEMT according to another embodiment of the present invention. This embodiment corresponds to a structure in which the metal mask layer (M10) is excluded from the embodiment of FIG. 5.

[0092] Referring to FIG. 6, as the metal mask layer (M10 in FIG. 5) is removed, the void region (V1) may have a structure that extends (extends) into the depletion forming layer (P10). The upper region of the void region (V1) may be inserted (i.e. embedded) into the depletion forming layer (P10). The insulating mask layer (N10) itself may be a 'mask pattern'.

[0093] In FIG. 6, the insulating mask layer (N10) can be removed, in which case the void region (V1) is further extended into the depletion forming layer (P10), and the upper region of the void region (V1) may have a slightly larger width than the lower region. Additionally, in FIG. 6, a structure in which the insulating mask layer (N10) and the insulating passivation layer (NP10) are excluded is also possible.

[0094] FIGS. 7a to 7g are cross-sectional views showing a method for manufacturing HEMT according to one embodiment of the present invention.

[0095] Referring to FIG. 7a, a first semiconductor layer (200) can be formed on a substrate (100). The substrate (100) may be, for example, a substrate composed of sapphire, Si, SiC, GaN, etc. However, the type of substrate (100) is not limited to the above and can be varied in many ways. The first semiconductor layer (200) may be a channel layer. The first semiconductor layer (200) may include a compound semiconductor of the III-V group. For example, the first semiconductor layer (200) may include a GaN-based material (e.g., GaN). In this case, the first semiconductor layer (200) may be an undoped GaN layer, but in some cases, it may be a GaN layer doped with a predetermined impurity. The first semiconductor layer (200) may be grown, for example, by MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy). The first semiconductor layer (200) may be an epitaxial layer formed by an epitaxy process.

[0096] Although not illustrated, a predetermined buffer layer may be further formed between the substrate (100) and the first semiconductor layer (200). The buffer layer may eliminate leakage current to the lower part of the 2DEG through high resistance characteristics and enable a high off-state breakdown voltage and a sharp pinch-off. Additionally, the buffer layer may be formed to prevent a decrease in crystallinity of the first semiconductor layer (200) by mitigating the difference in lattice constant and coefficient of thermal expansion between the substrate (100) and the first semiconductor layer (200). The buffer layer may be formed as a single layer or multilayer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B. As a specific example, the buffer layer may be formed as a single layer or multilayer structure comprising at least one of various materials such as AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN, etc. In some cases, a predetermined seed layer (not shown) may be further formed between the substrate (100) and the buffer layer. The seed layer may be a base layer for the growth of the buffer layer.

[0097] A second semiconductor layer (300) can be formed on the first semiconductor layer (200). The second semiconductor layer (300) may be a barrier layer or a channel supply layer. The second semiconductor layer (300) may be formed with a semiconductor different from the first semiconductor layer (200). The second semiconductor layer (300) may be a layer that induces 2DEG in the first semiconductor layer (200). 2DEG may be formed in the portion of the first semiconductor layer (200) below the interface between the first semiconductor layer (200) and the second semiconductor layer (300). The second semiconductor layer (300) may be formed with a material (semiconductor) that has different polarization characteristics and / or energy bandgap and / or lattice constants from the first semiconductor layer (200). The second semiconductor layer (300) may be formed with a material (semiconductor) that has a larger polarization rate and / or energy bandgap than the first semiconductor layer (200).

[0098] For example, the second semiconductor layer (300) may be formed as a single layer or multilayer structure comprising one or more materials selected from nitrides including at least one of Al, Ga, In, and B. As a specific example, the second semiconductor layer (300) may be formed as a single layer or multilayer structure comprising at least one of various materials including AlGaN, AlInN, InGaN, AlN, AlInGaN, etc. The second semiconductor layer (300) may be an undoped layer or a layer doped with a predetermined impurity. The second semiconductor layer (300) may be grown, for example, by MOCVD or MBE. The second semiconductor layer (300) may be an epitaxial layer formed by an epitaxy process.

[0099] Referring to FIG. 7b, a metal mask layer (400) can be formed on a portion of the second semiconductor layer (300). The metal mask layer (400) can be formed, for example, using electron beam evaporation or sputtering methods. Through the deposition and lift-off processes of the metal for the mask, the metal mask layer (400) can be formed only in a predetermined area. The predetermined area may correspond to or approximately correspond to the area where the gate is to be formed.

[0100] According to one embodiment, the metal mask layer (400) may be composed of or include a metal having a melting point of about 1000°C or higher. The melting point of the metal may be, for example, about 1000°C to 4000°C. As a specific example, the metal mask layer (400) may have a single-layer or multi-layer structure including at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), and palladium (Pd). The thickness of the metal mask layer (400) may be about 0.1 to 100 nm or about 1 to 50 nm, but is not limited thereto. In some cases, the thickness of the metal mask layer (400) may be about 100 nm or higher.

[0101] Referring to FIG. 7c, an insulating material layer (500) covering a metal mask layer (400) can be formed on a second semiconductor layer (300). The insulating material layer (500) may include, for example, at least one of silicon oxide, silicon nitride, silicon nitrate, and a high-dielectric (high-k) material. The high-dielectric material may be a material having a dielectric constant higher than that of silicon nitride, and may include, as a non-limiting example, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), etc. The insulating material layer (500) may be formed by a deposition method.

[0102] Referring to FIG. 7d, the insulating material layer (500) can be patterned to define (form) an insulating mask material layer (550) having an opening that exposes the regions of the second semiconductor layer (300) on both sides of the metal mask layer (400) on the second semiconductor layer (300), and additionally, a mask pattern (MP1) having a multilayer structure including the metal mask layer (400) and the insulating mask layer (510) disposed thereon can be defined. Through this, a state can be defined in which a mask pattern (MP1) having a multilayer structure including the metal mask layer (400) and the insulating mask layer (510) sequentially disposed on a part of the second semiconductor layer (300) is disposed, and an insulating mask material layer (550) having an opening that exposes the regions of the second semiconductor layer (300) on both sides of the mask pattern (MP1) is disposed on the second semiconductor layer (300). The insulating mask material layer (550) and the insulating mask layer (510) may be formed from the insulating material layer (500). However, the method of forming the mask pattern (MP1) and the insulating mask material layer (550) as in FIG. 7d is not limited to the above and may be changed depending on the circumstances.

[0103] Referring to FIG. 7e, a void region (V1) can be formed by recessing the portion of the second semiconductor layer (300) under the metal mask layer (400) while forming a depletion forming layer (600) that grows to cover the mask pattern (MP1) from the second semiconductor layer (300) region exposed on both sides of the mask pattern (MP1) to form a depletion region in the 2DEG.

[0104] The depletion forming layer (600) can be formed by a growth (regrowth) method. The depletion forming layer (600) can be formed by an epitaxy process using MOCVD or MBE equipment. The step of forming a void region (V1) while forming the depletion forming layer (600) can be performed under temperature conditions of about 1000°C or higher in a gas atmosphere containing hydrogen. The process temperature for the growth (regrowth) of the depletion forming layer (600) can be in the range of about 1000°C to 2500°C or about 1000°C to 2000°C. The depletion forming layer (600) can be grown from an exposed second semiconductor layer (300) region, can be grown laterally at a height above the mask pattern (MP1), and can be formed to partially or entirely cover the upper surface of the mask pattern (MP1). Although not illustrated, the depletion forming layer (600) may also grow laterally and extend somewhat above the insulating mask material layer (550). If necessary, the portion of the depletion forming layer (600) extended above the insulating mask material layer (550) may be removed in a predetermined manner.

[0105] While the depletion forming layer (600) is being formed, the portion of the second semiconductor layer (300) under the metal mask layer (400) may be etched (recessed) by a decomposition reaction to form a void region (V1). When the depletion forming layer (600) is formed under a temperature condition of about 1000°C or higher in a gas atmosphere containing hydrogen, the portion of the second semiconductor layer (300) under the metal mask layer (400) may be etched by a hydrogen radical reaction to form a void region (V1). At this time, a carrier gas containing hydrogen may be used in an atmosphere of high temperature of about 1000°C or higher and low pressure (e.g., about 100 torr or less). The carrier gas may be, for example, hydrogen gas or a mixed gas of hydrogen and nitrogen. The depletion forming layer (600) may be formed while supplying the carrier gas into the growth chamber, and a void region (V1) may be formed during this process. However, specific process conditions for forming the depletion forming layer (600) and the void region (V1) are not limited to those described above. In some cases, a process temperature lower than about 1000°C may be applied.

[0106] An insulating mask layer (510) is placed on a metal mask layer (400) and can serve to enable the depletion forming layer (600) to grow more stably during the growth process of the depletion forming layer (600). Stable growth of the depletion forming layer (600) may be possible through the insulating mask layer (510), and the film quality of the depletion forming layer (600) may be improved. By applying a mask pattern (MP1) of a multilayer structure including a metal mask layer (400) and an insulating mask layer (510) composed of a different material, stable growth (re-growth) of the depletion forming layer (600) may be possible. Additionally, the insulating mask layer (510) can be easily removed later by a wet etching method as needed.

[0107] The void region (V1) may be an air-void region and may be referred to as a recess region. The void region (V1) may have a tunnel shape (horizontal tunnel), and the corners on both lower sides of the void region (V1) may have a rounded shape or a slanted shape. A discontinuous region may be formed in the 2DEG at the interface between the first semiconductor layer (200) and the second semiconductor layer (300) by the void region (V1). The portion of the 2DEG corresponding to the void region (V1) may be broken or have different characteristics (electron concentration, etc.) from the remaining region.

[0108] The void region (V1) may be a region formed as the portion of the second semiconductor layer (300) in contact with the metal mask layer (400) is decomposed and recessed during the growth process of the depletion forming layer (600). Therefore, the void region (V1) may not be a region formed by a dry etching method, and etching damage issues such as plasma damage may not occur when forming the void region (V1).

[0109] The depletion forming layer (600) may be a p-type semiconductor layer or a layer doped with p-type impurities (i.e., a p-doped layer). Additionally, the depletion forming layer (600) may include a III-V series nitride semiconductor. For example, the depletion forming layer (600) may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with p-type impurities such as Mg. As a specific example, the depletion forming layer (600) may be a p-GaN layer or a p-AlGaN layer. The depletion forming layer (600) may include a compound semiconductor, and the compound semiconductor may be a p-type semiconductor, for example, Al x Ga 1-x N (0<x≤1), In x Al 1-x N (0 < x ≤ 1) and In x Al y Ga1-x-y N may include any one selected from [0<x≤1, 0<y≤1, 0<(x+y)≤1]. As the energy bandgap of the second semiconductor layer (300) in contact with it is increased by this depletion forming layer (600), a disconnected region may be formed in the 2DEG. The 2DEG portion corresponding to the region of the second semiconductor layer (300) in contact with the depletion forming layer (600) may be disconnected or have characteristics (electron concentration, etc.) different from the remaining region.

[0110] Referring to FIG. 7f, the insulating mask material layer (550) and the insulating mask layer (510) can be removed. As a non-limiting example, the insulating mask material layer (550) and the insulating mask layer (510) can be removed by a wet etching method using an etchant for etching oxides or nitrides. At this time, a portion of the etchant may be introduced into the void region (V1). As the insulating mask layer (510) is removed, the metal mask layer (400) may also be removed. That is, when the insulating mask layer (510) is removed, the metal mask layer (400) may also be removed.

[0111] As the insulating mask material layer (550) and the insulating mask layer (510) are removed, the void region (V1) can be extended toward the depletion forming layer (600). Accordingly, the void region (V1) can have a structure that extends (extended) into the depletion forming layer (600).

[0112] Referring to FIG. 7g, a gate electrode (710) can be formed on the depletion forming layer (600). The gate electrode (710) can be formed from various metals or metal compounds. A source electrode (720) and a drain electrode (730) can be formed spaced apart from the gate electrode (710) and electrically connected to at least one of the first and second semiconductor layers (200, 300). The source electrode (720) and the drain electrode (730) can be formed on both sides of the gate electrode (710). The source electrode (720) and the drain electrode (730) can make ohmic contact with the second semiconductor layer (300). In some cases, an ohmic contact layer (not shown) may be further formed between the source electrode (720) and the second semiconductor layer (300) and between the drain electrode (730) and the second semiconductor layer (300).

[0113] The source electrode (720) and drain electrode (730) may be formed in a structure that is inserted into the interior of the second semiconductor layer (300) or the interior of the first semiconductor layer (200). For example, after etching (recessing) a portion of the second semiconductor layer (300) and the first semiconductor layer (200), the source electrode (720) and drain electrode (730) may be formed in the etched area (recessed area). At this time, the depth of the etched area (recessed area) may be deeper than the depth of the 2DEG. Therefore, the source electrode (720) and drain electrode (730) may come into direct contact with the side of the 2DEG. Alternatively, the source / drain electrodes (720, 730) may be formed after etching only a portion of the second semiconductor layer (300) to a predetermined depth. That is, after etching (recessing) a portion of the second semiconductor layer (300) to the interface between the first semiconductor layer (200) and the second semiconductor layer (300) or to a shallower depth, source / drain electrodes (720, 730) can be formed in the etched region (recessed region). In addition, the configuration of the source electrode (720) and the drain electrode (730) can be varied. The gate electrode (710) and the source / drain electrodes (720, 730) may be formed simultaneously or in a predetermined order. When forming the gate electrode (710) and the source / drain electrodes (720, 730), lithography and metal-based material deposition processes may be used.

[0114] The void region (V1) may have a structure that extends (extends) into the depletion forming layer (600). The upper region of the void region (V1) may be inserted (i.e., embedded) into the depletion forming layer (600). Thus, the depletion forming layer (600) may cover the upper surface and both sides of the upper region. The thickness (t1) of the portion extending from the void region (V1) into the depletion forming layer (600) may be in the range of about 5 to 1000 nm or about 10 to 500 nm. Additionally, the depletion forming layer (600) may have a width greater than that of the void region (V1) and may have a structure that extends in both directions of the void region (V1).

[0115] According to an embodiment of the present invention, by using a growth (re-growth) technique for a depletion forming layer (600) using a metal mask layer (400) to decompose the portion of the second semiconductor layer (300) in contact with the metal mask layer (400), a void region (V1) caused by a recess can be formed during the thin film growth process without a separate etching process (dry etching process). Therefore, the problem of plasma damage occurring during dry etching can be prevented.

[0116] In addition, according to an embodiment of the present invention, since the depletion forming layer (600) can be formed in a growth (re-growth) manner only in a desired area without a patterning process using etching, problems regarding the reproducibility and reliability of the etching process can be prevented and the ease of the process can be improved. Furthermore, according to an embodiment of the present invention, by utilizing the void formation effect caused by the recess of the second semiconductor layer (300), a relatively thick barrier layer (i.e., 300) can be applied compared to the conventional method of applying a p-type gallium nitride layer, and an ON-current improvement effect can be obtained accordingly. Moreover, according to an embodiment of the present invention, by applying the void region (V1) caused by the recess and the depletion forming layer (600) together, a HEMT device having a high threshold voltage and stable normally-off characteristics can be reproducibly implemented.

[0117] Additionally, according to an embodiment of the present invention, by using a mask pattern (MP1) having a multilayer structure including a metal mask layer (400) and an insulating mask layer (510), the film quality of the growing depletion forming layer (600) can be improved and the depletion forming layer (600) can be formed stably, thereby enabling the improvement of HEMT performance and processability.

[0118] FIG. 8 is a scanning electron microscope (SEM) cross-sectional image showing a structure manufactured according to a process similar to an embodiment of the present invention.

[0119] Referring to FIG. 8, when a metal mask is formed on a part of a GaN-based semiconductor layer according to a process similar to the embodiment, and then a regrowth semiconductor layer is formed from an exposed region of the GaN-based semiconductor layer, a void region may be formed under the metal mask. The regrowth semiconductor layer may be a GaN-based semiconductor layer. For example, when the regrowth semiconductor layer is formed under a temperature condition of about 1000°C or higher in a gas atmosphere containing hydrogen, the portion of the GaN-based semiconductor layer under the metal mask may be etched by a hydrogen radical reaction, thereby forming a void region.

[0120] FIGS. 9a to 9c are cross-sectional views showing a method for manufacturing HEMT according to another embodiment of the present invention.

[0121] Referring to FIG. 9a, a device structure (intermediate device structure) such as FIG. 7e may be provided. The device structure of FIG. 9a may be manufactured in the same manner as described in FIG. 7a to FIG. 7e. First and second semiconductor layers (200, 300) may be formed sequentially on a substrate (100), and a mask pattern (MP1) and an insulating mask material layer (550) may be formed on the second semiconductor layer (300), and a depletion forming layer (600) and a void region (V1) may be formed. The mask pattern (MP1) may have a multilayer structure including a metal mask layer (400) and an insulating mask layer (510).

[0122] Referring to FIG. 9b, after forming the depletion forming layer (600) and the void region (V1), a step of removing the region where the source electrode and the drain electrode are to be formed in the insulating mask material layer (550) can be performed. The remaining insulating mask material layer (550) can be used as an insulating passivation layer. Hereinafter, the remaining insulating mask material layer (550) is referred to as an "insulating passivation layer." In addition, the insulating mask layer (510) and the metal mask layer (400) can be removed in this step. When the insulating mask layer (510) is removed, the metal mask layer (400) can be removed together. For example, a structure such as FIG. 9b can be obtained from the structure of FIG. 9a through a masking process and an etching process using photoresist.

[0123] Referring to FIG. 9c, a gate electrode (710), a source electrode (720), and a drain electrode (730) can be formed. The source electrode (720) and the drain electrode (730) can be formed on the exposed portion of the second semiconductor layer (300) by removing a portion of the insulating mask material layer (550) described above. The source electrode (720) and the drain electrode (730) may also be formed in a structure that is inserted into the interior of the second semiconductor layer (300) or into the interior of the first semiconductor layer (200). The insulating passivation layer (550) can be disposed on the region of the second semiconductor layer (300) between the depletion forming layer (600) and the source electrode (720), and between the depletion forming layer (600) and the drain electrode (730).

[0124] FIGS. 10a to 10c are cross-sectional views showing a method for manufacturing HEMT according to another embodiment of the present invention.

[0125] Referring to FIG. 10a, a device structure such as FIG. 7e can be provided.

[0126] Referring to FIG. 10b, a step of removing the region where the source electrode and the drain electrode are to be formed in the insulating mask material layer (550) can be performed. For example, a portion of the insulating mask material layer (550) can be removed through a masking process using photoresist and an etching process. Hereinafter, the remaining insulating mask material layer (550) is referred to as an 'insulating passivation layer'.

[0127] Referring to FIG. 10c, a gate electrode (710), a source electrode (720), and a drain electrode (730) can be formed.

[0128] FIG. 11 is a cross-sectional view illustrating a method for manufacturing HEMT according to another embodiment of the present invention.

[0129] Referring to FIG. 11, the metal mask layer (400) can be removed in step 10a or step 10b. For example, the metal mask layer (400) can be selectively removed by a wet etching method using a metal etchant. At this time, the metal etchant can be introduced through a void region (V1) to etch the metal mask layer (400). In this case, as the metal mask layer (400) is removed, the void region (V1) can be extended toward the depletion forming layer (600). Thus, the void region (V1) can have a structure that extends into the depletion forming layer (600). Next, a gate electrode (710), a source electrode (720), and a drain electrode (730) can be formed.

[0130] FIGS. 12a to 12e are cross-sectional views showing a method for manufacturing HEMT according to another embodiment of the present invention.

[0131] Referring to FIG. 12a, a device structure (intermediate device structure) such as FIG. 7c can be provided.

[0132] Referring to FIG. 12b, by patterning the insulating material layer (500), a mask pattern (MP1) having a multilayer structure including a metal mask layer (400) and an insulating mask layer (510) sequentially disposed on a part of the second semiconductor layer (300) can be defined, and an insulating mask material layer (550) having an opening that exposes the regions of the second semiconductor layer (300) on both sides of the mask pattern (MP1) can be disposed on the second semiconductor layer (300). The insulating mask material layer (550) and the insulating mask layer (510) may be formed from the insulating material layer (500). In this embodiment, the insulating mask layer (510) may have a wider width than the metal mask layer (400). The insulating mask layer (510) may be disposed to cover the upper surface and both sides of the metal mask layer (400).

[0133] Referring to FIG. 12c, a void region (V1) can be formed by recessing the portion of the second semiconductor layer (300) under the metal mask layer (400) while forming a depletion forming layer (600) that is grown to cover the mask pattern (MP1) from the second semiconductor layer (300) region exposed on both sides of the mask pattern (MP1) to form a depletion region in the 2DEG. In the case of the present embodiment, since the insulating mask layer (N10) can act as an insulating barrier on the upper surface and both sides of the metal mask layer (M10), the depletion forming layer (600) can be grown more stably and the film quality can be improved.

[0134] Referring to FIG. 12d, a step of removing the region where the source electrode and the drain electrode are to be formed in the insulating mask material layer (550) can be performed. The remaining insulating mask material layer (550) can be referred to as an 'insulating passivation layer'.

[0135] Referring to FIG. 12e, a gate electrode (710), a source electrode (720), and a drain electrode (730) can be formed.

[0136] FIG. 13 is a cross-sectional view illustrating a method for manufacturing HEMT according to another embodiment of the present invention.

[0137] Referring to FIG. 13, the metal mask layer (400) can be removed in step 12c or step 12d. For example, the metal mask layer (400) can be selectively removed by a wet etching method using a metal etchant. Then, the gate electrode (710), source electrode (720), and drain electrode (730) can be formed.

[0138] Although not illustrated, a device structure in which the insulating mask layer (510) in FIG. 13 is removed may be formed. Alternatively, a device structure in which the insulating mask layer (510) and the insulating mask material layer (550) in FIG. 13 are removed may be formed. This can be easily understood from the embodiments described above.

[0139] HEMTs according to embodiments of the present invention can be applied to various electronic devices, such as power devices. The power device may be a power semiconductor device. As the configuration of a power device including a HEMT is well known, a detailed description thereof is omitted. HEMTs according to embodiments of the present invention can be applied for various purposes in other electronic devices as well as power devices.

[0140] According to the embodiments of the present invention described above, a HEMT having normally-off characteristics and a method for manufacturing the same can be realized, which can be manufactured to have excellent physical properties without etching damage caused by dry etching. Furthermore, according to the embodiments of the present invention, the invention provides a HEMT having stable normally-off characteristics with a relatively high threshold voltage, which can prevent problems regarding the reproducibility and reliability of the etching process, and a method for manufacturing the same. Additionally, according to the embodiments of the present invention, it is possible to apply a barrier layer (channel supply layer) that is relatively thicker than in conventional methods, thereby providing a HEMT and a method for manufacturing the same that can secure a higher ON-current.

[0141] According to one embodiment, by using a growth (re-growth) technique for a compound semiconductor (depletion forming layer) utilizing a metal mask to decompose the portion of the lower semiconductor layer in contact with the metal mask, void regions formed by recesses can be formed during the thin film growth process without a separate etching process (dry etching process), and a HEMT having normally-off characteristics can be manufactured without etching damage. Therefore, the problem of plasma damage occurring during dry etching can be prevented. According to one embodiment, since a depletion forming layer (e.g., a p-type semiconductor layer) can be formed only in a desired area by a growth (re-growth) method without a patterning process using etching, problems regarding the reproducibility and reliability of the etching process can be prevented, and the ease of the process can be improved. According to one embodiment, by utilizing the void formation effect caused by recesses in the semiconductor layer, a relatively thicker barrier layer (channel supply layer) can be applied compared to the conventional method of applying a p-type gallium nitride layer, and an improvement in ON-current can be obtained accordingly. According to one embodiment, by applying a void region formed by a recess and a depletion forming layer (e.g., a p-type semiconductor layer) together, a HEMT device having a high threshold voltage and stable normally-off characteristics can be reproducibly realized. According to one embodiment, by using a multilayer mask including a metal mask layer and an insulating mask layer, the film quality of the growing depletion forming layer (e.g., a p-type semiconductor layer) can be improved and the depletion forming layer can be formed stably; thus, the effect of improving the performance and processability of the HEMT can be obtained. By applying the HEMT according to the embodiments of the present invention described above, various electronic devices (e.g., power devices) with excellent performance can be realized.

[0142] This specification discloses preferred embodiments of the present invention. Although specific terms have been used, they are used merely in a general sense to facilitate the explanation of the technical content of the invention and to aid in understanding the invention, and are not intended to limit the scope of the invention. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other variations based on the technical concept of the present invention are possible. Those skilled in the art will understand that the high electron mobility transistor (HEMT), the method of manufacturing the same, and the electronic device including the high electron mobility transistor (HEMT) according to the embodiments described with reference to FIGS. 1 to 13 can be variously substituted, changed, and modified within the scope of the technical concept of the present invention. Therefore, the scope of the invention should not be determined by the described embodiments but by the technical concept described in the claims. Explanation of the symbols

[0143] * Explanation of symbols for major parts of the drawing * D10: Drain electrode G10: Gate electrode M10: Metal mask layer MP1: Mask pattern N10: Insulating mask layer NP10: Insulating passivation layer P10: Depletion forming layer S10: Source electrode SL10: 1st semiconductor layer SL20: 2nd semiconductor layer SUB10 : Substrate V1 : Void area 100 : Substrate 200 : First semiconductor layer 300: Second semiconductor layer 400: Metal mask layer 500: Insulating material layer 510: Insulating mask layer 550: Insulating mask material layer 600: Depletion formation layer 710: Gate electrode 720: Source electrode 730 : Drain electrode

Claims

Claim 1 A high electron mobility transistor (HEMT) comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer and inducing a 2-dimensional electron gas (2DEG) in the first semiconductor layer; a depletion forming layer disposed on the second semiconductor layer and forming a depletion region in the 2DEG; a void region defined below the depletion forming layer, formed such that at least a portion of the second semiconductor layer is recessed and extends into the second semiconductor layer, having a structure extending into the depletion forming layer, wherein the thickness of the portion extending into the depletion forming layer is in the range of 5 to 1000 nm; a gate disposed on the depletion forming layer; and a source and a drain spaced apart from the gate and electrically connected to at least one of the first and second semiconductor layers; wherein the depletion forming layer has a width greater than that of the void region and has a structure extended in both directions of the void region. Claim 2 delete Claim 3 A high electron mobility transistor (HEMT) according to claim 1, wherein the upper region of the void region is disposed within the depletion forming layer, and the depletion forming layer is disposed to cover the upper surface and both sides of the upper region. Claim 4 A high electron mobility transistor (HEMT) according to claim 1, further comprising an insulating passivation layer disposed on the second semiconductor layer region between the depletion forming layer and the source and between the depletion forming layer and the drain. Claim 5 A high electron mobility transistor (HEMT) having a single-layer or multi-layer structure, wherein the first semiconductor layer comprises a gallium nitride-based material, and the second semiconductor layer comprises one or more materials selected from nitrides including at least one of Al, Ga, In, and B. Claim 6 In claim 1, the depletion forming layer comprises a high electron mobility transistor (HEMT) including a p-type semiconductor. Claim 7 A high electron mobility transistor (HEMT) comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer and inducing a 2-dimensional electron gas (2DEG) in the first semiconductor layer; a depletion forming layer disposed on the second semiconductor layer and forming a depletion region in the 2DEG; a void region defined below the depletion forming layer and formed such that at least a portion of the second semiconductor layer is recessed and extends into the second semiconductor layer; a mask pattern disposed between the depletion forming layer and the void region and including an insulating mask layer; a gate disposed on the depletion forming layer; and a source and a drain spaced apart from the gate and electrically connected to at least one of the first and second semiconductor layers, wherein the mask pattern is embedded within the depletion forming layer. Claim 8 delete Claim 9 In claim 7, the depletion forming layer has a width greater than the mask pattern and is arranged to cover the upper surface and both sides of the mask pattern, a high electron mobility transistor (HEMT). Claim 10 A high electron mobility transistor (HEMT) having a multilayer structure comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer and inducing a 2-dimensional electron gas (2DEG) in the first semiconductor layer; a depletion forming layer disposed on the second semiconductor layer and forming a depletion region in the 2DEG; a void region defined below the depletion forming layer and formed such that at least a portion of the second semiconductor layer is recessed and extends into the second semiconductor layer; a mask pattern disposed between the depletion forming layer and the void region and including an insulating mask layer; a gate disposed on the depletion forming layer; and a source and a drain spaced apart from the gate and electrically connected to at least one of the first and second semiconductor layers, wherein the mask pattern further includes a metal mask layer disposed between the insulating mask layer and the void region. Claim 11 In claim 10, the metal mask layer comprises a metal having a melting point of 1000°C or higher, in a high electron mobility transistor (HEMT). Claim 12 In claim 10, the metal mask layer comprises a single-layer or multi-layer structure comprising at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), and palladium (Pd), forming a high electron mobility transistor (HEMT). Claim 13 A high electron mobility transistor (HEMT) according to claim 7, further comprising an insulating passivation layer disposed on the second semiconductor layer region between the depletion forming layer and the source and between the depletion forming layer and the drain. Claim 14 A high electron mobility transistor (HEMT) having a single-layer or multi-layer structure, wherein the first semiconductor layer comprises a gallium nitride-based material, and the second semiconductor layer comprises one or more materials selected from nitrides including at least one of Al, Ga, In, and B. Claim 15 In claim 7, the depletion forming layer comprises a high electron mobility transistor (HEMT) comprising a p-type semiconductor. Claim 16 A power device comprising a high electron mobility transistor (HEMT) as described in any one of claims 1, 3 to 7 and 9 to 15. Claim 17 A method for manufacturing a high electron mobility transistor (HEMT), comprising: a step of forming a first semiconductor layer; a step of forming a second semiconductor layer on the first semiconductor layer that causes a 2DEG within the first semiconductor layer; a step of defining a state in which a mask pattern having a multilayer structure including a metal mask layer and an insulating mask layer sequentially disposed on a part of the second semiconductor layer is disposed, and an insulating mask material layer having an opening that exposes the second semiconductor layer regions on both sides of the mask pattern is disposed on the second semiconductor layer; a step of forming a void region by recessing the portion of the second semiconductor layer below the metal mask layer while forming a depletion forming layer that grows to cover the mask pattern from the second semiconductor layer regions exposed on both sides of the mask pattern and forms a depletion region in the 2DEG; a step of forming a gate on the depletion forming layer; and a step of forming a source and a drain that are spaced apart from the gate and are electrically connected to at least one of the first and second semiconductor layers. Claim 18 A method for manufacturing a high electron mobility transistor (HEMT) according to claim 17, wherein the step of forming the void region while forming the depletion forming layer is performed under a temperature condition of 1000°C or higher in a gas atmosphere containing hydrogen, and the second semiconductor layer portion below the metal mask layer is etched by a hydrogen radical reaction to form the void region. Claim 19 A method for manufacturing a high electron mobility transistor (HEMT), wherein the metal mask layer comprises a metal having a melting point of 1000°C or higher. Claim 20 A method for manufacturing a high electron mobility transistor (HEMT) having a single-layer or multi-layer structure, wherein the metal mask layer comprises at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), titanium (Ti), rhenium (Re), osmium (Os), niobium (Nb), hafnium (Hf), rhodium (Rh), chromium (Cr), zirconium (Zr), and palladium (Pd). Claim 21 A method for manufacturing a high electron mobility transistor (HEMT) according to claim 17, further comprising the step of removing the insulating mask material layer after the step of forming the void region while forming the depletion forming layer. Claim 22 A method for manufacturing a high electron mobility transistor (HEMT) according to claim 17, further comprising the step of removing the region to which the source and drain are to be formed in the insulating mask material layer after the step of forming the void region while forming the depletion forming layer, wherein the remaining insulating mask material layer is used as an insulating passivation layer. Claim 23 A method for manufacturing a high electron mobility transistor (HEMT) according to claim 17, further comprising the step of removing the metal mask layer or removing the insulating mask layer and the metal mask layer before forming the gate, source, and drain. Claim 24 A method for manufacturing a high electron mobility transistor (HEMT) having a single-layer or multi-layer structure, wherein the first semiconductor layer comprises a gallium nitride-based material, and the second semiconductor layer comprises one or more materials selected from nitrides including at least one of Al, Ga, In, and B. Claim 25 In claim 17, the method for manufacturing a high electron mobility transistor (HEMT) comprising a p-type semiconductor in the depletion forming layer.

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