Host, memory system communicate with the host, and computing system having the same

Abstract

A memory system includes a semiconductor memory device comprising a plurality of memory cells, and a controller that controls the operation of the semiconductor memory device and communicates with a host. The controller includes a condition storage unit, a condition monitor, and a host interface. The condition storage unit stores at least one condition related to the internal state of the memory system. The condition monitor monitors whether the at least one condition is satisfied and, if the at least one condition is satisfied, outputs an acknowledgment signal. In response to the acknowledgment signal, the host interface outputs a condition acknowledgment message to the host indicating that the at least one condition is satisfied. To output the condition acknowledgment message to the host, the memory system does not require a command from the host.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a host, a memory system communicating therewith, and a computing system including the same. Background Technology

[0002] A semiconductor memory device may be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. A three-dimensional semiconductor memory device is a semiconductor memory device designed to overcome the integration density limitations of a two-dimensional memory device and may include a plurality of memory cells stacked vertically on a semiconductor substrate. A controller can control the operation of the semiconductor memory device. A memory system includes a semiconductor memory device and a controller and can communicate with a host. The host and the memory system can constitute a computing system. The problem to be solved

[0003] An embodiment of the present invention provides a memory system capable of efficiently transmitting an internal state to a host.

[0004] Another embodiment of the present invention provides a host capable of efficiently determining the internal state of a memory system.

[0005] Another embodiment of the present invention provides a computing system capable of efficiently transmitting the internal state of a memory system to a host. means of solving the problem

[0006] A memory system according to one embodiment of the present invention includes a semiconductor memory device comprising a plurality of memory cells and a controller that controls the operation of the semiconductor memory device and communicates with a host. The controller includes a condition storage unit, a condition monitor, and a host interface. The condition storage unit stores at least one condition related to the internal state of the memory system. The condition monitor monitors whether the at least one condition is satisfied and, if the at least one condition is satisfied, outputs a confirmation signal. In response to the confirmation signal, the host interface outputs a condition confirmation message to the host indicating that the at least one condition is satisfied. To output the condition confirmation message to the host, the memory system does not require a command from the host.

[0007] In one embodiment, the at least one condition may be received from the host and stored in the condition storage unit.

[0008] In one embodiment, the at least one condition may be stored in the condition storage unit at the time of manufacturing the memory system.

[0009] In one embodiment, the controller may further include a code storage unit that stores at least one code, and a code execution unit that executes the at least one code.

[0010] In one embodiment, the host interface may include a first port and a second port. The first port may exchange data and commands of a first type with the host. The second port may exchange data of a second type with the host. The controller may output the condition check message through the second port.

[0011] In one embodiment, the host interface receives from the host through the first port a command identifying a code to be executed in response to the satisfied condition among the at least one code, and can output a control signal to control the code execution unit to execute the code identified by the command.

[0012] In one embodiment, the code execution unit executes the code in response to the control signal and can transmit the result of the code execution to the host interface.

[0013] In one embodiment, the host interface can transmit an execution result message indicating the execution result of the code to the host through the first port.

[0014] In one embodiment, the execution result may indicate either a success or a failure of execution of the code.

[0015] In one embodiment, the second port can establish a communication link with the host using the Universal Asynchronous Receiver / Transmitter (UART) protocol.

[0016] According to another embodiment of the present invention, by a method of operation of a host that exchanges data and commands of a first type with a memory system through a first link, a message indicating that a condition related to the internal state of the memory system is satisfied is received through a second link different from the first link, a code to be executed by the memory system is determined in response to the satisfied condition, and a command identifying the code is transmitted to the memory system through the first link.

[0017] In one embodiment, the code may be for performing a test operation of the memory system.

[0018] In one embodiment, the operation method may further include the step of receiving a message indicating the execution result of the code through the first link from the memory system.

[0019] In one embodiment, the second link may use a Universal Asynchronous Receiver / Transmitter (UART) protocol.

[0020] According to another embodiment of the present invention, by a method of operation of a memory system communicating with a host through a first link for transmitting and receiving data and commands of a first type and a second link for transmitting and receiving data of a second type, at least one condition is detected for the memory system, and a message indicating the detected condition is transmitted to the host through the second link.

[0021] In one embodiment, the memory system may require a corresponding command from the host to transmit data to the host through the first link. On the other hand, the memory system may not require a corresponding command from the host to transmit data to the host through the second link.

[0022] In one embodiment, the method of operation of the memory system may further include the steps of receiving a command corresponding to a message transmitted to the host through the first link from the host, executing code corresponding to the received command, and transmitting a message indicating the result of the execution of the code to the host through the first link.

[0023] In one embodiment, the execution result may indicate either a success or a failure of execution of the code.

[0024] In one embodiment, the second link may use a Universal Asynchronous Receiver / Transmitter (UART) protocol. Effects of the invention

[0025] This technology can provide a memory system capable of efficiently transmitting its internal state to a host. Furthermore, this technology can provide a host capable of efficiently determining the internal state of the memory system. Meanwhile, this technology can provide a computing system capable of efficiently transmitting the internal state of the memory system to a host. Brief explanation of the drawing

[0026] FIG. 1 is a block diagram showing a memory system including a controller according to one embodiment of the present invention. Figure 2 is a block diagram showing the semiconductor memory device of Figure 1. Figure 3 is a diagram showing an example of the memory cell array of Figure 2. FIG. 4 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 3. FIG. 5 is a circuit diagram showing another embodiment of a memory block (BLKb) among the memory blocks (BLK1~BLKz) of FIG. 3. FIG. 6 is a circuit diagram showing an example of one memory block (BLKc) among a plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 2. FIG. 7 is a block diagram showing an exemplary embodiment of the controller of FIG. 1. FIG. 8 is a flowchart illustrating a method of operation of a memory system according to one embodiment of the present invention. FIG. 9 is a flowchart illustrating a method of operation of a host according to another embodiment of the present invention. FIG. 10 is a block diagram illustrating, by way of example, the operation of a memory system and a host according to FIG. 8 and FIG. 9 of the present invention. FIG. 11 is a flowchart illustrating a method of operation of a computing system according to another embodiment of the present invention. FIG. 12 is a block diagram showing an example of a controller illustrated in FIG. 1. Figure 13 is a block diagram showing an application example of the memory system of Figure 1. FIG. 14 is a block diagram showing a computing system including a memory system described with reference to FIG. 13. Specific details for implementing the invention

[0027] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0029] FIG. 1 is a block diagram showing a memory system including a controller according to one embodiment of the present invention.

[0030] Referring to FIG. 1, the memory system (1000) includes a semiconductor memory device (100) and a controller (200). The memory system (1000) also communicates with a host (300). The controller (200) controls the general operation of the semiconductor memory device (100). Additionally, the controller (200) controls the operation of the semiconductor memory device (100) based on commands received from the host (300). The host (300) and the memory system (1000) communicating with it can form a computing system.

[0031] According to one embodiment of the present invention, a memory system (1000) and a host (300) can communicate through a first link (410). More specifically, the host (300) can transmit commands and data to the memory system (1000) through the first link (410). For example, the host (300) can transmit a write command for storing data and write data to the memory system (1000) through the first link (410). The memory system (1000) can perform a write operation for the write data in response to the write command. Additionally, the host (300) can transmit a read command for reading data to the memory system (1000) through the first link (410). Meanwhile, the memory system (1000) can perform a read operation in response to the read command and transmit the read data to the host (300) through the first link (410). The first link (410) may be composed of a first device port (211) included in the controller (200) of the memory system (1000) and a first host port (311) included in the host (300). The first link (410) may use a protocol defined to transmit and receive commands and data, such as user data, between the host (300) and the memory system (1000).

[0032] Meanwhile, according to an embodiment of the present invention, the memory system (1000) and the host (300) can also communicate through a second link (420). The second link (420) can be used to transmit log data and debugging data. The second link (420) may be composed of a second device port (213) included in the controller (200) of the memory system (1000) and a second host port (313) included in the host (300).

[0033] In order for the memory system (1000) to transmit data to the host (300) through the first link (410), it may first require a command from the host (300). This means that data cannot be transmitted to the host (300) through the first link (410) by the decision of the memory system (1000) without a command from the host (300). The memory system (1000) can transmit data to the host (300) through the first link (410) in the form of responding to a command received from the host (300) through the first link (410).

[0034] On the other hand, when the memory system (1000) transmits data to the host (300) via the second link (420), it may not require a command from the host (300). That is, the operation of transmitting data from the memory system (1000) to the host (300) via the second link (420) is not performed in the form of a response to a command or request from the host (300). Therefore, even without a command or request from the host (300), the memory system (1000) can transmit specific data to the host (300).

[0035] As described above, data transmission through the first link (410) and the second link (420) can be performed in different ways. That is, the transmission protocols used in the first link (410) and the second link (420), respectively, may be different from each other.

[0036] For example, the first link (410) may use a USB (Universal Serial Bus) protocol, an MMC (multimedia card) protocol, a PCI (peripheral component interconnection) protocol, a PCI-E (PCI-express) protocol, etc., to perform data exchange between the host (300) and the memory system (1000). Meanwhile, as these are exemplary, various other types of data transmission and reception protocols may be used for the first link (410).

[0037] Meanwhile, the second link (420) can use the Universal Asynchronous Receiver / Transmitter (UART) protocol. UART is a type of computer hardware that converts parallel data into a serial format to transmit data. UART can generally be used with communication standards such as EIA RS-232, RS-422, and RS-485. Since UART is asynchronous communication, no synchronization signal is transmitted. Therefore, it is agreed that the receiving end can detect the synchronization signal to determine the start and end of the data in time and process it. Through this, the memory system (1000) can transmit data to the second link (420) even without a command or request from the host (300).

[0038] Figure 2 is a block diagram showing the semiconductor memory device of Figure 1.

[0039] Referring to FIG. 2, the semiconductor memory device (100) includes a memory cell array (110), an address decoder (120), a read and write circuit (130), control logic (140), and a voltage generation unit (150).

[0040] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to an address decoder (120) via word lines (WL). The plurality of memory blocks (BLK1 to BLKz) are connected to a read and write circuit (130) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. As an example, the plurality of memory cells are non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure. The memory cell array (110) may be composed of a memory cell array with a two-dimensional structure. According to an example, the memory cell array (110) may be composed of a memory cell array with a three-dimensional structure. Meanwhile, each of the plurality of memory cells included in the memory cell array may store at least 1 bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a single-level cell (SLC) that stores 1 bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a multi-level cell (MLC) that stores 2 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a triple-level cell (TLC) that stores 3 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a quad-level cell (QLC) that stores 4 bits of data. According to an embodiment, the memory cell array (110) may include a plurality of memory cells that each store 5 bits or more of data.

[0041] The address decoder (120), the read and write circuit (130), the control logic (140), and the voltage generation unit (150) operate as peripheral circuits that drive the memory cell array (110). The address decoder (120) is connected to the memory cell array (110) through word lines (WL). The address decoder (120) is configured to operate in response to the control of the control logic (140). The address decoder (120) receives an address through an input / output buffer (not shown) inside the semiconductor memory device (100).

[0042] The address decoder (120) is configured to decode a block address among the received addresses. The address decoder (120) selects at least one memory block according to the decoded block address. Additionally, during a read operation, when a read voltage is applied, the address decoder (120) applies a read voltage (Vread) generated by the voltage generator (150) to the selected word line among the selected memory blocks, and applies a pass voltage (Vpass) to the remaining unselected word lines. Additionally, during a program verification operation, when a verification voltage generated by the voltage generator (150) is applied to the selected word line among the selected memory blocks, and applies a pass voltage (Vpass) to the remaining unselected word lines.

[0043] The address decoder (120) is configured to decode the column address among the received addresses. The address decoder (120) transmits the decoded column address to the read and write circuit (130).

[0044] The read operation and program operation of the semiconductor memory device (100) are performed in page units. The address received upon request for a read operation and program operation includes a block address, a row address, and a column address. The address decoder (120) selects one memory block and one word line according to the block address and row address. The column address is decoded by the address decoder (120) and provided to the read and write circuit (130).

[0045] The address decoder (120) may include a block decoder, a row decoder, a column decoder, and an address buffer, etc.

[0046] The read and write circuit (130) includes a plurality of page buffers (PB1 to PBm). The read and write circuit (130) can operate as a "read circuit" during a read operation of the memory cell array (110) and as a "write circuit" during a write operation. The plurality of page buffers (PB1 to PBm) are connected to the memory cell array (110) through bit lines (BL1 to BLm). The plurality of page buffers (PB1 to PBm) continuously supply sensing current to the bit lines connected to the memory cells to sense the threshold voltage of the memory cells during a read operation and a program verification operation, and detect through a sensing node that the amount of current flowing changes according to the program state of the corresponding memory cell, and latch it as sensing data. The read and write circuit (130) operates in response to page buffer control signals output from the control logic (140).

[0047] The read and write circuit (130) senses data in a memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to an input / output buffer (not shown) of a semiconductor memory device (100). As an exemplary embodiment, the read and write circuit (130) may include a column selection circuit, etc., in addition to page buffers (or page registers).

[0048] The control logic (140) is connected to the address decoder (120), the read and write circuit (130), and the voltage generation unit (150). The control logic (140) receives a command (CMD) and a control signal (CTRL) through an input / output buffer (not shown) of the semiconductor memory device (100). The control logic (140) is configured to control the general operation of the semiconductor memory device (100) in response to the control signal (CTRL). Additionally, the control logic (140) outputs a control signal to adjust the sensing node precharge potential level of a plurality of page buffers (PB1~PBm). The control logic (140) can control the read and write circuit (130) to perform a read operation of the memory cell array (110).

[0049] The voltage generation unit (150) generates a read voltage (Vread) and a pass voltage (Vpass) during a read operation in response to a control signal output from the control logic (140). To generate multiple voltages having various voltage levels, the voltage generation unit (150) includes multiple pumping capacitors that receive an internal power supply voltage, and will generate multiple voltages by selectively activating the multiple pumping capacitors in response to the control of the control logic (140). As described above, the voltage generation unit (150) may include a charge pump, and the charge pump may include the aforementioned multiple pumping capacitors. The specific configuration of the charge pump included in the voltage generation unit (150) can be designed in various ways as needed.

[0050] The address decoder (120), the read and write circuit (130), and the voltage generation unit (150) can function as "peripheral circuits" that perform read, write, and erase operations on the memory cell array (110). The peripheral circuits perform read, write, and erase operations on the memory cell array (110) based on the control of the control logic (140).

[0051] Figure 3 is a diagram showing an example of the memory cell array of Figure 2.

[0052] Referring to FIG. 3, the memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block is described in more detail with reference to FIG. 4 and FIG. 5.

[0053] FIG. 4 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 3.

[0054] Referring to FIG. 4, the memory block (BLKa) includes a plurality of cell strings (CS11–CS1m, CS21–CS2m). As an example, each of the plurality of cell strings (CS11–CS1m, CS21–CS2m) may be formed in a 'U' shape. Within the memory block (BLKa), m cell strings are arranged in the row direction (i.e., +X direction). In FIG. 4, two cell strings are shown arranged in the column direction (i.e., +Y direction). However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in the column direction.

[0055] Each of the plurality of cell strings (CS11~CS1m, CS21~CS2m) includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), a pipe transistor (PT), and at least one drain select transistor (DST).

[0056] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0057] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCp).

[0058] As an example, source select transistors of cell strings arranged in the same row are connected to a source select line extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 4, source select transistors of cell strings (CS11–CS1m) of the first row are connected to a first source select line (SSL1). Source select transistors of cell strings (CS21–CS2m) of the second row are connected to a second source select line (SSL2).

[0059] As another embodiment, the source selection transistors of the cell strings (CS11~CS1m, CS21~CS2m) can be commonly connected to a single source selection line.

[0060] The first to nth memory cells (MC1 to MCn) of each cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0061] The first to n memory cells (MC1 to MCn) can be divided into the first to p memory cells (MC1 to MCp) and the p+1 to n memory cells (MCp+1 to MCn). The first to p memory cells (MC1 to MCp) are arranged sequentially in the +Z direction and in the reverse direction and are connected in series between a source select transistor (SST) and a pipe transistor (PT). The p+1 to n memory cells (MCp+1 to MCn) are arranged sequentially in the +Z direction and are connected in series between a pipe transistor (PT) and a drain select transistor (DST). The first to p memory cells (MC1 to MCp) and the p+1 to n memory cells (MCp+1 to MCn) are connected through a pipe transistor (PT). The gates of the first to nth memory cells (MC1~MCn) of each cell string are each connected to the first to nth word lines (WL1~WLn).

[0062] The gate of the pipe transistor (PT) of each cell string is connected to the pipeline (PL).

[0063] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MCp+1 to MCn). The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings of the first row (CS11 to CS1m) are connected to the first drain select line (DSL1). The drain select transistors of the cell strings of the second row (CS21 to CS2m) are connected to the second drain select line (DSL2).

[0064] Cell strings arranged in a column direction are connected to a bit line extending in a column direction. In FIG. 4, the cell strings of the first column (CS11, CS21) are connected to the first bit line (BL1). The cell strings of the m-th column (CS1m, CS2m) are connected to the m-th bit line (BLm).

[0065] Memory cells connected to the same word line within cell strings arranged in a row direction constitute one page. For example, among the cell strings (CS11–CS1m) of the first row, memory cells connected to the first word line (WL1) constitute one page. Among the cell strings (CS21–CS2m) of the second row, memory cells connected to the first word line (WL1) constitute another page. By selecting either of the drain selection lines (DSL1, DSL2), cell strings arranged in a row direction will be selected. By selecting any of the word lines (WL1–WLn), one page among the selected cell strings will be selected.

[0066] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). And among the cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the even-numbered cell strings may be connected to the even bit lines, and among the cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the odd-numbered cell strings may be connected to the odd bit lines.

[0067] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCp). Or, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MCp+1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKa) is improved, while the size of the memory block (BLKa) increases. As fewer memory cells are provided, the size of the memory block (BLKa) decreases, while the reliability of operation for the memory block (BLKa) may decrease.

[0068] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKa). If an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0069] FIG. 5 is a circuit diagram showing another embodiment of a memory block (BLKb) among the memory blocks (BLK1~BLKz) of FIG. 3.

[0070] Referring to FIG. 5, the memory block (BLKb) includes a plurality of cell strings (CS11'~CS1m', CS21'~CS2m'). Each of the plurality of cell strings (CS11'~CS1m', CS21'~CS2m') is extended along the +Z direction. Each of the plurality of cell strings (CS11'~CS1m', CS21'~CS2m') includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), and at least one drain select transistor (DST), which are stacked on a substrate (not shown) below the memory block (BLKb).

[0071] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1 to MCn). The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings arranged in the first row (CS11' to CS1m') are connected to the first source select line (SSL1). The source select transistors of cell strings arranged in the second row (CS21' to CS2m') are connected to the second source select line (SSL2). In another embodiment, the source select transistors of cell strings (CS11' to CS1m', CS21' to CS2m') may be commonly connected to a single source select line.

[0072] The first to nth memory cells (MC1 to MCn) of each cell string are connected in series between a source select transistor (SST) and a drain select transistor (DST). The gates of the first to nth memory cells (MC1 to MCn) are each connected to the first to nth word lines (WL1 to WLn).

[0073] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1–MCn). The drain select transistors of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings of the first row (CS11'–CS1m') are connected to the first drain select line (DSL1). The drain select transistors of the cell strings of the second row (CS21'–CS2m') are connected to the second drain select line (DSL2).

[0074] Consequently, the memory block (BLKb) of FIG. 5 has an equivalent circuit similar to the memory block (BLKa) of FIG. 4, except that the pipe transistor (PT) is excluded from each cell string.

[0075] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). And among the cell strings arranged in the row direction (CS11'~CS1m' or CS21'~CS2m'), the even-numbered cell strings may be connected to the even bit lines, and among the cell strings arranged in the row direction (CS11'~CS1m' or CS21'~CS2m'), the odd-numbered cell strings may be connected to the odd bit lines.

[0076] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCn). Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MC1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKb) is improved, while the size of the memory block (BLKb) increases. As fewer memory cells are provided, the size of the memory block (BLKb) decreases, while the reliability of operation for the memory block (BLKb) may decrease.

[0077] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKb). If an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0078] FIG. 6 is a circuit diagram showing an example of one memory block (BLKc) among a plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 2.

[0079] Referring to FIG. 6, a memory block (BKLc) includes a plurality of cell strings (CS1 to CSm). The plurality of cell strings (CS1 to CSm) can each be connected to a plurality of bit lines (BL1 to BLm). Each of the plurality of cell strings (CS1 to CSm) includes at least one source select transistor (SST), first to nth memory cells (MC1 to MCn), and at least one drain select transistor (DST).

[0080] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0081] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCn).

[0082] The first to nth memory cells (MC1 to MCn) of each cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0083] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1~MCn).

[0084] Memory cells connected to the same word line constitute one page. Cell strings (CS1–CSm) will be selected by selecting the drain selection line (DSL). One page of the selected cell strings will be selected by selecting any one of the word lines (WL1–WLn).

[0085] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). Among the cell strings (CS1~CSm), the even-numbered cell strings may be connected to the even-bit lines, and the odd-numbered cell strings may be connected to the odd-bit lines.

[0087] FIG. 7 is a block diagram showing an exemplary embodiment of the controller of FIG. 1.

[0088] Referring to FIG. 7, a controller (200) according to one embodiment of the present invention may include a host interface (201), a condition monitor (203), a condition storage unit (205), a code execution unit (207), and a code storage unit (209). The host interface (201) may include a first device port (211) and a second device port (213). As described above with reference to FIG. 1, the first device port (211) may form a first link (410) together with the first host port (311) of the host (300). Meanwhile, the second device port (213) may form a second link (420) together with the second host port (313) of the host (300).

[0089] The host interface (201) can communicate with the host (300). More specifically, the host interface (201) may include a protocol for performing data exchange between the host (300) and the controller (200). To this end, the host interface (201) may be configured to communicate with the host (300) through at least one of various interface protocols. As described above, when the controller (200) of the memory system (1000) intends to send data to the host (300) through the first link (410), it may first require a command or request from the host (300). Meanwhile, when the controller (200) of the memory system (1000) intends to send data to the host (300) through the second link (420), it may not require a command or request from the host (300).

[0090] The condition monitor (203) can receive at least one of a plurality of conditions (CND) stored in the condition storage unit (205). Meanwhile, the condition monitor (203) can monitor whether the received condition (CND) is satisfied. If the received condition (CND) is satisfied, the condition monitor (203) can transmit a confirmation signal (CNF) indicating that the condition is satisfied to the host interface (201). Based on the received confirmation signal (CNF), the host interface (201) transmits a condition confirmation message (MSG CNF Generates ) and the generated condition check message (MSG CNF ) can be transmitted to the host (300). Condition check message (MSG CNF ) may be a message indicating a satisfied condition (CND).

[0091] At this time, the condition check message (MSG CNF ) may not be a message generated in response to a command or message received from the host (300). For example, a condition check message (MSG CNF) may be a message transmitted from the memory system (1000) to the host (300) via the universal asynchronous receiver and transmitter (UART) interface protocol. Thus, a condition check message (MSG CNF ) can be transmitted to the second device port (213) and transmitted to the host (300) via the second link (420).

[0092] For example, any of the conditions (CMDs) stored in the condition storage unit (205) may be a condition regarding whether the number of free blocks included in the semiconductor memory device (100) has become less than a specific threshold, which is related to garbage collection operations. In this case, when the number of free blocks becomes smaller than the specific threshold, the condition monitor (203) transmits a confirmation signal (CNF) indicating that the condition has been satisfied to the host interface (201), and the host interface (201) transmits a condition confirmation message (MSG) indicating that the number of free blocks has become smaller than the specific threshold. CNF ) can be passed to the host (300).

[0093] As another example, one of the conditions (CMDs) stored in the condition storage unit (205) may be a condition regarding whether the internal temperature of the memory system has exceeded a specific threshold temperature. In this case, if the internal temperature of the memory system has exceeded the specific threshold temperature, the condition monitor (203) transmits a confirmation signal (CNF) indicating that the condition has been satisfied to the host interface (201), and the host interface (201) transmits a condition confirmation message (MSG) indicating that the internal temperature of the memory system has exceeded the specific threshold temperature. CNF ) can be passed to the host (300).

[0094] In the example described above, conditions regarding whether the number of free blocks has fallen below a specific threshold, or conditions regarding whether the internal temperature of the memory system (1000) has exceeded a specific threshold temperature were described. However, the present invention is not limited thereto, and various other conditions may be stored in the condition storage unit (205). At least one of the above conditions may be a condition received from the host (300). In this case, the condition storage unit (205) may store the condition received from the host. As another example, at least one of the above conditions may be a condition determined in advance during the manufacture of the memory system (1000). In this case, the above condition may be stored in the condition storage unit (205) during the manufacture of the memory system (1000). As yet another example, the above condition may be stored in the memory cell array (110) of the semiconductor memory device (100). When the memory system (1000) is turned on, the controller (200) can read the conditions stored in the semiconductor memory device (100) and store them in the condition storage unit (205).

[0095] The condition storage unit (205) may be implemented as volatile memory such as Random Access Memory (RAM), or as non-volatile memory such as Read-Only Memory (ROM) or Flash Memory.

[0096] Meanwhile, the host interface (201) can receive various commands (CMD) from the host. The host (300) can control the operation of the memory system (1000) by means of the commands (CMD). As an example, the commands (CMD) may be commands that control read operations or write operations of the memory system. In an exemplary embodiment, the host (300) can transmit the commands to the controller (200) of the memory system (1000) through the first link (410). Accordingly, in this case, the first device port (211) of the host interface (201) can receive the commands (CMD).

[0097] According to one embodiment of the present invention, a command (CMD) may control the memory system (1000) to execute a specific code among the codes stored in the code storage unit (209), in addition to general operations such as general read or write operations as described above. In this case, a host interface (201) may receive a command (CMD) that causes a specific code (CDE) stored in the code storage unit (209) to be executed. In response to the reception of the command (CMD), the host interface (201) may transmit a control signal (CTR) to the code execution unit (207) that causes the code (CDE) specified by the command (CMD) to be executed. The code execution unit (207) may execute at least one code (CDE) among a plurality of codes stored in the code storage unit (209) in response to the control signal (CTR).

[0098] At least one of the above codes may be a code received from a host (300). In this case, the code storage unit (209) may store the code received from the host. As another example, at least one of the above codes may be a code determined in advance at the time of manufacturing the memory system (1000). In this case, the codes may be stored in the code storage unit (209) at the time of manufacturing the memory system (1000). As yet another example, the codes may be stored in the memory cell array (110) of the semiconductor memory device (100). When the memory system (1000) is turned on, the controller (200) may read the code stored in the semiconductor memory device (100) and store it in the code storage unit (209).

[0099] Similar to the condition storage unit (205), the code storage unit (209) may be implemented as volatile memory such as Random Access Memory (RAM), or as non-volatile memory such as Read-Only Memory (ROM) or Flash Memory.

[0100] Meanwhile, the code execution unit (207) can transmit the execution result (RSL) to the host interface (201) after the execution of the code (CDE). The execution result (RSL) may have various values ​​depending on the type of code (CDE). For example, whether the execution of the code (CDE) was successful or failed may be transmitted to the host interface (201) as the execution result (RSL). Alternatively, a specific value may be generated as a result of executing the code (CDE), and in this case, the code execution unit (207) may transmit the value generated by the execution of the code (CDE) to the host interface (201) as the execution result (RSL). The host interface (201) may transmit an execution result message (MSG) containing information indicated by the received execution result (RSL). RSL) is transmitted to the host (300). Consequently, the memory system (1000) executes a specific code (CDE) according to the command (CMD) received from the host (300), and an execution result message (MSG) indicating the result. RSL ) is transmitted to the host (300). Execution result message (MSG RSL ) can be transmitted to the host (300) in the form of a response to a command (CMD). Accordingly, an execution result message (MSG) is transmitted to the host (300) via the first link (410) from the first device port (211) of the host interface (201). RSL ) can be transmitted.

[0101] In many cases, the code storage unit (209) may store codes for testing the memory system (1000). Among these tests, there may be tests that need to be executed when the memory system (1000) satisfies certain conditions.

[0102] In the usual case, when the memory system (1000) needs to perform such a test, the host (300) periodically or arbitrarily transmits a confirmation command to the memory system (1000), and the memory system (1000) transmits a message to the host (300) indicating whether the corresponding condition is satisfied as a response to the received confirmation command. In this case, if the memory system (1000) does not satisfy the above condition, the host (300) must repeatedly transmit a confirmation command to the memory system (1000) through the first link (410). This impairs the operational efficiency of the memory system (1000). As the number of conditions that the host (300) wishes to check increases, this inefficiency also increases.

[0103] According to the present invention, the memory system (1000) internally monitors whether a specific condition is satisfied without the need for the host (300) to check repeatedly, and transmits this to the host (300) when the condition is satisfied. That is, the memory system (1000) transmits a condition confirmation message (MSG) indicating that the condition is satisfied, even without a request or command from the host (300). CNF ) can be transmitted to the host (300) via the second link (420). Therefore, since the host (300) no longer needs to repeatedly transmit commands to the memory system (1000) to check whether the condition is satisfied, the memory system (1000) and the computing system including it can operate more efficiently.

[0105] FIG. 8 is a flowchart illustrating a method of operation of a memory system according to one embodiment of the present invention.

[0106] Referring to FIG. 8, a method of operating a memory system according to an embodiment of the present invention includes the steps of: monitoring whether at least one condition related to the internal state of the memory system (1000) is satisfied (S110); determining whether the at least one condition is satisfied (S120); transmitting a message indicating the satisfied condition to a host (300) (S130); receiving a command associated with the message from the host (300) (S140); executing code corresponding to the received command (S150); and transmitting a message indicating the result of the code execution to the host (S160).

[0107] In step (S110), a condition monitor (203) included in the controller (200) of the memory system (1000) can monitor whether at least one of the conditions (CND) stored in the condition storage unit (205) is satisfied. The condition monitor (203) may monitor only one condition or may monitor multiple conditions simultaneously.

[0108] In step (S120), it is determined whether at least one condition is satisfied. If no satisfied condition exists (S120: No), the process proceeds to step (S110) to continue monitoring the condition.

[0109] If at least one condition (CND) is satisfied (S120: Yes), a condition check message (MSG) indicating the satisfied condition CNF ) is transmitted to the host (300) (S130). In step (S130), the memory system (1000) transmits a condition check message (MSG) through the second link (420). CNF ) can be transmitted to the host (300). The host (300) can transmit a condition check message (MSG CNF It will receive ) and determine the code that the memory system (1000) must execute in response. In addition, the host (300) will transmit a command (CMD) to the memory system (1000) to cause the memory system (1000) to execute the determined code. Condition check message (MSG CNF The operation of the host (300) that received the ) will be explained with reference to FIG. 10.

[0110] In step (S140), the memory system (1000) receives a condition check message (MSG) from the host (300). CNF A command corresponding to ) is received. In step (S140), the memory system (1000) may receive a command (CMD) from the host (300) via the first link (410). As described above, the command (CMD) is a condition check message (MSG CNF It may be a command indicating code that the memory system (1000) must execute in response to ). Accordingly, the memory system (1000) will execute the code identified by the command (CMD) (S150).

[0111] After executing code identified by a command (CMD), the memory system (1000) provides an execution result message (MSG) indicating the result of the code execution. RSL ) is transmitted to the host (300) (S160). If the above code is test code, the execution result message (MSG RSL ) may include information regarding the above test results. In step (S160), the memory system (1000) receives an execution result message (MSG) through the first link (410). RSL ) can be transmitted to the host (300). The host (300) can transmit the execution result message (MSG RSL It can receive ) to evaluate test results and perform subsequent actions.

[0113] FIG. 9 is a flowchart illustrating a method of operation of a host according to another embodiment of the present invention. A host performing the operation according to FIG. 9 can communicate with a memory system (1000) performing the operation according to FIG. 8.

[0114] Referring to FIG. 9, a method of operation of a host according to another embodiment of the present invention includes the steps of receiving a message from a memory system (1000) indicating that a specific condition has been satisfied (S210), determining a code that the memory system must execute in response to the satisfied condition (S230), transmitting a command to the memory system (1000) to execute the determined code (S250), and receiving a message from the memory system (1000) indicating the result of the code execution (S270).

[0115] By step (S130) of FIG. 8, the memory system (1000) receives a condition check message (MSG CNF ) transmits to the host (300). Accordingly, the host (300) receives a condition check message (MSG) from the memory system (1000). CNF) receives (S210). In step (S210), the host (300) receives a condition check message (MSG) through the second host port (313) that constitutes the second link (420). CNF Can receive ).

[0116] In step (S230), the host (300) receives a condition check message (MSG CNF By analyzing the memory system (1000), the code that the memory system (1000) must execute is determined. In relation to the test, the host (300) can determine test-related code that can be executed when the state of the memory system (1000) satisfies a specific condition.

[0117] In step (S250), the host (300) transmits a command (CMD) to the memory system (1000) to cause the memory system (1000) to execute the code determined in step (S230). In step (S250), the host (300) may transmit the command (CMD) to the memory system (1000) through a first host port (311) that constitutes the first link (410). As step (S250) is performed, the memory system will receive the command (CMD) in step (S140) of FIG. 8.

[0118] Subsequently, as illustrated in FIG. 8, the memory system (1000) executes code corresponding to a command (CMD) (S150), and an execution result message (MSG) indicating the result of executing the code. RSL ) is transmitted to the host (S160). As step (S160) of FIG. 8 is performed, in step (S270) of FIG. 9, the host (300) receives an execution result message (MSG) from the memory system indicating the execution result of the code. RSL ) will receive. In step (S270), the host (300) receives the execution result message (MSG) through the first host port (311) constituting the first link (410). RSL) can be received. If the above code is code for a test operation of the memory system (1000), the host (300) receives the execution result message (MSG) as the test execution result. RSL ) can receive. As a result, the host (300) receives an execution result message (MSG RSL The test results of the memory system (1000) can be evaluated by analyzing )

[0120] FIG. 10 is a block diagram illustrating the operation of a memory system and a host according to FIG. 8 and FIG. 9 of the present invention in an exemplary manner. FIG. 10 is a diagram illustrating the operation method of a memory system according to FIG. 8 and the operation method of a host according to FIG. 9 in combination. In FIG. 10, only the condition storage unit (205), code storage unit (209), first device port (211), and second device port (213) within the controller (200) of the memory system (1000) are illustrated, and other components are omitted for convenience of explanation. Meanwhile, in FIG. 10, first to fifth conditions (CND1~CND5) are stored in the condition storage unit (205), and first to seventh codes (CDE1~CDE7) are stored in the code storage unit (209). This is exemplary, and various conditions and codes may be stored in the condition storage unit (205) and the code storage unit (209).

[0121] First, according to step (S110) of FIG. 8, the memory system (1000) can continuously monitor whether at least one of the plurality of conditions (CND1~CND5) stored in the condition storage unit (205) is satisfied (①). If, while monitoring the conditions, any one of the conditions, for example, the second condition (CND2), is satisfied (②, S120: Yes), the memory system (1000) sends a condition confirmation message (MSG) indicating that the second condition (CND2) is satisfied. CNF2) is transmitted to the host through the second device port (213) that constitutes the second link (420) (③, S130).

[0122] In FIG. 9, when any one of the multiple conditions (CND1~CND5), for example, the second condition (CND2), is satisfied, a condition confirmation message (MSG) indicating that the second condition (CND2) is satisfied is provided. CNF2 An example of transmitting ) to a host (300) is illustrated. However, this is exemplary, and when multiple conditions are satisfied, a condition confirmation message indicating that these conditions are satisfied may be transmitted to the host (300). In this case, the combination of multiple conditions may be determined in various ways as needed.

[0123] The host (300) receives a condition check message (MSG) from the second host port (313) that constitutes the second link (420). CNF2 ) received (S210), and the received condition confirmation message (MSG CNF2 In response to ), the memory system (1000) determines the code to be executed (S230). For example, the host (300) may determine that the fourth code (CDE4) among the first to seventh codes (CDE1~CDE7) will be executed as the second condition (CND2) of the memory system (1000) is satisfied (④). The host (300) provides a command (CMD) for executing the determined fourth code (CDE4). CDE4 Creates ) and the created command (CMD CDE4 ) can be transmitted to the memory system (1000) through the first host port (311) (⑤, S250).

[0124] The memory system (1000) receives a command (CMD) from the host (300) to execute the fourth code (CDE4). CDE4 ) is received from the first device port (211) (S140). The received command (CMD CDE4In response to ), the memory system (1000) executes the fourth code (CDE4) (⑥, S150). Afterwards, the memory system (1000) receives the result of executing the fourth code (CDE4) as an execution result message (MSG RSL As ), it is transmitted to the host (300) through the first device port (211) (⑦, S160). Accordingly, the host (300) receives an execution result message (MSG) from the memory system (1000). RSL ) can be received through the first host port (311) (S270), and the execution result message (MSG RSL You can analyze ) to evaluate it or perform other subsequent actions.

[0126] FIG. 11 is a flowchart illustrating a method of operation of a computing system according to another embodiment of the present invention. The computing system may include a memory system (1000) and a host (300). Referring to FIG. 11, a method of operation of a computing system according to another embodiment of the present invention includes: a step of monitoring whether at least one condition related to the internal state of the memory system (1000) is satisfied (S310); a step of detecting that at least one condition inside the memory system is satisfied (S320); a step of transmitting a message indicating the detected condition from the memory system (1000) to the host (300) (S330); a step of determining at least one code to be executed in response to the detected condition by the host (S340); a step of transmitting a command for executing the determined code from the host (300) to the memory system (S350); a step of executing a code corresponding to the command transmitted by the memory system (1000) (S360); and a step of transmitting the result of the code execution from the host (300) to the memory system (S370).

[0127] According to one embodiment of the present invention, a condition confirmation message (MSG) indicating a condition detected in step (S330) CNF) can be transmitted from the memory system (1000) to the host (300) via the second link (420). Therefore, a request or command from the host is not required as a prerequisite for performing step (S330).

[0128] Meanwhile, according to one embodiment of the present invention, a command (CMD) for executing the code determined in step (S340) may be transmitted from the host (300) to the memory system (1000) via the first link (410). Additionally, an execution result message (MSG) indicating the execution result of the code determined in step (S370) RSL ) can be transmitted from the memory system (1000) to the host (300) via the first link (410).

[0129] FIG. 11 illustrates the present invention in terms of a computing system by combining the operation method of the memory system illustrated in FIG. 8 and the operation of the host illustrated in FIG. 9. That is, step (S310) of FIG. 11 corresponds to step (S110) of FIG. 8, and step (S320) of FIG. 11 corresponds to step (S120) of FIG. 8. Also, step (S330) of FIG. 11 corresponds to step (S130) of FIG. 8 and step (S210) of FIG. 9, and step (S340) of FIG. 11 corresponds to step (S230) of FIG. 9. Meanwhile, step (S350) of FIG. 11 corresponds to step (S250) of FIG. 9 and step (S140) of FIG. 8, and step (S360) of FIG. 11 corresponds to step (S150) of FIG. 8. Finally, step (S370) of FIG. 11 corresponds to step (S160) of FIG. 8 and step (S270) of FIG. 9.

[0131] FIG. 12 is a block diagram showing an example of a controller illustrated in FIG. 1.

[0132] Referring to FIG. 12, the controller (200) is connected to the semiconductor memory device (100) and the host (HOST). The semiconductor memory device (100) may be the semiconductor memory device described with reference to FIG. 2. The controller (200) corresponds to the controller (200) of FIG. 1 or FIG. 7. Redundant descriptions below are omitted.

[0133] The controller (200) is configured to access the semiconductor memory device (100) in response to a request from the host. For example, the controller (200) is configured to control the read, write, erase, and background operations of the semiconductor memory device (100). The controller (200) is configured to provide an interface between the semiconductor memory device (100) and the host. The controller (200) is configured to run firmware for controlling the semiconductor memory device (100).

[0134] The controller (200) includes a RAM (210, Random Access Memory), a processing unit (220, processing unit), a host interface (230, host interface), a memory interface (240, memory interface), and an error correction block (250). The RAM (210) is used as at least one of the operating memory of the processing unit (220), a cache memory between the semiconductor memory device (100) and the host, and a buffer memory between the semiconductor memory device (100) and the host. As an example, at least one of the condition storage unit (205) and the code storage unit (209) of FIG. 7 may be implemented as the RAM (210) of FIG. 12. As another example, at least one of the condition storage unit (205) and the code storage unit (209) of FIG. 7 may be implemented as a Read-Only Memory (ROM) not shown in FIG. 12.

[0135] The processing unit (220) controls the general operations of the controller (200). The processing unit (220) of FIG. 12 can drive the firmware of the controller (200). In this case, the condition monitor (203) and the code execution unit (207) of FIG. 7 can be implemented as firmware driven by the processing unit (220).

[0136] The host interface (230) includes a protocol for performing data exchange between the host and the controller (200). As an exemplary embodiment, the controller (200) is configured to communicate with the host through at least one of various interface protocols, such as the USB (Universal Serial Bus) protocol, the MMC (multimedia card) protocol, the PCI (peripheral component interconnection) protocol, the PCI-E (PCI-express) protocol, the ATA (Advanced Technology Attachment) protocol, the Serial-ATA protocol, the Parallel-ATA protocol, the SCSI (small computer system interface) protocol, the ESDI (enhanced small disk interface) protocol, and the IDE (Integrated Drive Electronics) protocol, a private protocol, etc. For example, the aforementioned first link (410) may be configured to use the protocols listed above. The host interface (230) of FIG. 12 may be substantially the same component as the host interface (201) of FIG. 7. Meanwhile, in one embodiment of the present invention, the host interface (230) may include a universal asynchronous receiver and transmitter (UART). In this case, the second link (420) may use the UART protocol.

[0137] The memory interface (240) interfaces with the semiconductor memory device (100). For example, the memory interface includes a NAND interface or a NOR interface.

[0138] The error correction block (250) is configured to detect and correct errors in data received from the semiconductor memory device (100) using an error correction code (ECC). The processing unit (220) will control the semiconductor memory device (100) to adjust the read voltage and perform a re-read according to the error detection result of the error correction block (250). As an exemplary embodiment, the error correction block may be provided as a component of the controller (200).

[0139] The controller (200) and the semiconductor memory device (100) can be integrated into a single semiconductor device. As an exemplary embodiment, the controller (200) and the semiconductor memory device (100) can be integrated into a single semiconductor device to form a memory card. For example, the controller (200) and the semiconductor memory device (100) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0140] The controller (200) and the semiconductor memory device (100) can be integrated into a single semiconductor device to form a semiconductor drive (SSD, Solid State Drive). The semiconductor drive (SSD) includes a memory system (1000) configured to store data in semiconductor memory. When the memory system (1000) including the controller (200) and the semiconductor memory device (100) is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system (1000) is dramatically improved.

[0141] As another example, a memory system (1000) comprising a controller (200) and a semiconductor memory device (100) is one of a computer, UMPC (Ultra Mobile PC), workstation, netbook, PDA (Personal Digital Assistants), portable computer, web tablet, wireless phone, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, and various electronic devices constituting a computer network It is provided as one of the various components of an electronic device, such as one of the devices, one of the various electronic devices constituting a telematics network, an RFID device, or one of the various components constituting a computing system.

[0142] As an exemplary embodiment, a semiconductor memory device (100), a controller (200), and a memory system (1000) including the same may be mounted in various types of packages. For example, the semiconductor memory device (100) or the memory system may be mounted in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), etc.

[0143] Figure 13 is a block diagram showing an application example of the memory system of Figure 1.

[0144] Referring to FIG. 13, the memory system (2000) includes a semiconductor memory device (2100) and a controller (2200). The semiconductor memory device (2100) includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0145] In FIG. 13, a plurality of groups are each shown communicating with the controller (2200) through the first to k channels (CH1~CHk). Each semiconductor memory chip will be configured and operated in the same way as the semiconductor memory device (100) described with reference to FIG. 2.

[0146] Each group is configured to communicate with the controller (2200) through a common channel. The controller (2200) is configured in the same way as the controller (200) described with reference to FIG. 12 and is configured to control multiple memory chips of the semiconductor memory device (2100) through multiple channels (CH1~CHk).

[0148] FIG. 14 is a block diagram showing a computing system including a memory system described with reference to FIG. 13.

[0149] The computing system (3000) includes a central processing unit (3100), RAM (3200, RAM, Random Access Memory), a user interface (3300), a power supply (3400), a system bus (3500), and a memory system (2000).

[0150] The memory system (2000) is electrically connected to the central processing unit (3100), RAM (3200), user interface (3300), and power supply (3400) via the system bus (3500). Data provided through the user interface (3300) or processed by the central processing unit (3100) is stored in the memory system (2000).

[0151] In FIG. 13, the semiconductor memory device (2100) is shown as being connected to the system bus (3500) via a controller (2200). However, the semiconductor memory device (2100) may be configured to be directly connected to the system bus (3500). In this case, the function of the controller (2200) will be performed by the central processing unit (3100) and the RAM (3200).

[0152] In FIG. 13, the components of the computing system (3000), excluding the memory system (2000), such as the central processing unit (3100), RAM (3200, Random Access Memory), user interface (3300), power supply (3400), and system bus (3500), can constitute a host. That is, the host and the memory system (2000) communicating with it can constitute the computing system (3000) of FIG. 13.

[0153] In FIG. 14, a memory system (2000) described with reference to FIG. 13 is shown provided. However, the memory system (2000) may be replaced with a memory system comprising a controller (200) and a semiconductor memory device (100) described with reference to FIG. 12.

[0154] The embodiments of the present invention disclosed in this specification and drawings are provided merely as specific examples to facilitate the explanation of the technical content of the present invention and to aid in understanding the present invention, and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other variations based on the technical concept of the present invention are possible in addition to the embodiments disclosed herein. Explanation of the symbols

[0155] 100: Semiconductor memory device 200: Controller 300: Host 1000: Memory System

Claims

Claim 1 A memory system comprising: a semiconductor memory device including a plurality of memory cells; and a controller that controls the operation of the semiconductor memory device and communicates with a host, wherein the controller comprises: a condition storage unit that stores at least one condition related to an internal state of the memory system; a code storage unit configured to store at least one code for performing a test operation of the memory system; a condition monitor that monitors whether the at least one condition related to the internal state of the memory system and associated with the at least one code is satisfied, and outputs a confirmation signal when the at least one condition is satisfied; and a host interface that outputs a condition confirmation message to the host in response to the confirmation signal indicating that the at least one condition is satisfied, wherein the controller controls the host interface to execute the at least one code instructed by the host after outputting the condition confirmation message, and to transmit an execution result message to the host indicating the execution result of the at least one code. Claim 2 A memory system according to claim 1, wherein at least one condition is received from the host and stored in the condition storage unit. Claim 3 A memory system according to claim 1, wherein at least one condition is stored in a condition storage unit at the time of manufacturing the memory system. Claim 4 A memory system according to claim 1, wherein the controller further comprises a code execution unit that executes at least one code. Claim 5 A memory system according to claim 4, wherein the host interface comprises: a first port for exchanging data and commands of a first type with the host; and a second port for exchanging data of a second type with the host, and wherein the controller outputs a condition check message through the second port. Claim 6 A memory system according to claim 5, wherein the host interface receives from the host through the first port a command identifying a code to be executed in response to the satisfied condition among the at least one code, and outputs a control signal to control the code execution unit to execute the code identified by the command. Claim 7 A memory system according to claim 6, wherein the code execution unit executes the code in response to the control signal and transmits the result of the code execution to the host interface. Claim 8 A memory system according to claim 7, wherein the host interface transmits an execution result message indicating the execution result of the code to the host through the first port. Claim 9 A memory system according to claim 8, wherein the execution result indicates either success or failure of execution of the code. Claim 10 A memory system according to claim 5, wherein the second port forms a communication link with the host using the Universal Asynchronous Receiver / Transmitter (UART) protocol. Claim 11 A method of operation of a host that exchanges data and commands of a first type through a memory system and a first link, comprising: receiving a condition check message indicating that a condition related to an internal state of the memory system has been satisfied through a second link different from the first link; determining code to be executed by the memory system in response to the satisfied condition based on the condition check message; transmitting a command identifying the determined code to the memory system through the first link; and receiving an execution result message indicating the execution result of the code from the memory system through the first link. Claim 12 A method of operation of a host according to claim 11, characterized in that the code is for performing a test operation of the memory system. Claim 13 delete Claim 14 A method of operation of a host according to claim 11, characterized in that the second link uses the Universal Asynchronous Receiver / Transmitter (UART) protocol. Claim 15 A method of operation of a memory system communicating with a host through a first link for transmitting and receiving data and commands of a first type and a second link for transmitting and receiving data of a second type, the method comprising: monitoring whether at least one condition related to the internal state of the memory system is satisfied; generating a confirmation signal when the at least one condition is satisfied; transmitting a condition confirmation message indicating that the at least one condition is satisfied to the host through the second link in response to the confirmation signal; receiving a command corresponding to the condition confirmation message from the host through the first link; executing at least one code identified by the received command; and transmitting an execution result message indicating the execution result of the at least one code to the host through the first link. Claim 16 A method of operation of a memory system according to claim 15, characterized in that the memory system requires a corresponding command from the host to transmit data to the host through the first link, and the memory system does not require a corresponding command from the host to transmit data to the host through the second link. Claim 17 delete Claim 18 A method of operation of a memory system, wherein, in claim 15, the execution result indicates either success or failure of execution of the code. Claim 19 A method of operation of a memory system according to claim 15, characterized in that the second link uses a Universal Asynchronous Receiver / Transmitter (UART) protocol.

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