Signal line sensing amplifying circuit and integrated circuit to calibrate the draiving strength of mos transistors

Abstract

The integrated circuit includes an operation control circuit that controls the generation of a shared signal, a precharge signal, a sensing signal, a latch signal, and a calibration enable signal for calibration operation and sensing amplification operation; and a signal line sensing amplifier circuit that receives the shared signal, the precharge signal, the sensing signal, the latch signal, and the calibration enable signal and performs the calibration operation and the sensing amplification operation.

Description

Technology Field

[0001] The present invention relates to a signal line sensing amplifier circuit and an integrated circuit capable of correcting the driving strength of MOS transistors. Background Technology

[0002] Generally, an integrated circuit can receive or output various signals through multiple signal lines contained within it. When transmitting signals through these signal lines, the integrated circuit uses a signal line sensing amplifier circuit to sense and amplify the signals from the signal lines and transmit them to other signal lines. The signal line sensing amplifier circuit is equipped with multiple MOS transistors to sense and amplify the signals from the signal lines; since each MOS transistor has various process characteristics, it is configured to have a driving strength determined by those process characteristics. The problem to be solved

[0003] The present invention provides a signal line sensing amplifier circuit and an integrated circuit capable of correcting the driving strength of MOS transistors. means of solving the problem

[0004] To this end, the present invention provides an integrated circuit comprising: an operation control circuit that controls the generation of a shared signal, a precharge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sensing amplification operation; and a signal line sensing amplification circuit that receives the shared signal, the precharge signal, the sensing signal, the latch signal, and the calibration enable signal and performs the calibration operation and the sensing amplification operation.

[0005] In the present invention, the signal line sensing amplifier circuit includes MOS transistors that drive input nodes into which input data and inverted input data are input, and in the calibration operation, the driving strength of the MOS transistors is calibrated, and in the sensing amplifier operation performed after the calibration operation is performed, the input data and the inverted input data are sensed and amplified to generate output data and inverted output data.

[0006] In addition, the present invention provides a signal line sensing amplifier circuit comprising: a sensing amplifier circuit including MOS transistors that drive input nodes into which input data and inverted input data are input during a calibration operation and a sensing amplifier operation; and a calibration circuit that generates calibration signals for calibrating the driving strength of the MOS transistors during the calibration operation.

[0007] In the present invention, the sensing amplification circuit generates output data and inverted output data by sensing amplifying the input data and the inverted input data during a sensing amplification operation performed based on the correction signals.

[0008] In addition, the present invention comprises a sensing amplifier circuit including MOS transistors that drive input nodes into which input data and inverted input data are input during a calibration operation and a sensing amplifier operation; a first calibration circuit that generates first calibration signals for calibrating the driving strength of the MOS transistors during the calibration operation; and a second calibration circuit that generates second calibration signals for calibrating the driving strength of the MOS transistors during the calibration operation. In the present invention, the sensing amplifier circuit generates output data and inverted output data by sensing amplifying the input data and the inverted input data during a sensing amplifier operation that proceeds while the calibration operation is performed, based on the first calibration signals and the second calibration signals. Effects of the invention

[0009] According to the present invention, by providing a correction operation based on correction elements that are selectively activated to correct the driving strength of MOS transistors, it is possible to prevent the phenomenon in which the logic level of a signal transmitted through a signal line by a MOS transistor with a weakly set driving strength is reversed.

[0010] In addition, according to the present invention, by providing compensation elements capable of compensating for the capacitance difference between input nodes when calibration elements are selectively activated to calibrate the driving strength of MOS transistors, the capacitance difference between input nodes can be minimized. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram illustrating the configuration of an integrated circuit according to an example of the present invention. FIG. 2 is a circuit diagram of a signal line sensing amplifier circuit according to an example of the present invention. FIGS. 3 to 8 are timing diagrams and circuit diagrams for explaining the correction operation of a signal line sensing amplifier circuit according to an example of the present invention. FIGS. 9 to 12 are drawings for explaining the sensing amplification operation of a signal line sensing amplification circuit according to an example of the present invention. FIG. 13 is a block diagram illustrating the configuration of an integrated circuit according to another example of the present invention. FIG. 14 is a circuit diagram of a signal line sensing amplifier circuit according to another example of the present invention. FIG. 15 is a timing diagram for explaining the correction operation of a signal line sensing amplifier circuit according to another example of the present invention. FIG. 16 is a circuit diagram of a signal line sensing amplifier circuit according to another example of the present invention. Specific details for implementing the invention

[0012] In the description of the following embodiments, the term "pre-set" means that the numerical value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on the embodiment, the numerical value of the parameter may be set when the process or algorithm starts or during the period in which the process or algorithm is executed.

[0013] Terms such as "first" and "second," used to distinguish various components, are not limited by the components. For example, the first component may be named the second component, and conversely, the second component may be named the first component.

[0014] When it is stated that one component is "connected" or "connected" to another component, it should be understood that they are connected directly or through an intermediate component. On the other hand, the descriptions "directly connected" and "directly connected" should be understood as meaning that one component is directly connected to another component without any intermediary component.

[0015] "Logic high level" and "logic low level" are used to describe the logic levels of signals. A signal having a "logic high level" is distinguished from a signal having a "logic low level." For example, when a signal having a first voltage corresponds to a signal having a "logic high level," a signal having a second voltage may correspond to a signal having a "logic low level." According to one embodiment, the "logic high level" may be set to a voltage greater than the "logic low level." Meanwhile, the logic levels of the signals may be set to different logic levels or opposite logic levels according to an embodiment. For example, a signal having a logic high level may be set to have a logic low level according to an embodiment, and a signal having a logic low level may be set to have a logic high level according to an embodiment.

[0016] "Logic bit set" may refer to a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit set of the signal may be set differently. For example, when 2 bits are included in a signal, the logic bit set of the signal may be set to the first logic bit set when the logic level of each of the 2 bits included in the signal is "logic low level, logic low level," and the logic bit set of the signal may be set to the second logic bit set when the logic level of each of the 2 bits included in the signal is "logic low level, logic high level."

[0017] The present invention will be described in more detail below through examples. These examples are merely for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

[0018] FIG. 1 is a block diagram illustrating the configuration of an integrated circuit (1) according to an example of the present invention. As shown in FIG. 1, the integrated circuit (1) may include an operation control circuit (OP CTR, 11) and a signal line sensing amplifier circuit (SLSA, 13).

[0019] The operation control circuit (11) can control the generation of a sharing signal (SHAR), a precharge signal (PCG), a sensing signal (SEN), a latch signal (LATS), and a calibration enable signal (CEN) based on a calibration operation signal (CAL_OP) and a sensing amplification operation signal (SA_OP). The sharing signal (SHAR) can be generated to share the first signal line (SL1 in FIG. 2) and the first inverted signal line (SL1B in FIG. 2) with input nodes (n111, n112 in FIG. 2). When the first signal line (SL1 in FIG. 2) and the first inverted signal line (SL1B in FIG. 2) and the input nodes (n111, n112 in FIG. 2) are shared, a voltage level difference between the input nodes (n111, n112 in FIG. 2) may occur due to the signals of the first signal line (SL1 in FIG. 2) and the first inverted signal line (SL1B in FIG. 2). A precharge signal (PCG) may be generated for a precharge operation that sets the voltage levels of the input nodes (n111, n112 in FIG. 2) to be equal. A sensing signal (SEN) may be generated to sense and amplify the input data (DIN in FIG. 2) and the inverted input data (DINB in ​​FIG. 2). Latch signals (LATS) can be generated to produce output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) from input data (DIN in FIG. 2) and inverted input data (DINB in ​​FIG. 2). Output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) can be output through a second signal line (SL2 in FIG. 2) and a second inverted signal line (SL2B in FIG. 2). A calibration enable signal (CEN) can be generated to produce a first calibration signal (CAL1) and a second calibration signal (CAL2) by the output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) during a calibration operation. The calibration operation signal (CAL_OP) can be generated to perform a calibration operation to calibrate the driving strength of the MOS transistors (113_1, 113_2 of FIG. 2) included in the signal line sensing amplifier circuit (13).The operation control circuit (11) can sequentially apply a precharge signal (PCG), a sensing signal (SEN), a latch signal (LATS), and a calibration enable signal (CEN), which are controlled to be generated based on the calibration operation signal (CAL_OP) in the calibration operation, to the signal line sensing amplifier circuit (13). The sensing amplifier operation signal (SA_OP) can be generated to perform a sensing amplifier operation that senses and amplifies input data (DIN in FIG. 2) and inverted input data (DINB in ​​FIG. 2) input through the first signal line (SL1 in FIG. 2) and the first inverted signal line (SL1B in FIG. 2) when the driving strength of the MOS transistors (113_1, 113_2 in FIG. 2) is calibrated after the calibration operation is performed. The operation control circuit (11) can sequentially apply a precharge signal (PCG), a sharing signal (SHAR), a sensing signal (SEN), and a latch signal (LATS), which are controlled to be generated based on the sensing amplification operation signal (SA_OP) in the sensing amplification operation, to the signal line sensing amplification circuit (13).

[0020] The signal line sensing amplifier circuit (13) is connected to the operation control circuit (11) and can receive a sharing signal (SHAR), a precharge signal (PCG), a sensing signal (SEN), a latch signal (LATS), and a calibration enable signal (CEN) from the operation control circuit (11). The signal line sensing amplifier circuit (13) can perform a calibration operation by receiving a reset signal (RSTB), a precharge signal (PCG), a sensing signal (SEN), a latch signal (LATS), and a calibration enable signal (CEN). The signal line sensing amplifier circuit (13) can be initialized by the reset signal (RSTB) during the calibration operation. The signal line sensing amplifier circuit (13) can perform a precharge operation during the calibration operation by setting the logic levels of the input data (DIN in FIG. 2) and the inverted input data (DINB in ​​FIG. 2) to be the same by the precharge signal (PCG). The signal line sensing amplifier circuit (13) can sense and amplify input data (DIN in FIG. 2) and inverted input data (DINB in ​​FIG. 2) by means of a sensing signal (SEN) during a calibration operation. The signal line sensing amplifier circuit (13) can generate output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) from input data (DIN in FIG. 2) and inverted input data (DINB in ​​FIG. 2) by means of a latch signal (LATS) during a calibration operation, and can output output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) through a second signal line (SL2 in FIG. 2) and a second inverted signal line (SL2B in FIG. 2). The signal line sensing amplifier circuit (13) can generate a first calibration signal (CAL1) and a second calibration signal (CAL2) from output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) by means of a calibration enable signal (CEN) in a calibration operation. The signal line sensing amplifier circuit (13) can calibrate the driving strength of MOS transistors (113_1, 113_2 in FIG. 2) by means of the first calibration signal (CAL1) and the second calibration signal (CAL2).The signal line sensing amplifier circuit (13) can perform a sensing amplification operation by receiving a precharge signal (PCG), a sharing signal (SHAR), a sensing signal (SEN), and a latch signal (LATS) after a calibration operation. The signal line sensing amplifier circuit (13) can stop the precharge operation by the precharge signal (PCG) during the sensing amplification operation performed after the calibration operation. The signal line sensing amplifier circuit (13) can share the first signal line (SL1 in FIG. 2) and the first inverted signal line (SL1B in FIG. 2) with the input nodes (n111, n112 in FIG. 2) by the sharing signal (SHAR) during the sensing amplification operation performed after the calibration operation. The signal line sensing amplifier circuit (13) generates output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) from input data (DIN in FIG. 2) and inverted input data (DINB in ​​FIG. 2) by means of a latch signal (LATS) in a sensing amplifier operation performed after a calibration operation, and can output the output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) through a second signal line (SL2 in FIG. 2) and a second inverted signal line (SL2B in FIG. 2).

[0021] FIG. 2 is a circuit diagram of a signal line sensing amplifier circuit (13A) according to an example of the present invention. As shown in FIG. 2, the signal line sensing amplifier circuit (13A) may include a sensing amplifier circuit (110) and a calibration circuit (120).

[0022] The sensing amplifier circuit (110) may include PMOS transistors (111_1, 111_2, 111_3, 111_4, 111_5), NMOS transistors (113_1, 113_2, 113_3), NAND gates (115_1, 115_2), and switch elements (117_1, 117_2). The PMOS transistor (111_1) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so as to drive the input data (DIN) to a logic high level. The PMOS transistor (111_2) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so as to drive the inverted input data (DINB) to a logic high level. The PMOS transistor (111_3) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so that the voltage level of the input data (DIN) can be set to be the same as the voltage level of the inverted input data (DINB). The PMOS transistors (111_1, 111_2, 111_3) can be turned off by the precharge signal (PCG) generated at a logic high level during calibration operation and sensing amplification operation. The PMOS transistor (111_4) is turned on by the inverted input data (DINB) of node (n112) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, so that the input data (DIN) of node (n111) can be driven to a logic high level. Nodes (n111, n112) can be set as input nodes. The PMOS transistor (111_5) is turned on by the input data (DIN) of node (n111) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, and can drive the inverted input data (DINB) of node (n112) to a logic high level.The NMOS transistor (113_1) is connected between nodes (n111, n113) and is turned on by the inverted input data (DINB) of node (n112) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, thereby driving the input data (DIN) of node (n111) to a logic low level. The NMOS transistor (113_2) is connected between nodes (n112, n113) and is turned on by the input data (DIN) of node (n111) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, thereby driving the inverted input data (DINB) of node (n112) to a logic low level. The NMOS transistor (113_3) is turned on when the sensing signal (SEN) is generated at a logic high level during the calibration operation and sensing amplification operation, and can drive the node (n113) to a logic low level. The NAND gate (115_1) can receive the latch signal (LATS) and input data (DIN) and perform a negative AND operation. The NAND gate (115_1) can invert buffer the input data (DIN) when the latch signal (LATS) is generated at a logic high level during the calibration operation and sensing amplification operation, and output it as the inverted output data (DOUTB) of the node (n114). The inverted output data (DOUTB) can be output through the second inverted signal line (SL2B). The NAND gate (115_2) can receive the latch signal (LATS) and inverted input data (DINB) and perform a negative AND operation. The NAND gate (115_2) can invert the input data (DINB) and output it as output data (DOUT) of the node (n115) when the latch signal (LATS) is generated at a logic high level during the calibration operation and the sensing amplification operation. The output data (DOUT) can be output through the second signal line (SL2).The switch element (117_1) is turned on when the shared signal (SHAR) is generated at a logic high level during the sensing amplification operation, so that the first signal line (SL1) and the input data (DIN) of the node (n111) can be connected so that the input data (DIN) of the first signal line (SL1) and the node (n111) are shared with each other. The switch element (117_2) is turned on when the shared signal (SHAR) is generated at a logic high level during the sensing amplification operation, so that the first inverted signal line (SL1B) and the inverted input data (DINB) of the node (n112) can be connected so that the inverted input data (DINB) of the first inverted signal line (SL1B) and the node (n112) are shared with each other. A voltage difference may occur between the input data (DIN) shared in the first signal line (SL1) and the inverted input data (DINB) shared in the first inverted signal line (SL1B).

[0023] The calibration circuit (120) may include PMOS transistors (121_1, 121_2), NMOS transistors (122_1, 122_2, 125_1, 125_2, 125_3, 125_4, 127_1, 127_2) and inverters (123_1, 123_2, 123_3, 123_4). The PMOS transistor (121_1) may be turned on when a reset signal (RSTB) is generated at a logic low level for initialization, thereby initializing node (n121) to a logic high level. The PMOS transistor (121_2) may be turned on when a reset signal (RSTB) is generated at a logic low level for initialization, thereby initializing node (n123) to a logic high level. The NMOS transistor (122_1) is connected between nodes (n114, n121) and is turned on when the calibration enable signal (CEN) is generated at a logic high level for calibration operation, so that the logic level of node (n121) can be set according to the inverted output signal (DOUTB) of node (n114). The NMOS transistor (122_2) is connected between nodes (n115, n123) and is turned on when the calibration enable signal (CEN) is generated at a logic high level for calibration operation, so that the logic level of node (n123) can be set according to the output signal (DOUT) of node (n115). The inverter (123_1) can invert buffer the signal of node (n121) and output it as the first calibration signal (CAL1) of node (n122). The inverter (123_2) can output the first correction signal (CAL1) of node (n122) to node (n121) by inverting the buffer when the correction enable signal (CEN) is generated at a logic low level because the correction operation is not performed. The inverter (123_3) can output the second correction signal (CAL2) of node (n124) by inverting the buffer of the signal of node (n123). The inverter (123_4) can output the second correction signal (CAL2) of node (n124) to node (n123) by inverting the buffer when the correction enable signal (CEN) is generated at a logic low level because the correction operation is not performed.The logic levels of the first calibration signal (CAL1) and the second calibration signal (CAL2), respectively, can be determined by the driving strength of the NMOS transistor (113_1) and the NMOS transistor (113_2). For example, when the driving strength of the NMOS transistor (113_1) is set weaker than the driving strength of the NMOS transistor (113_2), the first calibration signal (CAL1) may be generated at a logic high level and the second calibration signal (CAL2) may be generated at a logic low level. For another example, when the driving strength of the NMOS transistor (113_2) is set weaker than the driving strength of the NMOS transistor (113_1), the first calibration signal (CAL1) may be generated at a logic low level and the second calibration signal (CAL2) may be generated at a logic high level. As another example, when the driving strength of the NMOS transistor (113_2) and the NMOS transistor (113_1) is set to be the same, the first calibration signal (CAL1) and the second calibration signal (CAL2) can both be generated at a logic high level. The NMOS transistors (125_1, 125_2) can be connected in series between node (n111) and node (n113). The NMOS transistor (125_1) can be turned on when the driving strength of the NMOS transistor (113_1) is set weaker than the driving strength of the NMOS transistor (113_2) and the first calibration signal (CAL1) is generated at a logic high level, and can operate as a calibration element to calibrate the driving strength of the NMOS transistor (113_1). The NMOS transistor (125_2) can be turned on when the inverted input signal (DINB) of node (n112) is at a logic high level. NMOS transistors (125_3, 125_4) can be connected in series between node (n112) and node (n113). The NMOS transistor (125_3) can be turned on when the second calibration signal (CAL2) is generated at a logic high level by setting the driving strength of the NMOS transistor (113_2) to be weaker than the driving strength of the NMOS transistor (113_1), and can operate as a calibration device to calibrate the driving strength of the NMOS transistor (113_2).The NMOS transistor (125_4) can be turned on when the input signal (DIN) of the node (n111) is at a logic high level. The NMOS transistor (127_1) is connected between the node (n111) and the floating node and can be turned on by a second calibration signal (CAL2). The NMOS transistor (127_2) is connected between the node (n112) and the floating node and can be turned on by a first calibration signal (CAL1). Each of the NMOS transistors (127_1) and (127_2) can operate as a compensation element to compensate for the capacitance difference between the input nodes (n111, n112) after the calibration operation is performed. For example, when a first calibration signal (CAL1) is generated at a logic high level and a second calibration signal (CAL2) is generated at a logic low level by a calibration operation, the NMOS transistor (125_1) connected to node (n111) and the NMOS transistor (127_2) connected to node (n112) are symmetrically turned on, and the NMOS transistor (125_3) connected to node (n112) and the NMOS transistor (127_1) connected to node (n111) are symmetrically turned off, so the capacitance difference between the input nodes (n111, n112) can be minimized. As another example, when the first calibration signal (CAL1) is generated at a logic low level and the second calibration signal (CAL2) is generated at a logic high level by the calibration operation, the NMOS transistor (125_3) connected to node (n112) and the NMOS transistor (127_1) connected to node (n111) are symmetrically turned on, and the NMOS transistor (125_1) connected to node (n111) and the NMOS transistor (127_2) connected to node (n112) are symmetrically turned off, so the capacitance difference between the input nodes (n111, n112) can be minimized. The NMOS transistors (127_1, 127_2) may not be used depending on the embodiment.

[0024] The signal line sensing amplifier circuit (13A) can perform a calibration operation to set the logic level of each of the first calibration signal (CAL1) and the second calibration signal (CAL2) according to the driving strength of the NMOS transistor (113_1) and the NMOS transistor (113_2), and can perform a sensing amplification operation to sense and amplify the signals of the first signal line (SL1) and the first inverted signal line (SL1B) and output them to the second signal line (SL2) and the second inverted signal line (SL2B) while the driving strength of the NMOS transistor (113_1) and the NMOS transistor (113_2) is calibrated.

[0025] FIGS. 3 to 8 are timing diagrams and circuit diagrams for explaining the calibration operation of a signal line sensing amplifier circuit according to an example of the present invention. Hereinafter, the calibration operation of the signal line sensing amplifier circuit (13A) is examined with reference to FIGS. 3 to 8, and is described as follows under the assumption that the driving strength of the NMOS transistor (113_1) is weaker than the driving strength of the NMOS transistor (113_2). In FIGS. 3 to 8, the same reference numerals as in FIG. 2 indicate the same components.

[0026] First, as shown in FIGS. 3 and 4, when the reset signal (RSTB) is generated at the logic low level ("L") for initialization at time T111, the NMOS transistors (121_1, 121_2) are turned on, so the nodes (n121, n123) are all initialized to the logic high level ("H"), and the first correction signal (CAL1) of node (n122) and the second correction signal (CAL2) of node (n124) are both initialized to the logic low level ("L").

[0027] Next, as illustrated in FIGS. 3 and 5, since the precharge signal (PCG) is generated at a logic low level ("L") for precharge operation during the interval prior to time T112, all PMOS transistors (111_1, 111_2, 111_3) are turned on, and the input data (DIN) of node (n111) and the inverted input data (DINB) of node (n112) are both set to a logic high level ("H").

[0028] Next, as shown in FIGS. 3 and 6, at time T112, the precharge signal (PCG) transitions from a logic low level ("L") to a logic high level ("H"), so all PMOS transistors (111_1, 111_2, 111_3) are turned off.

[0029] Next, as illustrated in FIGS. 3 and 6, since the sensing signal (SEN) is generated at a logic high level ("H") from time T113, the input data (DIN) of node (n111) and the inverted input data (DINB) of node (n112) are sensed amplified by PMOS transistors (111_4, 111_5) and NMOS transistors (113_1, 113_2). Since the driving strength of the NMOS transistor (113_1) is weaker than the driving strength of the NMOS transistor (113_2), the input data (DIN) of node (n111) maintains a logic high level ("H") by the sensing amplification operation by the PMOS transistors (111_4, 111_5) and the NMOS transistors (113_1, 113_2), and the inverted input data (DINB) of node (n112) transitions from a logic high level ("H") to a logic low level ("L").

[0030] Next, as illustrated in FIGS. 3 and 7, since the latch signal (LATS) is generated at a logic high level ("H") from time T114, the inverted output data (DOUTB) is generated at a logic low level ("L") by the input data (DIN) at a logic high level ("H"), and the output data (DOUT) is generated at a logic high level ("H") by the inverted input data (DINB) at a logic low level ("L").

[0031] Next, as illustrated in FIGS. 3 and FIGS. 8, since the calibration enable signal (CEN) is generated at a logic high level ("H") from time T115, the first calibration signal (CAL1) is generated at a logic high level ("H") by the inverted output data (DOUTB) of a logic low level ("L"), and the second calibration signal (CAL2) is generated at a logic low level ("L") by the output data (DOUT) of a logic high level ("H"). When the NMOS transistor (125_1) is turned on by the first calibration signal (CAL1) of a logic high level ("H"), the NMOS transistors (125_1, 125_2) can drive the input data (DIN) of the node (n111) together with the NMOS transistor (113_1). Accordingly, the driving strength of the NMOS transistor (113_1) is corrected by the NMOS transistors (125_1, 125_2).

[0032] Finally, as illustrated in FIG. 3, at time T116, the precharge signal (PCG) transitions from a logic high level ("H") to a logic low level ("L"), so that all PMOS transistors (111_1, 111_2, 111_3) are turned on, and thus a precharge operation is performed in which the input data (DIN) of node (n111) and the inverted input data (DINB) of node (n112) are both set to a logic high level ("H").

[0033] FIGS. 9 to 12 are drawings for explaining the sensing amplification operation of a signal line sensing amplification circuit according to an example of the present invention. Hereinafter, the sensing amplification operation of the signal line sensing amplification circuit (13A) is examined with reference to FIGS. 9 to 11. The explanation is as follows, assuming a case where the sensing amplification operation is performed for a first signal line (SL1) set to a logic low level and a first inverted signal line (SL1B) set to a logic high level while the driving strength of the NMOS transistor (113_1) is weaker than the driving strength of the NMOS transistor (113_2). In FIGS. 9 to 12, the same reference numerals as in FIG. 2 indicate the same components.

[0034] First, as shown in FIGS. 9 and 10, when the first calibration signal (CAL1) is generated at a logic high level by the calibration operation, the NMOS transistor (125_1) connected to the node (n111) is turned on, so that the NMOS transistor (113_1) having a weaker driving strength than the NMOS transistor (113_2) can be calibrated. In addition, when the first calibration signal (CAL1) is generated at a logic high level and the second calibration signal (CAL2) is generated at a logic low level by the calibration operation, the NMOS transistor (125_1) connected to node (n111) and the NMOS transistor (127_2) connected to node (n112) are symmetrically turned on, and the NMOS transistor (125_3) connected to node (n112) and the NMOS transistor (127_1) connected to node (n111) are symmetrically turned off, so the capacitance difference between the input nodes (n111, n112) can be minimized.

[0035] Next, as illustrated in FIGS. 9 and FIGS. 11, at time T121, the precharge signal (PCG) transitions from a logic low level ("L") to a logic high level ("H"), so that all PMOS transistors (111_1, 111_2, 111_3) are turned off. At time T122, the shared signal (SHAR) is generated at a logic high level ("H"), so that the first signal line (SL1) and the first inverted signal line (SL1B) are shared with the input nodes (n111, n112), so that the inverted input data (DINB) of node (n112) can be set to a voltage level greater than the input data (DIN) of node (n111). Since the sensing signal (SEN) is generated at a logic high level ("H") from time T123, the input data (DIN) of node (n111) is generated at a logic low level ("L"), and the inverted input data (DINB) of node (n112) is generated at a logic high level ("H").

[0036] Next, as illustrated in FIGS. 9 and FIGS. 12, since the latch signal (LATS) is generated at a logic high level ("H") from time T124, the inverted output data (DOUTB) is generated at a logic high level ("H") by the input data (DIN) at a logic low level ("L"), and the output data (DOUT) is generated at a logic low level ("L") by the inverted input data (DINB) at a logic high level ("H").

[0037] Finally, as illustrated in FIG. 9, at time T125, the precharge signal (PCG) transitions from a logic high level ("H") to a logic low level ("L"), so that all PMOS transistors (111_1, 111_2, 111_3) are turned on, and thus a precharge operation is performed in which the input data (DIN) of node (n111) and the inverted input data (DINB) of node (n112) are both set to a logic high level.

[0038] In this embodiment, although the case where the sensing signal (SEN) and the latch signal (LATS) are implemented as separate signals has been described as an example, depending on the embodiment, the sensing signal (SEN) and the latch signal (LATS) may be implemented as the same signal. The NAND gates (115_1, 115_2) included in the sensing amplifier circuit (110) may be implemented to receive the sensing signal (SEN) instead of the latch signal (LATS) and operate.

[0039] FIG. 13 is a block diagram illustrating the configuration of an integrated circuit (2) according to an example of the present invention. As shown in FIG. 1, the integrated circuit (2) may include an operation control circuit (OP CTR, 21) and a signal line sensing amplifier circuit (SLSA, 23).

[0040] The operation control circuit (21) can control the generation of the sharing signal (SHAR), precharge signal (PCG), sensing signal (SEN), latch signal (LATS), and calibration enable signals (CEN<1:N>) based on the calibration operation signal (CAL_OP) and the sensing amplification operation signal (SA_OP). When the calibration operation signal (CAL_OP) is generated, the operation control circuit (21) can sequentially apply the precharge signal (PCG), sensing signal (SEN), latch signal (LATS), and calibration enable signals (CEN<1:N>), which are controlled to be generated for the calibration operation, to the signal line sensing amplification circuit (23). The operation control circuit (21) can sequentially apply a precharge signal (PCG), a sharing signal (SHAR), a sensing signal (SEN), and a latch signal (LATS), which are controlled to be generated for the sensing amplification operation when the sensing amplification operation signal (SA_OP) is generated, to the signal line sensing amplification circuit (23).

[0041] The signal line sensing amplifier circuit (23) is connected to the operation control circuit (21) and can receive a sharing signal (SHAR), a precharge signal (PCG), a sensing signal (SEN), a latch signal (LATS), and calibration enable signals (CEN<1:N>) from the operation control circuit (21). The signal line sensing amplifier circuit (23) can perform a calibration operation by receiving a reset signal (RSTB), a precharge signal (PCG), a sensing signal (SEN), a latch signal (LATS), and calibration enable signals (CEN<1:N>). The signal line sensing amplifier circuit (23) can be initialized by the reset signal (RSTB) during the calibration operation. The signal line sensing amplifier circuit (23) can perform a precharge operation in which the logic levels of the input data (DIN in FIG. 14) and the inverted input data (DINB in ​​FIG. 14) are set to be the same by the precharge signal (PCG) during the calibration operation. The signal line sensing amplifier circuit (23) can sense and amplify the input data (DIN in FIG. 14) and the inverted input data (DINB in ​​FIG. 2) by the sensing signal (SEN) during the calibration operation. The signal line sensing amplifier circuit (23) can output the output data (DOUT in FIG. 14) and the inverted output data (DOUTB in FIG. 14) through the second signal line (SL2 in FIG. 14) and the second inverted signal line (SL2B in FIG. 14) by the latch signal (LATS) during the calibration operation.

[0042] The signal line sensing amplifier circuit (23) can generate a first calibration signal (CAL1<1:N>) and a second calibration signal (CAL2<1:N>) by the output data (DOUT in FIG. 14) and the inverted output data (DOUTB in FIG. 14) by the calibration enable signals (CEN<1:N>) in the calibration operation. The signal line sensing amplifier circuit (23) can calibrate the driving strength of the MOS transistors (213_1, 213_2 in FIG. 14) by the first calibration signal (CAL1<1:N>) and the second calibration signal (CAL2<1:N>). The signal line sensing amplifier circuit (23) may include MOS transistors (225_1<1:N> in FIG. 14) that operate as calibration elements to correct the driving strength of a MOS transistor (213_1 in FIG. 14) for each bit included in the first calibration signal (CAL1<1:N>). The signal line sensing amplifier circuit (23) may include MOS transistors (225_3<1:N> in FIG. 14) that operate as calibration elements to correct the driving strength of a MOS transistor (213_2 in FIG. 14) for each bit included in the second calibration signal (CAL2<1:N>). At least one of the MOS transistors (225_1<1:N> in FIG. 14) or at least one of the MOS transistors (225_3<1:N> in FIG. 14) may be turned on by the calibration operation.

[0043] The signal line sensing amplifier circuit (23) can perform a sensing amplifier operation by receiving a precharge signal (PCG), a sharing signal (SHAR), a sensing signal (SEN), and a latch signal (LATS) during a sensing amplifier operation performed after a calibration operation. The signal line sensing amplifier circuit (23) can stop the precharge operation by the precharge signal (PCG) during a sensing amplifier operation performed after a calibration operation. The signal line sensing amplifier circuit (23) can share the first signal line (SL1 in FIG. 14) and the first inverted signal line (SL1B in FIG. 14) with the input nodes (n211, n212 in FIG. 14) by the sharing signal (SHAR) during a sensing amplifier operation performed after a calibration operation. The signal line sensing amplifier circuit (23) can output output data (DOUT in FIG. 2) and inverted output data (DOUTB in FIG. 2) through the second signal line (SL2 in FIG. 14) and the second inverted signal line (SL2B in FIG. 14) by means of a latch signal (LATS) in the sensing amplifier operation performed after the calibration operation.

[0044] FIG. 14 is a circuit diagram of a signal line sensing amplifier circuit (23A) according to another example of the present invention. As shown in FIG. 14, the signal line sensing amplifier circuit (23A) may include a sensing amplifier circuit (210) and a calibration circuit (220).

[0045] The sensing amplifier circuit (210) may include PMOS transistors (211_1, 211_2, 211_3, 211_4, 211_5), NMOS transistors (213_1, 213_2, 213_3), NAND gates (215_1, 215_2), and switch elements (217_1, 217_2). The PMOS transistor (211_1) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so as to drive the input data (DIN) to a logic high level. The PMOS transistor (211_2) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so as to drive the inverted input data (DINB) to a logic high level. The PMOS transistor (211_3) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so that the voltage level of the input data (DIN) can be set to be the same as the voltage level of the inverted input data (DINB). The PMOS transistors (211_1, 211_2, 211_3) can be turned off by the precharge signal (PCG) generated at a logic high level during calibration operation and sensing amplification operation. The PMOS transistor (211_4) is turned on by the inverted input data (DINB) of node (n212) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, so that the input data (DIN) of node (n211) can be driven to a logic high level. Nodes (n211, n212) can be set as input nodes. The PMOS transistor (211_5) is turned on by the input data (DIN) of node (n211) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, and can drive the inverted input data (DINB) of node (n212) to a logic high level.The NMOS transistor (213_1) is connected between nodes (n211, n213) and is turned on by the inverted input data (DINB) of node (n212) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, thereby driving the input data (DIN) of node (n211) to a logic low level. The NMOS transistor (213_2) is connected between nodes (n212, n213) and is turned on by the input data (DIN) of node (n211) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, thereby driving the inverted input data (DINB) of node (n212) to a logic low level. The NMOS transistor (213_3) is turned on when the sensing signal (SEN) is generated at a logic high level during the calibration operation and sensing amplification operation, and can drive the node (n213) to a logic low level. The NAND gate (215_1) can receive the latch signal (LATS) and input data (DIN) and perform a negative AND operation. The NAND gate (215_1) can invert buffer the input data (DIN) when the latch signal (LATS) is generated at a logic high level during the calibration operation and sensing amplification operation, and output it as the inverted output data (DOUTB) of the node (n214). The inverted output data (DOUTB) can be output through the second inverted signal line (SL2B). The NAND gate (215_2) can receive the latch signal (LATS) and inverted input data (DINB) and perform a negative AND operation. The NAND gate (215_2) can invert the input data (DINB) and output it as output data (DOUT) of the node (n215) when the latch signal (LATS) is generated at a logic high level during the calibration operation and the sensing amplification operation. The output data (DOUT) can be output through the second signal line (SL2).The switch element (217_1) is turned on when the shared signal (SHAR) is generated at a logic high level during the sensing amplification operation, so that the first signal line (SL1) and the input data (DIN) of the node (n211) can be connected so that the input data (DIN) of the first signal line (SL1) and the node (n211) are shared with each other. The switch element (217_2) is turned on when the shared signal (SHAR) is generated at a logic high level during the sensing amplification operation, so that the first inverted signal line (SL1B) and the inverted input data (DINB) of the node (n212) can be connected so that the inverted input data (DINB) of the first inverted signal line (SL1B) and the node (n212) are shared with each other. A voltage difference may occur between the input data (DIN) shared in the first signal line (SL1) and the inverted input data (DINB) shared in the first inverted signal line (SL1B).

[0046] The calibration circuit (220) may include PMOS transistors (221_1, 221_2), NMOS transistors (222_1<1:N>, 222_2<1:N>, 225_1<1:N>, 225_2, 225_3<1:N>, 225_4, 227_1<1:N>, 227_2<1:N>) and inverters (223_1, 223_2<1:N>, 223_3, 223_4<1:N>). The PMOS transistor (221_1) is turned on when a reset signal (RSTB) is generated at a logic low level for initialization, so as to initialize the node (n221) to a logic high level. The PMOS transistor (221_2) is turned on when the reset signal (RSTB) is generated at a logic low level for initialization, so that the node (n223) can be initialized to a logic high level. Each of the NMOS transistors (222_1<1:N>) is connected between the nodes (n214, n221) and is turned on when each of the calibration enable signals (CEN<1:N>) is generated at a logic high level for calibration operation, so that the logic level of the node (n221) can be set according to the inverted output signal (DOUTB) of the node (n214). Each NMOS transistor (222_2<1:N>) is connected between nodes (n215, n223) and is turned on when each of the calibration enable signals (CEN<1:N>) is generated at a logic high level for calibration operation, so that the logic level of node (n223) can be set according to the output signal (DOUT) of node (n215). Inverter (223_1) can invert buffer the signal of node (n221) and output it as the first calibration signal (CAL1<1:N>) of node (n222). Each of the inverters (223_2<1:N>) can invert buffer the first calibration signal (CAL1<1:N>) of node (n222) and output it to node (n221) when the calibration operation is not performed and each of the calibration enable signals (CEN<1:N>) is generated at a logic low level. The inverter (223_3) can invert the signal of node (n223) and output it as the second correction signal (CAL2<1:N>) of node (n224).Each of the inverters (223_4<1:N>) can output the second calibration signal (CAL2<1:N>) of node (n224) to node (n223) by inverting buffering it when the calibration enable signals (CEN<1:N>) are each generated at a logic low level because the calibration operation is not performed. The logic level of each of the first calibration signal (CAL1<1:N>) and the second calibration signal (CAL2<1:N>) can be determined by the driving strength of the NMOS transistor (213_1) and the NMOS transistor (213_2). The NMOS transistors (225_1<1:N>, 225_2) can be connected in series between node (n211) and node (n213). Each of the NMOS transistors (225_1<1:N>) can be turned on when the first calibration signal (CAL1<1:N>) is generated at a logic high level, such that the driving strength of the NMOS transistor (213_1) is set weaker than the driving strength of the NMOS transistor (213_2), and can operate as calibration elements to calibrate the driving strength of the NMOS transistor (213_1). The NMOS transistor (225_2) can be turned on when the inverted input signal (DINB) of the node (n212) is at a logic high level. The NMOS transistors (225_3<1:N>, 225_4) can be connected in series between the node (n212) and the node (n213). Each of the NMOS transistors (225_3<1:N>) can be turned on when the second calibration signal (CAL2<1:N>) is generated at a logic high level, such that the driving strength of the NMOS transistor (213_2) is set weaker than the driving strength of the NMOS transistor (213_1), and can operate as calibration elements to calibrate the driving strength of the NMOS transistor (213_2). The NMOS transistor (225_4) can be turned on when the input signal (DIN) of the node (n211) is at a logic high level. The NMOS transistor (227_1<1:N>) is connected between the node (n211) and the floating node and can be turned on by the second calibration signal (CAL2<1:N>).The NMOS transistor (227_2<1:N>) is connected between the node (n212) and the floating node and can be turned on by a first calibration signal (CAL1<1:N>). Each of the NMOS transistors (227_1<1:N>) and the NMOS transistor (227_2<1:N>) can operate as a compensation element to compensate for the capacitance difference between the input nodes (n211, n212) after the calibration operation is performed. Depending on the embodiment, the NMOS transistors (227_1<1:N>, 227_2<1:N>) may not be used.

[0047] The signal line sensing amplifier circuit (23A) can perform a calibration operation to set the logic level of each of the first calibration signal (CAL1) and the second calibration signal (CAL2) according to the driving strength of the NMOS transistor (213_1) and the NMOS transistor (213_2), and can perform a sensing amplification operation to sense and amplify the signals of the first signal line (SL1) and the first inverted signal line (SL1B) and output them to the second signal line (SL2) and the second inverted signal line (SL2B) while the driving strength of the NMOS transistor (213_1) and the NMOS transistor (213_2) is calibrated.

[0048] FIG. 15 is a timing diagram for explaining the calibration operation of a signal line sensing amplifier circuit (23A) according to another example of the present invention. Referring to FIG. 15, the calibration operation of a signal line sensing amplifier circuit (23A) according to another example of the present invention is described as follows, assuming a state in which the driving strength of the NMOS transistor (213_1) is weaker than the driving strength of the NMOS transistor (213_2).

[0049] First, when the reset signal (RSTB) is generated at a logic low level ("L") for initialization in the section prior to time T211, the NMOS transistors (221_1, 221_2) are turned on, so the nodes (n221, n223) are all initialized to a logic high level ("H"), and the first correction signal (CAL1<1:N>) of node (n222) and the second correction signal (CAL2<1:N>) of node (n224) are both initialized to a logic low level ("L").

[0050] In addition, since the precharge signal (PCG) is generated at a logic low level ("L") for precharge operation during the period prior to time T211, all PMOS transistors (211_1, 211_2, 211_3) are turned on, and the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are both set to a logic high level.

[0051] Next, at time T211, the precharge signal (PCG) transitions from a logic low level ("L") to a logic high level ("H"), so all PMOS transistors (211_1, 211_2, 211_3) are turned off.

[0052] Next, since the sensing signal (SEN) is generated at a logic high level ("H") from time T212, the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are sensed amplified by PMOS transistors (211_4, 211_5) and NMOS transistors (213_1, 213_2). Since the driving strength of the NMOS transistor (213_1) is weaker than the driving strength of the NMOS transistor (213_2), the input data (DIN) of node (n211) maintains a logic high level ("H") by the sensing amplification operation by the PMOS transistors (211_4, 211_5) and the NMOS transistors (213_1, 213_2), and the inverted input data (DINB) of node (n212) transitions from a logic high level ("H") to a logic low level ("L").

[0053] Next, since the latch signal (LATS) is generated at a logic high level ("H") from time T213, the inverted output data (DOUTB) is generated at a logic low level ("L") by the input data (DIN) at a logic high level ("H"), and the output data (DOUT) is generated at a logic high level ("H") by the inverted input data (DINB) at a logic low level ("L").

[0054] Next, from time T214, the first bit (CEN) of the correction enable signal <1> Since ) is generated as a logic high level ("H"), the first bit (CAL1) of the first correction signal is determined by the inverted output data (DOUTB) of the logic low level ("L"). <1> ) is generated as a logic high level ("H"), and the first bit (CAL2) of the second correction signal is determined by the output data (DOUT) of the logic high level ("H"). <1> ) is generated as a logic low level ("L"). The first bit (CAL1) of the first correction signal of a logic high level ("H"). <1> NMOS transistor (225_1) by ) <1> When ) is turned on, NMOS transistors (225_1 <1> , 225_2) can drive the input data (DIN) of node (n211) together with the NMOS transistor (213_1). Therefore, the NMOS transistors (225_1 <1> The driving strength of the NMOS transistor (213_1) is corrected by , 225_2).

[0055] Next, at time T215, the precharge signal (PCG) transitions from a logic high level ("H") to a logic low level ("L"), so that all PMOS transistors (211_1, 211_2, 211_3) are turned on, and thus a precharge operation is performed in which the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are both set to a logic high level ("H").

[0056] Next, since the precharge signal (PCG) is generated at a logic low level ("L") for precharge operation during the period prior to time T221, all PMOS transistors (211_1, 211_2, 211_3) are turned on, and the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are both set to a logic high level.

[0057] Next, at time T221, the precharge signal (PCG) transitions from a logic low level ("L") to a logic high level ("H"), so all PMOS transistors (211_1, 211_2, 211_3) are turned off.

[0058] Next, since the sensing signal (SEN) is generated at a logic high level ("H") from time T222, the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are sensed amplified by PMOS transistors (211_4, 211_5) and NMOS transistors (213_1, 213_2). Since the driving strength of the NMOS transistor (213_1) is weaker than the driving strength of the NMOS transistor (213_2), the input data (DIN) of node (n211) maintains a logic high level ("H") by the sensing amplification operation by the PMOS transistors (211_4, 211_5) and the NMOS transistors (213_1, 213_2), and the inverted input data (DINB) of node (n212) transitions from a logic high level ("H") to a logic low level ("L").

[0059] Next, since the latch signal (LATS) is generated at a logic high level ("H") from time T223, the inverted output data (DOUTB) is generated at a logic low level ("L") by the input data (DIN) at a logic high level ("H"), and the output data (DOUT) is generated at a logic high level ("H") by the inverted input data (DINB) at a logic low level ("L").

[0060] Next, from time T224, the second bit (CEN) of the correction enable signal <2> Since ) is generated as a logic high level ("H"), the second bit (CAL1) of the first correction signal is determined by the inverted output data (DOUTB) of the logic low level ("L"). <2> ) is generated as a logic high level ("H"), and the second bit (CAL2) of the second correction signal is determined by the output data (DOUT) of the logic high level ("H"). <2> ) is generated as a logic low level ("L"). The second bit (CAL1) of the first correction signal of a logic high level ("H"). <2> NMOS transistor (225_1) by ) <2> When ) is turned on, NMOS transistors (225_1 <2> , 225_2) can drive the input data (DIN) of node (n211) together with the NMOS transistor (213_1). Therefore, the NMOS transistors (225_1 <2> The driving strength of the NMOS transistor (213_1) is corrected by , 225_2).

[0061] Next, at time T225, the precharge signal (PCG) transitions from a logic high level ("H") to a logic low level ("L"), so that all PMOS transistors (211_1, 211_2, 211_3) are turned on, and thus a precharge operation is performed in which the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are both set to a logic high level ("H").

[0062] Next, since the precharge signal (PCG) is generated at a logic low level ("L") for precharge operation during the period prior to time T231, all PMOS transistors (211_1, 211_2, 211_3) are turned on, and the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are both set to a logic high level.

[0063] Next, at time T231, the precharge signal (PCG) transitions from a logic low level ("L") to a logic high level ("H"), so all PMOS transistors (211_1, 211_2, 211_3) are turned off.

[0064] Next, since the sensing signal (SEN) is generated at a logic high level ("H") from time T232, the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are sensed amplified by PMOS transistors (211_4, 211_5) and NMOS transistors (213_1, 213_2). Since the driving strength of the NMOS transistor (213_1) is weaker than the driving strength of the NMOS transistor (213_2), the input data (DIN) of node (n211) maintains a logic high level ("H") by the sensing amplification operation by the PMOS transistors (211_4, 211_5) and the NMOS transistors (213_1, 213_2), and the inverted input data (DINB) of node (n212) transitions from a logic high level ("H") to a logic low level ("L").

[0065] Next, since the latch signal (LATS) is generated at a logic high level ("H") from time T233, the inverted output data (DOUTB) is generated at a logic low level ("L") by the input data (DIN) at a logic high level ("H"), and the output data (DOUT) is generated at a logic high level ("H") by the inverted input data (DINB) at a logic low level ("L").

[0066] Next, from time T234, the Nth bit (CEN) of the correction enable signal <n>Since ) is generated as a logic high level ("H"), the Nth bit (CAL1) of the first correction signal is determined by the inverted output data (DOUTB) of the logic low level ("L"). <n>) is generated as a logic high level ("H"), and the Nth bit (CAL2) of the second correction signal is determined by the output data (DOUT) of the logic high level ("H"). <n>) is generated as a logic low level ("L"). The Nth bit (CAL1) of the first correction signal of a logic high level ("H"). <n>NMOS transistor (225_1) by ) <n>When ) is turned on, NMOS transistors (225_1 <n>, 225_2) can drive the input data (DIN) of node (n211) together with the NMOS transistor (213_1). Therefore, the NMOS transistors (225_1 <n>The driving strength of the NMOS transistor (213_1) is corrected by , 225_2).

[0067] Finally, at time T235, the precharge signal (PCG) transitions from a logic high level ("H") to a logic low level ("L"), so that all PMOS transistors (211_1, 211_2, 211_3) are turned on, and thus a precharge operation is performed in which the input data (DIN) of node (n211) and the inverted input data (DINB) of node (n212) are both set to a logic high level ("H").

[0068] As described above, the signal line sensing amplifier circuit (23A) includes NMOS transistors (225_1<1:N>, 225_3<1:N>) which operate as calibration elements capable of calibrating the driving strength of NMOS transistors (213_1, 213_2), and can perform a calibration operation to determine whether each of the NMOS transistors (225_1<1:N>, 225_3<1:N>) is turned on for each bit included in the calibration enable signal (CEN<1:N>). When at least one of the NMOS transistors (225_1<1:N>, 225_3<1:N>) is turned on, the driving strength of the NMOS transistors (213_1, 213_2) can be calibrated.

[0069] In this embodiment, the case where the sensing signal (SEN) and the latch signal (LATS) are implemented as separate signals has been described as an example, but depending on the embodiment, the sensing signal (SEN) and the latch signal (LATS) may be implemented as the same signal. The NAND gates (215_1, 215_2) included in the sensing amplifier circuit (210) may be implemented to receive the sensing signal (SEN) instead of the latch signal (LATS) and operate.

[0070] FIG. 16 is a circuit diagram of a signal line sensing amplifier circuit (23B) according to another example of the present invention. As shown in FIG. 16, the signal line sensing amplifier circuit (23B) may include a sensing amplifier circuit (310) and a calibration circuit (320).

[0071] The sensing amplifier circuit (310) may include PMOS transistors (311_1, 311_2, 311_3, 311_4, 311_5), NMOS transistors (313_1, 313_2, 313_3), NAND gates (315_1, 315_2), and switch elements (317_1, 317_2). The PMOS transistor (311_1) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so as to drive the input data (DIN) to a logic high level. The PMOS transistor (311_2) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so as to drive the inverted input data (DINB) to a logic high level. The PMOS transistor (311_3) is turned on when the precharge signal (PCG) is generated at a logic low level for precharge operation, so that the voltage level of the input data (DIN) can be set to be the same as the voltage level of the inverted input data (DINB). The PMOS transistors (311_1, 311_2, 311_3) can be turned off by the precharge signal (PCG) generated at a logic high level during calibration operation and sensing amplification operation. The PMOS transistor (311_4) is turned on by the inverted input data (DINB) of node (n312) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, so that the input data (DIN) of node (n311) can be driven to a logic high level. Nodes (n311, n312) can be set as input nodes. The PMOS transistor (311_5) is turned on by the input data (DIN) of node (n311) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, and can drive the inverted input data (DINB) of node (n312) to a logic high level.The NMOS transistor (313_1) is connected between nodes (n311, n313) and is turned on by the inverted input data (DINB) of node (n312) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, thereby driving the input data (DIN) of node (n311) to a logic low level. The NMOS transistor (313_2) is connected between nodes (n312, n313) and is turned on by the input data (DIN) of node (n311) when the sensing signal (SEN) is generated at a logic high level during calibration operation and sensing amplification operation, thereby driving the inverted input data (DINB) of node (n312) to a logic low level. The NMOS transistor (313_3) is turned on when the sensing signal (SEN) is generated at a logic high level during the calibration operation and sensing amplification operation, and can drive the node (n313) to a logic low level. The NAND gate (315_1) can receive the latch signal (LATS) and input data (DIN) and perform a negative AND operation. The NAND gate (315_1) can invert buffer the input data (DIN) when the latch signal (LATS) is generated at a logic high level during the calibration operation and sensing amplification operation, and output it as the inverted output data (DOUTB) of the node (n314). The inverted output data (DOUTB) can be output through the second inverted signal line (SL2B). The NAND gate (315_2) can receive the latch signal (LATS) and inverted input data (DINB) and perform a negative AND operation. The NAND gate (315_2) can invert the input data (DINB) and output it as output data (DOUT) of the node (n315) when the latch signal (LATS) is generated at a logic high level during the calibration operation and the sensing amplification operation. The output data (DOUT) can be output through the second signal line (SL2).The switch element (317_1) is turned on when the shared signal (SHAR) is generated at a logic high level during the sensing amplification operation, so that the first signal line (SL1) and the input data (DIN) of the node (n311) can be connected so that the input data (DIN) of the first signal line (SL1) and the node (n311) are shared with each other. The switch element (317_2) is turned on when the shared signal (SHAR) is generated at a logic high level during the sensing amplification operation, so that the first inverted signal line (SL1B) and the inverted input data (DINB) of the node (n312) can be connected so that the inverted input data (DINB) of the first inverted signal line (SL1B) and the node (n312) are shared with each other. A voltage difference may occur between the input data (DIN) shared in the first signal line (SL1) and the inverted input data (DINB) shared in the first inverted signal line (SL1B).

[0072] The calibration circuit (320) may include PMOS transistors (321_1, 321_2), OR gates (324_1, 324_2), NMOS transistors (322_1, 322_2, 325_1<1:N>, 325_2, 325_3<1:N>, 325_4, 327_1<1:N>, 327_2<1:N>) and inverters (323_1, 323_2<1:N>, 323_3, 323_4<1:N>). The PMOS transistor (321_1) may be turned on when a reset signal (RSTB) is generated at a logic low level for initialization, thereby initializing the node (n321) to a logic high level. The PMOS transistor (321_2) is turned on when the reset signal (RSTB) is generated at a logic low level for initialization, so that the node (n323) can be initialized to a logic high level. Each of the OR gates (324_1, 324_2) can receive the correction enable signals (CEN<1:N>) and perform a logical OR operation. Each of the OR gates (324_1, 324_2) can output a logic high level when one bit of the correction enable signals (CEN<1:N>) is at a logic high level. The NMOS transistor (322_1) is connected between the nodes (n314, n321) and is turned on when the output of the OR gate (324_1) is generated at a logic high level for correction operation, so that the logic level of the node (n321) can be set according to the inverted output signal (DOUTB) of the node (n314). The NMOS transistor (322_2) is connected between the nodes (n315, n323) and is turned on when the output of the OR gate (324_2) is generated at a logic high level for calibration operation, so that the logic level of the node (n323) can be set according to the output signal (DOUT) of the node (n315). The inverter (323_1) can invert the signal of the node (n321) and output it as the first calibration signal (CAL1<1:N>) of the node (n322).Each of the inverters (323_2<1:N>) can output the first correction signal (CAL1<1:N>) of node (n322) to node (n321) by inverting the buffer when each of the correction enable signals (CEN<1:N>) is generated at a logic low level because no correction operation is performed. Inverter (323_3) can output the second correction signal (CAL2<1:N>) of node (n324) by inverting the buffer when the signal of node (n323) is output. Each of the inverters (323_4<1:N>) can output the second correction signal (CAL2<1:N>) of node (n324) to node (n323) by inverting the buffer when each of the correction enable signals (CEN<1:N>) is generated at a logic low level because no correction operation is performed. The logic level of each of the first calibration signal (CAL1<1:N>) and the second calibration signal (CAL2<1:N>) can be determined by the driving strength of the NMOS transistor (313_1) and the NMOS transistor (313_2). The NMOS transistors (325_1<1:N>, 325_2) can be connected in series between node (n311) and node (n313). Each of the NMOS transistors (325_1<1:N>) can be turned on when the first calibration signal (CAL1<1:N>) is generated at a logic high level by setting the driving strength of the NMOS transistor (313_1) to be weaker than the driving strength of the NMOS transistor (313_2), and can operate as calibration elements that calibrate the driving strength of the NMOS transistor (313_1). The NMOS transistor (325_2) can be turned on when the inverted input signal (DINB) of node (n312) is at a logic high level. The NMOS transistors (325_3<1:N>, 325_4) can be connected in series between node (n312) and node (n313). Each of the NMOS transistors (325_3<1:N>) can be turned on when a second calibration signal (CAL2<1:N>) is generated at a logic high level by setting the driving strength of the NMOS transistor (313_2) to be weaker than the driving strength of the NMOS transistor (313_1), and can operate as calibration elements to calibrate the driving strength of the NMOS transistor (313_2).The NMOS transistor (325_4) can be turned on when the input signal (DIN) of node (n311) is at a logic high level. The NMOS transistor (327_1<1:N>) is connected between node (n311) and the floating node and can be turned on by a second calibration signal (CAL2<1:N>). The NMOS transistor (327_2<1:N>) is connected between node (n312) and the floating node and can be turned on by a first calibration signal (CAL1<1:N>). Each of the NMOS transistors (327_1<1:N>) and NMOS transistor (327_2<1:N>) can operate as a compensation element to compensate for the capacitance difference between the input nodes (n311, n312) after the calibration operation is performed. NMOS transistors (327_1<1:N>, 327_2<1:N>) may not be used depending on the embodiment.

[0073] The signal line sensing amplifier circuit (23B) includes NMOS transistors (325_1<1:N>, 325_3<1:N>) which operate as calibration elements capable of calibrating the driving strength of NMOS transistors (313_1, 313_2), and can perform a calibration operation to determine whether each of the NMOS transistors (325_1<1:N>, 325_3<1:N>) is turned on for each bit included in the calibration enable signal (CEN<1:N>). When at least one of the NMOS transistors (325_1<1:N>, 325_3<1:N>) is turned on, the driving strength of the NMOS transistors (313_1, 313_2) can be calibrated.

[0074] In this embodiment, the case where the sensing signal (SEN) and the latch signal (LATS) are implemented as separate signals has been described as an example, but depending on the embodiment, the sensing signal (SEN) and the latch signal (LATS) may be implemented as the same signal. The NAND gates (315_1, 315_2) included in the sensing amplifier circuit (310) may be implemented to receive the sensing signal (SEN) instead of the latch signal (LATS) and operate.

[0075] The present invention has been described above with reference to embodiments. Those skilled in the art will understand that the present invention may be embodied in modified forms without departing from the essential characteristics of the invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the scope of equivalents should be interpreted as being included in the invention. Explanation of the symbols

[0077] 11: Operation control circuit 13: Signal line sensing amplifier circuit 110: Sensing amplifier circuit 120: Calibration circuit< / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

Claim 1 An integrated circuit comprising: an operation control circuit that controls the generation of a shared signal, a precharge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sensing amplification operation; and a signal line sensing amplifier circuit that receives the shared signal, the precharge signal, the sensing signal, the latch signal, and the calibration enable signal and performs the calibration operation and the sensing amplification operation, wherein the signal line sensing amplifier circuit includes MOS transistors that drive input nodes into which input data and inverted input data are input, and in the calibration operation, the driving strength of the MOS transistors is calibrated, and in the sensing amplification operation performed in the state in which the calibration operation is performed, the input data and the inverted input data are sense-amplified to generate output data and inverted output data, and in the calibration operation, a first calibration signal and a second calibration signal are generated from the output data and the inverted output data by the calibration enable signal. Claim 2 In claim 1, the operation control circuit is an integrated circuit that sequentially applies the precharge signal, the sensing signal, the latch signal, and the calibration enable signal, which are controlled to be generated based on the calibration operation signal in the calibration operation, to the signal line sensing amplifier circuit. Claim 3 In claim 1, the signal line sensing amplifier circuit is an integrated circuit that can be initialized by a reset signal in the calibration operation. Claim 4 In claim 1, the signal line sensing amplifier circuit is an integrated circuit that sets the logic levels of the input data and the inverted input data to be the same by the precharge signal in the calibration operation. Claim 5 In claim 1, the signal line sensing amplifier circuit is an integrated circuit that senses and amplifies the input data and the inverted input data by the sensing signal in the calibration operation. Claim 6 In claim 1, the signal line sensing amplifier circuit is an integrated circuit that generates the output data and the inverted output data from the input data and the inverted input data by the latch signal in the calibration operation. Claim 7 delete Claim 8 An integrated circuit according to claim 1, wherein the MOS transistors include a first MOS transistor and a second MOS transistor, and the signal line sensing amplifier circuit further includes a first calibration element connected in parallel with the first MOS transistor and turned on based on the first calibration signal; and a second calibration element connected in parallel with the second MOS transistor and turned on based on the second calibration signal. Claim 9 In claim 8, the input nodes include a first input node and a second input node, and the signal line sensing amplifier circuit further includes a first compensation element connected between the first input node where the input data is generated and a floating node and turned on based on the second correction signal; and a second compensation element connected between the second input node where the inverted input data is generated and the floating node and turned on based on the first correction signal, wherein the first compensation element and the second compensation element are an integrated circuit that compensates for the capacitance difference between the first input node and the second input node. Claim 10 In claim 1, the operation control circuit is an integrated circuit that sequentially applies the precharge signal, the shared signal, the sensing signal, and the latch signal, which are controlled to be generated based on the sensing amplification operation signal in the sensing amplification operation, to the signal line sensing amplification circuit. Claim 11 In claim 1, the signal line sensing amplifier circuit is an integrated circuit that, in the sensing amplifier operation, shares a first signal line and a second inverted signal line with the input nodes by means of the shared signal to generate a voltage difference between the input nodes. Claim 12 In claim 1, the signal line sensing amplifier circuit senses and amplifies the input data and the inverted input data by the sensing signal in the sensing amplification operation, generates the output data and the inverted output data from the input data and the inverted input data by the latch signal in the sensing amplification operation, and outputs the output data and the inverted output data to a second signal line and a second inverted signal line. Claim 13 In claim 1, the signal line sensing amplifier circuit includes a sensing amplifier circuit, wherein the sensing amplifier circuit sets the logic levels of the input data and the inverted input data to be the same by the precharge signal in the calibration operation, senses and amplifies the input data and the inverted input data by the sensing signal in the calibration operation, and generates the output data and the inverted output data from the input data and the inverted input data by the latch signal in the calibration operation. Claim 14 In claim 13, the sensing amplifier circuit generates a voltage level difference between the input nodes by sharing a first signal line and a second inverted signal line by the shared signal in the sensing amplifier operation, senses and amplifies the input data and the inverted input data by the sensing signal in the sensing amplifier operation, generates the output data and the inverted output data from the input data and the inverted input data by the latch signal in the sensing amplifier operation, and outputs the output data and the inverted output data to the second signal line and the second inverted signal line. Claim 15 In claim 1, the signal line sensing amplifier circuit is an integrated circuit including a calibration circuit. Claim 16 In claim 15, the MOS transistors include a first MOS transistor and a second MOS transistor, and the calibration circuit includes a first calibration element connected in parallel with the first MOS transistor and turned on based on the first calibration signal; and a second calibration element connected in parallel with the second MOS transistor and turned on based on the second calibration signal. Claim 17 A sensing amplifier circuit comprising MOS transistors that drive input nodes into which input data and inverted input data are input during a calibration operation and a sensing amplifier operation; and a calibration circuit that generates a first calibration signal and a second calibration signal for calibrating the driving strength of the MOS transistors during the calibration operation, wherein the sensing amplifier circuit generates output data and inverted output data by sensing amplifying the input data and the inverted input data during a sensing amplifier operation in which the calibration operation is performed based on the first calibration signal and the second calibration signal, and the calibration circuit generates the first calibration signal and the second calibration signal from the output data and the inverted output data by a calibration enable signal during the calibration operation. Claim 18 In claim 17, the MOS transistors include a first MOS transistor and a second MOS transistor, and the calibration circuit includes a first calibration element connected in parallel with the first MOS transistor and turned on based on the first calibration signal; and a second calibration element connected in parallel with the second MOS transistor and turned on based on the second calibration signal, comprising a signal line sensing amplifier circuit. Claim 19 In claim 18, the input nodes include a first input node and a second input node, and the sensing amplifier circuit includes a first compensation element connected between the first input node where the input data is generated and a floating node and turned on based on the second correction signal; and a second compensation element connected between the second input node where the inverted input data is generated and the floating node and turned on based on the first correction signal, wherein the first compensation element and the second compensation element are a signal line sensing amplifier circuit that compensates for the capacitance difference between the first input node and the second input node. Claim 20 In claim 17, the sensing amplifier circuit sets the logic levels of the input data and the inverted input data to be the same by a precharge signal in the calibration operation, senses and amplifies the input data and the inverted input data by a sensing signal in the calibration operation, and generates the output data and the inverted output data from the input data and the inverted input data by a latch signal in the calibration operation. Claim 21 In claim 17, the sensing amplifier circuit shares a first signal line and a second inverted signal line with the input nodes by means of a shared signal in the sensing amplifier operation to generate a voltage level difference between the input nodes, senses and amplifies the input data and the inverted input data by means of a sensing signal in the sensing amplifier operation, generates the output data and the inverted output data from the input data and the inverted input data by means of a latch signal in the sensing amplifier operation, and outputs the output data and the inverted output data to the second signal line and the second inverted signal line. Claim 22 A sensing amplifier circuit comprising MOS transistors that drive input nodes into which input data and inverted input data are input during a calibration operation and a sensing amplifier operation; a first calibration circuit that generates first calibration signals to calibrate the driving strength of the MOS transistors during the calibration operation; and a second calibration circuit that generates second calibration signals to calibrate the driving strength of the MOS transistors during the calibration operation, wherein the sensing amplifier circuit generates output data and inverted output data by sensing amplifying the input data and the inverted input data during a sensing amplifier operation in which the calibration operation is performed based on the first calibration signals and the second calibration signals, and the first calibration circuit and the second calibration circuit generate the first calibration signal and the second calibration signal from the output data and the inverted output data by a calibration enable signal during the calibration operation.

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