Display apparatus and method of manufacturing the same

Abstract

The present invention provides a method for manufacturing a display device comprising: a step of cleaning the surface of a substrate with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution; and a step of forming a lower metal layer on the surface of the substrate, the lower metal layer comprising a first layer and a second layer on the first layer; wherein the surface roughness of the substrate after cleaning is greater than the surface roughness of the substrate before cleaning.

Description

Technology Field

[0001] The present invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] Recently, display devices have become more diverse in their applications. In addition, there is a trend of display devices becoming thinner and lighter, expanding their range of use.

[0004] As display devices are utilized in diverse ways, there are various methods for designing their forms, and the number of functions that can be integrated or linked with them is increasing. The problem to be solved

[0005] Embodiments of the present invention may provide a display device and a method for manufacturing the same in which the occurrence of copper hillock (Cu Hillock) is prevented or minimized even when a buffer layer is deposited on a lower metal layer provided with copper (Cu) under high temperature conditions (e.g., a temperature of about 370°C or higher). However, this problem is exemplary and the scope of the present invention is not limited by it. means of solving the problem

[0006] According to one aspect of the present invention, a method for manufacturing a display device is provided, comprising the steps of: cleaning the surface of a substrate with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution; and forming a lower metal layer on the surface of the substrate, the lower metal layer comprising a first layer and a second layer on the first layer, wherein the surface roughness of the substrate after cleaning is greater than the surface roughness of the substrate before cleaning.

[0007] In this embodiment, the first layer is provided with a first material, and the second layer may be provided with a second material different from the first material.

[0008] In this embodiment, the first material may include titanium (Ti), and the second material may include copper (Cu).

[0009] In this embodiment, after the step of forming the lower metal layer, the step of forming a buffer layer on the lower metal layer may be further included.

[0010] In the present embodiment, the buffer layer may include a first buffer layer and a second buffer layer stacked sequentially.

[0011] In this embodiment, the first buffer layer and the second buffer layer may be provided with different materials.

[0012] In this embodiment, the first buffer layer is silicon nitride (SiN X ) is provided, and the second buffer layer is silicon oxide (SiO X It can be provided as ).

[0013] In this embodiment, the peak of the (002) plane in the X-ray diffraction spectrum of the first layer by X-ray diffraction analysis may be larger than the peak of the (103) plane.

[0014] In this embodiment, in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis, the peak of the (111) plane may be larger than the peak of the (220) plane.

[0015] In this embodiment, the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis may be 0.3 or higher.

[0016] In the present embodiment, after the step of forming the buffer layer, the method may further include the step of forming a semiconductor layer on the buffer layer; and the step of forming a gate electrode on the semiconductor layer.

[0017] According to another aspect of the present invention, a display device is provided comprising: a substrate; and a lower metal layer disposed on the substrate and comprising a first layer and a second layer on the first layer, wherein in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis, the peak of the (111) plane is larger than the peak of the (220) plane.

[0018] In this embodiment, the first layer is provided with a first material, and the second layer may be provided with a second material different from the first material.

[0019] In this embodiment, the first material may include titanium (Ti), and the second material may include copper (Cu).

[0020] In this embodiment, a buffer layer disposed on the lower metal layer may be further included.

[0021] In the present embodiment, the buffer layer may include a first buffer layer and a second buffer layer stacked sequentially.

[0022] In this embodiment, the first buffer layer and the second buffer layer may be provided with different materials.

[0023] In this embodiment, the first buffer layer is silicon nitride (SiN X ) is provided, and the second buffer layer is silicon oxide (SiO X It can be provided as ).

[0024] In this embodiment, the peak of the (002) plane in the X-ray diffraction spectrum of the first layer by X-ray diffraction analysis may be larger than the peak of the (103) plane.

[0025] In this embodiment, the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis may be 0.3 or higher.

[0026] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention. Effects of the invention

[0027] According to one embodiment of the present invention as described above, by increasing the surface roughness of the substrate, it is possible to prevent or minimize the occurrence of copper hillocks (Cu Hillock) even when a buffer layer is deposited on a lower metal layer provided with copper (Cu) under high temperature conditions (e.g., a temperature of about 370°C or higher). Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0028] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention. FIGS. 3 to 5 are cross-sectional views schematically illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figures 6a and 6b are drawings illustrating the surface conditions of sample #1 and sample #5, respectively. Figure 7 is a diagram showing the X-ray diffraction characteristics of sample #2 and sample #6. Figures 8 and 9 are diagrams showing the X-ray diffraction characteristics of sample #3 and sample #7, respectively. Specific details for implementing the invention

[0029] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0030] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0031] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0033] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0034] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0035] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. Additionally, in this specification, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0036] In the following embodiments, the meaning of "the wiring extends in a first direction or a second direction" includes not only extending in a straight line shape, but also extending in a zigzag or curved shape along the first direction or the second direction.

[0037] In the following embodiments, "planar" refers to the view of the target part from above, and "cross-sectional" refers to the view of the cross-section obtained by vertically cutting the target part from the side. In the following embodiments, "superimposition" includes the superposition of the "planar" and "cross-sectional" views.

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings, and when describing with reference to the drawings, identical or corresponding components will be given the same reference numerals.

[0039] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment of the present invention.

[0040] Referring to FIG. 1, the display device (1) may include a display area (DA) that implements an image and a peripheral area (PA) placed around the display area (DA). The display device (1) may provide an image to the outside using light emitted from the display area (DA).

[0041] The substrate (100) may be provided with glass or a polymer resin. In one embodiment, the substrate (100) may include a flexible material. Here, the flexible material may be a material that can be easily bent, folded, or rolled. For example, the flexible material may be composed of ultra-thin glass, metal, or plastic.

[0042] Pixels (PX) equipped with various display elements, such as organic light-emitting diodes (OLEDs), can be arranged in the display area (DA) of the substrate (100). The pixels (PX) are composed of multiple pixels, and the multiple pixels (PX) can be arranged in various forms, such as a stripe array, a pentile array, or a mosaic array, to realize an image.

[0043] In one embodiment, when the display area (DA) is viewed as a planar shape, the display area (DA) may be provided in a rectangular shape as shown in FIG. 1. Alternatively, the display area (DA) may be provided in a polygonal shape such as a triangle, pentagon, or hexagon, or in a circular shape, elliptical shape, irregular shape, etc.

[0044] The peripheral area (PA) of the substrate (100) is an area placed around the display area (DA) and may be an area where no image is displayed. Various wirings that transmit electrical signals applied to the display area (DA), and pads to which printed circuit boards or driver IC chips are attached may be located in the peripheral area (PA).

[0045] FIG. 2 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.

[0046] Referring to FIG. 2, the display device (1) may include a substrate (100), a thin-film transistor (TFT), and a light-emitting element (OLED).

[0047] The substrate (100) may be provided with glass or a polymer resin. In this case, the polymer resin may include at least one of polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The substrate (100) may have a structure in which layers containing organic material and layers containing inorganic material are alternately stacked. For example, the substrate (100) may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer that are sequentially stacked.

[0048] A lower metal layer (105) may be disposed on a substrate (100). The lower metal layer (105) may be disposed directly on the substrate (100). The lower metal layer (105) may include a first layer (105a) and a second layer (105b). The first layer (105a) of the lower metal layer (105) may be disposed on the substrate (100), and the second layer (105b) of the lower metal layer (105) may be disposed on the first layer (105a).

[0049] The lower metal layer (105) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multilayer of one or more materials. In one embodiment, the first layer (105a) of the lower metal layer (105) may include the first material, and the second layer (105b) of the lower metal layer (105) may include the second material. The first material and the second material may each be one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first material and the second material may be different from each other. For example, the first material may be titanium (Ti) and the second material may be copper (Cu). That is, the first layer (105a) of the lower metal layer (105) may be provided with titanium (Ti), and the second layer (105b) of the lower metal layer (105) may be provided with copper (Cu).

[0050] As described above, the substrate (100) may be made of glass, the first layer (105a) of the lower metal layer (105) may be made of titanium (Ti), and the second layer (105b) of the lower metal layer (105) may be made of copper (Cu). At this time, the first layer (105a) made of titanium (Ti) may be directly disposed on the substrate (100) made of glass, and the second layer (105b) made of copper (Cu) may be directly disposed on the first layer (105a) made of titanium (Ti).

[0051] In one embodiment, in the X-ray diffraction spectrum of the first layer (105a) by X-ray diffraction analysis, the peak of the (002) plane may be larger than the peak of the (103) plane. This will be explained in more detail below.

[0052] In one embodiment, in the X-ray diffraction spectrum of the second layer (105b) by X-ray diffraction analysis, the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane may be 0.3 or greater, and the peak of the (111) plane may be larger than the peak of the (220) plane. This will be explained in more detail below.

[0053] In one embodiment, a buffer layer (110) may be disposed on the lower metal layer (105). The buffer layer (110) may be disposed directly on the lower metal layer (105) and the substrate (100). For example, the buffer layer (110) may be disposed directly on the lower metal layer (105) and the substrate (100) on which the lower metal layer (105) is not disposed. The buffer layer (110) may reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100).

[0054] The buffer layer (110) may include a first buffer layer (110a) and a second buffer layer (110b). The first buffer layer (110a) may be disposed on the lower metal layer (105), and the second buffer layer (110b) may be disposed on the first buffer layer (110a).

[0055] The buffer layer (110) is silicon nitride (SiN X ), silicon oxide (SiO X It may be provided with inorganic materials such as silicon oxynitride (SiON). In one embodiment, the first buffer layer (110a) and the second buffer layer (110b) may be provided with different materials. For example, the first buffer layer (110a) may be silicon nitride (SiN X It can be provided as ), and the second buffer layer (110b) is silicon oxide (SiO₂). XIt may be provided as follows. However, the present invention is not limited thereto. The first buffer layer (110a) and the second buffer layer (110b) may be provided with the same material.

[0056] A thin-film transistor (TFT) may be disposed on the buffer layer (110). The thin-film transistor (TFT) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0057] First, a semiconductor layer (Act) may be disposed on the buffer layer (110). The semiconductor layer (Act) may include a channel region, a source region, and a drain region. The source region and the drain region may be located on both sides of the channel region. The source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities.

[0058] In one embodiment, the semiconductor layer (Act) may include at least one of an oxide semiconductor material and a silicon semiconductor material. When the semiconductor layer (Act) includes an oxide semiconductor material, the semiconductor layer (Act) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer (Act) may include IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O), in which metals such as indium (In), gallium (Ga), and tin (Sn) are contained in ZnO. When the semiconductor layer (Act) includes a silicon semiconductor material, the semiconductor layer (Act) may include amorphous silicon or polysilicon.

[0059] In one embodiment, a gate electrode (GE) may be disposed on a semiconductor layer (Act). The gate electrode (GE) may overlap with the semiconductor layer (Act) with a first insulating layer (111) in between. That is, the semiconductor layer (Act) and the gate electrode (GE) may be insulated through the first insulating layer (111). The gate electrode (GE) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multilayer of one or more materials.

[0060] In one embodiment, the first insulating layer (111) is silicon oxide (SiO₂). X ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO X It may include at least one of the following. In this case, zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0061] In one embodiment, a second insulating layer (113) may be disposed on the gate electrode (GE). The second insulating layer (113) is silicon oxide (SiO₂). X ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO X It may include at least one of the following. In this case, zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0062] In one embodiment, a capacitor (Cst) may be disposed on the buffer layer (110). The capacitor (Cst) may include a lower electrode (CE1) and an upper electrode (CE2). The lower electrode (CE1) and the upper electrode (CE2) may overlap each other with a second insulating layer (113) in between. The gate electrode (GE) of the thin-film transistor (TFT) and the lower electrode (CE1) of the capacitor (Cst) may be provided as a single unit. That is, the gate electrode (GE) of the thin-film transistor (TFT) may function as the lower electrode (CE1) of the capacitor (Cst). In this way, the thin-film transistor (TFT) and the capacitor (Cst) may be formed by overlapping. However, the present invention is not limited thereto. For example, the lower electrode (CE1) of the capacitor (Cst) may be provided as a separate component from the gate electrode (GE) of the thin-film transistor (TFT) and spaced apart from the gate electrode (GE) of the thin-film transistor (TFT).

[0063] The upper electrode (CE2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or a multilayer of the aforementioned materials.

[0064] In one embodiment, a third insulating layer (115) may be disposed on the upper electrode (CE2). The third insulating layer (115) is silicon oxide (SiO₂). X ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO X It may include at least one of the following. In this case, zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0065] In one embodiment, a source electrode (SE) and a drain electrode (DE) may be disposed on the third insulating layer (115). The source electrode (SE) and the drain electrode (DE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the aforementioned materials. For example, the source electrode (SE) and the drain electrode (DE) may have a multilayer structure of Ti / Al / Ti. The source electrode (SE) and the drain electrode (DE) may be electrically connected to the source region and the drain region of the semiconductor layer (Act), respectively.

[0066] In one embodiment, an organic insulating layer (121) may be disposed on the source electrode (SE) and the drain electrode (DE). The organic insulating layer (121) may include an organic insulating material such as a general-purpose polymer like polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and blends thereof. Although FIG. 2 is illustrated as having one organic insulating layer (121), the present invention is not limited thereto. The organic insulating layer (121) may be provided in multiple layers. For example, the organic insulating layer (121) may be provided in two layers, three layers, or four layers. Additionally, wiring and / or connecting electrodes may be provided between the multiple organic insulating layers (121).

[0067] A light-emitting element may be disposed on the organic insulating layer (121). The light-emitting element may be an organic light-emitting diode (OLED). However, the present invention is not limited thereto. The light-emitting element may be an inorganic light-emitting diode, a quantum dot light-emitting diode, etc. Below, the case where the light-emitting element is an organic light-emitting diode (OLED) will be described in detail.

[0068] In one embodiment, the organic light-emitting diode (OLED) may include a pixel electrode (210), a light-emitting layer (220), and a counter electrode (230). The pixel electrode (210) may be disposed on an organic insulating layer (121). The pixel electrode (210) may be electrically connected to a thin-film transistor (TFT) through via holes defined in the organic insulating layer (121). The pixel electrode (210) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Alternatively, the pixel electrode (210) may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. Alternatively, the pixel electrode (210) may further include a film formed of ITO, IZO, ZnO, or In2O3 above and below the aforementioned reflective film.

[0069] A pixel defining film (180) may be disposed on the pixel electrode (210), wherein an opening (OP) is defined to expose at least a portion of the pixel electrode (210). The opening (OP) defined in the pixel defining film (180) may expose at least a portion of the pixel electrode (210). For example, the opening (OP) defined in the pixel defining film (180) may expose the central portion of the pixel electrode (210). A light emission region of light emitted from an organic light-emitting diode (OLED) may be defined by the opening (OP).

[0070] The pixel defining film (180) may include an organic insulating material. Alternatively, the pixel defining film (180) may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining film (180) may include both an organic insulating material and an inorganic insulating material. In one embodiment, the pixel defining film (180) may include a light-blocking material and may be provided in black. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste containing a black dye, metal particles (e.g., nickel, aluminum, molybdenum, and their alloys), metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). When the pixel defining film (180) includes a light-blocking material, it may reduce external light reflection by metal structures placed below the pixel defining film (180).

[0071] Although not illustrated, a spacer may be disposed on the pixel defining film (180). The spacer may include an organic insulating material such as polyimide. Alternatively, the spacer may include an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon oxide, etc., or may include both an organic insulating material and an inorganic insulating material.

[0072] In one embodiment, the spacer may include the same material as the pixel defining film (180). In this case, the pixel defining film (180) and the spacer may be formed together in a mask process using a halftone mask or the like. Alternatively, the spacer and the pixel defining film (180) may include different materials.

[0073] A light-emitting layer (220) may be disposed on the pixel electrode (210). The light-emitting layer (220) may be disposed in the opening of the pixel defining film (180). The light-emitting layer (220) may include a high-molecular organic material or a low-molecular organic material that emits light of a predetermined color.

[0074] A first functional layer may be disposed between the pixel electrode (210) and the light-emitting layer (220), and a second functional layer may be disposed between the light-emitting layer (220) and the counter electrode (230). However, the present invention is not limited thereto. At least one of the first functional layer and the second functional layer may be omitted.

[0075] The first functional layer may, for example, include a hole transport layer (HTL) or include a hole transport layer and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer and / or the second functional layer may be a common layer formed to cover the entire substrate (100).

[0076] The counter electrode (230) may be made of a conductive material with a low work function. For example, the counter electrode (230) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer comprising the aforementioned materials.

[0077] Although not illustrated, a capping layer may be further disposed on the counter electrode (230). The capping layer may include LiF, an inorganic material, or / and an organic material.

[0078] Although not illustrated, an encapsulation member may be disposed on an organic light-emitting diode (OLED). The encapsulation member may be a thin film encapsulation layer comprising at least one inorganic film layer and at least one organic film layer. Alternatively, the encapsulation member may be an encapsulation substrate.

[0079] FIGS. 3 to 5 are cross-sectional views schematically illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0080] Hereinafter, a method for manufacturing a display device will be examined sequentially with reference to FIGS. 3 to 5.

[0081] Referring to FIGS. 3 to 5, a method for manufacturing a display device may include the steps of cleaning the surface (100a) of a substrate (100) with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, forming a lower metal layer (105) on the surface (100a) of the substrate (100) including a first layer (105a) and a second layer (105b) on the first layer (105a), and forming a buffer layer (110) on the lower metal layer (105).

[0082] First, referring to FIG. 3, the surface (100a) of the substrate (100) can be cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. In one embodiment, the substrate (100) may be made of glass. However, the present invention is not limited thereto. For example, the substrate (100) may be made of a polymer resin. Additionally, although not illustrated, the surface (100a) of the substrate (100) may be cleaned using a cleaning solution containing tetramethylammonium hydroxide (TMAH) before cleaning the surface (100a) of the substrate (100) with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution.

[0083] In one embodiment, when the surface (100a) of a substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the surface roughness of the substrate (100) after cleaning may be greater than the surface roughness of the substrate (100) before cleaning. Specifically, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the surface (100a) of the substrate (100) may be etched, and as a result, the surface roughness of the substrate (100) after cleaning may increase compared to the surface roughness of the substrate (100) before cleaning. For example, the surface roughness of the substrate (100) before cleaning is about 0.22 nm, but the surface roughness of the substrate (100) after cleaning the surface (100a) of the substrate (100) with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution can increase to about 0.31 nm. This will be explained in more detail below.

[0084] Referring to FIG. 4, a lower metal layer (105) may subsequently be formed on a substrate (100). Specifically, after cleaning the surface (100a) of the substrate (100) with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, a lower metal layer comprising a first layer (105a) and a second layer (105b) may be formed on the substrate (100). The first layer (105a) of the lower metal layer (105) may be formed on the substrate (100), and the second layer (105b) of the lower metal layer (105) may be formed on the first layer (105a).

[0085] The lower metal layer (105) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multilayer of one or more materials. In one embodiment, the first layer (105a) of the lower metal layer (105) may include the first material, and the second layer (105b) of the lower metal layer (105) may include the second material. The first material and the second material may each be one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first material and the second material may be different from each other. For example, the first material may be titanium (Ti) and the second material may be copper (Cu). That is, the first layer (105a) of the lower metal layer (105) may be provided with titanium (Ti), and the second layer (105b) of the lower metal layer (105) may be provided with copper (Cu).

[0086] When the surface (100a) of a substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the surface roughness of the substrate (100) may increase compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. Additionally, when the surface roughness of the substrate (100) increases, the surface roughness of the first layer (105a) formed on the substrate (100) may increase. Specifically, in a structure in which a first layer (105a) is formed on a substrate (100), the surface roughness of the first layer (105a) when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution may be greater than the surface roughness of the first layer (105a) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the surface roughness of the substrate (100) may increase, and the surface roughness of the first layer (105a) may also increase. This will be explained in more detail below.

[0087] When the surface roughness of the substrate (100) increases, the surface roughness of the first layer (105a) formed on the substrate (100) may increase. However, even when the surface roughness of the substrate (100) and the surface roughness of the first layer (105a) increase, the surface roughness of the second layer (105b) formed on the first layer (105a) may decrease. Specifically, in a structure in which the first layer (105a) and the second layer (105b) are sequentially formed on the substrate (100), the surface roughness of the second layer (105b) when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution may be smaller than the surface roughness of the second layer (105b) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the surface roughness of the first layer (105a) increases, but the surface roughness of the second layer (105b) can decrease. This will be explained in more detail below.

[0088] In one embodiment, in the X-ray diffraction spectrum of the first layer (105a) by X-ray diffraction analysis, the peak of the (002) plane may be larger than the peak of the (103) plane. This will be explained in more detail below.

[0089] In one embodiment, in the X-ray diffraction spectrum of the second layer (105b) by X-ray diffraction analysis, the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane may be 0.3 or greater, and the peak of the (111) plane may be larger than the peak of the (220) plane. This will be explained in more detail below.

[0090] Referring to FIG. 5, after a lower metal layer (105) is formed on a substrate (100), a buffer layer (110) may be formed on the lower metal layer (105). The buffer layer (110) may include a first buffer layer (110a) and a second buffer layer (110b). The first buffer layer (110a) may be formed on the lower metal layer (105), and the second buffer layer (110b) may be formed on the first buffer layer (110a).

[0091] The buffer layer (110) is silicon nitride (SiN X ), silicon oxide (SiO X It may be provided with inorganic materials such as silicon oxynitride (SiON). In one embodiment, the first buffer layer (110a) and the second buffer layer (110b) may be provided with different materials. For example, the first buffer layer (110a) may be silicon nitride (SiN X It can be provided as ), and the second buffer layer (110b) is silicon oxide (SiO₂). X It may be provided as follows. However, the present invention is not limited thereto. The first buffer layer (110a) and the second buffer layer (110b) may be provided with the same material.

[0092] On the buffer layer (110), as shown in FIG. 2, a thin-film transistor (TFT, FIG. 2) including a semiconductor layer (Act, FIG. 2), a gate electrode (GE, FIG. 2), a source electrode (SE, FIG. 2), and a drain electrode (DE, FIG. 2), and an organic light-emitting diode (OLED) including a pixel electrode (210, FIG. 2), a light-emitting layer (220, FIG. 2), and a counter electrode (230, FIG. 2) may be formed.

[0093] Specifically, a semiconductor layer (Act) may be formed on the buffer layer (110), and a first insulating layer (111, see FIG. 2) may be formed on the semiconductor layer (Act). A gate electrode (GE) may be formed on the first insulating layer (111), and a second insulating layer (113, see FIG. 2) may be formed on the gate electrode (GE). An upper electrode (CE2, see FIG. 2) may be formed on the second insulating layer (113), and a third insulating layer (115, see FIG. 2) may be formed on the upper electrode (CE2), and a source electrode (SE) and a drain electrode (DE) may be formed on the third insulating layer (115).

[0094] Additionally, an organic insulating layer (121, see FIG. 2) may be formed on the source electrode (SE) and drain electrode (DE), a pixel electrode (210) and a pixel defining film (180, see FIG. 2) may be formed on the organic insulating layer (121), and a light-emitting layer (220) and a counter electrode (230) may be formed on the pixel electrode (210).

[0095] If the deposition temperature of the buffer layer (110) is low, oxygen gas within the buffer layer (110) may be released during a subsequent process, which may degrade the characteristics of the device formed on the buffer layer (110). That is, if the buffer layer (110) is deposited at a temperature that is too low, oxygen gas within the buffer layer (110) may be released, which may degrade the characteristics of the thin-film transistor (TFT) formed on the buffer layer (110). In order to prevent the release of oxygen gas within the buffer layer (110), the buffer layer (110) needs to be deposited at a high temperature.

[0096] Accordingly, the buffer layer (110) can be deposited at a high temperature (e.g., a temperature of about 370°C or higher). However, if the buffer layer (110) is deposited at a high temperature (e.g., a temperature of about 370°C or higher), copper nitride (CuN) is deposited at the grain boundary of the second layer (105b) of the lower metal layer (105). X) can be formed. In addition, copper nitride (CuN) can be formed due to compressive stress caused by the deposition temperature of the buffer layer (110) (e.g., a temperature of about 370°C or higher). X Copper atoms may move along the wall of the buffer layer (110), and a copper hillock may occur on the surface of the second layer (105b) of the lower metal layer (105) due to stress caused by heat during the deposition of the buffer layer (110). At this time, due to the copper hillock formed on the surface of the second layer (105b) of the lower metal layer (105), bending may be induced in the electrodes formed on the upper surface (e.g., gate electrode (GE), upper electrode (CE2), source electrode (SE), and drain electrode (DE)), and defects may occur in the electrodes (e.g., gate electrode (GE), upper electrode (CE2), source electrode (SE), and drain electrode (DE)).

[0097] Tables 1 and 2 below show the results of measuring the level of hilllock occurrence and surface roughness of various samples. In Table 1, TMAH cleaning means cleaning the surface (100a) of the substrate (100) using a cleaning solution containing tetramethylammonium hydroxide (TMAH), etchant cleaning means cleaning the surface (100a) of the substrate (100) with an etchant containing fluorine (F), and HF cleaning means cleaning the surface (100a) of the substrate (100) with a hydrofluoric acid (HF) solution. That is, TMAH cleaning + etchant cleaning means cleaning the surface (100a) of the substrate (100) using a cleaning solution containing tetramethylammonium hydroxide (TMAH), and then cleaning the surface (100a) of the substrate (100) with an etchant containing fluorine (F). Additionally, TMAH cleaning + HF cleaning means cleaning the surface (100a) of the substrate (100) using a cleaning solution containing tetramethylammonium hydroxide (TMAH), and then cleaning the surface (100a) of the substrate (100) with a hydrofluoric acid (HF) solution.

[0098] In Table 1, samples #2 and #6 represent cases where a first layer (Ti) is formed on a substrate (Glass), samples #3 and #7 represent cases where a first layer (Ti) and a second layer (Cu) are formed sequentially on a substrate (Glass), and samples #4, #8, and #9 represent cases where a first layer (Ti), a second layer (Cu), and a buffer layer are formed sequentially on a substrate (Glass). At this time, as described above in FIG. 2, the buffer layer is a first buffer layer (SiN X ) and second buffer layer (SiO X It may include ).

[0099] In Table 2, the level of hillock occurrence and RMS roughness were measured using an atomic force microscope (AFM).

[0100] Sample Information No. Process conditions Stacked structure #1 TMAH cleaning Substrate (Glass) #2 Substrate (Glass) / 1st layer (Ti) #3 Substrate (Glass) / 1st layer (Ti) / 2nd layer (Cu) #4 Substrate (Glass) / 1st Layer (Ti) / 2nd Layer (Cu) / Buffer #5 TMAH cleaning + Etched cleaning (including F) Substrate (Glass) #6 Substrate (Glass) / 1st layer (Ti) #7 Substrate (Glass) / 1st layer (Ti) / 2nd layer (Cu) #8 Substrate (Glass) / 1st Layer (Ti) / 2nd Layer (Cu) / Buffer #9 TMAH cleaning + HF cleaning Substrate (Glass) / 1st Layer (Ti) / 2nd Layer (Cu) / Buffer

[0101] No. Hillock level RMS Roughness(nm) medium Standard deviation 1 2 #1 - 0.232 0.217 0.22 0.011 #2 0.277 0.265 0.27 0.008 #3 river 3.634 3.616 3.63 0.013 #4 12.654 12.584 12.62 0.049 #5 - 0.306 0.313 0.31 0.005 #6 0.504 0.504 0.50 0 #7 Weakness / Medicine 1.719 1.630 1.67 0.063 #8 3.363 3.872 3.62 0.360 #9 approximately 4.534 4.376 4.46 0.112

[0102] Figures 6a and 6b are drawings illustrating the surface conditions of sample #1 and sample #5, respectively. Specifically, Figures 6a and 6b are drawings illustrating the surface conditions of sample #1 and sample #5 as measured by an atomic force microscope (AFM), respectively.

[0103] Referring to Table 1, Table 2, FIGS. 6a, and FIGS. 6b, it can be seen that the surface roughness of the substrate (100) when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) is greater than the surface roughness of the substrate (100) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F). That is, it can be seen that the surface roughness of the substrate (100) increases when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F).

[0104] Additionally, it can be confirmed that the surface roughness of the first layer (Ti) when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) is greater than the surface roughness of the first layer (Ti) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F). However, it can be confirmed that the surface roughness of the second layer (Cu) when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) is smaller than the surface roughness of the second layer (Cu) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F). That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F), the surface roughness of the first layer (Ti) increases compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F), but the surface roughness of the second layer (Cu) when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) may decrease compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F).

[0105] When the surface (100a) of a substrate (100) is cleaned with an etchant containing fluorine (F), the surface roughness of the substrate (100) may increase, and the surface roughness of the first layer (Ti) formed on the substrate (100) may increase. When the surface roughness of the substrate (100) and the surface roughness of the first layer (Ti) increase, the nucleation sites of copper (Cu) contained in the second layer (Cu) may increase, and when the nucleation sites of copper (Cu) increase, the grain size of copper (Cu) may decrease. In addition, when the grain size of copper (Cu) decreases, the stress inside the second layer (Cu) decreases, and the surface roughness of the second layer (Cu) may decrease. That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F), the surface roughness of the second layer (Cu) may be smaller than the surface roughness of the second layer (Cu) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F).

[0106] A high surface roughness of the second layer (Cu) may mean that a large amount (or a large number) of copper hillocks (Cu Hillock) are formed on the surface of the second layer (Cu), or that the size of the copper hillocks (Cu Hillock) formed on the surface of the second layer (Cu) is large. Conversely, a low surface roughness of the second layer (Cu) may mean that a small amount (or a large number) of copper hillocks (Cu Hillock) are formed on the surface of the second layer (Cu), or that the size of the copper hillocks (Cu Hillock) formed on the surface of the second layer (Cu) is small.

[0107] Accordingly, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F), the surface roughness of the second layer (Cu) is smaller than the surface roughness of the second layer (Cu) when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F). Therefore, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F), the amount (or number) of copper hillocks (Cu Hillock) formed on the surface of the second layer (Cu) can be reduced compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F), and the size of the copper hillocks (Cu Hillock) formed on the surface of the second layer (Cu) can be reduced.

[0108] In addition, it can be confirmed that the surface roughness of the buffer layer when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) is smaller than the surface roughness of the buffer layer when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F).

[0109] As described above, if the second layer (Cu) has a large surface roughness, the surface roughness of the buffer layer formed on the second layer (Cu) may also have a large value. Conversely, if the second layer (Cu) has a small surface roughness, the surface roughness of the buffer layer formed on the second layer (Cu) may also have a small value.

[0110] Accordingly, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F), the surface roughness of the second layer (Cu) is reduced, and the surface roughness of the buffer layer placed on the second layer (Cu) can be reduced.

[0111] Additionally, it can be confirmed that the surface roughness of the buffer layer when the surface (100a) of the substrate (100) is cleaned with an HF solution is smaller than the surface roughness of the buffer layer when the surface (100a) of the substrate (100) is not cleaned with an HF solution. For example, when the surface (100a) of the substrate (100) is cleaned with an HF solution, the surface roughness of the second layer (Cu) is reduced, and thus the surface roughness of the buffer layer placed on the second layer (Cu) can be reduced.

[0112] Additionally, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, it can be confirmed that a hillock occurs weakly on the surface of the second layer (Cu) compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution.

[0113] FIG. 7 is a diagram showing the X-ray diffraction characteristics of sample #2 and sample #6. Specifically, in FIG. 7, 7a is a graph showing the X-ray diffraction characteristics of sample #2, and 7b is a graph showing the X-ray diffraction characteristics of sample #6. That is, 7a corresponds to the case where the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, and 7b corresponds to the case where the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution.

[0114] Referring to Table 1, Table 2, and FIG. 7, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, it can be seen that compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the peaks of the (002) plane and (101) plane increase and the peak of the (103) plane decrease in the X-ray diffraction spectrum of the first layer (Ti).

[0115] In one embodiment, in the X-ray diffraction spectrum of the first layer (Ti) by X-ray diffraction analysis, the peak of the (002) plane may be larger than the peak of the (103) plane. That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the orientation distribution of the film plane direction (002) of the first layer (Ti) may increase.

[0116] FIGS. 8 and FIGS. 9 are drawings showing the X-ray diffraction characteristics of sample #3 and sample #7, respectively. Specifically, FIGS. 8 is a graph showing the X-ray diffraction characteristics of sample #3, and FIGS. 9 is a graph showing the X-ray diffraction characteristics of sample #6. That is, FIGS. 8 corresponds to the case where the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, and FIGS. 9 corresponds to the case where the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution.

[0117] Referring to Table 1, Table 2, Fig. 8 and Fig. 9, it can be seen that when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the peak of the (220) plane in the X-ray diffraction spectrum of the second layer (Cu) is larger than the peak of the (111) plane and the peak of the (200) plane. Additionally, when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the ratio (P4 / P5) of the peak (P4) of the (200) plane and the peak (P5) of the (111) plane in the X-ray diffraction spectrum of the second layer (Cu) may be about 0.17, and the ratio (P4 / P5) of the peak (P6) of the (220) plane and the peak (P5) of the (111) plane may be about 1.13.

[0118] On the other hand, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, it can be confirmed that the peak of the (111) plane in the X-ray diffraction spectrum of the second layer (Cu) is larger than the peak of the (220) plane and the peak of the (200) plane. Additionally, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer (Cu) may be about 0.32, and the ratio (P3 / P2) of the peak (P3) of the (220) plane and the peak (P2) of the (111) plane may be about 0.79.

[0119] In one embodiment, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the peak of the (220) plane in the X-ray diffraction spectrum of the second layer (Cu) may be reduced compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. Additionally, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the peaks of the (200) plane and the (111) plane in the X-ray diffraction spectrum of the second layer (Cu) may be increased compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. At this time, the peak of plane (220), the peak of plane (200), and the peak of plane (111) may be relative to each other.

[0120] In one embodiment, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer (Cu) may be about 0.3 or higher. That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the peak (P1) of the (200) plane in the X-ray diffraction spectrum of the second layer (Cu) increases compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, so that the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane may be about 0.3 or more.

[0121] Additionally, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the ratio (P3 / P2) of the peak (P3) of the (220) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer (Cu) may be about 1 or less. That is, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the peak (P3) of the (220) plane in the X-ray diffraction spectrum of the second layer (Cu) may be reduced and the peak (P2) of the (111) plane may be increased compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, so the ratio (P3 / P2) of the peak (P3) of the (220) plane and the peak (P2) of the (111) plane may be about 1 or less.

[0122] In one embodiment, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the orientation distribution (220) of the second layer (Cu) may be reduced compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution. Specifically, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the orientation distribution (002) of the film plane direction of the first layer (Ti) may be increased compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, and as a result, the orientation distribution (220) of the second layer (Cu) on the first layer (Ti) may be reduced.

[0123] Generally, as the (220) orientation distribution within the copper (Cu) thin film increases, the compressive stress within the copper (Cu) thin film increases. In the case of the present invention, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the (220) orientation distribution of the second layer (Cu) is reduced compared to when the surface (100a) of the substrate (100) is not cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, so the compressive stress within the second layer (Cu) can be reduced. Therefore, since the compressive stress within the second layer (Cu) is reduced, the occurrence of hillocks on the surface of the second layer (Cu) can be reduced even when a buffer layer is deposited under high temperature conditions (e.g., a temperature of about 370°C or higher).

[0124] In one embodiment, a lower metal layer (105) may be formed on a substrate (100), and a buffer layer (110) may be formed on the lower metal layer (105). The lower metal layer (105) may include a first layer (105a) and a second layer (105b). The first layer (105a) of the lower metal layer (105) may be formed on the substrate (100), and the second layer (105b) may be formed on the first layer (105a). At this time, the substrate (100) may be provided with glass, the first layer (105a) may be provided with titanium (Ti), and the second layer (105b) may be provided with copper (Cu).

[0125] When the surface (100a) of a substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, at least a portion of the surface (100a) of the substrate (100) is etched, and the surface roughness of the substrate (100) may increase. Additionally, as the surface roughness of the substrate (100) increases, the surface roughness of the first layer (105a) formed on the substrate (100) may also increase compared to the case where it is not cleaned. However, if the surface roughness of the first layer (105a) decreases, the deposition stress of the second layer (105b) decreases, and the surface roughness of the second layer (105b) may decrease. Additionally, if the surface roughness of the second layer (105b) decreases, the surface roughness of the buffer layer (110) formed on the second layer (105b) may also decrease compared to the case where it is not cleaned. Accordingly, when the surface (100a) of the substrate (100) is cleaned with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution, the hillock formed on the surface of the second layer (105b) can be reduced.

[0126] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0127] 1: Display device 100: Substrate 105: Lower metal layer 105a: 1st layer 105b: Second layer 110: Buffer layer 110a: First buffer layer 110b: Second buffer layer

Claims

Claim 1 A method for manufacturing a display device comprising: a step of cleaning the surface of a substrate with an etchant containing fluorine (F) or a hydrofluoric acid (HF) solution; and a step of forming a lower metal layer on the surface of the substrate, the lower metal layer comprising a first layer and a second layer on the first layer; wherein the surface roughness of the substrate after cleaning is greater than the surface roughness of the substrate before cleaning. Claim 2 A method for manufacturing a display device according to claim 1, wherein the first layer is provided with a first material and the second layer is provided with a second material different from the first material. Claim 3 A method for manufacturing a display device according to paragraph 2, wherein the first material comprises titanium (Ti) and the second material comprises copper (Cu). Claim 4 A method for manufacturing a display device according to claim 1, further comprising the step of forming a buffer layer on the lower metal layer after the step of forming the lower metal layer. Claim 5 A method for manufacturing a display device according to claim 4, wherein the buffer layer comprises a first buffer layer and a second buffer layer stacked sequentially. Claim 6 A method for manufacturing a display device according to claim 5, wherein the first buffer layer and the second buffer layer are provided with different materials. Claim 7 In claim 6, the first buffer layer is silicon nitride (SiN X ) is provided, and the second buffer layer is silicon oxide (SiO X A method for manufacturing a display device equipped with ). Claim 8 A method for manufacturing a display device according to claim 1, wherein in the X-ray diffraction spectrum of the first layer by X-ray diffraction analysis, the peak of the (002) plane is larger than the peak of the (103) plane. Claim 9 A method for manufacturing a display device according to claim 1, wherein in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis, the peak of the (111) plane is larger than the peak of the (220) plane. Claim 10 A method for manufacturing a display device according to claim 1, wherein the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis is 0.3 or greater. Claim 11 A method for manufacturing a display device according to claim 4, further comprising: a step of forming a semiconductor layer on the buffer layer after the step of forming the buffer layer; and a step of forming a gate electrode on the semiconductor layer. Claim 12 A display device comprising: a substrate; and a lower metal layer disposed on the substrate and comprising a first layer and a second layer on the first layer, wherein in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis, the peak of the (111) plane is larger than the peak of the (220) plane. Claim 13 A display device according to claim 12, wherein the first layer is provided with a first material and the second layer is provided with a second material different from the first material. Claim 14 A display device according to claim 13, wherein the first material comprises titanium (Ti) and the second material comprises copper (Cu). Claim 15 A display device according to claim 12, further comprising a buffer layer disposed on the lower metal layer. Claim 16 In item 15, the above buffer layer comprises a first buffer layer and a second buffer layer stacked sequentially, a display device. Claim 17 A display device according to claim 16, wherein the first buffer layer and the second buffer layer are provided with different materials. Claim 18 In claim 17, the first buffer layer is silicon nitride (SiN X ) is provided, and the second buffer layer is silicon oxide (SiO X A display device equipped with ). Claim 19 A display device according to claim 12, wherein in the X-ray diffraction spectrum of the first layer by X-ray diffraction analysis, the peak of the (002) plane is larger than the peak of the (103) plane. Claim 20 A display device according to claim 12, wherein the ratio (P1 / P2) of the peak (P1) of the (200) plane and the peak (P2) of the (111) plane in the X-ray diffraction spectrum of the second layer by X-ray diffraction analysis is 0.3 or greater.

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