Display device for driving a plurality of pixels sharing one bump and one driving circuit using analog data voltage in a time-multiplexed manner

Abstract

A display device is disclosed. The display device comprises a substrate, a pixel array having a plurality of pixel groups each comprising four pixels arranged on the substrate, and a pixel driving circuit provided for each pixel group to drive four pixels, wherein the anode electrode of each of the four pixels is commonly connected to a bump electrically connected to the pixel driving circuit and receives a driving current from the pixel driving circuit, and the cathode electrode of each of the four pixels is electrically separated from each other and is respectively connected to different cathode lines formed on the substrate, and the pixel driving circuit includes a capacitor that stores an analog pixel data voltage applied from the outside and a driving transistor that generates an analog driving current based on the magnitude of the voltage stored in the capacitor, and each of the four pixels is time-division driven by receiving an analog driving current sequentially based on control by different cathode lines and a light emission control signal of the pixel driving circuit.

Description

Technology Field

[0001] The present disclosure relates to a display device, and more specifically, to a method in which a plurality of pixels share a single bump and a single pixel driving circuit, and drive a plurality of pixels in a time multiplexing manner based on an analog data voltage. Background Technology

[0003] Recently, various display devices are configured to have a plurality of pixels, and each of the plurality of pixels is configured to have a pixel driving circuit. In this regard, FIGS. 1a to 1d show a pixel driving circuit related to the present invention.

[0004] FIG. 1a is a perspective view illustrating the overall stacked structure of a typical monochrome micro-LEDoS (micro-LED on Silicon) panel according to the prior art. Referring to FIG. 1a, a conventional micro-LEDoS panel has a printed circuit board (PCB) for power supply and signal transmission placed at the bottom, a CMOS backplane driver IC manufactured by a silicon wafer process mounted on top of it, and a micro-LED array stacked at the top. The driver IC includes a pixel driver circuit array composed of numerous transistors integrated on a silicon substrate, and the micro-LED array (30) is electrically coupled to the driver IC.

[0005] FIG. 1b is a cross-sectional view and a partial perspective view to specifically explain the physical / electrical connection structure between the micro LED array and the CMOS backplane in the structure of FIG. 1a. Referring to FIG. 1b, the upper micro LED array includes a common cathode layer on the underside of a transparent sapphire substrate and an anode layer (P-type) on an individual pixel basis. At this time, the lower CMOS backplane and the upper LED pixels are electrically coupled.

[0006] Specifically, the anode electrode of each pixel is connected one-to-one with the corresponding pixel pad on the CMOS backplane via a bump. Additionally, the common cathode layer is connected as a single unit across the entire pixel area and is commonly connected to the ground (GND) voltage source of the CMOS backplane through bumps or vias on the outer edge of the array. That is, in the conventional structure, the cathode of every pixel is fixed to ground, so the on / off control of individual pixels must rely entirely on the current applied to the anode side.

[0007] '1 pixel : 1 bump' matching structures, such as those shown in Figs. 1a and 1b, entail critical physical constraints for implementing high resolution. For example, to implement an ultra-high resolution panel of 4,000 PPI, the pixel pitch must be reduced to approximately 6 µm or less. This implies that millions of bumps must also be formed and aligned with a pitch of 6 µm or less. However, with current packaging process technology, it is extremely difficult to form bumps with such fine pitches at a uniform height and to bond millions of contacts simultaneously. Electrical short circuits caused by the narrow spacing between bumps or bonding defects caused by height variations are the main causes that drastically reduce the overall yield of the panel.

[0008] FIG. 1c is a diagram showing the pixel array wiring structure of a micro-LEDoS driving IC according to the prior art. Referring to FIG. 1c, a plurality of pixel driving circuits are arranged in the active area in the form of a matrix of N columns x M rows. To drive this, horizontal scan lines (SCAN_1 ~ SCAN_M) and vertical data lines (DATA_1 ~ DATA_N) intersect each other to form a grid. A unit pixel placed at each intersection point is selected by a scan signal and receives a grayscale voltage or current through the data lines.

[0009] At this time, as the resolution increases, the density of wiring and components that must be placed within a limited pixel area increases exponentially. Since data lines, scan lines, and power lines (VDD, VSS) must all be wired within a fine pixel pitch, problems such as interference between wires and parasitic capacitance occur. In addition, since all transistors and capacitors required for driving, as well as bumps for connecting to the upper LED, must be placed at each pixel location, a shortage of design space occurs, which limits the implementation of high-performance pixel driving circuits.

[0010] FIG. 1d is a detailed circuit diagram of a single pixel driving circuit according to the prior art. Referring to FIG. 1d, the prior pixel driving circuit is a structure for driving a micro LED using an analog data voltage and includes a switching transistor with its gate connected to a scan line (SCAN Line), a storage capacitor and a driving transistor connected to an LED power line (VCC Line), and a light emission control transistor with its gate connected to an emission control line (Emission EN Line). When a scan signal is applied through the scan line, the switching transistor is turned on, and the analog data voltage (Vx) supplied through the data line is stored in the storage capacitor. Subsequently, the driving transistor generates a driving current corresponding to the stored data voltage, and when the light emission control transistor is turned on according to the light emission control signal, the driving current is supplied to the micro LED to emit light.

[0011] However, this basic conventional analog driving circuit structure has critical limitations in achieving uniform image quality in high-resolution Micro LED displays. Due to variations in the semiconductor manufacturing process, the threshold voltage (Vth) of the driving transistor varies for each individual pixel, and as panel sizes increase and resolutions rise, a voltage drop (IR Drop) flowing through the power line (VCC Line) inevitably occurs.

[0012] The conventional structure illustrated in Fig. 1d lacks a mechanism to internally compensate for such threshold voltage (Vth) deviations or fluctuations in power supply voltage, so as a result, even when the same data voltage is applied, the driving current flowing through the actual LED varies depending on the pixel position, leading to a problem of severe luminance non-uniformity (Mura) that causes stains on the screen. The problem to be solved

[0014] The present disclosure is devised to solve the aforementioned conventional problems, and the objective of the present disclosure is to provide a pixel structure and a driving method that can substantially increase pixel density while maintaining the size and spacing of bumps at the level of existing processes.

[0015] In addition, the present disclosure aims to provide a pixel structure and a driving method that can expand the resolution fourfold through time-division driving using separated cathode lines, while four adjacent pixels share one driving circuit and one bump.

[0016] The problems that the technical concept of the present disclosure aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0018] A display device according to one or more embodiments of the present disclosure comprises: a substrate; a pixel array disposed on the substrate and having a plurality of pixel groups, each including four pixels, arranged therein; and a pixel driving circuit provided for each pixel group to drive the four pixels, wherein the anode electrode of each of the four pixels is commonly connected to a bump electrically connected to the pixel driving circuit and receives a driving current from the pixel driving circuit, and the cathode electrode of each of the four pixels is electrically separated from one another and is respectively connected to different cathode lines formed on the substrate, and the pixel driving circuit comprises a capacitor that stores an analog pixel data voltage applied from the outside and a driving transistor that generates an analog driving current based on the magnitude of the voltage stored in the capacitor, and each of the four pixels is time-division driven by sequentially receiving the analog driving current based on control by the different cathode lines and a light emission control signal of the pixel driving circuit.

[0019] The pixel driving circuit may include, corresponding to each of the four pixels, a first transistor connected between a common data line transmitting the analog pixel data voltage and a first node; the capacitor connected between the first node and a second node; the driving transistor connected between a power supply voltage terminal and a light emission control node, the gate of which is controlled by the voltage of the second node; a second transistor connected between the second node and a ground terminal; a third transistor connected between the second node and the light emission control node; and a fifth transistor connected between the light emission control node and the one bump.

[0020] The first transistor is sequentially turned on by a scan control signal that is activated at different timings, and can sequentially transmit the pixel data voltage for each of the four pixels, which is applied in time division through the common data line, to the corresponding first node.

[0021] The second transistor can be turned on simultaneously by a common initialization control signal to collectively initialize the voltage of the second node corresponding to each of the four pixels.

[0022] The third transistor can be simultaneously turned on by a common compensation control signal to diode-connect the driving transistors corresponding to each of the four pixels.

[0023] The fifth transistor is sequentially turned on by the light emission control signal (EMI) that is activated at different timings, so that the analog driving current generated in the driving transistor can pass through the one bump.

[0024] During the period when the third transistor is turned on, the voltage obtained by subtracting the threshold voltage of the driving transistor from the power supply voltage applied to the power supply voltage terminal can be sampled and stored in the second node corresponding to each of the four pixels.

[0025] The pixel array is arranged in a plurality of horizontal lines, and a common initialization control signal and a common compensation control signal are simultaneously applied to pixel groups included in the plurality of horizontal lines to perform compensation driving.

[0026] After the above compensation drive is completed, a scan control signal corresponding to each of the plurality of horizontal lines is sequentially activated on a horizontal line basis so that the pixel data voltage can be applied.

[0027] When the pixel data voltage is transmitted to the corresponding first node, the voltage of the second node may fluctuate in tandem based on the voltage fluctuation amount of the first node due to the coupling phenomenon of the capacitor.

[0028] During the period in which the light emission control signal corresponding to a specific pixel among the four pixels is activated to perform a light emission operation, the scan control signal corresponding to a non-light emission pixel among the four pixels is activated so that a data writing operation through the first transistor can be performed in overlap.

[0029] The display device further includes a cathode control circuit comprising a plurality of switching elements each connected to the different cathode lines, and the cathode control circuit can operate in synchronization with the light emission control signal.

[0030] The cathode control circuit above can block crosstalk by turning on only the switching element connected to the cathode line corresponding to the specific pixel when the light emission control signal for a specific pixel among the four pixels is activated, and connecting it to ground (GND), while keeping the cathode lines corresponding to the remaining non-light emission pixels in a floating state.

[0031] The four pixels included in the pixel group are arranged in a matrix of two rows and two columns, and the one bump is located at the bottom center of the four pixels arranged in the two rows and two columns and can be physically connected to the anode electrodes of the four pixels.

[0032] The magnitude of the analog driving current applied to a specific pixel among the four pixels above can be determined independently of the threshold voltage deviation of the driving transistor by the diode connection operation through the third transistor and the coupling operation by the capacitor. Effects of the invention

[0034] The present disclosure can overcome the physical limitations of bump pitch and improve the process yield of ultra-high resolution panels. Through a structure in which four pixels share a single bump and pixel driving circuit, the actual pixel density (PPI) can be increased fourfold while maintaining the bump size and spacing of existing processes.

[0035] Furthermore, the present disclosure can internally compensate for the luminance non-uniformity (Mura) problem, which is a critical limitation of analog voltage driving methods. By forming a diode connection within the driving circuit to compensate for the threshold voltage (Vth) of the driving transistor, the analog driving current finally supplied to the micro LED is equal to the threshold voltage (Vth) of the driving transistor. th ) deviation or power supply voltage (V DD Unaffected by the drop of ), only the input pixel data voltage (V DATA It can be determined proportionally only by ). This allows for the provision of very uniform and precise image quality across the entire panel.

[0036] Furthermore, the present disclosure can minimize noise interference and secure sufficient data writing time even in a high-speed time-division driving environment. During a long time (interval) in which a specific pixel performs a light-emitting operation, the capacitors (C) of the remaining pixels that do not emit light. ST By applying a pipeline driving method that sequentially writes analog data in advance to the data line, electromagnetic interference (EMI) caused by switching noise of the data line to the current of the light-emitting pixel is fundamentally isolated in the time domain.

[0037] In addition, the present disclosure can improve circuit integration efficiency within a limited silicon backplane area. By designing multiple (e.g., four) pixels to share bumps for light emission as well as to share common control signals, such as a node initialization signal (DIS) and a threshold voltage (Vth) compensation signal (PRE), in groups, wiring complexity can be minimized and an effective light-emitting area secured despite the introduction of analog compensation circuits.

[0038] Meanwhile, the effects obtainable from the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present disclosure belongs from the description below. Brief explanation of the drawing

[0040] FIGS. 1a to 1d are drawings for explaining a conventional micro-LED panel structure. FIG. 2 is a drawing for explaining the pixel arrangement structure and cathode wiring of an LED array chip according to one embodiment of the present disclosure. FIG. 3 is a detailed circuit diagram of a backplane IC including a 2x2 pixel driving circuit according to one embodiment of the present disclosure. FIG. 4 is a cross-sectional structure of a display device in which four pixels share one bump according to one embodiment of the present disclosure. FIG. 5 is a top view of the stacked structure of FIG. 4, illustrating an example of a matrix arrangement of 2x2 unit pixel groups and a cathode wiring structure for each pixel. FIG. 6 is a timing diagram for driving four pixels in a time-division manner according to one embodiment of the present disclosure. FIG. 7 is a diagram illustrating the detailed application timing of a scan control signal (EN) for each pixel line in a pixel array environment extended into a plurality of horizontal lines according to one embodiment of the present disclosure. Specific details for implementing the invention

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of the present invention, based on the principle that the inventor can appropriately define the concept of the terms to best describe his invention. Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical spirit of the present invention; therefore, it should be understood that various equivalents and modifications capable of replacing them may exist at the time of filing this application.

[0042] FIG. 2 is a drawing for explaining the pixel arrangement structure and cathode wiring of an LED array chip according to one embodiment of the present disclosure.

[0043] Referring to FIG. 2, the LED array chip includes a plurality of micro LED pixels arranged in a matrix form. In this embodiment, four adjacent subpixels (A, B, C, D) are arranged in a 2x2 (2x2) configuration to form a unit pixel group (e.g., 1-1, 1-2, ..., 4-4), and this unit pixel group has a repeating pattern in the row and column directions.

[0044] At this time, the anode electrodes of each of the four pixels (A, B, C, D) included within a single unit pixel group are physically and electrically connected in common to a single bump formed on the lower backplane IC, as shown as a circle in the center of the drawing. That is, by forming a structure in which four pixels share one bump and one set of pixel driving circuits, the bump pitch can be designed with leeway even when the pixel pitch is extremely fine, thereby overcoming physical limitations in the process.

[0045] On the other hand, unlike the conventional structure where all pixels are connected to a common cathode, the cathode electrodes of each pixel are wired by separating them into four groups according to the order and type of light emission of the pixels. Specifically, the cathodes of all A pixels on the LED array chip are commonly connected to the first cathode line (Cathode_A), the cathodes of B pixels are commonly connected to the second cathode line (Cathode_B), the cathodes of C pixels are commonly connected to the third cathode line (Cathode_C), and the cathodes of D pixels are commonly connected to the fourth cathode line (Cathode_D).

[0046] Multiple cathode lines (Cathode_A ~ Cathode_D) that are electrically separated from each other are routed to a lower backplane IC and are each connected to multiple switching elements (e.g., NMOS transistors) that constitute a cathode control circuit.

[0047] The switching elements of the above-mentioned backplane IC are turned on or turned off by sequentially applied light emission control signals (EMI_A, EMI_B, EMI_C, EMI_D). For example, when the light emission control signal EMI_A is applied at a high level, only the switching element connected to the first cathode line (Cathode_A) is turned on, and the cathode potential of the A pixels is connected to ground (GND). Accordingly, the analog driving current applied through the common bump flows only through the A pixels, forming a closed circuit and emitting light.

[0048] On the other hand, the remaining light emission control signals (EMI_B, EMI_C, EMI_D) that are not selected at this time maintain a low level, so the cathodes of the remaining B, C, and D pixels become floating, thereby fundamentally blocking the flow of current. This separate wiring and control structure physically prevents unintended light emission (crosstalk) between adjacent pixels that may occur as four pixels share an anode, and enables precise time-division driving.

[0049] Meanwhile, according to an advanced embodiment of the present disclosure, in a highly integrated 2x2 matrix layout in which the four pixels share a single common bump, parasitic capacitance (C) due to physical asymmetry P ) Non-uniformity issues may occur. Due to minute differences in the distance at which the four subpixels (A, B, C, D) are positioned from the center of the common bump or in wiring routing, the parasitic capacitance (C) corresponding to the denominator of the above [Equation 1] P The value of ) has a deviation between 4 pixels, which can cause a decrease in the precision of the analog driving current.

[0050] To overcome the inherent limitations of such shared bump structure, the second node (V) on the uppermost layer of the pixel driving circuit on the backplane ICABS ~ V DBS A dummy pattern shielding layer may be additionally placed between the common bump and the above.

[0051] A constant DC voltage (e.g., power supply voltage V) is applied to the shielding layer above. DD Or ground voltage) is applied, and can geometrically wrap around the second node of each of the four sub-driving circuits in a symmetrical manner. This blocks electromagnetic interference from adjacent wiring, while simultaneously blocking the parasitic capacitance (C) of the second node corresponding to each of the four pixels. P By equalizing the ) values, the luminance deviation between 4 pixels is fundamentally eliminated.

[0052] In addition, a data scaling function can be applied to electrically compensate for optical alignment asymmetry between the 2x2 shared pixel structure and the micro lens array stacked on top. When four pixels share a single lens center, a slight directional deviation in light extraction efficiency may occur depending on the distance between the optical axis and the pixel light-emitting point.

[0053] To compensate for this, the timing controller of the display device can pre-process the input image data based on the spatial position index of each of the four pixels (A, B, C, D). For example, a weight is multiplied to the data of the outer pixels where viewing angle brightness degradation is expected, and the final analog data voltage (V) applied to the common data line is DATA By upscaling the size of ), optical asymmetry can be compensated for software-wise at the analog driving circuit stage.

[0054] Meanwhile, a display device according to one embodiment of the present disclosure may further include a driving control unit (or display driving IC, DDI) for generally controlling the pixel array and cathode control circuit described above and applying various driving voltages and signals. The driving control unit may be configured to include a timing controller, a data driver, a scan driver, and a power controller.

[0055] The timing controller receives image data and control signals (e.g., vertical synchronization signal, horizontal synchronization signal, clock signal, etc.) input from an external host system, and based on this, generates timing control signals to control the operation timing of the data driver and the scan driver. The image data preprocessing and data scaling functions to compensate for the optical asymmetry described above can also be performed through the image quality compensation logic within the timing controller.

[0056] The data driver receives digital image data processed by the timing controller, converts it into an analog pixel data voltage ($V_{DATA}$), and outputs it to the plurality of common data lines. In particular, since four pixels share a single data line by time-dividing, the data driver according to the present disclosure is configured to time-multiplex the analog data voltages for four pixels (A, B, C, D) at high speed within one horizontal period (1H) under the control of the timing controller and output them sequentially.

[0057] A scan driver (or gate driver) generates various switching control signals to turn on or turn off a plurality of transistors in the pixel driving circuit. Specifically, the scan driver generates a scan control signal (EN) that controls the first transistor, a common initialization control signal (DIS) that controls the second transistor, a common compensation control signal (PRE) that controls the third transistor, and a light emission control signal (EMI) that synchronizes and controls the fifth transistor and the cathode control circuit, and supplies them to the corresponding wires of the pixel array.

[0058] The power controller (or PMIC) generates and supplies various direct current (DC) voltages required for driving the display device. The power controller supplies a high-potential power supply voltage (V) to the driving transistor (TR4). DD ), a reference voltage (V1) and a ground voltage (GND) are generated to initialize the first node.

[0059] Furthermore, the power control unit performs the role of generating the reverse bias voltage ($V_{REVERSE}$) applied to the cathode line of a non-emissive pixel and supplying it to the cathode control circuit to block parasitic coupling, which is a unique feature of the present disclosure. Through the integrated timing control and voltage application of the driving control unit organically combined in this way, flawless high-resolution analog time-division driving can be realized even under the constraint that four pixels share a single bump.

[0060] FIG. 3 is a detailed circuit diagram inside a backplane IC including a 2x2 pixel driving circuit according to one embodiment of the present disclosure.

[0061] Referring to FIG. 3, the pixel driving circuit includes four sub-driving circuits configured in parallel to drive one common bump (anode) and four micro LEDs (corresponding to pixels A, B, C, and D, respectively). For convenience of explanation, the sub-driving circuit for pixel A is described in detail, and the circuits for the remaining pixels B, C, and D may also have the same structure. In this embodiment, each transistor is shown as a PMOS (P-channel Metal Oxide Semiconductor), but depending on the embodiment, it may be implemented as an NMOS.

[0062] The 2x2 pixel driver circuit on the backplane IC is largely composed of the following five main blocks based on the driving signal and its role. The pixel driver circuit includes a Data block that processes pixel data voltage input as an analog value, a DIS and second transistor (TR2) block for node initialization, a PRE and third transistor (TR3) block for threshold voltage variation compensation (Vth Variation free), an EN_X and first transistor (TR1) block for data write switching, and an EMI_X and fifth transistor (TR5) block for selecting the light-emitting LED. Taking Pixel A as an example, it includes five transistors (A_TR1 ~ A_TR5) and one storage capacitor (C ST The specific connection relationships and operations of ) are as follows.

[0063] Analog pixel data voltage is input to the common data line (DATA). For example, assuming the LED's grayscale representation has 256 steps, the voltage values ​​applied to the data line range from V0 to V 255 It is divided and input up to, where V0 represents a non-luminous state where no current flows through the LED.

[0064] The first transistor (A_TR1) has a common data line (DATA) and a first node (V AXIt is connected between the circuits and performs the role of turning on / off (ON / OFF) the switch operation in accordance with the scan control signal (EN_X, EN_A in this example) so that the voltage of the data line is written to the pixel. The four sub-drive circuits share a common data line, but receive data by time-dividing the scan control signals (EN_A ~ EN_D) with different timings by applying them to the gates of each first transistor.

[0065] Storage capacitor (C ST ) is the first node (V AX ) and the second node (V ABS It is connected between ). This capacitor not only maintains the data voltage applied to the first node, but also the threshold voltage (V) of the driving transistor to be described later. th It plays a key role in inducing voltage coupling between the first node and the second node during the compensation process.

[0066] The second transistor (A_TR2) is the second node (V ABS It is an initialization transistor connected between ) and ground (GND). The second transistor (A_TR2) is turned on by the initialization control signal (DIS), and the second node (i.e., V), which is the gate node of the driving transistor (A_TR4). ABS It is a transistor for initializing the voltage of the node. At this time, all pixels (A, B, C, D) in the 2x2 pixel driving circuit share the DIS signal in common.

[0067] The third transistor (A_TR3) is the second node (V ABSIt is a compensation transistor connected between the drain electrode of the 4th transistor (A_TR4) and the 3rd transistor (A_TR3). The 3rd transistor (A_TR3) is turned on by the compensation control signal (PRE) and performs the role of a signal transmission and transistor to neutralize the inherent threshold voltage deviation (Vth Variation free) of the driving transistor (A_TR4). As with the preceding DIS signal, all pixels (A, B, C, D) share the PRE signal in common.

[0068] As such, the initialization control signal (DIS) and the compensation control signal (PRE) are shared among four sub-driving circuits, allowing multiple pixels to perform initialization and threshold voltage compensation operations collectively (simultaneously), which provides a structural advantage of reducing wiring complexity within a limited pixel pitch.

[0069] The fourth transistor (A_TR4) is a driving transistor connected between the power supply voltage terminal (VLED) and the fifth transistor (A_TR5), and generates a driving current proportional to the magnitude of the analog voltage stored in the second node. The subsequent fifth transistor (A_TR5) is a light emission control transistor connected between the drain electrode of the fourth transistor (A_TR4) and the common bump (Anode). The fifth transistor (A_TR5) is turned on by a light emission control signal (EMI_X, EMI_A in this example), and consequently serves to control the flow of a driving current to a specific LED selected by EMI_X.

[0070] Meanwhile, the cathode control circuit located at the bottom of the backplane IC also operates by sharing the light emission control signals (EMI_A ~ EMI_D) (it shares them as EMIB_A (in the form of an opposite signal) for the NMOS TR. For example, when the EMI_A signal is activated, the fifth transistor (A_TR5) of the sub-drive circuit is turned on, opening the anode-side current path, and at the same time, the corresponding switching element in the cathode control circuit is turned on, connecting the cathode line of pixel A to ground (GND). That is, by simultaneously completing the paths of both the anode and cathode of a specific pixel with a single light emission control signal (EMI), independent light emission control becomes possible even though four pixels share a single bump.

[0071] FIG. 4 is a cross-sectional structure of a display device (micro-LEDoS) in which four pixels share one bump according to one embodiment of the present disclosure.

[0072] Referring to FIG. 4, the display device according to the present embodiment has a stacked structure in which a lower CMOS backplane IC and an upper micro LED array are combined via a bump layer. The upper micro LED array includes a transparent sapphire substrate that emits light, a cathode layer and an anode electrode (Anode A to Anode D) disposed below it.

[0073] Looking at the pixel light-emitting region depicted on the right side of the drawing, four anode electrodes (Anode A, Anode B, Anode C, Anode D) corresponding to four adjacent subpixels (A, B, C, D) are placed on a single common bump at the bottom and are physically and electrically connected. This common bump is connected to a pixel driving circuit (specifically, the fifth transistor in FIG. 3) provided inside a CMOS backplane IC, and serves as a common path to transmit an analog driving current with a threshold voltage deviation compensated to the four pixels.

[0074] Meanwhile, looking at the cathode connection area shown on the left side of the drawing, the cathode layers of the four subpixels (A, B, C, D) are not conducted as a single unit across the entire array, but are patterned into physically and electrically separated cathode electrodes (Cathode A, Cathode B, Cathode C, Cathode D). These separated cathode electrodes are individually routed to the underlying CMOS backplane IC through cathode bumps.

[0075] Inside the CMOS backplane IC, cathode switching transistors are provided to selectively connect each routed cathode electrode to ground (GND). Light emission control signals (EMI_A, EMI_B, EMI_C, EMI_D) are each independently applied to the gate electrodes of these transistors.

[0076] Looking at the light emission mechanism indicated by the blue arrow, for example, when the light emission control signal EMI_A is activated and the cathode switching transistor is turned on, the cathode (Cathode A) of pixel A is connected to ground. At this time, the analog driving current supplied through the common bump forms a closed circuit that flows only through the anode (Anode A) of pixel A to the cathode (Cathode A). Accordingly, only pixel A selectively emits light with a brightness proportional to the analog data voltage and emits light onto the sapphire substrate.

[0077] On the other hand, the cathodes of the remaining B, C, and D pixels to which the light emission control signal is not applied remain in a floating state because the switching transistor at the bottom is in an off state. Therefore, even if voltage is applied to the common bump, the current path is blocked and light is not emitted.

[0078] In conclusion, as shown in the cross-sectional structure disclosed in FIG. 4, the present disclosure overcomes the physical limitations of the ultra-high resolution packaging process by enlarging the bump on the anode side, while simultaneously enabling precise time-division control of the analog driving current without crosstalk between pixels through thorough electrical isolation on the cathode side.

[0079] FIG. 5 is a top view of the stacked structure of FIG. 4, illustrating an example of a matrix arrangement of 2x2 unit pixel groups and a cathode wiring structure for each pixel.

[0080] Referring to FIG. 5, a plurality of unit pixel groups (e.g., 1-1, 1-2, 2-1, etc.) are arranged in a two-dimensional matrix form. For time-division driving, each unit pixel group is densely arranged with four types of subpixels (Anode A, Anode B, Anode C, Anode D) in a 2x2 (2 rows and 2 columns) configuration. In the figure, the yellow circular area located in the background of each unit pixel group represents the 'single common bump' described in FIG. 4. That is, the anode electrodes of the four subpixels (A, B, C, D) are located within the single common bump area at the bottom, forming a highly integrated physical connection structure that shares a single analog pixel driving circuit.

[0081] The linear patterns traversing the unit pixel groups represent electrically isolated cathode lines connecting the cathode electrodes of each pixel. Specifically, the first cathode line (Cathode A), indicated in orange in both horizontal and vertical directions, selectively connects only the 'A pixels (Anode A)' located within each unit pixel group. Similarly, the second cathode line (Cathode B), indicated in blue in a vertical direction, connects the 'B pixels (Anode B)'; the third cathode line (Cathode C), indicated in purple in a horizontal direction, connects the 'C pixels (Anode C)'; and the fourth cathode line (Cathode D), indicated in green in a vertical direction, connects the 'D pixels (Anode D)'.

[0082] This cathode isolation wiring structure is connected to the cathode control circuit of the backplane IC. As previously described, when a light emission control signal (e.g., EMI_A) is applied, only the first cathode line (Cathode A) is connected to ground (GND), and all A pixels in the array become ready for light emission (forming a closed circuit). At this time, the cathode lines of the remaining B, C, and D pixels are floating so that no current flows, thereby blocking unintended crosstalk between adjacent pixels.

[0083] In particular, the wiring structure according to the present embodiment has a regular and symmetric routing pattern to minimize wiring complexity that may occur as four pixels share a bump. This drastically simplifies the complex individual cross-wiring required in conventional matrix driving methods. Furthermore, cathode selection by the light emission control signal (EMI) and analog data voltage (V DATA By organically combining anode driving current control by ), an optimal hardware layout is provided that enables precise analog time-division driving without degradation of resolution even in a micro pixel pitch environment.

[0084] FIG. 6 is a timing diagram for driving four pixels in a time-division manner according to one embodiment of the present disclosure. Referring to FIG. 6, one frame period is a first to seventh interval ( <1> ~ <7> It is subdivided into multiple driving sections including ). Below, the detailed operating principle of the pixel driving circuit for each section is explained together with the circuit disclosed in FIG. 3.

[0085] <1> The section refers to an initialization section that initializes the node voltage of each sub-drive circuit. In this section, for all four pixels (A, B, C, D), the first transistor (TR1) and the second transistor (TR2) are turned ON, while the third transistor (TR3) and the fifth transistor (TR5) remain OFF. The common data line (V DATA ) is the threshold voltage (V) of the driving transistor (TR4). th A reference voltage (V1) at a level similar to ) (e.g., where the difference is below a threshold) is applied. Scan control signals (EN_1A ~ EN_1D) are activated, causing the first transistors (TR1) of the four sub-drive circuits to all turn on, and accordingly, the first node (V AX ~ V DX The voltage of ) is set to the reference voltage (V1). At the same time, the initialization control signal (DIS) is activated, and the second transistor (TR2) is turned on, thereby turning on the second node (V) corresponding to the gate electrode of the driving transistor (TR4). ABS ~ V DBS The voltage of ) is initialized to ground voltage, a voltage close to 0, or a voltage below a threshold.

[0086] <2> The section is threshold voltage sampling and compensation (V) that nullifies threshold voltage deviation thThis refers to the Variation Free section. In this section, for all four pixels, the first transistor (TR1) and the third transistor (TR3) are in the ON state, while the second transistor (TR2) and the fifth transistor (TR5) are in the OFF state. That is, the initialization control signal (DIS) is deactivated, causing the second transistor (TR2) to turn off, and the compensation control signal (PRE) is activated, causing the third transistor (TR3) to turn on. Due to the turning on of the third transistor (TR3), the gate and drain of the driving transistor (TR4) are connected, resulting in a diode connection state. As a result, the second node (V ABS ~ V DBS ) has power supply voltage V DD The threshold voltage (V) of the driving transistor (TR4) at ) th The voltage reduced by (TR4)) is sampled and stored. That is, connected via a diode connection, the voltage of the second node is V DD - V th (TR4) has a value, and the voltage of the first node maintains the reference voltage (V1) value of the previous section.

[0087] <3> The section refers to the first pixel data write section. In this section, only the first transistor (TR1) of pixel A becomes in a switching (ON / OFF) state for data writing, while the first transistors (TR1) of the remaining pixels B, C, and D remain in the OFF state. Additionally, the second, third, and fifth transistors (TR2, TR3, TR5) of all pixels are in the OFF state. The compensation control signal (PRE) is disabled, and only the scan control signal (EN_1A) for pixel A remains enabled. The common data line (V DATA When the analog pixel data voltage for pixel A is sequentially applied through ), the first node (V) of pixel A AX ) The voltage is the data voltage (V DATAIt changes to ). At this time, the first node (V) of the remaining B, C, and D pixels. BX , V CX , V DX ) maintains the reference voltage (V1). In pixel A, the storage capacitor (C ST A coupling phenomenon occurs due to ), so that the voltage fluctuation amount of the first node is the second node (V ABS It is reflected in the 2nd node voltage (V) of pixel A. Consequently, it is reflected in the 2nd node voltage of pixel A. ABS ) can be expressed as shown in [Mathematical Formula 1] below.

[0088] [Mathematical Formula 1]

[0089]

[0090] Here, C P represents the parasitic capacitance of the second node.

[0091] <4> The section refers to the second pixel data writing and first pixel light emission section. In this section, only the first transistor (TR1) of Pixel B becomes fluctuating for data writing, and Pixel A begins light emission, so that only the fifth transistor (TR5) of Pixel A becomes ON. That is, the scan control signal (EN1A) of Pixel A is deactivated, and the first node (V) of Pixel A AX )Is <3> Maintain the interval value, and the scan control signal (EN_1B) of pixel B is activated so that the first node (V) of pixel B is activated. BX ) is V DATA It varies (the first node of pixels C and D maintains the V1 value). At the same time, the light emission control signal (EMI_A) is activated, and the light emission control transistor (TR5) of pixel A is turned on. The driving transistor (TR4) of pixel A is at the gate-source voltage (V GS Driving current (I) proportional to ) ALED ) is supplied to a micro LED, and its size can be expressed as [Equation 2] below.

[0092] [Mathematical Formula 2]

[0093]

[0094] At this time, Therefore, V in the aforementioned mathematical formula 1 ABS Substituting the value into Equation 2, the driving current I ALED It can be expressed as [Mathematical Formula 3] below.

[0095] [Mathematical Formula 3]

[0096]

[0097] As shown in [Equation 3], the driving current finally supplied to the pixel is the power supply voltage (V DD ) or the threshold voltage (V) of the driving transistor th It becomes independent of ) variation, and only the input data voltage (V DATA It is determined solely by ).

[0098] Meanwhile, in a structure where the four pixels share a single common bump, the potential of the common bump can rise rapidly when a specific pixel emits light. At this time, if the cathode of the non-emissive pixel is simply left in a floating state, there is a risk that the voltage spike of the common bump will be coupled to the cathode line of the non-emissive pixel through the junction capacitance of the micro LED device, thereby causing a micro leakage current.

[0099] To electrically block this, the cathode control circuit may include an adaptive reverse bias controller that actively applies a reverse bias voltage (V_REVERSE), which is a specific level of positive (+) voltage, to the cathode lines corresponding to the remaining non-emitting pixels during the period when a specific pixel among the four pixels emits light.

[0100] In particular, the adaptive reverse bias controller described above has a data voltage (V) written to a specific pixel currently emitting light. DATAThe reverse bias voltage (V) is proportional to the grayscale level of ) REVERSE The size of ) is dynamically varied. When it is predicted that the potential of the common bump will rise significantly due to the high brightness of the emitting pixel, the level of the reverse bias voltage applied to the non-emitting pixel is also increased, thereby blocking micro-crosstalk caused by parasitic coupling under any high-brightness emission conditions.

[0101] Meanwhile, when the first transistor (TR1) is turned off during analog time-division driving, the switching kick-back voltage and charge injection phenomena can distort the voltage of the first node (V_AX) and cause an error in the final driving current. In particular, in a structure where four sub-driving circuits are densely packed, there is a risk that switching noise from adjacent pixels may be transferred to one another.

[0102] To prevent this, the pixel driving circuit of the present disclosure may further include a feed-through compensation technique that controls the falling edge slew rate of the scan control signal (EN) or provides a dummy compensation capacitor that receives a phase inversion signal between the scan control signal line and the first node to self-cancele the kickback voltage.

[0103] Additionally, the display device of the present disclosure is the above <1> It is possible to perform a dynamic reference voltage scaling function that dynamically adjusts the reference voltage (V1) applied to the common data line in the interval (initialization interval) according to environmental variables, rather than using it as a fixed value.

[0104] Specifically, based on panel temperature detected by a temperature sensor embedded in the panel or aging information resulting from the accumulation of display driving time, the level of the reference voltage (V1) is varied and applied in frame units or block units. Through this, even if the threshold voltage dispersion of the driving transistor (TR4) shifts drastically depending on temperature and time, the second node (V ABS Auto-calibration can be performed so that the voltage sampled in ) is always located within the optimal saturation region of the driving transistor.

[0105] <5> The interval is a section where the analog data writing operation for Pixel C and the light emission operation of Pixel B are performed in temporal overlap. In this interval, the scan control signal (EN1C) of Pixel C is activated, causing only the first transistor (TR1) of Pixel C to change between the turn-on and turn-off states, and the common data line (V DATA Through ), the analog data voltage of pixel C is the first node (V CX It is stored in ). At the same time, the light emission control signal (EMI_B) of pixel B is activated, and only the fifth transistor (TR5) of pixel B becomes ON. At this time, the driving current (I) flowing through the driving transistor (TR4) of pixel B BLED ) Likewise, following the same principle as the preceding [Mathematical Equation 3], the power supply voltage (V DD ) Drop and threshold voltage (V th Since it is determined regardless of the deviation, the B pixel emits light with an accurate brightness proportional only to the data voltage.

[0106] <6> The section is a section where the data writing operation for pixel D and the light emission operation for pixel C are performed in overlap. Due to the scan control signal (EN_1D) of pixel D, the first transistor (TR1) of pixel D becomes in a fluctuating state, and the voltage of the common data line becomes the first node (V DX It is stored in ) and at the same time, through coupling, the second node (VDBS The voltage of ) is varied. In parallel, as the light emission control signal (EMI_C) of the C pixel is activated, the fifth transistor (TR5) of the C pixel is turned on. Consequently, an analog driving current (I) in which power supply voltage fluctuations and threshold voltage deviations are internally compensated is applied to the micro-LED of the C pixel. CLED ) is supplied to perform a light-emitting operation.

[0107] <7> This section is the timeline where, after data writing for all four pixels (A, B, C, D) is completed, only the light emission operation of pixel D is performed independently. In this section, the scan control signals (EN_1A ~ EN_1D) included in the four sub-drive circuits are all deactivated, so all first transistors (TR1) remain in the OFF state. Only the light emission control signal (EMI_D) of pixel D is activated to turn on the fifth transistor (TR5) of pixel D, and the preceding <6> Compensated driving current (I) based on the data voltage entered in the section DLED ) is applied to D pixel.

[0108] The aforementioned <5> inside <7> During the interval, the first node (V) of the remaining unselected pixels that do not write current data or perform a light emission operation AX ~ V DX ) and the second node (V ABS ~ V DBS ) stores the voltage value written in the previous section in the storage capacitor (C ST It is maintained stably without leakage through ). That is, even in an environment where the fifth transistor (TR5) of the light-emitting pixel is switched, the data preservation of the non-light-emitting pixel is not compromised.

[0109] By applying a pipeline drive that overlaps the data writing section of the light-emitting section and the non-light-emitting pixel in this way, sufficient data writing time can be secured even though four pixels share a single data line in time division, and the interference phenomenon caused by switching noise of the data line to the light-emitting pixel can be temporally isolated.

[0110] FIG. 7 is a diagram illustrating the detailed application timing of a scan control signal (EN) for each pixel line in a pixel array environment extended with a plurality of horizontal lines (Line 1 to Line N) according to one embodiment of the present disclosure. This figure is explained using the case where the activation level is a low level based on the PMOS transistor as an example.

[0111] Referring to Fig. 7, <1> Section (initialization section) and <2> In the interval (threshold voltage sampling and compensation interval), scan control signals (EN_1A ~ EN_NA, EN_1B ~ EN_NB, etc.) for all horizontal lines (Line 1 ~ Line N) are activated simultaneously (see Initial area in Fig. 7).

[0112] That is, while the initialization control signal (DIS) and the compensation control signal (PRE) are applied, all pixels of the entire display panel (or a specific block unit) simultaneously initialize the first node and the threshold voltage (V) of the driving transistor th Global compensation driving is performed by sampling ). This global compensation method drastically reduces the massive time delay required when compensating the threshold voltage line by line in high-resolution panels, thereby providing a powerful advantage that can maximize the data write time and effective light emission time essential for time-division driving.

[0113] After global rewards were completed <3> In the section, sequential data writing to A pixels is performed. Pulses are sequentially activated from the A pixel scan control signal of the first horizontal line (EN_1A) to the A pixel scan control signal of the Nth horizontal line (EN_NA) (refer to the red 'Write' area in Fig. 7). Whenever the scan control signal of each line is activated, the A pixel data of the corresponding line applied to the common data line is transferred to the capacitor (C) of each sub-drive circuit. ST It is entered sequentially into ).

[0114] Next <4> In this section, sequential data writing to B pixels proceeds in the same manner. Starting with the B pixel scan control signal (EN_1B) of the first horizontal line, data writing pulses for B pixels are sequentially applied (refer to the blue 'Write' area in Fig. 7). As previously described in detail in Fig. 6, this <4> While data from B pixels is being written line by line in the section, A pixels, for which data writing is already complete, perform light emission operations simultaneously across the entire screen by the cathode separation control and light emission control signal (EMI_A).

[0115] In conclusion, the timing control structure of the present embodiment secures a time budget through simultaneous compensation of all pixels even under the physical constraint that four pixels share a bump and circuit, and implements high-speed analog driving through line-by-line sequential writing and pipelined light emission, thereby V th It provides a high-resolution time-division display with deviations eliminated.

[0116] Meanwhile, since the display device of the present disclosure performs high-speed time-division light emission by having four pixels share a single bump within a fine pitch, a thermal hotspot problem may occur in which heat is concentrated in a specific area within a 2x2 unit pixel group.

[0117] To structurally and timing-wise disperse such heat concentration phenomena, the present disclosure controls a thermal-dispersive light emission sequence. That is, instead of emitting four pixels within a first subframe in a physically adjacent order (e.g., A -> B -> C -> D), the order of application of the scan control signal (EN) and the light emission control signal (EMI) can be rearranged non-sequentially so that pixels in physically diagonal positions emit alternately (e.g., A -> D -> B -> C).

[0118] Furthermore, the order of the thermally dispersed light emission sequence is rotated for every frame or specific time period. For example, by performing dynamic scheduling to emit in the order 'A -> D -> B -> C' in Frame 1 and in the order 'D -> A -> C -> B' in Frame 2, the thermal gradient within the unit pixel group is flattened and the lifespan of the micro LED device is extended.

[0119] In addition, an important global compensation interval in analog time-division driving (the above <2> The time duration of the interval is also not fixed but can be adaptively allocated according to the panel condition. In the initial factory state, global compensation is performed with only a minimum time budget to maximize data write time; however, if transistor degradation occurs as panel driving time accumulates, the width of the global compensation interval is gradually increased to maintain the accuracy of threshold voltage (Vth) sampling until the end.

[0120] Finally, a fault self-isolation circuit is provided to defend against the 'short failure propagation' phenomenon, which is a weakness of a structure where four pixels share a single anode bump. If an anode-cathode short failure occurs in the micro LED device of a specific pixel (e.g., pixel A) among the four pixels due to a manufacturing process defect, the driving current applied to the bump leaks entirely to pixel A, which has zero resistance, and may result in a 'group black' failure in which even normal pixels B, C, and D cannot emit light.

[0121] To solve this, the cathode control circuit includes a current sensing block that monitors the amount of current flowing through each cathode line in real time. When the current sensing block detects an overcurrent exceeding a threshold at the light emission timing of Pixel A and determines it to be a short circuit defect, it locks the switching element connected to the first cathode line of the corresponding pixel group to a permanently open state.

[0122] Thus, the current path of the defective pixel A is hardware-isolated, and the remaining normal pixels (B, C, D) that share one bump can continue time-division light emission intact.

[0123] Furthermore, to visually conceal the dark spot caused by the isolated A pixel, the compensation logic of the backplane IC temporarily up-boosts the analog data voltage (VDATA) applied to adjacent normal pixels (B, C, D) at the timing when the A pixel is supposed to emit light. In other words, by the normal pixels emitting brightness to compensate for the lost light amount of the defective pixel, near-defective ultra-high resolution image quality can be realized even in a shared bump structure.

[0124] Although the present invention has been described above in relation to specific embodiments, this is merely illustrative and the present invention is not limited thereto. A person skilled in the art to which the present invention pertains may change or modify the described embodiments without departing from the scope of the present invention, and various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims set forth below.

Claims

Claim 1 A display device comprising: a substrate; and a pixel array disposed on the substrate, wherein a plurality of pixel groups, each comprising four pixels, are arranged thereon. and includes a pixel driving circuit provided for each pixel group to drive the four pixels, wherein the anode electrode of each of the four pixels is commonly connected to a single bump electrically connected to the pixel driving circuit to receive a driving current from the pixel driving circuit, and the cathode electrode of each of the four pixels is electrically separated from each other and is respectively connected to different cathode lines formed on the substrate, and the pixel driving circuit includes a capacitor that stores an analog pixel data voltage applied from the outside, and a driving transistor that generates an analog driving current based on the magnitude of the voltage stored in the capacitor, and each of the four pixels is time-division driven by sequentially receiving the analog driving current based on control by the different cathode lines and a light emission control signal (EMI) of the pixel driving circuit, and the pixel driving circuit corresponds to each of the four pixels and includes: a first transistor connected between a common data line transmitting the analog pixel data voltage and a first node; the capacitor connected between the first node and a second node; and between the power supply voltage terminal and the light emission control node A display device comprising: a driving transistor connected and whose gate is controlled by the voltage of the second node; a second transistor connected between the second node and a ground terminal; a third transistor connected between the second node and the light emission control node; and a fifth transistor connected between the light emission control node and the one bump. Claim 2 delete Claim 3 A display device according to claim 1, wherein the first transistor is sequentially turned on by a scan control signal activated at different timings and sequentially transmits the pixel data voltage for each of the four pixels, which is applied in time division through the common data line, to the corresponding first node. Claim 4 A display device according to claim 1, wherein the second transistor is simultaneously turned on by a common initialization control signal to collectively initialize the voltage of the second node corresponding to each of the four pixels. Claim 5 A display device according to claim 1, wherein the third transistor is simultaneously turned on by a common compensation control signal to diode-connect the driving transistors corresponding to each of the four pixels. Claim 6 A display device according to claim 1, wherein the fifth transistor is sequentially turned on by the light emission control signal (EMI) activated at different timings to pass the analog driving current generated in the driving transistor through the one bump. Claim 7 A display device according to claim 1, wherein during the period in which the third transistor is turned on, a voltage obtained by subtracting the threshold voltage of the driving transistor from the power supply voltage applied to the power supply voltage terminal is sampled and stored in the second node corresponding to each of the four pixels. Claim 8 A display device according to claim 1, wherein the pixel array is arranged in a plurality of horizontal lines, and a common initialization control signal and a common compensation control signal are simultaneously applied to pixel groups included in the plurality of horizontal lines to perform compensation driving. Claim 9 A display device according to claim 8, wherein, after the compensation drive is completed, a scan control signal corresponding to each of the plurality of horizontal lines is sequentially activated on a horizontal line basis so that the pixel data voltage is applied. Claim 10 A display device according to claim 9, wherein when the pixel data voltage is transmitted to the corresponding first node, the voltage of the second node fluctuates in tandem based on the voltage fluctuation amount of the first node due to the coupling phenomenon of the capacitor. Claim 11 A display device according to claim 1, wherein during the interval in which the light emission control signal corresponding to a specific pixel among the four pixels is activated to perform a light emission operation, a scan control signal corresponding to a non-light emission pixel among the four pixels is activated to perform a superposition of a data writing operation through the first transistor. Claim 12 In claim 1, the display device further comprises a cathode control circuit including a plurality of switching elements each connected to the different cathode lines, and the cathode control circuit operates in synchronization with the light emission control signal. Claim 13 A display device according to claim 12, wherein the cathode control circuit, when the light emission control signal for a specific pixel among the four pixels is activated, turns on only the switching element connected to the cathode line corresponding to the specific pixel and connects it to ground (GND), and maintains the cathode lines corresponding to the remaining non-light emission pixels in a floating state to block crosstalk. Claim 14 A display device according to claim 1, wherein four pixels included in the pixel group are arranged in a matrix of two rows and two columns, and one bump is located at the bottom center of the four pixels arranged in the matrix of two rows and two columns and is physically in common connection with the anode electrodes of the four pixels. Claim 15 A display device according to claim 1, wherein the magnitude of the analog driving current applied to a specific pixel among the four pixels is determined independently of the threshold voltage deviation of the driving transistor by the diode connection operation through the third transistor and the coupling operation by the capacitor.

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