Thin film transistor and display apparatus comprising the same

Abstract

One embodiment of the present invention provides a thin-film transistor comprising a first wiring pattern and a second wiring pattern spaced apart from each other, an active layer overlapping the first wiring pattern and the second wiring pattern, a gate insulating film on the active layer, and a gate electrode on the gate insulating film, wherein the active layer comprises a channel portion, a first portion overlapping and contacting the first wiring pattern, and a second portion overlapping and contacting the second wiring pattern, wherein the channel portion is disposed between the first wiring pattern and the second wiring pattern and overlaps with the gate electrode, and the gate insulating film covers the channel portion and exposes one side of the first wiring pattern and one side of the second wiring pattern. Additionally, one embodiment of the present invention provides a display device comprising the thin-film transistor.

Description

Technology Field

[0001] The present invention relates to a thin-film transistor and a display device including a thin-film transistor. Background Technology

[0002] Transistors are widely used in the field of electronic devices as switching devices or driving devices. In particular, since thin-film transistors can be manufactured on glass or plastic substrates, they are widely used as switching devices in display devices such as Liquid Crystal Displays (LCDs) or Organic Light Emitting Devices (OLEDs).

[0003] Thin film transistors can be classified based on the material constituting the active layer into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which oxide semiconductor is used as the active layer.

[0004] Since amorphous silicon can be deposited to form an active layer in a short time, amorphous silicon thin-film transistors (a-Si TFTs) have the advantages of short manufacturing process times and low production costs. On the other hand, amorphous silicon thin-film transistors have the disadvantage of limited use in applications such as active matrix organic light-emitting diodes (AMOLEDs) due to their low mobility resulting in poor current driving capability and the occurrence of threshold voltage fluctuations.

[0005] Polycrystalline silicon thin-film transistors (poly-Si TFTs) are fabricated by crystallizing amorphous silicon after it has been deposited. Polycrystalline silicon TFTs possess advantages such as high electron mobility, excellent stability, thin thickness, the ability to achieve high resolution, and high power efficiency. Examples of such polycrystalline silicon TFTs include Low Temperature Poly Silicon (LTPS) thin-film transistors or polysilicon thin-film transistors. However, because the manufacturing process of polycrystalline silicon TFTs requires a crystallization step for amorphous silicon, the number of process steps increases, leading to higher manufacturing costs, and crystallization must occur at high process temperatures. Consequently, there are difficulties in applying polycrystalline silicon TFTs to large-area devices. Furthermore, due to their polycrystalline characteristics, it is challenging to ensure the uniformity of polycrystalline silicon TFTs.

[0006] Oxide semiconductor thin-film transistors (TFTs), which possess high mobility and exhibit significant resistance changes depending on oxygen content, have the advantage of easily achieving desired physical properties. Additionally, manufacturing costs are low because the oxide forming the active layer can be deposited at relatively low temperatures during the fabrication process. Due to the inherent properties of oxides, oxide semiconductors are transparent, making them advantageous for realizing transparent displays. However, oxide semiconductor TFTs have the disadvantage of lower stability and electron mobility compared to polycrystalline silicon thin-film transistors.

[0007] When oxide semiconductor thin-film transistors are manufactured using a coplanar structure, also known as a top-gate type, conductive regions must be formed to facilitate electrical connections between devices. During the formation of these conductive regions, the oxide semiconductor layer may degrade, which can consequently reduce the reliability of the oxide semiconductor thin-film transistor. Therefore, it is necessary to develop structures or processes that prevent damage to the oxide semiconductor layer during the manufacturing process. The problem to be solved

[0008] One embodiment of the present invention aims to provide a thin-film transistor comprising a first wiring pattern and a second wiring pattern that overlap with an active layer.

[0009] One embodiment of the present invention aims to provide a thin-film transistor having a structure that eliminates the need for a separate conductor process for the active layer, since electrical connections are formed by a first wiring pattern and a second wiring pattern.

[0010] We aim to provide a thin-film transistor in which the gate insulating film covers the active layer and the active layer can be efficiently protected without a separate conductorization process.

[0011] The present invention aims to provide a thin-film transistor in which contact with the source electrode and the drain electrode is made through the sides of the first wiring pattern and the second wiring pattern that overlap with the active layer, thereby enabling the active layer to be efficiently protected.

[0012] Another embodiment of the present invention aims to provide a display device capable of having excellent stability and reliability by including a thin-film transistor as described above. means of solving the problem

[0013] One embodiment of the present invention for achieving the aforementioned technical problem provides a thin-film transistor comprising a first wiring pattern and a second wiring pattern spaced apart from each other, an active layer overlapping the first wiring pattern and the second wiring pattern, a gate insulating film on the active layer and a gate electrode on the gate insulating film, wherein the active layer comprises a channel portion, a first portion overlapping and contacting the first wiring pattern and a second portion overlapping and contacting the second wiring pattern, wherein the channel portion is disposed between the first wiring pattern and the second wiring pattern and overlaps with the gate electrode, and the gate insulating film covers the channel portion and exposes one side of the first wiring pattern and one side of the second wiring pattern.

[0014] The first wiring pattern and the second wiring pattern may be disposed between the substrate and the active layer.

[0015] The upper surface of the first wiring pattern may contact the lower surface of the first part of the active layer, and the upper surface of the second wiring pattern may contact the lower surface of the second part of the active layer.

[0016] The first wiring pattern and the second wiring pattern may each include a reducing conductive material.

[0017] The above reducing conductive material may include at least one selected from aluminum (Al), titanium (Ti), molybdenum (Mo), calcium (Ca), and barium (Ba).

[0018] The above channel portion, the first portion, and the second portion may be formed as a single unit.

[0019] The thin-film transistor may further include at least one of a source electrode in contact with the side of the first wiring pattern and a drain electrode spaced apart from the source electrode and in contact with the side of the second wiring pattern.

[0020] The source electrode and the drain electrode can be made of the same material as the gate electrode and by the same process.

[0021] The entire portion of the active layer positioned between the first wiring pattern and the second wiring pattern can overlap with the gate electrode.

[0022] The active layer may include a non-overlapping portion that does not overlap with any one of the first wiring pattern, the second wiring pattern, and the gate electrode.

[0023] The above non-overlapping portion can be made conductive.

[0024] The gate insulating film can cover the entire upper surface of the active layer.

[0025] The above active layer may include an oxide semiconductor material.

[0026] The active layer may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0027] The above active layer may further include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0028] Another embodiment of the present invention provides a display device comprising the above-described thin-film transistor. Effects of the invention

[0029] In a thin-film transistor according to one embodiment of the present invention, since electrical connections are made by a first wiring pattern and a second wiring pattern that overlap with the active layer, a separate conductorization process for the active layer is not required. As a result, damage to the active layer can be prevented or minimized during the manufacturing process of the thin-film transistor.

[0030] In addition, according to one embodiment of the present invention, the gate insulating film completely covers the active layer, and contact with the source electrode and the drain electrode can be made through the sides of the first wiring pattern and the second wiring pattern that overlap with the active layer. As a result, the active layer can be efficiently protected, the thin-film transistor can have excellent electrical characteristics, and excellent stability and reliability can be achieved.

[0031] A display device according to one embodiment of the present invention including such a thin-film transistor can have excellent reliability.

[0032] In addition to the effects mentioned above, other features and advantages of the present invention are described below, or will be clearly understood by those skilled in the art from such description and explanation. Brief explanation of the drawing

[0033] FIG. 1a is a plan view of a thin-film transistor according to one embodiment of the present invention. Figure 1b is a cross-sectional view taken along I-I' of Figure 1a. FIG. 2a is a plan view of a thin-film transistor according to another embodiment of the present invention. Figure 2b is a cross-sectional view taken along II-II' of Figure 2a. FIG. 3 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention. FIG. 4 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention. FIG. 5 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention. FIG. 6 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention. FIGS. 7a to 7g are schematic diagrams illustrating a method for manufacturing a thin-film transistor according to one embodiment of the present invention. FIG. 8 is a schematic diagram of a display device according to another embodiment of the present invention. Figure 9 is a circuit diagram for any pixel of Figure 8. Figure 10 is a plan view of the pixel of Figure 9. Figure 11 is a cross-sectional view taken along III-III' of Figure 10. FIG. 12 is a circuit diagram of a pixel of a display device according to another embodiment of the present invention. Fig. 13 is a plan view of the pixel of Fig. 12. Fig. 14 is a cross-sectional view taken along IV-IV' of Fig. 13. FIG. 15 is a circuit diagram of a pixel of a display device according to another embodiment of the present invention. Specific details for implementing the invention

[0034] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of the present invention is complete and to inform those skilled in the art of the scope of the invention. The present invention is defined only by the scope of the claims.

[0035] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, identical components may be referred to by the same reference numerals. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0036] Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless the expression 'only' is used. Where a component is expressed in the singular, it includes the plural unless specifically stated otherwise.

[0037] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0038] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless expressions such as 'immediately' or 'directly' are used.

[0039] Spatially relative terms such as "below" or "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one element or component and another, as illustrated in the drawings. Spatially relative terms should be understood as terms that include different orientations of the element during use or operation, in addition to the orientations illustrated in the drawings. For example, if an element illustrated in the drawings is flipped, the element described as "below" or "beneath" of another element may be placed "above" of that other element. Therefore, the exemplary term "below" may include both the lower and upper directions. Similarly, the exemplary terms "above" or "upper" may include both the upper and lower directions.

[0040] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using expressions such as 'after', 'following', 'next', or 'before', it may include cases where the sequence is not continuous unless expressions such as 'immediately' or 'directly' are used.

[0041] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0042] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item and the third item” may mean not only the first item, the second item or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item and the third item.

[0043] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0044] Hereinafter, a thin-film transistor according to an embodiment of the present invention and a display device including the same will be described in detail with reference to the attached drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings.

[0045] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished, but the source electrode and the drain electrode may be interchangeable. Specifically, in one embodiment, the electrode named as the source electrode may be used as the drain electrode, and the electrode named as the drain electrode may be used as the source electrode. Furthermore, the source electrode according to one embodiment may become the drain electrode in another embodiment, and the drain electrode according to one embodiment may become the source electrode in another embodiment.

[0046] In the embodiments of the present invention, for convenience of explanation, the source region and the source electrode are distinguished and the drain region and the drain electrode are distinguished, but the embodiments of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Additionally, the source region may be the drain electrode, and the drain region may be the source electrode.

[0047] Hereinafter, a thin-film transistor (100) according to one embodiment of the present invention will be described in detail with reference to FIGS. 1a and 1b.

[0048] FIG. 1a is a plan view of a thin-film transistor (100) according to one embodiment of the present invention, and FIG. 1b is a cross-sectional view taken along I-I' of FIG. 1a.

[0049] A thin-film transistor (100) according to one embodiment of the present invention comprises a first wiring pattern (125) and a second wiring pattern (126) spaced apart from each other, an active layer (130) overlapping the first wiring pattern (125) and the second wiring pattern (126), a gate insulating film (140) on the active layer (130), and a gate electrode (150) on the gate insulating film (140).

[0050] Referring to FIG. 1b, a thin-film transistor (100) can be placed on a substrate (110). Anything that supports the thin-film transistor (100) can be referred to as a substrate (110) without limitation.

[0051] Glass or plastic may be used as the substrate (110). As the plastic, a transparent plastic having flexible properties, for example, polyimide may be used. When polyimide is used as the substrate (110), considering that a high-temperature deposition process is performed on the substrate (110), a heat-resistant polyimide capable of withstanding high temperatures may be used.

[0052] A light-blocking layer (111) may be disposed on a substrate (110). The light-blocking layer (111) overlaps with at least the channel portion (130n) of the active layer (130). The light-blocking layer (111) blocks light incident from the outside, thereby protecting the channel portion (130n).

[0053] The light-blocking layer (111) may be made of a material having light-blocking properties. The light-blocking layer (111) may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe).

[0054] The light blocking layer (111) may be electrically connected to either the source electrode (161) or the drain electrode (162). The light blocking layer (111) may be omitted.

[0055] A buffer layer (120) may be disposed on the light-blocking layer (111). The buffer layer (120) may be made of an insulating material. For example, the buffer layer (120) may include at least one of insulating materials such as silicon oxide, silicon nitride, and metal oxide. The buffer layer (120) may have a single-layer structure or a multi-layer structure.

[0056] The buffer layer (120) can protect the active layer (130) by blocking air and moisture. Additionally, the buffer layer (120) can make the upper surface of the substrate (110) on which the light-blocking layer (111) is placed uniform.

[0057] A first wiring pattern (125) and a second wiring pattern (126) may be placed on the buffer layer (120). A configuration in which the first wiring pattern (125) is placed on the left and the second wiring pattern (126) is placed on the right is illustrated in FIGS. 1a and 1b. However, one embodiment of the present invention is not limited thereto, and the positions of the first wiring pattern (125) and the second wiring pattern (126) may be interchanged.

[0058] The first wiring pattern (125) and the second wiring pattern (126) are conductive. The first wiring pattern (125) and the second wiring pattern (126) can each serve as wiring. By the first wiring pattern (125) and the second wiring pattern (126) serving as wiring, the active layer (130) can be electrically connected to other components. More specifically, the first wiring pattern (125) and the second wiring pattern (126) are connected to the channel portion (130n) of the active layer (130), so that the channel portion (130n) can be electrically connected to other components of the thin-film transistor (100) or other components of the display device.

[0059] Since the first wiring pattern (125) and the second wiring pattern (126) can serve as conductive wiring, selective conductivity of the active layer (130) may not be required. Even without selective conductivity of the active layer (130), the active layer (130) can be electrically connected to other components by the first wiring pattern (125) and the second wiring pattern (126).

[0060] According to one embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) may have reducing properties. When the first wiring pattern (125) and the second wiring pattern (126) have reducing properties, the active layer (130) in contact with the first wiring pattern (125) and the second wiring pattern (126) is selectively reduced, so that a conductive portion can be formed on the active layer (130) without a separate conductive process.

[0061] According to one embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) may each include a reducing conductive material. According to one embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) may include, for example, at least one selected from aluminum (Al), titanium (Ti), molybdenum (Mo), calcium (Ca), and barium (Ba).

[0062] The active layer (130) is disposed on the first wiring pattern (125) and the second wiring pattern (126). According to one embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) may be disposed between the substrate (110) and the active layer (130).

[0063] According to one embodiment of the present invention, the active layer (130) may be formed by a semiconductor material. The active layer (130) may include, for example, an oxide semiconductor.

[0064] The oxide semiconductor material may include, for example, at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the active layer (130) may be made of other oxide semiconductor materials known in the art.

[0065] The active layer (130) may include a channel portion (130n), a first portion (131), and a second portion (132). The channel portion (130n), the first portion (131), and the second portion (132) may be formed integrally. More specifically, one active layer (130) including the channel portion (130n), the first portion (131), and the second portion (132) may be formed as a single pattern.

[0066] The channel portion (130n) is positioned between the first wiring pattern (125) and the second wiring pattern (126) and overlaps with the gate electrode (150). The channel portion (130n) does not overlap with the first wiring pattern (125) and the second wiring pattern (126).

[0067] The channel portion (130n) can come into contact with the first wiring pattern (125) and the second wiring pattern (126). According to one embodiment of the present invention, a signal can be transmitted and current or charge can be moved through the first wiring pattern (125), the channel portion (130n), and the second wiring pattern (126).

[0068] According to one embodiment of the present invention, the portion of the active layer (130) that overlaps with the first wiring pattern (125) is defined as the first portion (131), and the portion that overlaps with the second wiring pattern (126) can be defined as the second portion (132).

[0069] The upper surface of the first wiring pattern (125) may come into contact with the lower surface of the first part (131) of the active layer (130). The upper surface of the second wiring pattern (126) may come into contact with the lower surface of the second part (132) of the active layer (130). Here, the upper surface is defined as a surface facing the opposite side of the substrate (110), and the lower surface is defined as a surface facing the substrate (110).

[0070] The first part (131) and the second part (132) of the active layer (130) may or may not overlap with the gate electrode (150).

[0071] Referring to FIGS. 1a and 1, the first portion (131) of the active layer (130) and the first wiring pattern (125) may partially overlap with the gate electrode (150) in an area adjacent to the channel portion (130n). As a result, when a gate voltage is applied to the gate electrode (150), the channel portion (130n) is turned ON, and a stable electrical connection can be established between the channel portion (130n) and the first wiring pattern (125).

[0072] Additionally, referring to FIGS. 1a and 1, the second portion (132) of the active layer (130) and the second wiring pattern (126) may overlap with the gate electrode (150) in an area adjacent to the channel portion (130n). As a result, when a gate voltage is applied to the gate electrode (150), the channel portion (130n) becomes ON, and a stable electrical connection can be established between the channel portion (130n) and the second wiring pattern (126).

[0073] The first part (131) and the second part (132) may each include a region that does not overlap with the gate electrode (150). In the region that does not overlap with the gate electrode (150), the first part (131) and the second part (132) may each come into contact with the source electrode (161) and the drain electrode (162).

[0074] The first part (131) and the second part (132) are made of a semiconductor material and may be conductive. According to one embodiment of the present invention, when the first wiring pattern (125) and the second wiring pattern (126) are made of a reducing conductive material, an oxygen vacancy may occur in the first part (131) in contact with the first wiring pattern (125) and the second part (132) in contact with the second wiring pattern (126), and the first part (131) and the second part (132) and their surroundings may be conductive.

[0075] When the first part (131) and the second part (132) are each conductive, even if the first part (131) and the second part (132) do not overlap with the gate electrode (150), an electrical connection can be made between the channel part (130n) and the first wiring pattern (125) and the second wiring pattern (126) through the conductive part. For example, a stable electrical connection can be made between the first wiring pattern (125), the conductive part, and the channel part (130n). Additionally, a stable electrical connection can also be made between the second wiring pattern (126), the conductive part, and the channel part (130n).

[0076] According to one embodiment of the present invention, the first part (131) and the first wiring pattern (125) may be the source region, and the second part (132) and the second wiring pattern (126) may be the drain region. According to one embodiment of the present invention, the first part (131) and the first wiring pattern (125) may be referred to as the source electrode, and the second part (132) and the second wiring pattern (126) may be referred to as the drain electrode.

[0077] However, one embodiment of the present invention is not limited thereto, and the first part (131) and the first wiring pattern (125) may be the drain region, and the second part (132) and the second wiring pattern (126) may be the source region. Additionally, the first part (131) and the first wiring pattern (125) may be referred to as the drain electrode, and the second part (132) and the second wiring pattern (126) may be referred to as the source electrode.

[0078] According to one embodiment of the present invention, an active layer (130) is formed after the first wiring pattern (125) and the second wiring pattern (126) are formed, and an electrical connection is made through the sides of the first wiring pattern (125) and the second wiring pattern (126).

[0079] If a first wiring pattern (125) and a second wiring pattern (126) are formed on the active layer (130), a problem may occur in which the active layer (130) is damaged during the process of forming the first wiring pattern (125) and the second wiring pattern (126). On the other hand, according to the present invention, since the active layer (130) is formed after the first wiring pattern (125) and the second wiring pattern (126) are formed, a problem in which the active layer (130) is damaged during the process of forming the first wiring pattern (125) and the second wiring pattern (126) does not occur.

[0080] Additionally, when the first wiring pattern (125) and the second wiring pattern (126) include a reducing conductive material, an oxygen vacancy may occur in the first portion (131) in contact with the first wiring pattern (125) and the second portion (132) in contact with the second wiring pattern (126), thereby making the first (131) and the second portion (132) conductive. Accordingly, according to one embodiment of the present invention, the active layer (130) can be selectively made conductive without a separate conductive process such as plasma treatment, ion doping, or ultraviolet treatment. As a result, the reliability of the electrical connection can be ensured.

[0081] A gate insulating film (140) is disposed on the active layer (130). The gate insulating film (140) may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating film (140) may have a single-layer structure or a multilayer structure. The gate insulating film (140) protects the channel portion (130n).

[0082] Referring to FIG. 1b, the gate insulating film (140) can be configured to cover the channel portion (130n) and expose one side of the first wiring pattern (125) and one side of the second wiring pattern (126).

[0083] For example, the gate insulating film (140) may cover the upper surface of the channel portion (130n), the first portion (131), and the second portion (132), and may not cover either side of the first wiring pattern (125) and either side of the second wiring pattern (126). A source electrode (161) and a drain electrode (162) may each come into contact with one side of the first wiring pattern (125) and one side of the second wiring pattern (126) exposed from the gate insulating film (140).

[0084] The gate insulating film (140) can be patterned in various forms to cover the upper surface of the channel portion (130n) and expose one side of the first wiring pattern (125) and one side of the second wiring pattern (126). Additionally, according to one embodiment of the present invention, the gate insulating film (140) can cover the upper surface of the channel portion (130n) and be disposed on at least a portion of the first portion (131) of the active layer (130) adjacent to the channel portion (130n) and at least a portion of the second portion (132) of the active layer (130) adjacent to the channel portion (130n).

[0085] According to one embodiment of the present invention, the gate insulating film (140) can cover the entire upper surface of the active layer (130). As a result, the active layer (130) and the channel portion (130n) can be effectively protected by the gate insulating film (140). In particular, during the etching process for the gate electrode (150), metal materials included in the active layer (130) can be re-deposited on the sidewall of the gate insulating film (140), thereby preventing an electrical short circuit between the gate electrode (150) and the active layer (130).

[0086] The gate electrode (150) is placed on the gate insulating film (140). The gate electrode (150) overlaps with the channel portion (130n) of the active layer (130).

[0087] The gate electrode (150) may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode (150) may have a multilayer structure comprising at least two conductive films having different physical properties.

[0088] According to one embodiment of the present invention, the entire portion of the active layer (130) positioned between the first wiring pattern (125) and the second wiring pattern (126) may overlap with the gate electrode (130). Accordingly, the entire portion of the active layer (130) between the first wiring pattern (125) and the second wiring pattern (126) may become a channel portion (130n).

[0089] Referring to FIGS. 1a and 1b, a portion of the first wiring pattern (125) and a portion of the second wiring pattern (126) may overlap with the gate electrode (150). Additionally, a first portion (131) and a second portion (132) of the active layer (130) may also overlap with the gate electrode (150). Even if a portion of the first wiring pattern (125) and a portion of the second wiring pattern (126) overlap with the gate electrode (150), the first wiring pattern (125) and the second wiring pattern (126) are not connected to each other, so when the channel portion (130n) is not turned ON, an insulating state between the first wiring pattern (125) and the second wiring pattern (126) can be maintained.

[0090] Additionally, since a portion of the first wiring pattern (125) and a portion of the second wiring pattern (126) overlap with the gate electrode (150), when a gate voltage is applied to the gate electrode (150) and the channel portion (130n) is turned ON, a stable electrical connection is made between the channel portion (130n) and the first wiring pattern (125) and between the channel portion (130n) and the second wiring pattern (126), and as a result, the first wiring pattern (125) and the second wiring pattern (126) can be electrically connected.

[0091] Referring to FIG. 1a, an interlayer insulating film (145) is disposed on the gate electrode (150) and the gate insulating film (140). The interlayer insulating film (145) is an insulating layer made of an insulating material. The interlayer insulating film (145) may be made of an organic material, may be made of an inorganic material, or may be made of a laminate of an organic layer and an inorganic layer.

[0092] A source electrode (161) and a drain electrode (162) can be spaced apart from each other on an interlayer insulating film (145).

[0093] The source electrode (161) and the drain electrode (162) may each include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The source electrode (161) and the drain electrode (162) may each be made of a single layer made of a metal or an alloy of a metal, or may be made of two or more layers.

[0094] The source electrode (161) is connected to the active layer (130) through a contact hole (CH2) formed in the interlayer insulating film (145). Specifically, the source electrode (161) can be electrically connected to a first portion (131) and a first wiring pattern (125) of the active layer (130) through the contact hole (CH2). Additionally, the source electrode (161) can be connected to the light blocking layer (111) through a contact hole (CH1).

[0095] The drain electrode (162) is spaced apart from the source electrode (161) and connected to the active layer (130) through a contact hole (CH3) formed in the interlayer insulating film (145). Specifically, the drain electrode (162) can be electrically connected to a second part (132) and a second wiring pattern (126) of the active layer (130) through the contact hole (CH3).

[0096] According to one embodiment of the present invention, the source electrode (161) may be in contact with the side of the first wiring pattern (125). The drain electrode (162) may be spaced apart from the source electrode (161) and may be in contact with the side of the second wiring pattern (126).

[0097] According to one embodiment of the present invention, the first portion (131) and the second portion (132) of the active layer (130) are made of a semiconductor material, and the first wiring pattern (125) and the second wiring pattern (126) may be made of a conductive material, for example, a metal. Accordingly, the first wiring pattern (125) and the second wiring pattern (126) may have better electrical conductivity than the first portion (131) and the second portion (132) of the active layer (130).

[0098] The first wiring pattern (125) is formed in a structure that is connected to the channel portion (130n) and simultaneously connected to the source electrode (161), so that it can serve as a connecting wiring that connects the source electrode (161) and the channel portion (130n). Additionally, the second wiring pattern (126) is formed in a structure that is connected to the channel portion (130n) and simultaneously connected to the drain electrode (162), so that it can serve as a connecting wiring that connects the drain electrode (162) and the channel portion (130n).

[0099] In this way, according to one embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) serve as connecting wires with conductivity superior to that of a semiconductor material. As a result, the current characteristics between the channel portion (130n) and the source electrode (161) or between the channel portion (130n) and the drain electrode (162) can be improved.

[0100] In addition, according to one embodiment of the present invention, the gate insulating film (140) covers the entire upper surface of the active layer (130) to protect the active layer (130) and the channel portion (130n), and the sides of the first wiring pattern (125) and the second wiring pattern (126) are exposed so that the first wiring pattern (125) and the second wiring pattern (126) can serve as connecting wires.

[0101] Accordingly, according to one embodiment of the present invention, the active layer (130) and the channel portion (130n) are efficiently protected, and at the same time, the current characteristics between the channel portion (130n) and the source electrode (161) or between the channel portion (130n) and the drain electrode (162) can be improved.

[0102] According to one embodiment of the present invention, either the source electrode (161) and the drain electrode (162) in the thin-film transistor (100) may be omitted. In this case, the assembly of the first part (131) of the active layer (130) and the first connecting wire (125) or the assembly of the second part (132) of the active layer (130) and the second connecting wire (126) may serve as the source electrode (161) or the drain electrode (162).

[0103] Referring to FIG. 1b, a protective layer (170) may be disposed on the source electrode (161) and the drain electrode (162). The protective layer (170) is made of an insulating material and can protect the thin-film transistor (100).

[0104] FIG. 2a is a plan view of a thin-film transistor (200) according to another embodiment of the present invention, and FIG. 2b is a cross-sectional view taken along II-II' of FIG. 2a. Hereinafter, to avoid duplication, descriptions of components already described are omitted.

[0105] Referring to FIGS. 2a and 2b, the active layer (130) may include a non-overlapping portion (135) that does not overlap with any of the first wiring pattern (125), the second wiring pattern (126), and the gate electrode (150).

[0106] Referring to FIG. 2a, the distance between the first wiring pattern (125) and the second wiring pattern (126) is greater than the width (w) of the gate electrode (150). As a result, in the active layer (130), a portion of the part disposed between the first wiring pattern (125) and the second wiring pattern (126) may not overlap with the gate electrode (150). Thus, the part of the active layer (130) that does not overlap with any of the first wiring pattern (125), the second wiring pattern (126), and the gate electrode (150) is called the non-overlapping portion (135).

[0107] The non-overlapping portion (135) is not a channel portion (130n) and can be described as part of an active layer (130) positioned between the channel portion (130n) and the first wiring pattern (125) and between the channel portion (130n) and the second wiring pattern (126). If the non-overlapping portion (135) is not conductive, an electrical connection between the channel portion (130n) and the first wiring pattern (125) or between the channel portion (130n) and the second wiring pattern (126) may not be formed.

[0108] According to another embodiment of the present invention, the non-overlapping portion (135) may be conductive. More specifically, according to another embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) are made of a reducing conductive material, so that an oxygen vacancy occurs in the first portion (131) in contact with the first wiring pattern (125), the second portion (132) in contact with the second wiring pattern (126), and the non-overlapping portion (135), so that the first portion (131), the second portion (132), and the non-overlapping portion (135) may be conductive.

[0109] Referring to FIG. 2b, when the non-overlapping portion (135) is conductive, even if the non-overlapping portion (135) does not overlap with the gate electrode (150), electrical connections can be made between the channel portion (130n) and the first wiring pattern (125) and between the channel portion (130n) and the second wiring pattern (126) through the conductive non-overlapping portion (135).

[0110] According to another embodiment of the present invention, the non-overlapping portion (135) may be intentionally formed by design or may be formed due to errors in the manufacturing process. Even if the non-overlapping portion (135) is formed between the channel portion (130n) and the first wiring pattern (125) or between the channel portion (130n) and the second wiring pattern (126) due to errors in the manufacturing process, according to another embodiment of the present invention, since the non-overlapping portion (135) can be made conductive, electrical connections can be smoothly made between the channel portion (130n) and the first wiring pattern (125) and between the channel portion (130n) and the second wiring pattern (126).

[0111] According to another embodiment of the present invention, the non-overlapping portion (135) may have a length of 2 μm or less. If the length of the non-overlapping portion (135) exceeds 2 μm, electrical connection may not be smoothly established between the channel portion (130n) and the first wiring pattern (125) or between the channel portion (130n) and the second wiring pattern (126), even if the non-overlapping portion (135) is conductive. The length of the non-overlapping portion (135) may be defined as the distance between the gate electrode (150) and the first wiring pattern (125) or the distance between the gate electrode (150) and the second wiring pattern (126) in a planar manner.

[0112] FIG. 3 is a cross-sectional view of a thin-film transistor (300) according to another embodiment of the present invention.

[0113] Referring to FIG. 3, a gate electrode (150) is disposed on the gate insulating film (140), and also a source electrode (161) and a drain electrode (162) are disposed on the gate insulating film (140).

[0114] According to another embodiment of the present invention illustrated in FIG. 3, the source electrode (161) and the drain electrode (162) can be made of the same material as the gate electrode (150) and by the same process.

[0115] In FIG. 3, the gate insulating film (140) may be configured to cover the channel portion (130n) and expose one side of the first wiring pattern (125) and one side of the second wiring pattern (126). More specifically, the gate insulating film (140) covers the upper surface of the channel portion (130n), the first portion (131), and the second portion (132), and does not cover either side of the first wiring pattern (125) and either side of the second wiring pattern (126).

[0116] The source electrode (161) is disposed on the gate insulating film (140) and extends along the sidewall of the gate insulating film (140) to contact the side of the first portion (131) and the side of the first wiring pattern (125). Additionally, the source electrode (161) can contact the light blocking layer (111) through a contact hole formed in the buffer layer (120).

[0117] The drain electrode (162) is spaced apart from the source electrode (161) and is disposed on the gate insulating film (140), extending along the sidewall of the gate insulating film (140) so as to be in contact with the side of the second portion (132) and the side of the second wiring pattern (125).

[0118] Referring to FIG. 3, an interlayer insulating film (145) may be disposed on the gate electrode (150), source electrode (161), and drain electrode (162).

[0119] FIG. 4 is a cross-sectional view of a thin-film transistor (400) according to another embodiment of the present invention.

[0120] According to another embodiment of the present invention, FIG. 4 shows that a gate insulating film (140) may be disposed over the entire upper portion of a substrate (110) including the upper portion of an active layer (130), and contact holes for electrical contact may be formed in the gate insulating film (140).

[0121] Referring to FIG. 4, a contact hole (CH2) may be formed in the gate insulating film (140) so as to expose the side of the first part (131) and the side of the first wiring pattern (125), and another contact hole (CH3) may be formed in the gate insulating film (140) so as to expose the side of the second part (132) and the side of the second wiring pattern (125).

[0122] The source electrode (161) can be placed on the gate insulating film (140) and can contact the side of the first part (131) and the side of the first wiring pattern (125) through a contact hole (CH2) formed in the gate insulating film (140). Additionally, the source electrode (161) can contact the light blocking layer (111) through a contact hole formed in the gate insulating film (140) and the buffer layer (120).

[0123] The drain electrode (162) can be placed on the gate insulating film (140) and can contact the side of the second part (132) and the side of the second wiring pattern (125) through a contact hole (CH3) formed in the gate insulating film (140).

[0124] FIG. 5 is a cross-sectional view of a thin-film transistor (500) according to another embodiment of the present invention.

[0125] The thin film transistor (500) of FIG. 5 has an active layer (130) with a multilayer structure compared to the thin film transistor (100) of FIG. 1b.

[0126] Referring to FIG. 5, the active layer (130) includes a first oxide semiconductor layer (130a) and a second oxide semiconductor layer (130b) on the first oxide semiconductor layer (130a). The first oxide semiconductor layer (130a) and the second oxide semiconductor layer (130b) may include the same semiconductor material or different semiconductor materials.

[0127] The first oxide semiconductor layer (130a) supports the second oxide semiconductor layer (130b). Therefore, the first oxide semiconductor layer (130a) is also referred to as a "support layer." A channel portion (130n) may be formed in the second oxide semiconductor layer (130b). Therefore, the second oxide semiconductor layer (130b) is also referred to as a "channel layer." However, one embodiment of the present invention is not limited thereto, and the channel portion (130n) may also be formed in the first oxide semiconductor layer (130a).

[0128] The active layer (130) is a structure composed of a first oxide semiconductor layer (130a) and a second oxide semiconductor layer (130b), which is also called a bi-layer structure. The bi-layer structure shown in FIG. 5 can also be applied to the active layer (130) of a thin-film transistor (200, 300, 400) according to FIG. 2b, FIG. 3 and FIG. 4.

[0129] FIG. 6 is a cross-sectional view of a thin-film transistor (600) according to another embodiment of the present invention. Compared to the thin-film transistor (500) of FIG. 5, the thin-film transistor (600) of FIG. 6 further comprises a third oxide semiconductor layer on a second oxide semiconductor layer (130b) in the active layer (130).

[0130] Referring to FIG. 6, the active layer (130) includes a first oxide semiconductor layer (130a), a second oxide semiconductor layer (130b), and a third oxide semiconductor layer. However, other embodiments of the present invention are not limited thereto, and the active layer (130) may further include other semiconductor layers.

[0131] The structure of the active layer (130) shown in FIG. 6 can also be applied to the active layer (130) of the thin-film transistor (200, 300, 400) according to FIG. 2b, FIG. 3 and FIG. 4.

[0132] A method for manufacturing a thin-film transistor (100) according to one embodiment of the present invention will be described below with reference to FIGS. 7a to 7g.

[0133] FIGS. 7a to 7g are schematic diagrams illustrating a method for manufacturing a thin-film transistor (100) according to one embodiment of the present invention.

[0134] Referring to FIG. 7a, a light-blocking layer (111) may be formed on a substrate (110), and a buffer layer (120) may be formed on the light-blocking layer (111).

[0135] Referring to FIG. 7b, a first wiring pattern (125) and a second wiring pattern (126) can be formed on the buffer layer (120).

[0136] The first wiring pattern (125) and the second wiring pattern (126) may be made of a conductive material. For example, the first wiring pattern (125) and the second wiring pattern (126) may be made of metal. More specifically, the first wiring pattern (125) and the second wiring pattern (126) may include a reducing metal.

[0137] The first wiring pattern (125) and the second wiring pattern (126) may include at least one selected from, for example, aluminum (Al), titanium (Ti), molybdenum (Mo), calcium (Ca) and barium (Ba).

[0138] Referring to FIG. 7c, an active layer (130) is formed on the first wiring pattern (125) and the second wiring pattern (126). The active layer (130) may be arranged to overlap and contact the first wiring pattern (125) and the second wiring pattern (126).

[0139] Referring to FIG. 7d, a gate insulating film (140) is formed on the active layer (130). The gate insulating film (140) may be formed with an area larger than that of the active layer (130) to cover the first wiring pattern (125), the second wiring pattern (126), and the active layer (130).

[0140] Referring to FIG. 7e, a gate electrode (150) is formed on a gate insulating film (140). The gate electrode (150) overlaps at least partially with the active layer (130). Specifically, the gate electrode (150) is formed to overlap with the channel portion (130n).

[0141] Referring to FIG. 7e, during the process of forming the gate electrode (150), a portion of the edge of the gate insulating film (140) is removed so that the side of the first portion (131) and the side of the first wiring pattern (125) are exposed, and also the side of the second portion (132) and the side of the second wiring pattern (125) may be exposed. Additionally, referring to FIG. 7e, a contact hole (CH1) is formed in the buffer layer (120) so that a portion of the light blocking layer (111) may be exposed.

[0142] Referring to FIG. 7f, an interlayer insulating film (145) is formed on the gate electrode (150) and the gate insulating film (140). Contact holes (CH1, CH2, CH3) are formed in the interlayer insulating film (145).

[0143] In the interlayer insulating film (145), the side of the first part (131) and the side of the first wiring pattern (125) may be exposed through a contact hole (CH2), and the side of the second part (132) and the side of the second wiring pattern (125) may be exposed through another contact hole (CH3).

[0144] Referring to FIG. 7g, a source electrode (161) and a drain electrode (162) are formed on an interlayer insulating film (145). The source electrode (161) is connected to the side of the first part (131) of the active layer (130) and the side of the first wiring pattern (125) through a contact hole (CH2). The drain electrode (162) is connected to the side of the second part (132) of the active layer (130) and the side of the second wiring pattern (126) through a contact hole (CH3).

[0145] As a result, a thin film transistor (100) according to one embodiment of the present invention can be made.

[0146] Hereinafter, a display device including the thin-film transistors (100, 200, 300, 400, 500, 600) described above will be described in detail.

[0147] FIG. 8 is a schematic diagram of a display device (700) according to another embodiment of the present invention.

[0148] A display device (700) according to another embodiment of the present invention includes a display panel (310), a gate driver (320), a data driver (330), and a control unit (340), as shown in FIG. 8.

[0149] Gate lines (GL) and data lines (DL) are arranged on a display panel (310), and a pixel (P) is arranged in the intersection area of ​​the gate lines (GL) and data lines (DL). An image is displayed by driving the pixel (P).

[0150] The control unit (340) controls the gate driver (320) and the data driver (330).

[0151] The control unit (340) uses a signal supplied from an external system (not shown) to output a gate control signal (GCS) for controlling the gate driver (320) and a data control signal (DCS) for controlling the data driver (330). Additionally, the control unit (340) samples input image data input from the external system, rearranges it, and supplies the rearranged digital image data (RGB) to the data driver (330).

[0152] The gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK), etc. Additionally, the gate control signal (GCS) may include control signals for controlling shift registers.

[0153] The data control signal (DCS) includes the source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), polarity control signal (POL), etc.

[0154] The data driver (330) supplies data voltage to the data lines (DL) of the display panel (310). Specifically, the data driver (330) converts the image data (RGB) input from the control unit (340) into an analog data voltage and supplies the data voltage to the data lines (DL).

[0155] The gate driver (320) may include a shift register (350).

[0156] The shift register (350) sequentially supplies gate pulses to gate lines (GL) for one frame using a start signal and a gate clock transmitted from the control unit (340). Here, one frame refers to the period during which one image is output through the display panel (310). The gate pulse has a turn-on voltage capable of turning on a switching element (thin-film transistor) placed in the pixel (P).

[0157] Additionally, the shift register (350) supplies a gate-off signal to the gate line (GL) to turn off the switching element during the remaining period of time in one frame when no gate pulse is supplied. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the scan signal (SS or Scan).

[0158] According to one embodiment of the present invention, a gate driver (320) can be mounted on a substrate (110). In this way, a structure in which the gate driver (320) is directly mounted on the substrate (110) is called a Gate In Panel (GIP) structure.

[0159] FIG. 9 is a circuit diagram of a pixel (P) of FIG. 8, FIG. 10 is a plan view of a pixel (P) of FIG. 9, and FIG. 11 is a cross-sectional view taken along III-III' of FIG. 10.

[0160] The circuit diagram of FIG. 9 is an equivalent circuit diagram for a pixel (P) of a display device (700) that includes an organic light-emitting diode (OLED) as a display element (710).

[0161] The pixel (P) includes a display element (710) and a pixel driving unit (PDC) that drives the display element (710).

[0162] The pixel driving unit (PDC) of FIG. 9 includes a first thin-film transistor (TR1) which is a switching transistor and a second thin-film transistor (TR2) which is a driving transistor. For example, one of the thin-film transistors (100, 200, 300, 400, 500, 600) described above may be used as the first thin-film transistor (TR1) and the second thin-film transistor (TR2).

[0163] The first thin-film transistor (TR1) is connected to the gate line (GL) and the data line (DL), and is turned on or turned off by a scan signal (SS) supplied through the gate line (GL).

[0164] The data line (DL) provides a data voltage (Vdata) to the pixel driver (PDC), and the first thin-film transistor (TR1) controls the application of the data voltage (Vdata).

[0165] The driving power line (PL) provides a driving voltage (Vdd) to the display element (710), and the second thin-film transistor (TR2) controls the driving voltage (Vdd). The driving voltage (Vdd) is a pixel driving voltage for driving the organic light-emitting diode (OLED), which is the display element (710).

[0166] When the first thin-film transistor (TR1) is turned on by a scan signal (SS) applied through the gate line (GL) from the gate driver (320), a data voltage (Vdata) supplied through the data line (DL) is supplied to the gate electrode (G2) of the second thin-film transistor (TR2) connected to the display element (710). The data voltage (Vdata) is charged into a storage capacitor (Cst) formed between the gate electrode (G2) and the source electrode (S2) of the second thin-film transistor (TR2).

[0167] According to the data voltage (Vdata), the amount of current supplied to the organic light-emitting diode (OLED), which is the display element (710), through the second thin-film transistor (TR2) is controlled, and accordingly, the gradation of light output from the display element (710) can be controlled.

[0168] Referring to FIGS. 10 and 11, the first thin-film transistor (TR1) and the second thin-film transistor (TR2) are placed on a substrate (110).

[0169] The substrate (110) may be made of glass or plastic. As the substrate (110), a plastic having flexible properties, for example, polyimide (PI), may be used.

[0170] A light-blocking layer (111, 211) is disposed on a substrate (110). The light-blocking layer (111, 211) may have light-blocking properties. The light-blocking layer (111, 211) can protect the active layer (A1, A2) by blocking light incident from the outside.

[0171] A buffer layer (120) is disposed on the light-blocking layer (111, 211). The buffer layer (120) is made of an insulating material and protects the active layer (A1, A2) from moisture or oxygen entering from the outside.

[0172] A first wiring pattern (125) and a second wiring pattern (126) are disposed on a buffer layer (120). According to one embodiment of the present invention, the first wiring pattern (125) and the second wiring pattern (126) may have electrical conductivity and reduceability.

[0173] The active layer (A1) of the first thin-film transistor (TR1) and the active layer (A2) of the second thin-film transistor (TR2) are disposed on the first wiring pattern (125) and the second wiring pattern (126).

[0174] The active layer (A1, A2) may include, for example, an oxide semiconductor material. The active layer (A1, A2) may have a multilayer structure made of an oxide semiconductor material.

[0175] A gate insulating film (140) is disposed on the active layers (A1, A2). The gate insulating film (140) covers the upper surface of the active layers (A1, A2) and can be formed so that the side of the active layers (A1, A2), the side of the first wiring pattern (125), and the side of the second wiring pattern (126) are exposed.

[0176] The gate electrode (G1) of the first thin-film transistor (TR1) and the gate electrode (G2) of the second thin-film transistor (TR2) are placed on the gate insulating film (140).

[0177] Additionally, a gate line (GL) is disposed on the gate insulating film (140). The gate electrode (G1) of the first thin-film transistor (TR1) may extend from the gate line (GL) or be part of the gate line (GL).

[0178] Referring to FIG. 11, a first capacitor electrode (CE1) of a storage capacitor (Cst) is formed on a gate insulating film (140). The first capacitor electrode (CE1) can be formed by the same process using the same material as the gate electrodes (G1, G2).

[0179] An interlayer insulating film (145) is disposed on the gate electrodes (G1, G2), the gate line (GL), and the first capacitor electrode (CE1).

[0180] Data lines (DL) and driving power lines (PL) are disposed on the interlayer insulating film (145). Additionally, the source electrode (S1) and drain electrode (D1) of the first thin-film transistor (TR1) are disposed on the interlayer insulating film (145), and the source electrode (S2) and drain electrode (D2) of the second thin-film transistor (TR2) are disposed on the interlayer insulating film (145).

[0181] The source electrode (S1) of the first thin-film transistor (TR1) can be formed integrally with the data line (DL) and can have a structure extended from the data line (DL).

[0182] The source electrode (S1) of the first thin-film transistor (TR1) can contact the side of the active layer (A1) of the first thin-film transistor (TR1) and the side of the first wiring pattern (125) through the first contact hole (H1).

[0183] The drain electrode (D1) of the first thin-film transistor (TR1) contacts the other side of the active layer (A1) of the first thin-film transistor (TR1) and the side of the second wiring pattern (126) through the second contact hole (H2). Additionally, the drain electrode (D1) of the first thin-film transistor (TR1) is connected to the light-blocking layer (111) through the third contact hole (H3) and to the first capacitor electrode (CE1) through the fourth contact hole (H4). As a result, the first capacitor electrode (CE1) can be connected to the first thin-film transistor (TR1).

[0184] The drain electrode (D2) of the second thin-film transistor (TR1) can be formed integrally with the driving power line (PL) and can have a structure extended from the driving power line (PL).

[0185] The drain electrode (D2) of the second thin-film transistor (TR1) can contact the side of the active layer (A2) of the second thin-film transistor (TR2) and the side of the second wiring pattern (126) through the seventh contact hole (H7).

[0186] The source electrode (S2) of the second thin-film transistor (TR2) contacts the other side of the active layer (A2) of the second thin-film transistor (TR2) and the side of the first wiring pattern (125) through the sixth contact hole (H6). Additionally, the source electrode (S2) of the second thin-film transistor (TR2) is connected to the light-blocking layer (211) through the fifth contact hole (H5). The same voltage as the source electrode (S2) of the second thin-film transistor (TR2) can be applied to the light-blocking layer (211) that overlaps with the second thin-film transistor (TR2). As a result, the light-blocking layer (211) can serve as the second capacitor electrode (CE2) of the storage capacitor (Cst).

[0187] The source electrode (S2) of the second thin-film transistor (TR2) can be extended onto the interlayer insulating film (145) to form the third capacitor electrode (CE3) of the storage capacitor (Cst).

[0188] According to one embodiment of the present invention, a first capacitor electrode (CE1) and a second capacitor electrode (CE2) may overlap to form a first capacitor (C1), and a first capacitor electrode (CE1) and a third capacitor electrode (CE3) may overlap to form a second capacitor (C2). The first capacitor (C1) and the second capacitor (C2) formed in this way may constitute a storage capacitor (Cst).

[0189] According to one embodiment of the present invention, the storage capacitor (Cst) is formed in a double structure and can have a large capacity. The display device (700) according to one embodiment of the present invention has a storage capacitor (Cst) having a large capacity, and stable operation is possible.

[0190] Referring to FIG. 11, a flattening layer (180) is disposed on a data line (DL), a driving power line (PL), source electrodes (S1, S2), drain electrodes (D1, D2), and a third capacitor electrode (CE3). The flattening layer (180) flattens the upper portion of the first thin-film transistor (TR1) and the second thin-film transistor (TR2) and protects the first thin-film transistor (TR1) and the second thin-film transistor (TR2). The flattening layer (180) acts as a protective layer (170).

[0191] A first electrode (711) of a display element (710) is placed on a flattening layer (180). The first electrode (711) of the display element (710) contacts a third capacitor electrode (CE3) through an eighth contact hole (H8) formed in the flattening layer (180). As a result, the first electrode (711) of the display element (710) can be connected to the source electrode (S2) of a second thin-film transistor (TR2).

[0192] A bank layer (750) is disposed at the edge of the first electrode (711). The bank layer (750) defines a light-emitting region of the display element (710).

[0193] An organic light-emitting layer (712) is disposed on the first electrode (711), and a second electrode (713) is disposed on the organic light-emitting layer (712). Accordingly, a display element (710) is completed. The display element (710) illustrated in FIG. 11 is an organic light-emitting diode (OLED). Therefore, a display device (700) according to one embodiment of the present invention is an organic light-emitting display device.

[0194] FIG. 12 is a circuit diagram of a pixel (P) of a display device (800) according to another embodiment of the present invention.

[0195] FIG. 12 is an equivalent circuit diagram for a pixel (P) of an organic light-emitting display device.

[0196] A pixel (P) of a display device (800) illustrated in FIG. 12 includes an organic light-emitting diode (OLED), which is a display element (710), and a pixel driving unit (PDC) that drives the display element (710). The display element (710) is connected to the pixel driving unit (PDC).

[0197] In the pixel (P), signal lines (DL, GL, PL, RL, SCL) that supply a signal to the pixel driver (PDC) are arranged.

[0198] A data voltage (Vdata) is supplied through the data line (DL), a scan signal (SS) is supplied through the gate line (GL), a driving voltage (Vdd) for driving the pixel is supplied through the driving power line (PL), a reference voltage (Vref) is supplied through the reference line (RL), and a sensing control signal (SCS) is supplied through the sensing control line (SCL).

[0199] According to one embodiment of the present invention, a gate line (GL) can serve as a sensing control line (SCL).

[0200] The pixel driving unit (PDC) includes, for example, a first thin-film transistor (TR1) (switching transistor) connected to a gate line (GL) and a data line (DL), a second thin-film transistor (TR2) (driving transistor) that controls the magnitude of the current output to a display element (710) according to a data voltage (Vdata) transmitted through the first thin-film transistor (TR1), and a third thin-film transistor (TR3) (reference transistor) for detecting the characteristics of the second thin-film transistor (TR2).

[0201] A storage capacitor (Cst) is located between the gate electrode (G2) of the second thin-film transistor (TR2) and the display element (710). The storage capacitor (Cst) is also referred to as the storage capacitor (Cst).

[0202] The first thin-film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL) and transmits a data voltage (Vdata) supplied to the data line (DL) to the gate electrode (G2) of the second thin-film transistor (TR2).

[0203] The third thin-film transistor (TR3) is connected to the first node (n1) and reference line (RL) between the second thin-film transistor (TR2) and the display element (710), and is turned on or turned off by a sensing control signal (SCS), and detects the characteristics of the second thin-film transistor (TR2), which is the driving transistor, during the sensing period.

[0204] The second node (n2), connected to the gate electrode (G2) of the second thin-film transistor (TR2), is connected to the first thin-film transistor (TR1). A storage capacitor (Cst) is formed between the second node (n2) and the first node (n1).

[0205] When the first thin-film transistor (TR1) is turned on, the data voltage (Vdata) supplied through the data line (DL) is supplied to the gate electrode (G2) of the second thin-film transistor (TR2). The data voltage (Vdata) is charged into the storage capacitor (Cst) formed between the gate electrode (G2) and the source electrode (S2) of the second thin-film transistor (TR2).

[0206] When the second thin-film transistor (TR2) is turned on, current is supplied to the display element (710) through the second thin-film transistor (TR2) by the driving voltage (Vdd) that drives the pixel, and light is output from the display element (710).

[0207] FIG. 13 is a plan view of the pixel of FIG. 12, and FIG. 14 is a cross-sectional view taken along IV-IV' of FIG. 13.

[0208] Referring to FIG. 14, a light-blocking layer (111, 211) is disposed on a substrate (110), and a buffer layer (120) is disposed on the light-blocking layer (111, 211).

[0209] A first wiring pattern (125) and a second wiring pattern (126) are disposed on a buffer layer (120). The first wiring pattern (125) and the second wiring pattern (126) have electrical conductivity and may also have reducing properties.

[0210] Additionally, a data line (DL) and a reference line (RL) may be placed on the buffer layer (120).

[0211] The active layer (A1) of the first thin-film transistor (TR1), the active layer (A2) of the second thin-film transistor (TR2), and the active layer (A3) of the third thin-film transistor (TR3) are arranged on the first wiring pattern (125) and the second wiring pattern (126).

[0212] Referring to FIGS. 13 and 14, the active layer (A1) of the first thin-film transistor (TR1) and the second wiring pattern (126) can be extended to become the first capacitor electrode (C1) of the storage capacitor (Cst).

[0213] A gate insulating film (140) is disposed on the active layers (A1, A2, A3). The gate insulating film (140) covers the upper surface of the active layers (A1, A2, A3) and can be formed so that the side of the active layers (A1, A2, A3), the side of the first wiring pattern (125), and the side of the second wiring pattern (126) are exposed.

[0214] The gate electrode (G1) of the first thin-film transistor (TR1), the gate electrode (G2) of the second thin-film transistor (TR2), and the gate electrode (G3) of the third thin-film transistor (TR3) are disposed on the gate insulating film (140).

[0215] Additionally, a gate line (GL) is disposed on the gate insulating film (140). The gate electrode (G1) of the first thin-film transistor (TR1) may extend from the gate line (GL) or be part of the gate line (GL).

[0216] Referring to FIGS. 13 and 14, a source electrode (S1) of a first thin-film transistor (TR1) is placed on a gate insulating film (140), a source electrode (S2) and a drain electrode (D2) of a second thin-film transistor (TR2) are placed, and a source electrode (S3) and a drain electrode (D3) of a third thin-film transistor (TR3) are placed.

[0217] In addition, a third capacitor electrode (CE3) of the storage capacitor (Cst) is formed on the gate insulating film (140).

[0218] The source electrode (S1) of the first thin-film transistor (TR1) is connected to the data line (DL) through the first contact hole (H1) and to the light-blocking layer (111) through the second contact hole (H2). Additionally, the source electrode (S1) of the first thin-film transistor (TR1) can contact the side of the active layer (A1) and the side of the first wiring pattern (125) through the third contact hole (H3).

[0219] The active layer (A1) of the first thin-film transistor (TR1) and the second wiring pattern (126) overlap to serve as a drain electrode (D1).

[0220] Alternatively, an electrode disposed on the gate insulating film (140) and in contact with the side of the first capacitor electrode (C1) of the storage capacitor (Cst) through the fifth contact hole (H5) may be referred to as the drain electrode (D1) of the first thin-film transistor (TR1). In this case, the drain electrode (D1) of the first thin-film transistor (TR1) may be in contact with the other side of the active layer (A1) of the first thin-film transistor (TR1) and the other side of the second wiring pattern (126) through the fifth contact hole (H5), and may be formed integrally with the gate electrode (G2) of the second thin-film transistor (TR2).

[0221] The drain electrode (D2) of the second thin-film transistor (TR1) is placed on the gate insulating film (140) and can be formed integrally with the driving power line (PL).

[0222] The drain electrode (D2) of the second thin-film transistor (TR1) can contact the side of the active layer (A2) of the second thin-film transistor (TR2) and the side of the second wiring pattern (126) through the sixth contact hole (H6).

[0223] The source electrode (S2) of the second thin-film transistor (TR2) contacts the other side of the active layer (A2) of the second thin-film transistor (TR2) and the side of the first wiring pattern (125) through the seventh contact hole (H7). Additionally, the source electrode (S2) of the second thin-film transistor (TR2) is connected to the light-blocking layer (211) through the eighth contact hole (H3). As a result, the same voltage as the source electrode (S2) of the second thin-film transistor (TR2) can be applied to the light-blocking layer (211), and the light-blocking layer (211) can serve as the second capacitor electrode (CE2) of the storage capacitor (Cst).

[0224] Additionally, the source electrode (S2) of the second thin-film transistor (TR2) can be extended onto the gate insulating film (140) to form the third capacitor electrode (CE3) of the storage capacitor (Cst).

[0225] According to one embodiment of the present invention, a first capacitor electrode (CE1) and a second capacitor electrode (CE2) may overlap to form a first capacitor (C1), and a first capacitor electrode (CE1) and a third capacitor electrode (CE3) may overlap to form a second capacitor (C2). The first capacitor (C1) and the second capacitor (C2) formed in this way may constitute a storage capacitor (Cst).

[0226] According to one embodiment of the present invention, the storage capacitor (Cst) is formed in a double structure and can have a large capacity. The display device (800) according to one embodiment of the present invention has a storage capacitor (Cst) having a large capacity, and stable operation is possible.

[0227] Additionally, the source electrode (S2) of the second thin-film transistor (TR2) may be integrally formed with the drain electrode (S3) of the third thin-film transistor (TR3). The drain electrode (D3) of the third thin-film transistor (TR3) contacts the side of the active layer (A3) of the third thin-film transistor (TR3) and the side of the second wiring pattern (126) through the ninth contact hole (H9).

[0228] The gate electrode (G3) of the third thin-film transistor (TR3) is placed on the gate insulating film.

[0229] The source electrode (S3) of the third thin-film transistor (TR3) contacts the other side of the active layer (A3) of the third thin-film transistor (TR3) and the side of the first wiring pattern (125) through the tenth contact hole (H10). Additionally, the source electrode (S3) of the third thin-film transistor (TR3) is connected to the reference line (RL) through the eleventh contact hole (H10).

[0230] Referring to FIG. 14, an interlayer insulating film (145) is disposed on the first thin-film transistor (TR1), the second thin-film transistor (TR2), and the third thin-film transistor (TR3).

[0231] A flattening layer (180) is disposed on an interlayer insulating film (145). The flattening layer (180) flattens the upper portions of the first thin-film transistor (TR1), the second thin-film transistor (TR2), and the third thin-film transistor (TR3), and protects the first thin-film transistor (TR1), the second thin-film transistor (TR2), and the third thin-film transistor (TR3). The flattening layer (180) serves as a protective layer (170).

[0232] A first electrode (711) of a display element (710) is disposed on a flattening layer (180). The first electrode (711) of the display element (710) contacts a third capacitor electrode (CE3) through a fourth contact hole (H84) formed in the flattening layer (180) and the interlayer insulating film (145). As a result, the first electrode (711) of the display element (710) can be connected to the source electrode (S2) of a second thin-film transistor (TR2).

[0233] A bank layer (750) is disposed at the edge of the first electrode (711). The bank layer (750) defines a light-emitting region of the display element (710).

[0234] An organic light-emitting layer (712) is disposed on the first electrode (711), and a second electrode (713) is disposed on the organic light-emitting layer (712). Accordingly, a display element (710) is completed. The display element (710) illustrated in FIG. 14 is an organic light-emitting diode (OLED). Therefore, a display device (800) according to one embodiment of the present invention is an organic light-emitting display device.

[0235] FIG. 15 is a circuit diagram of a pixel of a display device (900) according to another embodiment of the present invention.

[0236] A pixel (P) of a display device (900) illustrated in FIG. 15 includes an organic light-emitting diode (OLED), which is a display element (710), and a pixel driving unit (PDC) that drives the display element (710). The display element (710) is connected to the pixel driving unit (PDC).

[0237] The pixel driver (PDC) includes thin-film transistors (TR1, TR2, TR3, TR4).

[0238] In the pixel (P), signal lines (DL, EL, GL, PL, SCL, RL) that supply a driving signal to the pixel driving unit (PDC) are arranged.

[0239] The pixel (P) of FIG. 15 includes an additional light emission control line (EL) compared to the pixel (P) of FIG. 12. A light emission control signal (EM) is supplied to the light emission control line (EL).

[0240] In addition, the pixel driver (PDC) of FIG. 15 further includes a fourth thin-film transistor (TR4), which is a light-emitting control transistor for controlling the light-emitting timing of the second thin-film transistor (TR2), compared to the pixel driver (PDC) of FIG. 12. The gate line (GL) can serve as a sensing control line (SCL).

[0241] A storage capacitor (Cst) is located between the gate electrode (G2) of the second thin-film transistor (TR2) and the display element (710).

[0242] The first thin-film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL) and transmits a data voltage (Vdata) supplied to the data line (DL) to the gate electrode (G2) of the second thin-film transistor (TR2).

[0243] The third thin-film transistor (TR3) is connected to the reference line (RL) and is turned on or off by the sensing control signal (SCS), and detects the characteristics of the second thin-film transistor (TR2), which is the driving transistor, during the sensing period.

[0244] The fourth thin-film transistor (TR4) transmits the driving voltage (Vdd) to the second thin-film transistor (TR2) or blocks the driving voltage (Vdd) according to the emission control signal (EM). When the fourth thin-film transistor (TR4) is turned on, current is supplied to the second thin-film transistor (TR2), and light is output from the display element (710).

[0245] A pixel driving unit (PDC) according to another embodiment of the present invention may be formed in various other structures other than the structure described above. The pixel driving unit (PDC) may include, for example, five or more thin-film transistors.

[0246] The present invention described above is not limited by the aforementioned embodiments and attached drawings, and it will be obvious to those skilled in the art that various substitutions, modifications, and changes are possible within the scope of the technical aspects of the present invention. Therefore, the scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0247] 100, 200, 300, 400, 500, 600: Thin-film transistor 700, 800, 900: Display device 110: Substrate 111: Light-blocking layer 125: 1st wiring pattern 126: 2nd wiring pattern 130: Active layer 130n: Channel section 131: Part 1 132: Part 2 140: Gate insulating film 150: Gate electrode 161: Source electrode 162: Drain electrode 710: Display element 711: First electrode 712: Organic light-emitting layer 713: Second electrode

Claims

Claim 1 A thin-film transistor comprising: a first wiring pattern and a second wiring pattern spaced apart from each other and disposed on a substrate; an active layer overlapping the first wiring pattern and the second wiring pattern; a gate insulating film on the active layer; and a gate electrode on the gate insulating film; wherein the active layer comprises a channel portion; a first portion overlapping and contacting the first wiring pattern; and a second portion overlapping and contacting the second wiring pattern; wherein the channel portion is disposed between the first wiring pattern and the second wiring pattern and overlaps with the gate electrode, and the gate insulating film covers the channel portion and exposes one side of the first wiring pattern and one side of the second wiring pattern, and the first wiring pattern and the second wiring pattern are disposed between the substrate and the active layer. Claim 2 delete Claim 3 A thin-film transistor according to claim 1, wherein the upper surface of the first wiring pattern contacts the lower surface of the first portion of the active layer, and the upper surface of the second wiring pattern contacts the lower surface of the second portion of the active layer. Claim 4 A thin-film transistor according to claim 1, wherein the first wiring pattern and the second wiring pattern each comprise a reducing conductive material. Claim 5 A thin-film transistor according to claim 4, wherein the reducing conductive material comprises at least one selected from aluminum (Al), titanium (Ti), molybdenum (Mo), calcium (Ca) and barium (Ba). Claim 6 A thin-film transistor according to claim 1, wherein the channel portion, the first portion, and the second portion are integrally formed. Claim 7 A thin-film transistor according to claim 1, further comprising at least one of a source electrode in contact with the side of the first wiring pattern and a drain electrode spaced apart from the source electrode and in contact with the side of the second wiring pattern. Claim 8 In claim 7, the source electrode and the drain electrode are made of the same material and by the same process as the gate electrode, in a thin-film transistor. Claim 9 A thin-film transistor according to claim 1, wherein the entire portion of the active layer disposed between the first wiring pattern and the second wiring pattern overlaps with the gate electrode. Claim 10 A thin-film transistor according to claim 1, wherein the active layer includes a non-overlapping portion that does not overlap with any one of the first wiring pattern, the second wiring pattern, and the gate electrode. Claim 11 In item 10, the above-mentioned non-overlapping portion is a conductive thin-film transistor. Claim 12 A thin-film transistor according to claim 1, wherein the gate insulating film covers the entire upper surface of the active layer. Claim 13 A thin-film transistor according to claim 1, wherein the active layer comprises an oxide semiconductor material. Claim 14 A thin film transistor according to claim 1, wherein the active layer comprises: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer. Claim 15 In claim 14, the thin film transistor further comprising an active layer, wherein the active layer comprises a third oxide semiconductor layer on the second oxide semiconductor layer. Claim 16 A display device comprising a thin-film transistor according to any one of claims 1 and 3 through 15. Claim 17 A thin-film transistor comprising: a first wiring pattern and a second wiring pattern spaced apart from each other; an active layer overlapping the first wiring pattern and the second wiring pattern; a gate insulating film on the active layer; and a gate electrode on the gate insulating film; wherein the active layer comprises a channel portion; a first portion overlapping and contacting the first wiring pattern; and a second portion overlapping and contacting the second wiring pattern; wherein the channel portion is disposed between the first wiring pattern and the second wiring pattern and overlaps with the gate electrode, and the gate insulating film covers the channel portion and exposes one side of the first wiring pattern and one side of the second wiring pattern, and further comprises at least one of a source electrode contacting the side of the first wiring pattern and a drain electrode spaced apart from the source electrode and contacting the side of the second wiring pattern. Claim 18 In claim 17, the first wiring pattern and the second wiring pattern each comprise a reducing conductive material, forming a thin film transistor. Claim 19 A thin-film transistor according to claim 17, wherein the entire portion of the active layer disposed between the first wiring pattern and the second wiring pattern overlaps with the gate electrode. Claim 20 A thin-film transistor according to claim 17, wherein the active layer comprises a non-overlapping portion that does not overlap with any one of the first wiring pattern, the second wiring pattern, and the gate electrode.

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