Semiconductor package

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a plurality of insulating layers and a plurality of metal pattern layers each disposed on the plurality of insulating layers and each having a wiring layer; at least one semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer; and non-contact pads disposed on the lower surface of the package substrate and isolated from the wiring layer, wherein the lowest level metal pattern layer among the plurality of metal pattern layers has an open area that overlaps with at least one non-contact pad among the non-contact pads in a direction perpendicular to the upper surface of the package substrate.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0002] In line with the development of the electronics industry and user demands, electronic devices are becoming lighter and lighter; accordingly, semiconductor packages used in these devices are required to be high-performance (e.g., high speed) and high-capacity. As one solution to this, semiconductor packages can be provided as Ball Grid Array (BGA) packages.

[0003] When mounting a semiconductor package on the main board of an electronic device, performance degradation may occur due to conductive bumps (e.g., balls) connected to the signal lines of the main board, and such performance degradation can have a greater impact on electronic devices requiring high-speed signal characteristics. The problem to be solved

[0004] One of the technical problems that the present invention aims to solve is to provide a semiconductor package capable of maintaining high-speed and high-reliability signal characteristics. means of solving the problem

[0006] One embodiment of the present invention provides a semiconductor package comprising: a plurality of insulating layers and a plurality of metal pattern layers each disposed on the plurality of insulating layers and each having a wiring layer; at least one semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer; and non-contact pads disposed on the lower surface of the package substrate and isolated from the wiring layer, wherein the lowest level metal pattern layer among the plurality of metal pattern layers has an open area that overlaps with at least one non-contact pad among the non-contact pads in a direction perpendicular to the upper surface of the package substrate.

[0008] One embodiment of the present invention provides a semiconductor package comprising: a plurality of insulating layers and a metal pattern layer disposed on each of the plurality of insulating layers and each having a wiring layer; a first semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; a second semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer, wherein the contact pads include first and second signal pads for transmitting a differential signal; and non-contact pads disposed on the lower surface of the package substrate and separated from the wiring layer; wherein the non-contact pads include at least one non-contact pad disposed around the second signal pad and located adjacent to the corner of the package substrate than the second signal pad, and the metal pattern layer of the lowest level among the plurality of wiring layers has an open area that overlaps with at least one of the non-contact pads in a direction perpendicular to the upper surface of the package substrate.

[0010] One embodiment of the present invention provides a semiconductor package comprising: a plurality of insulating layers and a plurality of metal pattern layers each disposed on the plurality of insulating layers and each having a wiring layer; at least one semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer, wherein the contact pads include a first signal pad and a second signal pad for transmitting a differential signal; non-contact pads disposed on the lower surface of the package substrate and separated from the wiring layer; contact bumps each disposed on the contact pads; and non-contact bumps each disposed on the non-contact pads; wherein the metal pattern layer at the lowest level among the plurality of wiring layers has an open area that overlaps with at least one of the non-contact pads in a direction perpendicular to the upper surface of the package substrate. Effects of the invention

[0012] According to one embodiment of the present invention, the capacitance generated by the non-contact bump can be reduced by forming an open region in a metal pattern layer located above a non-contact bump (or pad) that is connected to a signal line connected to a contact bump (or pad) for transmitting a signal (e.g., a differential signal). As a result, the discontinuity of the differential impedance can be reduced and the signal integrity (SI) characteristics can be improved.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 2 is a magnified view of a portion ("A1") of the semiconductor package of FIG. 1. FIG. 3 is a cross-sectional view showing a circuit board on which the semiconductor package of FIG. 1 is mounted. Figure 4 is a magnified view of the "A2" portion of Figure 3. FIG. 5 is a plan view showing signal routing of a circuit board on which a semiconductor package is mounted according to the present embodiment and an arrangement of conductive bumps of the semiconductor package. FIGS. 6 and FIGS. 7 are partial plan views showing the "A3" portion of FIG. 5 at the first level (LV1) and the second level (LV2), respectively. FIG. 8 is a plan view showing a part of a package substrate of a semiconductor package according to one embodiment of the present invention. FIG. 9 is a graph showing the improvement in transfer characteristics according to the introduction of the present invention (example). FIG. 10 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention, and FIG. 11 is a magnified view of a part ("B1") of the semiconductor package of FIG. 10. FIG. 12 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention, and FIG. 13 is a magnified view of a part ("B2") of the semiconductor package of FIG. 12. Specific details for implementing the invention

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0018] FIG. 1 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention, and FIG. 2 is an enlarged view of a part ("A1") of the semiconductor package of FIG. 1.

[0020] Referring to FIGS. 1 and 2, a semiconductor package (200) includes a package substrate and a first semiconductor chip and a second semiconductor chip disposed on the package substrate.

[0021] The above package substrate (100) may include a body portion (110) having a plurality of insulating layers (111, 112, 113), metal pattern layers (130) disposed on the plurality of insulating layers (111, 112, 113), and contact pads (140) and non-contact pads (150) disposed on the lower surface of the body portion (101). Here, the metal pattern layers (130) may include wiring layers (130L) and ground pattern layers (130G). The wiring layers (130L) may be interlayer-connected to each other by vias (V) and may form a rewiring circuit. The contact pads (140) are connected to the wiring layers (130L) by pad vias (Vp), and the non-contact pads (150) are not connected to the wiring layers (130L) and may be separated from the rewiring circuit.

[0022] For example, the package substrate (100) may be a printed circuit board. The package substrate (100) is not limited to a printed circuit board and may be a wiring board of various forms.

[0023] The above package substrate (100) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the above package substrate (100) may include FR4, tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, bismalimide triazine (BT), Thermount, cyanate ester, polyimide, or liquid crystal polymer. Additionally, the metal pattern layer (130), contact pads (140), and non-contact pads (150) may include, for example, copper (Cu), nickel (Ni), aluminum (Al), or beryllium copper.

[0024] Conductive bumps (160, 170) may be formed on the contact pads (140) and non-contact pads (150) of the package substrate (100), respectively. The conductive bumps (160, 170) may include, for example, solder balls, and the semiconductor package (200) may be a ball grid array (BGA) package.

[0025] The contact pads (140) connected to the wiring layer (130L) may include a first contact pad (140A) that transmits a signal sensitive to relatively impedance, and a second contact pad (140B) that transmits a power signal or a ground signal. First and second contact bumps (160A, 160B) may be disposed on the first and second contact pads (140A, 140B), respectively.

[0026] As previously described, the non-contact pad (150) connected to the wiring layer (130L) has a non-contact bump (170) placed on the non-contact pad (150) similar to the contact bump (160), and as shown in FIG. 3, stable support of the semiconductor package (200) on the main board (see FIG. 3) can be achieved.

[0027] In this embodiment, the non-contact pad (150) may be divided into a first non-contact pad (150A) and a second non-contact pad (150B) depending on whether it is connected to a signal line of the main board. Similarly, the non-contact bump (170) may be divided into first and second non-contact bumps (170A, 170B) respectively placed on the first and second non-contact pads (150A, 150B).

[0028] FIG. 3 is a cross-sectional view showing a circuit board (310) on which the semiconductor package (200) of FIG. 1 is mounted, and FIG. 4 is a magnified view showing the “A2” portion of FIG. 3. The electronic device (300) shown in FIG. 3 may be an electronic device equipped with a memory device such as a UFS (universe flash storage) card, for example.

[0029] Referring to FIG. 3, the first non-contact pad (150A) can be electrically connected to the same signal line (315B) as the first contact pad (140A) through the first non-contact bump (170A). Here, the first non-contact pad (150A) and the first non-contact bump (170A) can act as stubs of the signal line (315B).

[0030] In this embodiment, to reduce the stub effect caused by the first non-contact bump (170A), the metal pattern layer (130) on the lowest level insulating layer (111), that is, the lowest level metal pattern layer (130), may include an open area (OP) in a direction perpendicular to the upper surface of the package substrate (100).

[0031] By reducing the capacitance generated at the first beacon contact bump (170A) by this open region (OP), the stub effect caused by the first beacon contact bump (170A) can be significantly reduced. Since the thinner the thickness (d) of the lowest insulating layer (111), the capacitance caused by the adjacent metal pattern layer increases, so the impedance effect due to the formation of the open region (OP) can be effectively reduced. For example, when the thickness (d) of the lowest insulating layer (111) is 20 μm or less, particularly 15 μm or less, the effect due to the formation of the open region (OP) can be greatly expected.

[0032] The above open area (OP) may have an area larger than the planar area of ​​the first non-contact pad (150A). In some embodiments, the metal pattern layer on which the open area (OP) is formed may be a ground pattern (130G).

[0033] The first non-contact pad (150A) may be located in an area adjacent to the corner of the package substrate (100) around the first contact pad (140A) connected to the same signal line (see 315B in FIG. 3). In this arrangement, since the signal line (315B) connected by the first contact bump (160A) extends outward (in the direction of the arrow) toward the first non-contact pad (150A), the first non-contact bump (150A) located along the extension path must also be connected to the signal line (315B), and as a result, the first non-contact bump (150A) acts as a stub of the signal line (315B). As in the present embodiment, the first non-contact pad (150A) and the first non-contact bump (170A) may be positioned at the outermost side of the package substrate (100) so as to be adjacent to the corner of the package substrate (100).

[0034] Additionally, the non-contact pad (150) employed in this embodiment may include a second non-contact pad (150B) that is not electrically connected to the same signal line (315B) as the first contact pad (140A). Since the second non-contact pad (150B) does not act as a stub of a specific signal line, an additional open area may not be required in the adjacent metal pattern layer.

[0036] In this embodiment, the first and second contact pads (140A, 140B) and the first and second non-contact pads (150A, 150B) are depicted differently from each other, but in reality, they can be formed using the same material and the same process. Similarly, the first and second contact bumps (160A, 160B) and the first and second non-contact bumps (170A, 170B) are also depicted differently from each other, but in reality, they can be formed using the same material and the same process.

[0038] In this embodiment, the first semiconductor chip (210) may include a plurality of semiconductor chips provided as a chip stack structure. The chip stack structure may have a plurality of semiconductor chips (210) stacked in a stepped manner. The first semiconductor chips (210) may be memory chips. For example, the memory chips may include non-volatile memory semiconductor chips. The non-volatile memory semiconductor chip (320) may be, for example, NAND flash memory, RRAM (Resistive Random Access Memory), MRAM (Magnetoresistive RAM), PRAM (Phase-change RAM), or FRAM (Ferroelectric RAM).

[0039] An adhesive layer (230) may be interposed between the first semiconductor chips (210). For example, the adhesive layer (230) may be a material such as Direct Adhesive Film (DAF) or Film Over Wire (FOW). Each first semiconductor chip (210) may include chip pads disposed on one side of its upper surface. Each first semiconductor chip (210) is stacked so that the chip pads on one side are exposed, and a wire (250) may be connected to the chip pads between adjacent semiconductor chips (210) and to the upper pad (130P) of the package substrate (100).

[0040] The second semiconductor chip (220) may be a processor chip that controls the first semiconductor chip (210), which is a non-volatile memory semiconductor. Although not limited thereto, the processor chip may be configured to transmit and receive data with an external device using a serial interface. For example, the processor chip may be configured to support a UFS (universal flash storage) interface protocol, a PCIe (Peripheral Component Interconnect Express) interface protocol, or a USB 3.0 interface protocol.

[0042] In some embodiments, the first and second semiconductor chips (210, 220) may be other memory chips or processor chips. In some embodiments, the first semiconductor chip (210) is not limited to a non-volatile memory chip and may be a volatile memory chip or a combination thereof. For example, the volatile memory chip may include dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero capacitor RAM (ZRAM), or twin transistor RAM (TTRAM). In some embodiments, the second semiconductor chip (220) may include a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, or an application-specific IC (ASIC). Depending on the type of the first and second semiconductor chips (220), the semiconductor package (1000) may be a server-oriented semiconductor package, a mobile-oriented semiconductor package, or an automotive-oriented semiconductor package.

[0044] The semiconductor package (200) employed in this embodiment may further include a molding portion (290) surrounding the first semiconductor chip (210) and the second semiconductor chip (220).

[0045] The molding portion (290) can perform the function of protecting the first semiconductor chip (210) and the second semiconductor chip (220) from the outside. For example, the molding portion (290) can be formed by a process of injecting a suitable uncured resin onto a package substrate (100) and then curing it. In the process of forming the molding portion (290) (e.g., transfer molding), pressure can be applied to the molding resin by a pressurizing means such as a press. Here, process conditions such as the delay time between the injection of the molding resin and the pressurization, the amount of molding resin injected, and the pressurization temperature / pressure can be set by considering physical properties such as the viscosity of the molding resin. For example, the molding portion (290) may include an epoxy-group molding resin or a polyimide-group molding resin. For example, the molding part (290) may include an epoxy molding compound (EMC) or a high-k epoxy molding compound.

[0047] The present invention can be used more advantageously in a contact pad for transmitting a differential signal. Specifically, the first contact pad includes first and second signal pads for transmitting a differential signal, and can operate more advantageously when a non-contact bump (or pad) is connected to a signal line connected to either of the first and second signal lines.

[0049] FIG. 5 is a plan view showing signal routing of a circuit board on which a semiconductor package is mounted according to the present embodiment and an arrangement of conductive bumps of the semiconductor package.

[0050] Referring to FIG. 5, a plan view of a circuit board (310) on which a semiconductor package (200) according to the present embodiment is mounted is shown. The cross-section of FIG. 3 above can be understood as a cross-section taken by cutting along I-I' of the electronic device (300) of FIG. 5.

[0051] The semiconductor package (200) indicated by the dotted line may be the semiconductor package (200) described in FIGS. 1 and FIGS. 2. The semiconductor package (200) is configured to transmit and receive data with an external device using a serial interface, and FIG. 5 illustrates signal routing of a circuit board (310) according to this serial interface.

[0052] FIG. 4 illustrates a portion of the circuit lines of a circuit board along with the arrangement of conductive bumps (160, 170) of a semiconductor package (200), but for convenience of explanation, only the first and second signal lines for transmitting differential signals among the circuit lines are illustrated. The first and second signal lines (315A, 315B) are arranged diagonally on one side of the semiconductor package (200).

[0053] FIG. 6 is a partial enlarged plan view showing the "A3" portion of FIG. 5 at the first level ('LV1' of FIG. 4), showing the routing of the circuit board and the arrangement of conductive bumps.

[0054] Referring to FIG. 6 together with FIG. 5, the first contact bump (160A) employed in the present embodiment includes first and second signal bumps (160A1, 160A2) for transmitting differential signals, and each of the first and second signal bumps (160A1, 160A2) may be connected to one end of each of the first and second signal lines (315A, 315B). The first signal bump (160A1) may be positioned adjacent to the associated second signal bumps (160A2), but may be positioned adjacent to one corner of the semiconductor package (200) than the associated second signal bump (160A2). In the present embodiment, the first signal bump (160A1) may be positioned at the outermost side of the semiconductor package (200), and the second signal bump (160A2) may be positioned inwardly than the first signal bump (160A1).

[0055] The first and second signal lines (315A, 315B) include one or more lands (315L) having a relatively large area, and conductive bumps including the first and second signal bumps (160A1, 160A2) can each be placed on the land (315L).

[0056] As illustrated in FIG. 6, the first signal line (315A) connected to the first signal bump (160A1) extends outward without passing through other bumps, whereas the second signal line (315B) connected to the second signal bump (160A2) may extend through the first beacon contact bump (170A) positioned closer to the corner of the semiconductor package (200). Additionally, the first beacon contact bump (170A) may be positioned alongside the first signal pad (160A1) at the corner of the package substrate (100).

[0057] Another contact bump that transmits a power signal and / or a ground signal, i.e., a second contact bump (160B), may be connected to another signal line (not shown). Although not shown in FIG. 6, another non-contact bump, i.e., a second non-contact bump (170B), may be connected to a land or dummy land of a signal line other than the first and second signal lines (315A, 315B).

[0059] In this arrangement, the signal transmitted from the first signal bump (160A1) through the first signal line (351A) is not affected by other conductive bumps, whereas the signal transmitted from the second signal bump (160A2) through the second signal line (315B) may have its impedance affected by the first non-contact bump (170A) acting as a stub. As a result, impedance discontinuity may occur in the signals transmitted from the first and second signal lines.

[0060] To minimize the effect of such impedance, as shown in FIG. 7, the capacitance of the first beacon bump (170A) (or first beacon pad (150A)) and the adjacent metal pattern layer can be reduced by forming an open area (OP) in the area of ​​the metal pattern layer (130G) that is vertically superimposed with the first beacon bump (170A) (or first beacon pad (150A)).

[0061] FIG. 9 is a graph showing the improvement in transfer characteristics according to the introduction of the present invention (example).

[0062] Referring to FIG. 9, the impedance attenuation characteristics of a form with an open region (OP) introduced as shown in FIG. 7 (Example) and a form without an open region introduced (Comparative Example) are compared. It can be seen that there is a significant difference in characteristics in the high-frequency band of 10 GHz or higher. For example, in the band of 10 GHz or higher, the characteristic of the Example (S-parameter transfer characteristic) was -4.06 dB, whereas the characteristic of the Comparative Example showed a relatively large -9.47 dB. In the band of 18 GHz or higher, the difference becomes even greater, with the characteristic of the Example being -3.08 dB, while the Comparative Example showed a significantly larger -50.63 dB. As such, it was confirmed that the stub effect caused by non-contact bumps becomes more significant as the signal transmission speed increases, and the improvement effect due to the introduction of an open region is also significant.

[0064] In this embodiment, as shown in FIG. 7, the open area (OP) may have a hole shape located within the ground pattern (130G). This open area (OP) may have an area larger than the area of ​​the first non-contact pad (150A). The plan view of the level (LV2) shown in FIG. 7 represents the lowest level metal pattern layer located between the first and second insulating layers (111, 112) in the cross-section shown in FIG. 4.

[0065] By forming an open region (OP) in a metal pattern layer located on top of a first beacon contact bump (or pad) that is connected to a second signal line (351B) connected to one of the first and second signal pads (or bump (160A2)) for transmitting a differential signal, the capacitance generated by the first beacon contact bump (170A) can be reduced. As a result, the discontinuity of the differential impedance can be reduced and the SI characteristics can be improved.

[0067] FIG. 8 is a plan view showing a part of a package substrate of a semiconductor package according to one embodiment of the present invention.

[0068] Referring to FIG. 8, the open area (OP') introduced in this embodiment may not be a closed hole structure surrounded by a grounding pattern, but may have a shape with a portion open. That is, it may be provided as a spaced-out space between the first and second grounding patterns (130G1, 130G2). Additionally, the open area (OP') introduced in this embodiment may have various polygonal shapes, such as a square shape. In another embodiment, the open area introduced in this embodiment may not be a shape formed by additional processing of the grounding pattern, but may be provided as an open area where no metal pattern exists in the area overlapping perpendicularly with the first beacon contact bump by changing the path of the wiring layer.

[0070] FIG. 10 is a cross-sectional view showing a semiconductor package (200A) according to one embodiment of the present invention, and FIG. 11 is a magnified view of a part ("B1") of the semiconductor package (200A) of FIG. 10.

[0071] Referring to FIGS. 10 and 11, the semiconductor package (200A) according to the present embodiment can be understood as having a structure similar to the embodiment shown in FIGS. 1 to 7, except that it includes one semiconductor chip (220) and that an open region (OP) is located on a non-contact pad (170A) located in an internal region of the lower surface of the package substrate (100). Accordingly, the description of the embodiment shown in FIGS. 1 to 7 may be combined with the description of the present embodiment unless specifically stated otherwise.

[0072] The semiconductor package (200A) according to the present embodiment may include a single semiconductor chip (220). Additionally, a first contact pad (140A) that transmits a signal and an adjacent first non-contact pad (150A) may be located in an internal area of ​​the lower surface of the package substrate (100). The first contact bump (160A) of the first contact pad (140A) and the first non-contact bump (170A) of the first non-contact pad (150A) may be connected on the same line. In this case, as shown in FIG. 11, an open area (OP) may be located in an area of ​​a metal pattern layer (130) that is vertically superimposed with the first non-contact pad (170A).

[0074] FIG. 12 is a cross-sectional view showing a semiconductor package (200B) according to one embodiment of the present invention, and FIG. 13 is a magnified view of a part ("B2") of the semiconductor package (200B) of FIG. 12.

[0075] Referring to FIGS. 12 and 13, the semiconductor package (200B) according to the present embodiment can be understood as having a structure similar to the embodiment shown in FIGS. 1 to 7, except that the second semiconductor chip (220) is connected to the wiring layer (130L) (particularly, the upper pad (130P)) of the package substrate (100) by a wire (230'), and the first and second open regions (OP1, OP2) are located vertically on the non-contact pad (170A). Accordingly, the description of the embodiment shown in FIGS. 1 to 7 may be combined with the description of the present embodiment unless specifically stated otherwise.

[0076] Unlike the previous embodiment, the second semiconductor chip (220) employed in this embodiment can be connected to the wiring layer (130L) by a wire (230'). Meanwhile, the first contact pad (140A) that transmits a signal and the adjacent first non-contact pad (150A) are positioned adjacent to one corner of the package substrate (100), and the first contact bump (160A) of the first contact pad (140A) and the first non-contact bump (170A) of the first non-contact pad (150A) can be connected on the same line. In this case, as shown in FIG. 13, a first open area (OP1) and a second open area (OP2) can be formed in the regions of the two metal pattern layers (130) that overlap with the first non-contact pad (170A), respectively. That is, the first open region (OP1) may be formed on the metal pattern layer (131G1) located on the lowest insulating layer (111), and the second open region (OP2) may be formed on the metal pattern layer (131G2) located on the next-highest insulating layer (112). Each metal pattern layer may be a ground pattern (131G1, 131G2). The method according to the present embodiment may be useful when the first and second insulating layers (111, 112) are thin.

[0078] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0080] 200: Semiconductor package 100: Package substrate 110: Substrate body 110a, 110b, 110c: Insulating layer 130L: Wiring layer 130G: Grounding pattern 130: Metal pattern layer 140: Contact pad 140A: First contact pad (or differential signal pad): 140A1: 1st signal pad 140A2: 2nd signal pad 140B: Second contact pad 150: Non-contact pad 150A: 1st non-contact pad 150B: 2nd non-contact pad 160: Contact bump 160A: First contact bump 160A1: 1st signal bump 160A2: 2nd signal bump 160B: Second contact bump 170: Non-contact bump 170A: 1st beacon contact bump 170B: 2nd beacon contact bump 210: 1st semiconductor chip 220: 2nd semiconductor chip 230: Adhesive layer 250: Wire 240: Bump ball 260: Underfield 290: Molding member 300: Electronic device 310: Circuit board (main board) 315A: First signal line 315B: Second signal line 315L: Land

Claims

Claim 1 A semiconductor package comprising: a plurality of insulating layers and a plurality of metal pattern layers each disposed on the plurality of insulating layers and each having a wiring layer; at least one semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer; and non-contact pads disposed on the lower surface of the package substrate and isolated from the wiring layer; wherein the lowest level metal pattern layer among the plurality of metal pattern layers has an open area that overlaps with at least one non-contact pad among the non-contact pads in a direction perpendicular to the upper surface of the package substrate, and the at least one non-contact pad is located in an area adjacent to the corner of the package substrate around one of the contact pads. Claim 2 In claim 1, the lowest level metal pattern layer includes a ground pattern, and the open area is a semiconductor package located on the ground pattern. Claim 3 delete Claim 4 In claim 1, the at least one semiconductor chip comprises a plurality of semiconductor chips, and the plurality of semiconductor chips comprises a memory chip and a processor chip that controls the operation of the memory chip, forming a semiconductor package. Claim 5 A semiconductor package comprising: a plurality of insulating layers and a metal pattern layer disposed on each of the plurality of insulating layers and each having a wiring layer; a first semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; a second semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer - the contact pads include first and second signal pads for transmitting a differential signal -; and non-contact pads disposed on the lower surface of the package substrate and separated from the wiring layer; wherein the non-contact pads include at least one non-contact pad disposed around the second signal pad and located adjacent to the corner of the package substrate than the second signal pad, and the metal pattern layer of the lowest level among the plurality of wiring layers has an open area that overlaps with at least one of the non-contact pads in a direction perpendicular to the upper surface of the package substrate. Claim 6 In claim 5, the semiconductor package wherein the first signal pad is positioned closer to the corner of the package substrate than the second signal pad. Claim 7 In claim 6, the semiconductor package wherein the at least one non-contact pad and the first signal pad are arranged side by side at the corner of the package substrate. Claim 8 A semiconductor package according to claim 5, wherein the first semiconductor chip includes a memory element, and the second semiconductor chip includes a processor chip configured to transmit and receive data with an external device using a serial interface. Claim 9 In paragraph 8, the semiconductor package is a semiconductor package that is a UFS (Universal Flash Storage) device. Claim 10 A circuit board having circuit lines; and a semiconductor package disposed on the circuit board; wherein the semiconductor package comprises a package substrate having a plurality of insulating layers and a plurality of metal pattern layers each disposed on the plurality of insulating layers and each having a wiring layer; at least one semiconductor chip disposed on the upper surface of the package substrate and connected to the wiring layer; contact pads disposed on the lower surface of the package substrate and connected to the wiring layer - the contact pads include a first signal pad and a second signal pad for transmitting a differential signal - and non-contact pads disposed on the lower surface of the package substrate and separated from the wiring layer, contact bumps each disposed on the contact pads, and non-contact bumps each disposed on the non-contact pads; the lowest level metal pattern layer among the plurality of metal pattern layers has an open area that overlaps with at least one non-contact pad among the non-contact pads in a direction perpendicular to the upper surface of the package substrate; and the circuit line comprises a first signal line connected to a contact bump on the first signal pad, a contact bump on the second signal pad, and the at least one An electronic device comprising a second signal line connected to a beacon bump on a beacon pad.

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