Display device and tile shaped display device including the same

Abstract

A display device is provided. The display device comprises a substrate including a display area in which a plurality of subpixels are arranged, a plurality of anode electrodes each corresponding to the plurality of subpixels, and a cathode electrode corresponding to the plurality of subpixels and spaced apart from each of the plurality of anode electrodes, wherein the anode electrode is positioned closer to the substrate than the cathode electrode by a step correction structure corresponding to at least one of the anode electrode or the cathode electrode.

Description

Technology Field

[0001] The present invention relates to a display device and a tile-type display device including the same. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. Display devices may be flat panel display devices such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays.

[0003] A light-emitting display device may include an organic light-emitting display device comprising an organic light-emitting diode element as a light-emitting element, or a light-emitting diode display device comprising an inorganic light-emitting diode element such as an LED (Light Emitting Diode) as a light-emitting element. In the case of an organic light-emitting display device, the brightness or gradation of the light from the organic light-emitting diode element is adjusted by adjusting the magnitude of the driving current applied to the organic light-emitting diode element. However, since the wavelength of the light emitted by the inorganic light-emitting diode element varies depending on the driving current, the image quality may be lowered if driven in the same way as the organic light-emitting diode element. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of reducing mounting defects of a light-emitting element and a tile-type display device including the same.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a substrate including a display area in which a plurality of subpixels are arranged, an active layer disposed on the substrate, a first gate metal layer disposed on a gate insulating film covering the active layer, a second gate metal layer disposed on a first interlayer insulating film covering the first gate metal layer, a first source metal layer disposed on a second interlayer insulating film covering the second gate metal layer, a second source metal layer disposed on a first planarization film covering the first source metal layer, a third source metal layer disposed on a second planarization film covering the second source metal layer, and a fourth source metal layer disposed on a third planarization film covering the third source metal layer. Here, the fourth source metal layer comprises a plurality of anode electrodes corresponding to each of the plurality of subpixels, and a cathode electrode corresponding to the plurality of subpixels and spaced apart from each of the plurality of anode electrodes. And, the anode electrode is positioned closer to the substrate than the cathode electrode by a step correction structure corresponding to at least one of the anode electrode or the cathode electrode.

[0007] The above display device may further include a plurality of light-emitting elements disposed on each of the plurality of anode electrodes and the cathode electrode, each corresponding to the plurality of subpixels. The plurality of light-emitting elements may be flip-chip type micro light-emitting diode elements.

[0008] The above step correction structure includes a correction hole corresponding to the anode electrode and penetrating the third flattening film, and the anode electrode can be placed on the second flattening film exposed through the correction hole.

[0009] The above step correction structure further includes an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode can be superimposed on the dummy pattern.

[0010] The display device may further include a first auxiliary inorganic insulating film covering the second planarization film. In this case, the third source metal layer may be disposed on the first auxiliary inorganic insulating film.

[0011] The display device may further include a second auxiliary inorganic insulating film covering the second source metal layer. In this case, the second planarization film may be disposed on the second auxiliary inorganic insulating film.

[0012] The correction hole may further penetrate the second planarization film and expose a portion of the auxiliary inorganic insulating film. In this case, the anode electrode may be placed on the exposed auxiliary inorganic insulating film. Additionally, the step correction structure may further include an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer.

[0013] The correction hole may further penetrate a portion of the second planarization film. In this case, the anode electrode may be placed on another portion of the second planarization film. Additionally, the step correction structure may further include an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer.

[0014] The above display device may further include a scan write wiring to which a scan write signal is applied, a scan initialization wiring to which a scan initialization signal is applied, a sweep signal wiring to which a sweep signal is applied, a first data wiring to which a first data voltage is applied, and a second data wiring to which a second data voltage is applied. Each of the plurality of subpixels may be connected to the scan write wiring, the scan initialization wiring, the sweep signal wiring, the first data wiring, and the second data wiring. Each of the plurality of subpixels may include a first pixel driver that generates a control current according to the first data voltage of the first data wiring, a second pixel driver that generates a driving current applied to the anode electrode according to the second data voltage of the second data wiring, and a third pixel driver that controls the period for applying the driving current to the light-emitting element according to the control current of the first pixel driver. And, the first pixel driving unit may include a first transistor that generates the control current according to the first data voltage, a second transistor that applies the first data voltage of the first data wiring to the first electrode of the first transistor according to the scan write signal, a third transistor that applies the initial voltage of the initial voltage wiring to the gate electrode of the first transistor according to the scan initialization signal, a fourth transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal, and a first capacitor disposed between the sweep signal wiring and the gate electrode of the first transistor.

[0015] The display device may further comprise a first power line to which a first power voltage is applied, a second power line to which a second power voltage is applied, a first light-emitting line to which a first light-emitting signal is applied, and a scan control line to which a scan control signal is applied. The first pixel driving unit may further include a fifth transistor that connects the first power line to the first electrode of the first transistor according to the first light-emitting signal, a sixth transistor that connects the second electrode of the first transistor to the first node according to the first light-emitting signal, and a seventh transistor that connects the sweep signal line to the gate-off voltage line to which a gate-off voltage is applied according to the scan control signal.

[0016] The second pixel driving unit may include an eighth transistor that generates the driving current according to the second data voltage, a ninth transistor that applies the second data voltage of the second data wiring to the first electrode of the eighth transistor according to the scan write signal, a tenth transistor that applies the initialization voltage of the initialization voltage wiring to the gate electrode of the eighth transistor according to the scan initialization signal, and an eleventh transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal.

[0017] And, the second pixel driver may further include a 12th transistor that connects the first power wiring to the second node according to the scan control signal, a 13th transistor that connects the second power wiring to the first electrode of the ninth transistor according to the first light emission signal, a 14th transistor that connects the second power wiring to the second node according to the first light emission signal, and a second capacitor disposed between the gate electrode of the ninth transistor and the second node.

[0018] The third pixel driver may include a 15th transistor including a gate electrode connected to the third node, a 16th transistor connecting the first node to the initialization voltage wiring according to the scan control signal, a 17th transistor connecting the second electrode of the 15th transistor to the first electrode of the light-emitting element according to the second light-emitting signal, an 18th transistor connecting the first electrode of the light-emitting element to the initialization voltage wiring according to the scan control signal, and a third capacitor disposed between the first node and the initialization voltage wiring.

[0019] The display device may further comprise a test signal wiring to which a test signal is applied, and a third power wiring to which a third power supply voltage is applied. The third pixel driver may further include a 19th transistor that connects the first electrode of the light-emitting element to the third power wiring according to the test signal. And, the cathode electrode may be connected to the third power wiring.

[0020] The active layer may include a channel, a source electrode, and a drain electrode for each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, twelfth, thirteenth, eleventh, twelfth, twelfth, twelfth, twelfth, eighth, and twelfth transistors.

[0021] The first gate metal layer may include the gate electrodes of each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, twelfth, thirteenth, thirteenth, twelfth, thirteenth, thirteenth, thirteenth, and thirteenth transistors, and the first, third, and fifth capacitor electrodes which are one end of each of the first, second, and third capacitors.

[0022] The second gate metal layer may include second, fourth, and sixth capacitor electrodes, which are different ends of each of the first, second, and third capacitors.

[0023] The first source metal layer may include the initialization voltage wiring, the scan initialization wiring, the scan writing wiring, the first light-emitting wiring, the second light-emitting wiring, the first horizontal power wiring to which the first power supply voltage is applied, the sweep signal wiring, the gate off voltage wiring, the scan control wiring, the test signal wiring, and the third power auxiliary wiring to which the third power supply voltage is applied.

[0024] The second source metal layer may include the first data wiring, the first vertical power wiring to which the first power voltage is applied, the second data wiring, and the first anode connection electrode.

[0025] The first anode connection electrode can be connected to the drain electrode of the 17th transistor and the drain electrode of the 18th transistor.

[0026] The third source metal layer may include a third power wiring to which the third power voltage is applied, and a second anode connecting electrode connected to the first anode connecting electrode.

[0027] The display device may further include an anode pad disposed on the anode electrode corresponding to each of the plurality of subpixels, and a cathode pad disposed on the cathode electrode corresponding to each of the plurality of subpixels. Each of the plurality of light-emitting elements may include a base substrate, an n-type semiconductor disposed on one surface of the base substrate facing the substrate, an active layer disposed on a part of the n-type semiconductor, a p-type semiconductor disposed on the active layer, a first contact electrode disposed on the p-type semiconductor and facing the anode electrode, and a second contact electrode disposed on another part of the n-type semiconductor and facing the cathode electrode. The first contact electrode may be attached to the anode pad through an anode contact electrode, and the second contact electrode may be attached to the cathode pad through a cathode contact electrode. A tile-type display device according to an embodiment for solving the above problem comprises a plurality of display devices and a joint disposed between the plurality of display devices. One of the plurality of display devices comprises a substrate including a display area in which a plurality of subpixels are arranged, an active layer disposed on a first surface of the substrate, a gate insulating film covering the active layer, a first interlayer insulating film covering a first gate metal layer disposed on the gate insulating film, a second interlayer insulating film covering a second gate metal layer disposed on the first interlayer insulating film, a first planarization film covering a first source metal layer disposed on the second interlayer insulating film, a second planarization film covering a second source metal layer disposed on the first planarization film, a third planarization film covering a third source metal layer disposed on the second planarization film, and a fourth source metal layer disposed on the third planarization film. The fourth source metal layer comprises a plurality of anode electrodes corresponding to each of the plurality of subpixels, and a cathode electrode corresponding to the plurality of subpixels and spaced apart from each of the plurality of anode electrodes.The anode electrode is positioned closer to the substrate than the cathode electrode by a step correction structure corresponding to at least one of the anode electrode or the cathode electrode. The substrate may be made of glass. Any one of the display devices may further include a pad positioned on a first surface of the substrate, and a side wiring positioned on a first surface of the substrate, a second surface opposite to the first surface, and a side between the first surface and the second surface, and connected to the pad. Any one of the display devices may further include a connecting wiring positioned on the second surface of the substrate, and a flexible film connected to the connecting wiring through a conductive adhesive member. The side wiring may be connected to the connecting wiring. Any one of the display devices may be arranged in a matrix form with M rows and N columns. Any one of the display devices may further include a plurality of light-emitting elements corresponding to each of the plurality of subpixels and positioned on each of the plurality of anode electrodes and the cathode electrode. The plurality of light-emitting elements may be flip-chip type micro light-emitting diode elements. The step correction structure may include a correction hole corresponding to the anode electrode and penetrating the third planarization film. In this case, the anode electrode is placed on the second planarization film exposed through the correction hole. The step correction structure may further include an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer. In this case, the cathode electrode is superimposed on the dummy pattern. Any one of the display devices may further include a first auxiliary inorganic insulating film covering the second planarization film. In this case, the third source metal layer is placed on the first auxiliary inorganic insulating film. Any one of the display devices may further include a second auxiliary inorganic insulating film covering the second source metal layer. In this case, the second planarization film is placed on the second auxiliary inorganic insulating film.The correction hole may further penetrate the second planarization film and expose a portion of the auxiliary inorganic insulating film. In this case, the anode electrode is placed on the exposed auxiliary inorganic insulating film. The step correction structure may further include an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer. In this case, the cathode electrode is superimposed on the dummy pattern. The correction hole may further penetrate a portion of the second planarization film. In this case, the anode electrode is placed on another portion of the second planarization film. The step correction structure may further include an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer. In this case, the cathode electrode is superimposed on the dummy pattern. Any one of the display devices may further include an anode pad corresponding to each of the plurality of subpixels and placed on the anode electrode, and a cathode pad corresponding to each of the plurality of subpixels and placed on the cathode electrode. Each of the plurality of light-emitting elements may comprise a base substrate, an n-type semiconductor disposed on one surface of the base substrate facing the substrate, an active layer disposed on a part of the n-type semiconductor, a p-type semiconductor disposed on the active layer, a first contact electrode disposed on the p-type semiconductor and facing the anode electrode, and a second contact electrode disposed on another part of the n-type semiconductor and facing the cathode electrode. Here, the first contact electrode may be attached to the anode pad through an anode contact electrode, and the second contact electrode may be attached to the cathode pad through a cathode contact electrode.

[0028] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0029] A display device according to the embodiments includes an anode electrode corresponding to each of a plurality of subpixels and a cathode electrode corresponding to a plurality of subpixels. Here, the anode electrode is positioned closer to the substrate than the cathode electrode by means of a step correction structure corresponding to at least one of the anode electrode or the cathode electrode.

[0030] In addition, the light-emitting element disposed on the anode electrode and cathode electrode corresponding to each of the plurality of subpixels may be of the flip-chip type.

[0031] In this way, since the anode electrode is positioned closer to the substrate than the cathode electrode by the step correction structure, the step difference between the first and second contact electrodes of the flip-chip type light-emitting element can be compensated. Therefore, since placement defects of the light-emitting element can be reduced, the yield can be improved and the reliability of the display quality can be enhanced.

[0032] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0033] FIG. 1 is a plan view showing a display device according to one embodiment. Figure 2 is an example drawing showing one example of a pixel of Figure 1. Figure 3 is an example drawing showing another example of the pixel of Figure 1. FIG. 4 is a cross-sectional view showing an example of a display device cut along A-A' of FIG. 3. FIG. 5 is a block diagram showing a display device according to one embodiment. FIG. 6 is a circuit diagram showing a first subpixel according to one embodiment. FIG. 7 is a graph showing the wavelength of light emitted by the light-emitting element of the first subpixel, the wavelength of light emitted by the light-emitting element of the second subpixel, and the wavelength of light emitted by the light-emitting element of the third subpixel according to the driving current according to one embodiment. FIG. 8 is a graph showing the luminous efficiency of a light-emitting element of a first subpixel, the luminous efficiency of a light-emitting element of a second subpixel, and the luminous efficiency of a light-emitting element of a third subpixel according to a driving current according to one embodiment. FIG. 9 is an example drawing showing the operation of a display device during the Nth to N+2nd frame period. FIG. 10 is another example drawing showing the operation of a display device during the Nth to N+2nd frame period. FIG. 11 is a waveform diagram showing scan initialization signals, scan write signals, scan control signals, PWM light emission signals, PAM light emission signals, and sweep signals applied to subpixels placed on the k to k+5 row lines during the Nth frame period according to one embodiment. FIG. 12 is a waveform diagram showing the period during which a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAM light emission signal, and a k-th sweep signal are applied to each of the subpixels placed on the k-th row line during the N-th frame period according to one embodiment, and a driving current applied to the third node and the light-emitting element. FIG. 13 is a timing diagram showing the k-th sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the 15th transistor during the fifth and sixth periods according to one embodiment. FIGS. 14 to 17 are circuit diagrams showing the operation of the first subpixel during the first, second, third, and sixth periods of FIG. 12. FIG. 18 is a layout diagram showing a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one embodiment. Figure 19 is an enlarged layout diagram showing the area I of Figure 18 in detail. FIG. 20 is an enlarged layout diagram showing the area II of FIG. 18 in detail. Figure 21 is an enlarged layout diagram showing the III region of Figure 18 in detail. FIG. 22 is a layout diagram showing a third source metal layer of a first subpixel according to one embodiment. FIG. 23 is a layout diagram showing a fourth source metal layer of a first subpixel according to one embodiment. FIG. 24 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 18. FIG. 25 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 18. FIG. 26 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 18. FIG. 27 is a cross-sectional view showing an example of a display panel cut along E-E' of FIG. 18. FIG. 28 is a cross-sectional view showing an example of a display panel cut along F-F' of FIG. 18. FIG. 29 is a cross-sectional view showing an example of a display panel cut along G-G' of FIG. 18. FIG. 30 is a cross-sectional view showing an example of a display panel cut along H-H' of FIG. 18. FIG. 31 is a cross-sectional view showing an example of a display panel cut along I-I' of FIG. 18. FIG. 32 is a cross-sectional view showing an example of a display panel cut along J-J' of FIG. 18. FIG. 33 is a cross-sectional view showing a first embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 34 is a cross-sectional view showing a second embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 35 is a layout diagram showing a third source metal layer of a first subpixel according to a second embodiment. FIG. 36 is a cross-sectional view showing a third embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 37 is a cross-sectional view showing a fourth embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 38 is a cross-sectional view showing a fifth embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 39 is a cross-sectional view showing a sixth embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 40 is a perspective view showing a tile-type display device including a plurality of display devices according to one embodiment. Figure 41 is an enlarged layout diagram showing the L region of Figure 40 in detail. FIG. 42 is a cross-sectional view showing an example of a tile-type display device cut along N-N' of FIG. 41. Figure 43 is an enlarged layout diagram showing the M area of ​​Figure 40 in detail. FIG. 44 is a cross-sectional view showing an example of a tile-type display device cut along O-O' of FIG. 43. FIG. 45 is a block diagram showing a tile-type display device according to one embodiment. Specific details for implementing the invention

[0034] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0035] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0036] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0037] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0038] Specific embodiments will be described below with reference to the attached drawings.

[0039] FIG. 1 is a plan view showing a display device according to one embodiment. FIG. 2 is an example drawing showing one example of a pixel of FIG. 1. FIG. 3 is an example drawing showing another example of a pixel of FIG. 1.

[0040] Referring to FIG. 1, a display device including a flat display panel (100) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0041] The display panel (100) may be formed as a rectangular plane having a long side in a first direction (DR1) and a short side in a second direction (DR2) that intersects the first direction (DR1). The corner where the long side in the first direction (DR1) and the short side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0042] The display panel (100) may further include pixels (PX), scan lines extending in a first direction (DR1), and data lines extending in a second direction (DR2) to display an image. The pixels (PX) may be arranged in a matrix form in the first direction (DR1) and the second direction (DR2).

[0043] Each of the pixels (PX) may include a plurality of subpixels (RP, GP, BP) as shown in FIGS. 2 and FIGS. 3. FIGS. 2 and FIGS. 3 illustrate that each of the pixels (PX) includes three subpixels (RP, GP, BP), namely a first subpixel (RP), a second subpixel (GP), and a third subpixel (BP), but the embodiments of the present specification are not limited thereto.

[0044] The first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) can be connected to any one of the data lines and at least one of the scan lines.

[0045] Each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may have a rectangular, square, or rhombus-shaped planar form.

[0046] For example, as shown in FIG. 2, each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2).

[0047] Alternatively, as shown in FIG. 3, each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may have a planar shape of a square or a rhombus that includes sides having the same length in the first direction (DR1) and the second direction (DR2).

[0048] As shown in FIG. 2, the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may be arranged in a first direction (DR1). Alternatively, either one of the second subpixel (GP) and the third subpixel (BP) and the first subpixel (RP) may be arranged in a first direction (DR1), and the other one and the first subpixel (RP) may be arranged in a second direction (DR2).

[0049] For example, as shown in FIG. 3, the first subpixel (RP) and the second subpixel (GP) may be arranged in the first direction (DR1), and the first subpixel (RP) and the third subpixel (BP) may be arranged in the second direction (DR2).

[0050] Alternatively, either one of the first subpixel (RP) and the third subpixel (BP) and the second subpixel (GP) may be arranged in the first direction (DR1), and the other one and the second subpixel (GP) may be arranged in the second direction (DR2). Alternatively, either one of the first subpixel (RP) and the second subpixel (GP) and the third subpixel (BP) may be arranged in the first direction (DR1), and the other one and the third subpixel (BP) may be arranged in the second direction (DR2).

[0051] A first subpixel (RP) emits a first light, a second subpixel (GP) emits a second light that is a different color from the first light, and a third subpixel (BP) can emit a third light that is a different color from the first light and the second light.

[0052] For example, the first light may be light in the red wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the blue wavelength band. Here, the red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0053] Each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element. For example, the inorganic light-emitting element may be a flip-chip type micro LED (Light Emitting Diode), but the embodiments of this specification are not limited thereto.

[0054] As shown in FIGS. 2 and 3, the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be substantially the same, but the embodiments of this specification are not limited thereto. At least one of the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be different from the other. Or, any two of the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be substantially the same, and the remaining one may be different from the two. Or, the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be different from each other.

[0055] FIG. 4 is a cross-sectional view showing an example of a display device cut along A-A' of FIG. 3.

[0056] Referring to FIG. 4, a thin film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin film transistor layer (TFTL) may be a layer on which thin film transistors (TFTs) are formed. A detailed description of the thin film transistor layer (TFTL) will be provided later.

[0057] The substrate (SUB) may be a base substrate or base member for supporting the display device (10). The substrate (SUB) may be a rigid substrate made of glass material. Alternatively, the substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. In this case, the substrate (SUB) may include an insulating material such as a polymer resin such as polyimide (PI).

[0058] A light-emitting element layer (EML) can be placed on the thin-film transistor layer (TFTL).

[0059] The light-emitting element layer (EML) includes anode electrodes (AND), cathode electrodes (CSD), and light-emitting elements (LE).

[0060] In addition, the light-emitting element layer (EML) may further include an anode contact electrode (ANDC) between the light-emitting element (LE) and the anode electrode (AND), and a cathode contact electrode (CSDC) between the light-emitting element (LE) and the cathode electrode (CSD).

[0061] Each of the light-emitting elements (LE) may include a base substrate (SPUB), an n-type semiconductor (NSEM), an active layer (MQW), a p-type semiconductor (PSEM), a first contact electrode (CTE1), and a second contact electrode (CTE2).

[0062] The base substrate (SPUB) may be a sapphire substrate, but the embodiments of this specification are not limited thereto.

[0063] The n-type semiconductor (NSEM) can be placed on one side of the base substrate (PSUB). For example, the n-type semiconductor (NSEM) can be placed on the lower side of the base substrate (SSUB). The n-type semiconductor (NSEM) can be made of GaN doped with n-type conductive dopants such as Si, Ge, Sn, etc.

[0064] The active layer (MQW) may be disposed on a portion of one surface of an n-type semiconductor (NSEM). The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0065] A p-type semiconductor (PSEM) can be disposed on one side of an active layer (MQW). The p-type semiconductor (PSEM) can be made of GaN doped with p-type conductive dopants such as Mg, Zn, Ca, Se, Ba, etc.

[0066] A first contact electrode (CTE1) is disposed on a p-type semiconductor (PSEM), and a second contact electrode (CTE2) may be disposed on another part of one side of an n-type semiconductor (NSEM). The other part of the side of the n-type semiconductor (NSEM) on which the second contact electrode (CTE2) is disposed may be disposed apart from the part of the side of the n-type semiconductor (NSEM) on which the active layer (MQW) is disposed.

[0067] The first contact electrode (CTE1) and the anode electrode (AND) can be bonded to each other through the anode contact electrode (ANDC).

[0068] The second contact electrode (CTE2) and the cathode electrode (CSD) can be bonded to each other through the cathode contact electrode (CSDC).

[0069] The anode contact electrode (ANDC) and cathode contact electrode (CSDC) may be conductive adhesive members such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP).

[0070] Alternatively, the light-emitting element (LE) does not include an anode contact electrode (ANDC) and a cathode contact electrode (CSDC), and instead, the first contact electrode (CTE1) and the anode electrode (AND) and the second contact electrode (CTE2) and the cathode electrode (CSD) can be bonded through a soldering process.

[0071] The light-emitting element (LE) can be a flip-chip type micro LED.

[0072] This flip-chip type light-emitting element (LE) includes a first contact electrode (CTE1) disposed on a p-type semiconductor (PSEM), and a second contact electrode (CTE2) on an n-type semiconductor (NSEM) exposed by removing a portion of the active layer (MQW) and the p-type semiconductor (PSEM). That is, the flip-chip type light-emitting element (LE) forms a mesa structure in which the first contact electrode (CTE1) protrudes more than the second contact electrode (CTE2).

[0073] Accordingly, a display panel (100) according to one embodiment may include a step correction structure for correcting the step difference between a first contact electrode (CTE1) and a second contact electrode (CTE2).

[0074] For example, as shown in FIG. 4, the step correction structure may include a correction hole (CRH) that penetrates at least a portion of the top organic film of the thin-film transistor layer (TFTL).

[0075] Each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) includes a light-emitting element (LE) connected to an anode electrode (AND) and a cathode electrode (CSD). Since the anode electrode (AND) corresponds to each of the multiple subpixels (RP, GP, BP), it can be referred to as a pixel electrode. Also, since the cathode electrode (CSD) corresponds to the multiple subpixels (RP, GP, BP) in common, it can be referred to as a common electrode.

[0076] The anode electrodes (AND) and cathode electrodes (CSD) may include highly reflective metallic materials such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0077] In the light-emitting element (LE), the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) may each be several to several hundred μm. For example, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of the light-emitting element (LE) may each be approximately 100 μm or less.

[0078] Light-emitting elements (LEs) can be formed by growing on a semiconductor substrate such as a silicon wafer. Each light-emitting element (LE) can be transferred directly from the silicon wafer onto the anode electrode (AND) and cathode electrode (CSD) of a substrate (SUB). Alternatively, each light-emitting element (LE) can be transferred onto the anode electrode (AND) and cathode electrode (CSD) of the substrate (SUB) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0079] The light-emitting diode layer (EML) may further include a protective film (PAS) covering the edges of the anode electrode (AND) and the cathode electrode (CSD), respectively.

[0080] For example, the protective film (PAS) can be formed from inorganic films such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0081] FIG. 5 is a block diagram showing a display device according to one embodiment.

[0082] Referring to FIG. 5, a display device (10) according to one embodiment includes a display panel (100), a scan driving unit (110), a source driving unit (200), a timing control unit (300), and a power supply unit (400).

[0083] The display area (DA) of the display panel (100) may include subpixels (RP, GP, BP) for displaying an image, scan write lines (GWL) connected to the subpixels (RP, GP, BP), scan initialization lines (GIL), scan control lines (GCL), sweep signal lines (SWL), PWM light emission lines (PWEL), PAM light emission lines (PAEL), PWM data lines (DL), first PAM data lines (RDL), second PAM data lines (GDL), and third PAM data lines (BDL).

[0084] Scan write lines (GWL), scan initialization lines (GIL), scan control lines (GCL), sweep signal lines (SWL), PWM light-emitting lines (PWEL), and PAM light-emitting lines (PAEL) may be extended in a first direction (DR1) and arranged in a second direction (DR2) that intersects the first direction (DR1). PWM data lines (DL), first PAM data lines (RDL), second PAM data lines (GDL), and third PAM data lines (BDL) may be extended in a second direction (DR2) and arranged in the first direction (DR1). The first PAM data lines (RDL) may be electrically connected to each other, the second PAM data lines (GDL) may be electrically connected to each other, and the third PAM data lines (BDL) may be electrically connected to each other.

[0085] The subpixels (RP, GP, BP) may include first subpixels (RP) emitting a first light, second subpixels (GP) emitting a second light, and third subpixels (BP) emitting a third light. The first light refers to light in the red wavelength band, the second light refers to light in the green wavelength band, and the third light refers to light in the blue wavelength band. For example, the main peak wavelength of the first light may be located approximately 600 nm to 750 nm, the main peak wavelength of the second light may be located approximately 480 nm to 560 nm, and the main peak wavelength of the third light may be located approximately 370 nm to 460 nm.

[0086] Each of the subpixels (RP, GP, BP) may be connected to any one of the scan write lines (GWL), any one of the scan initialization lines (GIL), any one of the scan control lines (GCL), any one of the sweep signal lines (SWL), any one of the PWM light emission lines (PWEL), and any one of the PAM light emission lines (PAEL). Additionally, each of the first subpixels (RP) may be connected to any one of the PWM data lines (DL) and any one of the first PAM data lines (RDL). Additionally, each of the second subpixels (GP) may be connected to any one of the PWM data lines (DL) and any one of the second PAM data lines (GDL). Additionally, each of the third subpixels (BP) may be connected to any one of the PWM data lines (DL) and any one of the third PAM data lines (BDL).

[0087] A scan driver (110) for applying signals to scan write wires (GWL), scan initialization wires (GIL), scan control wires (GCL), sweep signal wires (SPWL), PWM light-emitting wires (PWEL), and PAM light-emitting wires (PAEL) may be disposed in the non-display area (NDA) of the display panel (100). In FIG. 5, the scan driver (110) is illustrated as being disposed on one edge of the first direction (DR1) of the display panel (100), but is not limited thereto. The scan driver (110) may be disposed on both edges of the first direction (DR1) of the display panel (100).

[0088] The scan driving unit (110) may include a first scan signal driving unit (111), a second scan signal driving unit (112), a sweep signal driving unit (113), and a light emission signal driving unit (114).

[0089] The first scan signal driver (111) can receive a first scan drive control signal (GDCS1) from the timing control unit (300). The first scan signal driver (111) can output scan initialization signals to the scan initialization wires (GIL) and output scan write signals to the scan write wires (GWL) according to the first scan drive control signal (GDCS1). That is, the first scan signal driver (111) can output two scan signals together, namely scan initialization signals and scan write signals.

[0090] The second scan signal driving unit (112) can receive a second scan driving control signal (GDCS2) from the timing control unit (300). The second scan signal driving unit (112) can output scan control signals to the scan control wires (GCL) according to the second scan driving control signal (GDCS2).

[0091] The sweep signal driver (113) can receive a first light emission control signal (ECS1) and a sweep control signal (SPCS) from the timing control unit (300). The sweep signal driver (113) can output PWM light emission signals to PWM light emission wires (PWEL) and sweep signals to sweep signal wires (SWPL) according to the first light emission control signal (ECS1). That is, the sweep signal driver (113) can output PWM light emission signals and sweep signals together.

[0092] The light emission signal output unit (114) can receive a second light emission control signal (ECS2) from the timing control unit (300). The light emission signal output unit (114) can output PAM light emission signals to the PAM light emission wiring (PAEL) according to the second light emission control signal (ECS2).

[0093] The timing control unit (300) receives digital video data (DATA) and timing signals (TS). The timing control unit (300) can generate a scan timing control signal (STCS) to control the operation timing of the scan drive unit (110) according to the timing signals (TS). The scan timing control signal (STCS) can generate a first scan drive control signal, a second scan drive control signal (GDSC2), a first light emission control signal (ECS1), a second light emission control signal (ECS2), and a sweep control signal (SWCS). Additionally, the timing control unit (300) can generate a source control signal (DCS) to control the operation timing of the source drive unit (200).

[0094] The timing control unit (300) outputs a first scan drive control signal (GDCS1), a second scan drive control signal (GDSC2), a first light emission control signal (ECS1), a second light emission control signal (ECS2), and a sweep control signal (SWCS) to the scan drive unit (110). The timing control unit (300) outputs digital video data (DATA) and a PWM control signal (DCS) to the source drive unit (200).

[0095] The source driver (200) converts digital video data (DATA) into analog PWM data voltages and outputs them to PWM data wires (DL). As a result, subpixels (RP, GP, BP) are selected by the scan write signals of the scan driver (110), and PWM data voltages can be supplied to the selected subpixels (RP, GP, BP).

[0096] The power supply unit (400) can output a first PAM data voltage to the first PAM data lines (RDL) in common, output a second PAM data voltage to the second PAM data lines (GDL) in common, and output a third PAM data voltage to the third PAM data lines (BDL) in common. Additionally, the power supply unit (400) can generate a plurality of power voltages and output them to the display panel (100).

[0097] The power supply unit (400) can output a first power voltage (VDD1), a second power voltage (VDD2), a third power voltage (VSS), an initialization voltage (VINT), a gate-on voltage (VGL), and a gate-off voltage (VGH) to the display panel (100). The first power voltage (VDD1) and the second power voltage (VDD2) may be high-potential driving voltages for driving the light-emitting elements of each of the subpixels (RP, GP, BP). The third driving voltage (VINT) may be a low-potential driving voltage for driving the light-emitting elements of each of the subpixels (RP, GP, BP). The initialization voltage (VINT) and the gate-off voltage (VGH) are applied to each of the subpixels (RP, GP, BP), and the gate-on voltage (VGL) and the gate-off voltage (VGH) may be applied to the scan driving unit (110).

[0098] Each of the source driving unit (200), the timing control unit (300), and the power supply unit (400) can be formed as an integrated circuit. Additionally, the source driving unit (200) can be formed as a plurality of integrated circuits.

[0099] FIG. 6 is a circuit diagram showing a first subpixel according to one embodiment.

[0100] Referring to FIG. 6, a first subpixel (RP) according to one embodiment may be connected to the k-th (k is a positive integer) scan write wire (GWLk), the k-th scan initialization wire (GILk), the k-th scan control wire (GCLk), the k-th sweep signal wire (SWPLk), the k-th PWM light emission wire (PWELk), and the k-th PAM light emission wire (PAELk). Additionally, the first subpixel (RP) may be connected to the j-th PWM data wire (DLj) and the first PAM data wire (RDL). Additionally, the first subpixel (RP) may be connected to a first power line (VDL1) to which a first power voltage (VDD1) is applied, a second power line (VDL2) to which a second power voltage (VDD2) is applied, a third power line (VSL) to which a third power voltage (VSS) is applied, an initialization voltage line (VIL) to which an initialization voltage (VINT) is applied, and a gate-off voltage line (VGHL) to which a gate-off voltage (VGH) is applied. Meanwhile, for convenience of explanation, the j-th PWM data line (DLj) may be referred to as the first data line, and the first PAM data line (RDL) may be referred to as the second data line.

[0101] The first subpixel (RP) may include a light-emitting element (EL), a first pixel driver (PDU1), a second pixel driver (PDU2), and a third pixel driver (PDU3).

[0102] The first pixel driver (PDU1), the second pixel driver (PDU2), and the third pixel driver (PDU3) are interconnected, and the light-emitting element (EL) emits light according to the driving current (Ids) generated by the second pixel driver (PDU2).

[0103] A light-emitting element (EL) may be placed between the 17th transistor (T17) and the 3rd power line (VSL). The first electrode of the light-emitting element (EL) may be connected to the second electrode of the 17th transistor (T17), and the second electrode may be connected to the 3rd power line (VSL). The first electrode of the light-emitting element (EL) may be an anode electrode (i.e., a pixel electrode), and the second electrode may be a cathode electrode (i.e., a common electrode). The light-emitting element (EL) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor placed between the first electrode and the second electrode. For example, the light-emitting element (EL) may be a micro light-emitting diode made of an inorganic semiconductor, but is not limited thereto.

[0104] The first pixel driver (PDU1) generates a control current (Ic) according to the j-th PWM data voltage of the j-th PWM data line (DLj) and controls the voltage of the third node (N3) of the third pixel driver (PDU3). Since the pulse width of the driving current (Ids) flowing to the light-emitting element (EL) can be adjusted by the control current (Ic) of the first pixel driver (PDU1), the first pixel driver (PDU1) may be a pulse width modulation unit (PWM unit) that performs pulse width modulation of the driving current (Ids) flowing to the light-emitting element (EL).

[0105] The first pixel driver (PDU1) may include first to seventh transistors (T1 to T7) and a first capacitor (C1).

[0106] The first transistor (T1) controls the control current (Ic) flowing between the second electrode and the first electrode according to the PWM data voltage applied to the gate electrode.

[0107] The second transistor (T2) is turned on by the k-th scan write signal of the k-th scan write wire (GWLk) to supply the PWM data voltage of the j-th PWM data wire (DLj) to the first electrode of the first transistor (T1). The gate electrode of the second transistor (T2) is connected to the k-th scan write wire (GWLk), the first electrode is connected to the j-th PWM data wire (DLj), and the second electrode can be connected to the first electrode of the first transistor (T1).

[0108] The third transistor (T3) is turned on by the k-th scan initialization signal of the k-th scan initialization wiring (GILk) to connect the initialization voltage wiring (VIL) to the gate electrode of the first transistor (T1). As a result, during the period when the third transistor (T3) is turned on, the gate electrode of the first transistor (T1) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL). At this time, the gate-on voltage (VGL) of the k-th scan initialization signal may be different from the initialization voltage (VINT) of the initialization voltage wiring (VIL). In particular, since the difference voltage between the gate-on voltage (VGL) and the initialization voltage (VINT) is greater than the threshold voltage of the third transistor (T3), the third transistor (T3) can be stably turned on even after the initialization voltage (VINT) is applied to the gate electrode of the first transistor (T1). Therefore, when the third transistor (T3) is turned on, an initialization voltage (VINT) can be stably applied to the gate electrode of the first transistor (T1) regardless of the threshold voltage of the third transistor (T3).

[0109] The third transistor (T3) may include a plurality of transistors connected in series. For example, the third transistor (T3) may include a first sub-transistor (T31) and a second sub-transistor (T32). This prevents the voltage of the gate electrode of the first transistor (T1) from leaking through the third transistor (T3). The gate electrode of the first sub-transistor (T31) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the gate electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the second sub-transistor (T32). The gate electrode of the second sub-transistor (T32) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the second electrode of the first sub-transistor (T31), and the second electrode may be connected to the initialization voltage wiring (VIL).

[0110] The fourth transistor (T4) is turned on by the k-th scan write signal of the k-th scan write wiring (GWLk) to connect the gate electrode of the first transistor (T1) and the second electrode. As a result, the first transistor (T1) can operate as a diode during the period when the fourth transistor (T4) is turned on.

[0111] The fourth transistor (T4) may include a plurality of transistors connected in series. For example, the fourth transistor (T4) may include a third sub-transistor (T41) and a fourth sub-transistor (T42). This prevents the voltage of the gate electrode of the first transistor (T1) from leaking through the fourth transistor (T4). The gate electrode of the third sub-transistor (T41) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the fourth sub-transistor (T42). The gate electrode of the fourth sub-transistor (T42) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the third sub-transistor (T41), and the second electrode may be connected to the gate electrode of the first transistor (T1).

[0112] The fifth transistor (T5) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the first electrode of the first transistor (T1) to the first power wiring (VDL1). The gate electrode of the fifth transistor (T5) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the first power wiring (VDL1), and the second electrode can be connected to the first electrode of the first transistor (T1).

[0113] The sixth transistor (T6) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the second electrode of the first transistor (T1) to the third node (N3) of the third pixel driver (PDU3). The gate electrode of the sixth transistor (T6) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the second electrode of the first transistor (T1), and the second electrode can be connected to the third node (N3) of the third pixel driver (PDU3).

[0114] The seventh transistor (T7) can be turned on by the k-th scan control signal of the k-th scan control line (GCLk) to supply the gate off voltage (VGH) of the gate off voltage line (VGHL) to the first node (N1) connected to the k-th sweep signal line (SWPLk). As a result, the voltage change of the gate electrode of the first transistor (T1) by the first capacitor (C1) can be prevented from being reflected in the k-th sweep signal of the k-th sweep signal line (SWPLk) during the period when the initialization voltage (VINT) is applied to the gate electrode of the first transistor (T1) and the period when the PWM data voltage of the j-th PWM data line (DLj) and the threshold voltage (Vth1) of the first transistor (T1) are programmed. The gate electrode of the seventh transistor (T7) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the gate off voltage wiring (VGHL), and the second electrode can be connected to the first node (N1).

[0115] The first capacitor (C1) can be placed between the gate electrode of the first transistor (T1) and the first node (N1). One electrode of the first capacitor (C1) can be connected to the gate electrode of the first transistor (T1), and the other electrode can be connected to the first node (N1).

[0116] The first node (N1) may be the contact of the k-th sweep signal wiring (SWPLk), the second electrode of the seventh transistor (T7), and the other electrode of the first capacitor (C1).

[0117] The second pixel driver (PDU2) generates a driving current (Ids) applied to a light-emitting element (EL) according to the first PAM data voltage of the first PAM data wiring (RDL). The second pixel driver (PDU2) may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driver (PDU2) may be a constant current generator that generates a constant driving current (Ids) according to the first PAM data voltage.

[0118] Additionally, the second pixel driver (PDU2) of each of the first subpixels (RP) can receive the same first PAM data voltage regardless of the brightness of the first subpixel (RP) and generate the same driving current (Ids). Similarly, the second pixel driver (PDU2) of each of the second subpixels (GP) can receive the same second PAM data voltage regardless of the brightness of the second subpixel (GP) and generate the same driving current (Ids). The third pixel driver (PDU3) of each of the third subpixels (BP) can receive the same third PAM data voltage regardless of the brightness of the third subpixel (BP) and generate the same driving current (Ids).

[0119] The second pixel driver (PDU2) may include eight to fourteen transistors (T8 to T14) and a second capacitor (C2).

[0120] The eighth transistor (T8) controls the driving current (Ids) flowing to the light-emitting element (EL) according to the voltage applied to the gate electrode.

[0121] The ninth transistor (T9) is turned on by the k-th scan write signal of the k-th scan write wiring (GWLk) to supply the first PAM data voltage of the first PAM data wiring (RDL) to the first electrode of the eighth transistor (T8). The gate electrode of the eighth transistor (T8) is connected to the k-th scan write wiring (GWLk), the first electrode is connected to the first PAM data wiring (RDL), and the second electrode can be connected to the first electrode of the eighth transistor (T1).

[0122] The 10th transistor (T10) is turned on by the k-th scan initialization signal of the k-th scan initialization wire (GILk) to connect the initialization voltage wire (VIL) to the gate electrode of the 8th transistor (T8). As a result, during the period when the 10th transistor (T10) is turned on, the gate electrode of the 8th transistor (T8) can be discharged to the initialization voltage (VINT) of the initialization voltage wire (VIL). At this time, the gate-on voltage (VGL) of the k-th scan initialization signal may be different from the initialization voltage (VINT) of the initialization voltage wire (VIL). In particular, since the difference voltage between the gate-on voltage (VGL) and the initialization voltage (VINT) is greater than the threshold voltage of the 10th transistor (T10), the 10th transistor (T10) can be stably turned on even after the initialization voltage (VINT) is applied to the gate electrode of the 8th transistor (T8). Therefore, when the 10th transistor (T10) is turned on, an initialization voltage (VINT) can be stably applied to the gate electrode of the 8th transistor (T8) regardless of the threshold voltage of the 10th transistor (T10).

[0123] The tenth transistor (T10) may include a plurality of transistors connected in series. For example, the tenth transistor (T10) may include a fifth sub-transistor (T101) and a sixth sub-transistor (T102). This prevents the voltage of the gate electrode of the eighth transistor (T8) from leaking through the tenth transistor (T10). The gate electrode of the fifth sub-transistor (T101) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the gate electrode of the eighth transistor (T8), and the second electrode may be connected to the first electrode of the sixth sub-transistor (T102). The gate electrode of the sixth sub-transistor (T102) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the second electrode of the fifth sub-transistor (T101), and the second electrode may be connected to the initialization voltage wiring (VIL).

[0124] The 11th transistor (T11) is turned on by the k-th scan write signal of the k-th scan write wiring (GWLk) to connect the gate electrode of the 8th transistor (T8) and the 2nd electrode. As a result, the 8th transistor (T8) can operate as a diode during the period when the 11th transistor (T11) is turned on.

[0125] The eleventh transistor (T11) may include a plurality of transistors connected in series. For example, the eleventh transistor (T11) may include a seventh sub-transistor (T111) and an eighth sub-transistor (T112). This prevents the voltage of the gate electrode of the eighth transistor (T8) from leaking through the eleventh transistor (T11). The gate electrode of the seventh sub-transistor (T111) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the eighth transistor (T8), and the second electrode may be connected to the first electrode of the eighth sub-transistor (T112). The gate electrode of the eighth sub-transistor (T112) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the seventh sub-transistor (T111), and the second electrode may be connected to the gate electrode of the eighth transistor (T8).

[0126] The 12th transistor (T12) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the first electrode of the 8th transistor (T8) to the second power supply wiring (VDL2). The gate electrode of the 12th transistor (T12) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the first power supply wiring (VDL1), and the second electrode can be connected to the first electrode of the 8th transistor (T8).

[0127] The 13th transistor (T13) is turned on by the k-th scan control signal of the k-th scan control wire (GCLk) to connect the first power wire (VDL1) to the second node (N2). The gate electrode of the 13th transistor (T13) is connected to the k-th scan control wire (GCLk), the first electrode is connected to the first power wire (VDL1), and the second electrode can be connected to the second node (N2).

[0128] The 14th transistor (T14) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the second power wiring (VDL2) to the second node (N2). As a result, when the 14th transistor (T14) is turned on, the second power voltage (VDD2) of the second power wiring (VDL2) can be supplied to the second node (N2). The gate electrode of the 14th transistor (T14) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the second power wiring (VDL2), and the second electrode can be connected to the second node (N2).

[0129] The second capacitor (C2) can be placed between the gate electrode of the eighth transistor (T8) and the second node (N2). One electrode of the second capacitor (C2) can be connected to the gate electrode of the eighth transistor (T8), and the other electrode can be connected to the second node (N2).

[0130] The second node (N2) may be a contact point between the second electrode of the 13th transistor (T13), the second electrode of the 14th transistor (T14), and the other electrode of the second capacitor (C2).

[0131] The third pixel driver (PDU3) adjusts the period during which the driving current (Ids) is applied to the light-emitting element (EL) according to the voltage of the third node (N3).

[0132] The third pixel driver (PDU3) may include 15 to 19 transistors (T15 to T19) and a third capacitor (C3).

[0133] The 15th transistor (T15) is turned on or turned off depending on the voltage of the 3rd node (N3). When the 15th transistor (T15) is turned on, the driving current (Ids) of the 8th transistor (T8) is supplied to the light-emitting element (EL), and when the 15th transistor (T15) is turned off, the driving current (Ids) of the 8th transistor (T8) may not be supplied to the light-emitting element (EL). Therefore, the turn-on period of the 15th transistor (T15) may be substantially the same as the light-emitting period of the light-emitting element (EL). The gate electrode of the 15th transistor (T15) is connected to the 3rd node (N3), the first electrode is connected to the second electrode of the 8th transistor (T8), and the second electrode may be connected to the first electrode of the 17th transistor (T17).

[0134] The 16th transistor (T16) is turned on by the k-th scan control signal of the k-th scan control wire (GCLk) to connect the initialization voltage wire (VIL) to the third node (N3). As a result, during the period when the 16th transistor (T16) is turned on, the third node (N3) can be discharged to the initialization voltage of the initialization voltage wire (VIL).

[0135] The 16th transistor (T16) may include a plurality of transistors connected in series. For example, the 16th transistor (T16) may include a 9th sub-transistor (T161) and a 10th sub-transistor (T162). This prevents the voltage of the 3rd node (N3) from leaking through the 16th transistor (T16). The gate electrode of the 9th sub-transistor (T161) may be connected to the k-th scan control wiring (GCLk), the first electrode may be connected to the 3rd node (N3), and the second electrode may be connected to the first electrode of the 10th sub-transistor (T162). The gate electrode of the 10th sub-transistor (T162) may be connected to the k-th scan control wiring (GCLk), the first electrode may be connected to the second electrode of the 9th sub-transistor (T161), and the second electrode may be connected to the initialization voltage wiring (VIL).

[0136] The 17th transistor (T17) is turned on by the k-th PAM light emission signal of the k-th PAM light emission wiring (PAELk) to connect the second electrode of the 15th transistor (T15) to the first electrode of the light-emitting element (EL). The gate electrode of the 17th transistor (T17) is connected to the k-th PAM light emission wiring (PAELk), the first electrode is connected to the second electrode of the 15th transistor (T15), and the second electrode can be connected to the first electrode of the light-emitting element (EL).

[0137] The 18th transistor (T18) is turned on by the k-th scan control signal of the k-th scan control wiring (GCLk) to connect the initialization voltage wiring (VIL) to the first electrode of the light-emitting element (EL). As a result, during the period when the 18th transistor (T18) is turned on, the first electrode of the light-emitting element (EL) can be discharged to the initialization voltage of the initialization voltage wiring (VIL). The gate electrode of the 18th transistor (T18) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the first electrode of the light-emitting element (EL), and the second electrode can be connected to the initialization voltage wiring (VIL).

[0138] The 19th transistor (T19) is turned on by a test signal from the test signal wiring (TSTL) to connect the first electrode of the light-emitting element (EL) to the third power wiring (VSL). The gate electrode of the 19th transistor (T19) is connected to the test signal wiring (TSTL), the first electrode is connected to the first electrode of the light-emitting element (EL), and the second electrode can be connected to the third power wiring (VSL).

[0139] A third capacitor (C3) may be placed between the third node (N3) and the initialization voltage wiring (VIL). One electrode of the third capacitor (C3) may be connected to the third node (N3), and the other electrode may be connected to the initialization voltage wiring (VIL).

[0140] The third node (N3) may be a contact of the second electrode of the sixth transistor (T6), the gate electrode of the fifth transistor (T15), the first electrode of the ninth sub-transistor (T161), and one electrode of the third capacitor (C3).

[0141] For each of the first to 19 transistors (T1 to T19), either the first electrode or the second electrode may be a source electrode and the other may be a drain electrode. The active layer of each of the first to 19 transistors (T1 to T19) may be formed from any one of polysilicon, amorphous silicon, and oxide semiconductor. When the active layer of each of the first to 19 transistors (T1 to T19) is polysilicon, it may be formed by a low-temperature polysilicon (LTPS) process.

[0142] Additionally, although FIG. 6 describes the first to ninth transistors (T1 to T19) as being formed as P-type MOSFETs, the embodiments of this specification are not limited thereto. For example, each of the first to ninth transistors (T1 to T19) may be formed as N-type MOSFETs.

[0143] Alternatively, to increase the black expression capability of the light-emitting element (EL) by blocking leakage current, the first sub-transistor (T31) and the second sub-transistor (T32) of the third transistor (T3) in the first sub-pixel (RP), the third sub-transistor (T41) and the fourth sub-transistor (T42) of the fourth transistor (T4), the fifth sub-transistor (T101) and the sixth sub-transistor (T102) of the tenth transistor (T10), and the seventh sub-transistor (T111) and the eighth sub-transistor (T112) of the eleventh transistor (T11) may be formed as N-type MOSFETs. In this case, the gate electrode of the third sub-transistor (T41) of the fourth transistor (T4) and the gate electrode of the fourth sub-transistor (T42), and the gate electrode of the seventh sub-transistor (T111) and the gate electrode of the eighth sub-transistor (T112) of the eleventh transistor (T11) can be connected to the k-th control signal (GNLk). The k-th scan initialization signal (GILk) and the k-th control signal (GNLk) may have pulses generated as gate off voltage (VGH). Additionally, the active layers of the first sub-transistor (T31) and second sub-transistor (T32) of the third transistor (T3), the third sub-transistor (T41) and fourth sub-transistor (T42) of the fourth transistor (T4), the fifth sub-transistor (T101) and sixth sub-transistor (T102) of the tenth transistor (T10), and the seventh sub-transistor (T111) and eighth sub-transistor (T112) of the eleventh transistor (T11) may be formed of oxide semiconductor, and the remaining transistors may be formed of polysilicon.

[0144] Alternatively, either the first sub-transistor (T31) or the second sub-transistor (T32) of the third transistor (T3) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the first sub-transistor (T31) and the second sub-transistor (T32) of the third transistor (T3), the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0145] Alternatively, either the third sub-transistor (T41) or the fourth sub-transistor (T42) of the fourth transistor (T4) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the third sub-transistor (T41) and the fourth sub-transistor (T42) of the fourth transistor (T4), the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0146] Alternatively, either one of the fifth sub-transistor (T101) and the sixth sub-transistor (T102) of the tenth transistor (T10) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the fifth sub-transistor (T101) and the sixth sub-transistor (T102) of the tenth transistor (T10), the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0147] Alternatively, either the seventh sub-transistor (T111) or the eighth sub-transistor (T112) of the eleventh transistor (T11) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the seventh sub-transistor (T111) and the eighth sub-transistor (T112) of the eleventh transistor (T11), the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0148] Meanwhile, the second subpixel (GP) and the third subpixel (BP) according to one embodiment may be substantially the same as the first subpixel (RP) described in conjunction with FIG. 6. Therefore, the description of the second subpixel (GP) and the third subpixel (BP) according to one embodiment is omitted.

[0149] FIG. 7 is a graph showing the wavelength of light emitted by the light-emitting element of the first subpixel, the wavelength of light emitted by the light-emitting element of the second subpixel, and the wavelength of light emitted by the light-emitting element of the third subpixel according to the driving current according to one embodiment.

[0150] FIG. 7 is a graph showing the wavelength of light emitted by the light-emitting element of the first subpixel, the wavelength of light emitted by the light-emitting element of the second subpixel, and the wavelength of light emitted by the light-emitting element of the third subpixel according to the driving current according to one embodiment.

[0151] Figure 7(a) shows the wavelength of light emitted by the light-emitting element (EL) of the first subpixel (RP) according to the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) when the light-emitting element (EL) of the first subpixel (RP) includes an inorganic material, for example, GaN.

[0152] Figure 7(b) shows the wavelength of light emitted by the light-emitting element (EL) of the second subpixel (GP) according to the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) when the light-emitting element (EL) of the second subpixel (GP) includes an inorganic material, for example, GaN.

[0153] Figure 7 (c) shows the wavelength of light emitted by the light-emitting element (EL) of the third subpixel (BP) according to the driving current (Ids) applied to the light-emitting element (EL) of the third subpixel (BP) when the light-emitting element (EL) of the third subpixel (BP) includes an inorganic material, for example, GaN.

[0154] In each of the graphs of Fig. 7 (a), (b), and (c), the X-axis indicates the driving current (Ids), and the Y-axis indicates the wavelength of light emitted by the light-emitting element.

[0155] Referring to FIG. 7, when the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) is 1 to 300 μA, the wavelength of the light emitted by the light-emitting element (EL) of the first subpixel (RP) is approximately 618 nm. As the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) increases from 300 μA to 1000 μA, the wavelength of the light emitted by the light-emitting element (EL) of the first subpixel (RP) increases from approximately 618 nm to 620 nm.

[0156] As the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) increases from 1 μA to 1000 μA, the wavelength of the light emitted by the light-emitting element (EL) of the second subpixel (GP) decreases from approximately 536 nm to 520 nm.

[0157] As the driving current (Ids) applied to the light-emitting element (EL) of the third subpixel (BP) increases from 1 μA to 1000 μA, the wavelength of the light emitted by the light-emitting element (EL) of the third subpixel (BP) decreases from approximately 464 nm to 461 nm.

[0158] In summary, the wavelength of light emitted by the light-emitting element (EL) of the first subpixel (RP) and the wavelength of light emitted by the light-emitting element (EL) of the third subpixel (BP) hardly change even when the driving current (Ids) changes. In contrast, the wavelength of light emitted by the light-emitting element (EL) of the second subpixel (GP) is inversely proportional to the driving current (Ids). Therefore, when the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) is adjusted, the wavelength of light emitted by the light-emitting element (EL) of the second subpixel (GP) changes, and the color coordinates of the image displayed by the display panel (100) may change.

[0159] FIG. 8 is a graph showing the luminous efficiency of a light-emitting element of a first subpixel, the luminous efficiency of a light-emitting element of a second subpixel, and the luminous efficiency of a light-emitting element of a third subpixel according to a driving current according to one embodiment.

[0160] Figure 8(a) shows the luminous efficiency of the light-emitting element (EL) of the first subpixel (RP) according to the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) when the light-emitting element (EL) of the first subpixel (RP) is made of an inorganic material.

[0161] Figure 8(b) shows the luminous efficiency of the light-emitting element (EL) of the second subpixel (GP) according to the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) when the light-emitting element (EL) of the second subpixel (GP) is made of inorganic material.

[0162] Figure 8 (c) shows the luminous efficiency of the light-emitting element (EL) of the third subpixel (BP) according to the driving current (Ids) applied to the light-emitting element (EL) of the third subpixel (BP) when the light-emitting element (EL) of the third subpixel (BP) is made of inorganic material.

[0163] Referring to FIG. 8, when the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) is 10 μA, the luminous efficiency of the light-emitting element (EL) of the first subpixel (RP) is approximately 8.5 cd / A. When the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) is 50 μA, the luminous efficiency of the light-emitting element (EL) of the first subpixel (RP) is approximately 18 cd / A. That is, when the driving current (Ids) applied to the light-emitting element (EL) of the first subpixel (RP) is 50 μA, it increases by approximately 2.1 times compared to when it is 10 μA.

[0164] When the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) is 10 µA, the luminous efficiency of the light-emitting element (EL) of the second subpixel (GP) is approximately 72 cd / A. When the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) is 50 µA, the luminous efficiency of the light-emitting element (EL) of the second subpixel (GP) is approximately 80 cd / A. That is, when the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) is 50 µA, it increases by approximately 1.1 times compared to when it is 10 µA.

[0165] When the driving current (Ids) applied to the light-emitting element (EL) of the third subpixel (BP) is 10 μA, the luminous efficiency of the light-emitting element (EL) of the third subpixel (BP) is approximately 14 cd / A. When the driving current (Ids) applied to the light-emitting element (EL) of the third subpixel (BP) is 50 μA, the luminous efficiency of the light-emitting element (EL) of the third subpixel (BP) is approximately 13.2 cd / A. That is, when the driving current (Ids) applied to the light-emitting element (EL) of the third subpixel (BP) is 50 μA, it increases by approximately 1.06 times compared to when it is 10 μA.

[0166] In summary, the luminous efficiency of the light-emitting element of the first subpixel (RP), the luminous efficiency of the light-emitting element of the second subpixel (GP), and the luminous efficiency of the third subpixel (BP) may vary depending on the driving current (Ids).

[0167] As shown in FIGS. 7 and 8, when the driving current (Ids) applied to the light-emitting element (EL) of the second subpixel (GP) is adjusted, the color coordinates of the image displayed by the display panel (100) may change. Additionally, the light-emitting efficiency of the light-emitting element of the first subpixel (RP), the light-emitting efficiency of the light-emitting element of the second subpixel (GP), and the light-emitting efficiency of the third subpixel (BP) may vary depending on the driving current (Ids). Therefore, it is necessary to maintain the color coordinates of the image displayed by the display panel (100) constant, and to maintain the driving current (Ids) constant in each of the first subpixel (RP), second subpixel (GP), and third subpixel (BP) so that the light-emitting element (EL) of the first subpixel (RP), the light-emitting element of the second subpixel (GP), and the light-emitting element (EL) of the third subpixel (BP) have optimal light-emitting efficiency, and to adjust the brightness of each of the first subpixel (RP), second subpixel (GP), and third subpixel (BP) by adjusting the period during which the driving current (Ids) is applied.

[0168] That is, as shown in FIG. 6, the second pixel driver (PDU2) of the first subpixel (RP) generates a driving current (Ids) to drive the light-emitting element (EL) of the first subpixel (RP) with optimized light-emitting efficiency according to the first PAM data voltage of the first PAM data line (RDL). The first pixel driver (PDU1) of the first subpixel (RP) generates a control current (Ic) according to the PWM data voltage of the PWM data line to control the voltage of the third node (N3) of the third pixel driver (PDU3), and the third pixel driver (PDU3) adjusts the period during which the driving current (Ids) is applied to the light-emitting element (EL) according to the voltage of the third node (N3). Therefore, the first subpixel (RP) generates a constant driving current (Ids) to drive with optimized luminous efficiency, and by adjusting the duty ratio of the light-emitting element (EL), that is, the period during which the driving current (Ids) is applied to the light-emitting element (EL), the brightness of the light emitted by the light-emitting element (EL) can be adjusted.

[0169] Additionally, the second pixel driver (PDU2) of the second subpixel (GP) generates a driving current (Ids) to drive the light-emitting element (EL) of the second subpixel (GP) with optimized light-emitting efficiency according to the second PAM data voltage of the second PAM data line (GDL). The first pixel driver (PDU1) of the second subpixel (GP) generates a control current (Ic) according to the PWM data voltage of the PWM data line to control the voltage of the third node (N3) of the third pixel driver (PDU3), and the third pixel driver (PDU3) adjusts the period during which the driving current (Ids) is applied to the light-emitting element (EL) according to the voltage of the third node (N3). Therefore, the second subpixel (GP) generates a constant driving current (Ids) to drive with optimized luminous efficiency, and by adjusting the duty ratio of the light-emitting element (EL), that is, the period during which the driving current (Ids) is applied to the light-emitting element (EL), the brightness of the light emitted by the light-emitting element (EL) can be adjusted.

[0170] Additionally, the second pixel driver (PDU2) of the third subpixel (BP) generates a driving current (Ids) to drive the light-emitting element (EL) of the third subpixel (BP) with optimized light-emitting efficiency according to the third PWM data voltage of the third PAM data line (BDL). The first pixel driver (PDU1) of the third subpixel (BP) generates a control current (Ic) according to the PWM data voltage of the PWM data line to control the voltage of the third node (N3) of the third pixel driver (PDU3), and the third pixel driver (PDU3) adjusts the period during which the driving current (Ids) is applied to the light-emitting element (EL) according to the voltage of the third node (N3). Therefore, the third subpixel (BP) generates a constant driving current (Ids) to drive with optimized luminous efficiency, and by adjusting the duty ratio of the light-emitting element (EL), that is, the period during which the driving current (Ids) is applied to the light-emitting element (EL), the brightness of the light emitted by the light-emitting element (EL) can be adjusted.

[0171] Accordingly, the wavelength of the light emitted varies depending on the driving current applied to the light-emitting element (EL), thereby reducing or preventing the degradation of image quality. In addition, the light-emitting element (EL) of the first subpixel (RP), the light-emitting element (EL) of the second subpixel (GP), and the light-emitting element (EL) of the third subpixel (GP) can each emit light with optimized light-emitting efficiency.

[0172] FIG. 9 is an example drawing showing the operation of a display device during the Nth to N+2nd frame period.

[0173] Referring to FIG. 9, each of the Nth to N+2nd frame periods may include an active period (ACT) and a blank period (VB). The active period (ACT) may include a data addressing period (ADDR) that supplies a PWM data voltage and a first / second / third PWM data voltage to each of the first to third subpixels (RP, GP, BP), and a plurality of light-emitting periods (EP1, EP2, EP3, EP4, EP5, …, EPn) in which the light-emitting element (EL) of each of the subpixels (SP) emits light. The blank period (VB) may be a period during which the subpixels (RP, GP, BP) of the display panel (100) are idle.

[0174] The address period (ADDR) and the first light emission period (EP1) may be shorter than each of the second to nth light emission periods (EP2, EP3, EP4, EP5, …, EPn). For example, the address period (ADDR) and the first light emission period (EP1) may be approximately 5 horizontal periods, and each of the second to nth light emission periods (EP2, EP3, EP4, EP5, …, EPn) may be approximately 12 horizontal periods, but the embodiments of this specification are not limited thereto. Additionally, the active period (ACT) may include 25 light emission periods, but the number of light emission periods (EP1, EP2, EP3, EP4, EP5, …, EPn) of the active period (ACT) is not limited thereto.

[0175] The subpixels (RP, GP, BP) of the display panel (100) can receive PWM data voltage and the first / second / third PWM data voltage sequentially by row line during the address period (ADDR). For example, the PWM data voltage and the first / second / third PWM data voltage can be received sequentially from the subpixels (RP, GP, BP) placed on the first row line to the subpixels (RP, GP, BP) placed on the nth row line corresponding to the last row line.

[0176] The subpixels (RP, GP, BP) of the display panel (100) can emit light sequentially by row line in each of the plurality of light emission periods (EP1, EP2, EP3, EP4, EP5, …, EPn). For example, they can emit light sequentially from the subpixels (RP, GP, BP) placed in the first row line to the subpixels (RP, GP, BP) placed in the last row line.

[0177] The address period (ADDR) may overlap with at least one of the light emission periods (EP1, EP2, EP3, EP4, …, EPn). For example, as shown in FIG. 9, the address period (ADDR) may overlap with the first to third light emission periods (EP1, EP2, EP3). In this case, when subpixels (RP, GP, BP) placed on the p-th row line (p is a positive integer) receive a PWM data voltage and a first / second / third PWM data voltage, subpixels (RP, GP, BP) placed on the q-th row line (q is a positive integer smaller than p) may emit light.

[0178] Additionally, each of the light emission periods (EP1, EP2, EP3, EP4, …, EPn) may overlap with an adjacent light emission period. For example, the second light emission period (EP2) may overlap with the first light emission period (EP1) and the third light emission period (EP3). In this case, subpixels (RP, GP, BP) placed on the p-th row line may emit light during the second light emission period (EP2), while subpixels (RP, GP, BP) placed on the q-th row line may emit light during the first light emission period (EP1).

[0179] FIG. 10 is another example drawing showing the operation of a display device during the Nth to N+2nd frame period.

[0180] The embodiment of FIG. 10 differs from the embodiment of FIG. 9 in that the subpixels (RP, GP, BP) of the display panel (100) emit light simultaneously during each of the plurality of light-emitting periods (EP1, EP2, EP3, EP4, EP5, …, EPn).

[0181] Referring to FIG. 10, the address period (ADDR) may not overlap with multiple light emission periods (EP1, EP2, EP3, EP4, …, EPn). The first light emission period (EP1) may occur after the address period (ADDR) has completely ended.

[0182] Multiple light emission periods (EP1, EP2, EP3, EP4, …, EPn) may not overlap each other. In each of the multiple light emission periods (EP1, EP2, EP3, EP4, EP5, …, EPn), subpixels (RP, GP, BP) placed on all row lines may emit light simultaneously.

[0183] FIG. 11 is a waveform diagram showing scan initialization signals, scan write signals, scan control signals, PWM light emission signals, PAM light emission signals, and sweep signals applied to subpixels placed on the k to k+5 row lines during the Nth frame period according to one embodiment.

[0184] Referring to FIG. 11, the subpixels (RP, GP, BP) placed on the k-th row line refer to the subpixels (RP, GP, BP) connected to the k-th scan initialization wire (GWLk), the k-th scan write wire (GWLk), the k-th scan control wire (GCLk), the k-th PWM light emission wire (PWELk), the k-th PAM light emission wire (PAELk), and the k-th sweep signal wire (SWPLk). The k-th scan initialization signal (GIk) refers to the signal applied to the k-th scan initialization wire (GWLk), and the k-th scan write signal (GWk) refers to the signal applied to the k-th scan write wire (GWLk). The k-th scan control signal (GCk) refers to the signal applied to the k-th scan control wire (GCLk), and the k-th PWM light emission signal (PWEMk) refers to the signal applied to the k-th PWM light emission wire (PWELk). The k-th PAM light-emitting signal (PAEMk) refers to the signal applied to the k-th PAM light-emitting wiring (PAELk), and the k-th sweep signal (SWPk) refers to the signal applied to the k-th sweep signal wiring (SWPLk).

[0185] Scan initialization signals (GIk~GIk+5), scan write signals (GWk~GWk+5), scan control signals (GCk~GCk+5), PWM light emission signals (PWEMk~PAEMk+5), PAM light emission signals (PAEMk~PAEMk+5), and sweep signals (SWPk~SWPk+5) can be sequentially shifted by one horizontal period (1H). The k-th scan write signal (GWk) is a signal in which the k-th scan initialization signal (GIk) is shifted by one horizontal period, and the k+1 scan write signal (GWk+1) is a signal in which the k+1 scan initialization signal (GIk+1) is shifted by one horizontal period. In this case, the k+1 scan initialization signal (GIk+1) is a signal that is shifted by one horizontal period from the k scan initialization signal (GIk), so the k scan write signal (GWk) and the k+1 scan initialization signal (GIk+1) can be substantially the same.

[0186] FIG. 12 is a waveform diagram showing the period during which a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAM light emission signal, and a k-th sweep signal are applied to each of the subpixels placed on the k-th row line during the N-th frame period according to one embodiment, and a driving current applied to the third node and the light-emitting element.

[0187] Referring to FIG. 12, the k-th scan initialization signal (GIk) is a signal for controlling the turn-on and turn-off of the third and tenth transistors (T3, T10) of each of the subpixels (RP, GP, BP). The k-th scan write signal (GWk) is a signal for controlling the turn-on and turn-off of the second, fourth, ninth, and eleventh transistors (T2, T4, T9, T11) of each of the subpixels (RP, GP, BP). The k-th scan control signal (GCk) is a signal for controlling the turn-on and turn-off of the seventh, thirteenth, sixteenth, and eighteenth transistors (T7, T13, T16, T18) of each of the subpixels (RP, GP, BP). The k-th PWM light-emitting signal (PWEMk) is a signal for controlling the turn-on and turn-off of the 5th, 6th, 12th, and 14th transistors (T5, T6, T12, T14). The k-th PAM light-emitting signal (PAEMk) is a signal for controlling the turn-on and turn-off of the 17th transistor (T17). The k-th scan initialization signal, the k-th scan write signal, the k-th scan control signal, the k-th PWM light-emitting signal, the k-th PAM light-emitting signal, and the k-th sweep signal may occur with a period of 1 frame.

[0188] The data address period (ADDR) includes the first to fourth periods (t1 to t4). The first period (t1) and the fourth period (t4) are first initialization periods for initializing the voltage of the first electrode of the light-emitting element (EL) and the third node (N3). The second period (t2) is a second initialization period for initializing the gate electrode of the first transistor (T1) and the gate electrode of the eighth transistor (T8). The third period (t3) is a period for sampling the PWM data voltage (Vdata) of the j-th PWM data line (DLj) and the threshold voltage (Vth1) of the first transistor (T1) at the gate electrode of the first transistor (T1), and sampling the first PAM data voltage (Rdata) of the first PAM data line (RDL) and the threshold voltage (Vth8) of the eighth transistor (T8) at the gate electrode of the eighth transistor (T8).

[0189] The first light emission period (EM1) includes the fifth period (t5) and the sixth period (t6). The first light emission period (EM1) is a period for controlling the turn-on period of the 15th transistor (T15) according to the control current (Ic) and supplying a driving current (Ids) to the light-emitting element (EL).

[0190] Each of the second to nth emission periods (EM2~EMn) includes the seventh to ninth periods (t7~t9). The seventh period (t7) is a third initialization period for initializing the third node (N3), the eighth period (t8) is substantially the same period as the fifth period (t5), and the ninth period (t9) is substantially the same period as the sixth period (t6).

[0191] Among the first to nth luminescence periods (EM1~EMn), adjacent luminescence periods may be spaced apart by approximately several to tens of horizontal periods.

[0192] The k-th scan initialization signal (GIk) may have a gate-on voltage (VGL) during the second period (t2) and a gate-off voltage (VGH) during the remaining periods. That is, the k-th scan initialization signal (GIk) may have a scan initialization pulse that occurs at the gate-on voltage (VGL) during the second period (t2). The gate-off voltage (VGH) may be a voltage level higher than the gate-on voltage (VGL).

[0193] The k-th scan write signal (GWk) may have a gate-on voltage (VGL) during the third period (t3) and a gate-off voltage (VGH) during the remaining periods. That is, the k-th scan write signal (GWk) may have a scan write pulse that occurs at the gate-on voltage (VGL) during the third period (t3).

[0194] The k-th scan control signal (GCk) may have a gate-on voltage (VGL) during the first to fourth periods (t1 to t4) and the seventh period (t7), and a gate-off voltage (VGH) during the remaining periods. That is, the k-th scan control signal (GCk) may have a scan control pulse that occurs at the gate-on voltage (VGL) during the first to fourth periods (t1 to t4) and the seventh period (t7).

[0195] The k-th sweep signal (SWPk) may have a triangular wave-shaped sweep pulse during the sixth period (t6) and the ninth period (t9), and may have a gate-off voltage (VGH) during the remaining periods. For example, the sweep pulse of the k-th sweep signal (SWPk) may have a triangular wave-shaped pulse that decreases linearly from the gate-off voltage (VGH) to the gate-on voltage (Von) during the sixth period (t6) and the ninth period (t9), respectively, and increases directly from the gate-on voltage (Von) to the gate-off voltage (Voff) at the end of the sixth period (t6) and the end of the ninth period (t9).

[0196] The k-th PWM light emission signal (PWEMk) may have a gate-on voltage (VGL) during the fifth and sixth periods (t5, t6) and the eighth and ninth periods (t8, t9), and a gate-off voltage (VGH) during the remaining periods. That is, the k-th PWM light emission signal (PWEMk) may include PWM pulses that occur at the gate-on voltage (VGL) during the fifth and sixth periods (t5, t6) and the eighth and ninth periods (t8, t9).

[0197] The k-th PAM emission signal (PAEMk) may have a gate-on voltage (VGL) during the sixth period (t6) and the ninth period (t9), and a gate-off voltage (VGH) during the remaining periods. That is, the k-th PAM emission signal (PAEMk) may include PAM pulses generated at the gate-on voltage (VGL) during the sixth period (t6) and the ninth period (t9). The PWM pulse width of the k-th PWM emission signal (PWEMk) may be greater than the sweep pulse width of the k-th sweep signal (SWPk).

[0198] FIG. 13 is a timing diagram showing the k-th sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the 15th transistor during the fifth and sixth periods according to one embodiment. FIG. 14 to 17 are circuit diagrams showing the operation of the first subpixel during the first, second, third, and sixth periods of FIG. 12.

[0199] Hereinafter, in conjunction with FIGS. 13 to 17, the operation of a first subpixel (RP) according to one embodiment during the first to ninth periods (t1 to t9) will be examined in detail.

[0200] First, as shown in FIG. 14, during the first period (t1), the 7th transistor (T7), the 13th transistor (T13), the 16th transistor (T16), and the 18th transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL).

[0201] Due to the turn-on of the 7th transistor (T7), the gate-off voltage (VGH) of the gate-off voltage wiring (VGHL) is applied to the 1st node (N1). Due to the turn-on of the 13th transistor (T13), the 1st power supply voltage (VDD1) of the 1st power supply wiring (VDL1) is applied to the 2nd node (N2).

[0202] Due to the turn-on of the 16th transistor (T16), the 3rd node (N3) is initialized to the initial voltage (VINT) of the initial voltage wiring (VIL), and the 15th transistor (T15) is turned on by the initial voltage (VINT) of the 3rd node (N3). Due to the turn-on of the 18th transistor (T18), the 1st electrode of the light-emitting element (EL) is initialized to the initial voltage (VINT) of the initial voltage wiring (VIL).

[0203] Secondly, as shown in FIG. 15, during the second period (t2), the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL). Additionally, during the second period (t2), the third transistor (T3) and the tenth transistor (T10) are turned on by the k-th scan initialization signal (GILk) of the gate-on voltage (VGL).

[0204] The 7th transistor (T7), the 13th transistor (T13), the 15th transistor (T15), the 16th transistor (T16), and the 18th transistor (T18) are substantially the same as those described in the first period (t1).

[0205] Due to the turn-on of the third transistor (T3), the gate electrode of the first transistor (T1) is initialized to the initial voltage (VINT) of the initial voltage wiring (VIL). Also, due to the turn-on of the tenth transistor (T10), the gate electrode of the eighth transistor (T8) is initialized to the initial voltage (VINT) of the initial voltage wiring (VIL).

[0206] At this time, since the gate off voltage (VGH) of the gate off voltage wiring (VGHL) is applied to the first node (N1), the amount of voltage change of the gate electrode of the first transistor (T1) is reflected in the k-th sweep signal wiring (SWPLk) by the first pixel capacitor (PC1), thereby preventing the gate off voltage (VGH) of the k-th sweep signal (SWPk) from fluctuating.

[0207] Thirdly, as shown in FIG. 16, during the third period (t3), the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL). Additionally, during the third period (t3), the second transistor (T2), the fourth transistor (T4), the ninth transistor (T9), and the eleventh transistor (T11) are turned on by the k-th scan write signal (GWk) of the gate-on voltage (VGL).

[0208] The 7th transistor (T7), the 13th transistor (T13), the 15th transistor (T15), the 16th transistor (T16), and the 18th transistor (T18) are substantially the same as those described in the first period (t1).

[0209] Due to the turn-on of the second transistor (T2), the PWM data voltage (Vdata) of the j-th PWM data line (DLj) is applied to the first electrode of the first transistor (T1). Due to the turn-on of the fourth transistor (T4), the gate electrode of the first transistor (T1) and the second electrode are connected to each other, so the first transistor (T1) is driven as a diode.

[0210] At this time, since the voltage between the gate electrode and the first electrode of the first transistor (T1) (Vgs = Vint - Vdata) is greater than the threshold voltage (Vth1), the first transistor (T1) is turned on and forms a current path until the voltage between the gate electrode and the first electrode (Vgs) reaches the threshold voltage (Vth1). As a result, the voltage of the gate electrode of the first transistor (T1) can rise from “Vint” to “Vdata + Vth1”. Since the first transistor (T1) is formed as a P-type MOSFET, the threshold voltage (Vth1) of the first transistor (T1) can be less than 0V.

[0211] In addition, since the gate off voltage (VGH) of the gate off voltage wiring (VGHL) is applied to the first node (N1), the amount of voltage change of the gate electrode of the first transistor (T1) by the first pixel capacitor (PC1) is reflected in the k-th sweep signal wiring (SWPLk), thereby preventing the gate off voltage (VGH) of the k-th sweep signal (SWPk) from fluctuating.

[0212] Due to the turn-on of the ninth transistor (T9), the first PAM data voltage (Rdata) of the first PAM data line (RDL) is applied to the first electrode of the eighth transistor (T8). Due to the turn-on of the ninth transistor (T9), the gate electrode and the second electrode of the eighth transistor (T8) are connected to each other, so the eighth transistor (T8) is driven as a diode.

[0213] At this time, since the voltage (Vgs = Vint - Rdata) between the gate electrode and the first electrode of the eighth transistor (T8) is greater than the threshold voltage (Vth8), the eighth transistor (T8) forms a current path until the voltage (Vgs) between the gate electrode and the first electrode reaches the threshold voltage (Vth8). As a result, the voltage of the gate electrode of the eighth transistor (T8) can rise from “Vint” to “Rdata + Vth”.

[0214] Fourth, during the fourth period (t4), the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL).

[0215] The 7th transistor (T7), the 13th transistor (T13), the 16th transistor (T16), and the 18th transistor (T18) are substantially the same as those described in the first period (t1).

[0216] Fifth, as shown in FIG. 17, during the fifth period (t5), the fifth transistor (T5), the sixth transistor (T6), the twelfth transistor (T12), and the fourteenth transistor (T14) are turned on by the k-th PWM light emission signal (PWEMk) of the gate-on voltage (VGL).

[0217] Due to the turn-on of the fifth transistor (T5), the first power supply voltage (VDD1) is applied to the first electrode of the first transistor (T1). Additionally, due to the turn-on of the sixth transistor (T6), the second electrode of the first transistor (T1) is connected to the third node (N3).

[0218] The control current (Ic) flowing according to the voltage (Vdata+Vth1) of the gate electrode of the first transistor (T1) during the fifth period (t5) may not depend on the threshold voltage (Vth1) of the first transistor (T1) as shown in Equation 1.

[0219]

[0220] In mathematical formula 1, k” is a proportionality constant determined by the structure and physical characteristics of the first transistor (T1), Vth1 is the threshold voltage of the first transistor (T1), VDD1 is the first power supply voltage, and Vdata is the PWM data voltage.

[0221] Additionally, due to the turn-on of the 12th transistor (T12), the first electrode of the 8th transistor (T8) can be connected to the 2nd power wiring (VDL2).

[0222] Additionally, due to the turn-on of the 14th transistor (T14), the second power supply voltage (VDD2) of the second power supply wiring (VDL2) is applied to the second node (N2). When the second power supply voltage (VDD2) of the second power supply wiring (VDL2) fluctuates due to voltage drop or the like, the voltage difference (ΔV2) between the first power supply voltage (VDD1) and the second power supply voltage (VDD2) can be reflected to the gate electrode of the 8th transistor (T8) by the second pixel capacitor (PC2).

[0223] Due to the turn-on of the 14th transistor (T14), a driving current (Ids) flowing according to the voltage (Rdata+Vth8) of the gate electrode of the 8th transistor (T8) can be supplied to the 15th transistor (T15). The driving current (Ids) may not depend on the threshold voltage (Vth8) of the 8th transistor (T8) as shown in Equation 2.

[0224]

[0225] In mathematical formula 2, k' is a proportionality constant determined by the structure and physical characteristics of the eighth transistor (T8), Vth8 is the threshold voltage of the eighth transistor (T8), VDD2 is the second power supply voltage, and Rdata is the first PAM data voltage.

[0226] Sixth, as shown in FIG. 17, during the sixth period (t6), the fifth transistor (T5), the sixth transistor (T6), the twelfth transistor (T12), and the fourteenth transistor (T14) are turned on by the k-th PWM light emission signal (PWEMk) of the gate-on voltage (VGL).

[0227] During the 6th period (t6), the 17th transistor (T17) is turned on by the k-th PAM light emission signal (PAEMk) of the gate-on voltage (VGL). During the 6th period (t6), the k-th sweep signal (SWPk) decreases linearly from the gate-off voltage (VGH) to the gate-on voltage (Von).

[0228] The fifth transistor (T5), the sixth transistor (T6), the twelfth transistor (T12), and the fourteenth transistor (T14) are substantially the same as those described in the fifth period (t5).

[0229] Due to the turn-on of the 17th transistor (T17), the first electrode of the light-emitting element (EL) can be connected to the second electrode of the 15th transistor (T15).

[0230] During the sixth period (t6), the k-th sweep signal (SWPk) decreases linearly from the gate-off voltage (VGH) to the gate-on voltage (Von). Since the voltage change amount (ΔV1) of the k-th sweep signal (SWPk) is reflected by the first pixel capacitor (PC1) to the gate electrode of the first transistor (T1), the voltage of the gate electrode of the first transistor (T1) can be Vdata + Vth1 - ΔV1. That is, during the sixth period (t6), the voltage of the gate electrode of the first transistor (T1) can be linearly lowered according to the voltage decrease of the k-th sweep signal (SWPk).

[0231] The period during which the control current (Ic) is applied to the third node (N3) can vary depending on the magnitude of the PWM data voltage (Vdata) applied to the first transistor (T1). As a result, since the voltage of the third node (N3) varies depending on the magnitude of the PWM data voltage (Vdata) applied to the first transistor (T1), the turn-on period of the 15th transistor (T15) can be controlled. Therefore, by controlling the turn-on period of the 15th transistor (T15), the period (SEP) during which the driving current (Ids) is applied to the light-emitting element (EL) during the 6th period (t6) can be controlled.

[0232] Additionally, as shown in FIG. 13, when the PWM data voltage (Vdata) of the gate electrode of the first transistor (T1) is a grayscale PWM data voltage, the voltage (VG_T1) of the gate electrode of the first transistor (T1) may have a level higher than the first power supply voltage during the first sub-period (t61) and a level lower than the first power supply voltage during the second sub-period (t62) according to the voltage reduction of the k-th sweep signal (SWPk). Therefore, the first transistor (T1) may be turned on during the second sub-period (t62) of the sixth period (t6). In this case, the control current (Ic) of the first transistor (T1) flows to the third node (N3) during the second sub-period (t62), so the voltage of the third node (N3) may have a high level (VH) during the second sub-period (t62). Therefore, the 15th transistor (T15) can be turned off during the second sub-period (t62). Accordingly, the driving current (Ids) is applied to the light-emitting element (EL) during the first sub-period (t61) and is not applied to the light-emitting element (EL) during the second sub-period (t62). That is, the light-emitting element (EL) can emit light during the first sub-period (t61), which is part of the sixth period (t6). The closer the first sub-pixel (RP) expresses a gray scale close to the peak black scale, the shorter the light-emitting period (SET) of the light-emitting element (EL) can be. Also, the closer the first sub-pixel (RP) expresses a gray scale close to the peak white scale, the longer the light-emitting period (SET) of the light-emitting element (EL) can be.

[0233] Additionally, as shown in FIG. 13, when the PWM data voltage (Vdata) of the gate electrode of the first transistor (T1) is a PWM data voltage of peak white gradation, the voltage (VG_T1) of the gate electrode of the first transistor (T1) may be higher than the first power supply voltage (VDD1) during the sixth period (t6), despite the voltage reduction of the k-th sweep signal (SWPk). As a result, the first transistor (T1) may be turned off throughout the sixth period (t6). In this case, since the control current (Ic) of the first transistor (T1) does not flow to the third node (N3) throughout the sixth period (t6), the voltage of the third node (N3) may maintain the initialization voltage (VINT). Therefore, the fifth transistor (T15) may be turned on throughout the sixth period (t6). Accordingly, the driving current (Ids) is applied to the light-emitting element (EL) throughout the 6th period (t6), and the light-emitting element (EL) can emit light throughout the 6th period (t6).

[0234] Additionally, as the k-th sweep signal (SWPk) rises from the gate-on voltage (VGL) to the gate-off voltage (VGH) at the end of the sixth period (t6), the voltage (VG_T1) of the gate electrode of the first transistor (T1) at the end of the sixth period (t6) can rise to be substantially the same as in the fifth period (t5).

[0235] As seen above, the light emission period of the light-emitting element (EL) can be adjusted by adjusting the PWM data voltage applied to the gate electrode of the first transistor (T1). Therefore, rather than adjusting the magnitude of the driving current (Ids) applied to the light-emitting element (EL), the driving current (Ids) applied to the light-emitting element (EL) can be kept constant, and the driving current (Ids) applied to the light-emitting element (EL) can be adjusted by adjusting the period during which the driving current (Ids) is applied to the light-emitting element (EL).

[0236] Meanwhile, when the digital video data converted into PWM data voltages is 8 bits, the digital video data of the peak black gradation may be 0, and the digital video data of the peak white gradation may be 255. Additionally, the digital video data of the black gradation region may be 0 to 63, the digital video data of the gray gradation region may be 64 to 191, and the digital video data of the white gradation region may be 192 to 255.

[0237] Additionally, each of the 7th period (t7), 8th period (t8), and 9th period (t9) of the 2nd to 9th light-emitting periods (EP2~EPn) is substantially the same as the 1st period (t1), 5th period (t5), and 6th period (t6) described above. That is, in each of the 2nd to 9th light-emitting periods (EP2~EPn), after initializing the 3rd node (N3), the period for applying the driving current (Ids) generated according to the 1st PAM data voltage (Rdata) written to the gate electrode of the 8th transistor (T8) based on the PWM data voltage (Vdata) written to the gate electrode of the 1st transistor (T1) during the address period (ADDR) can be adjusted.

[0238] Additionally, since the test signal of the test signal wiring (TSTL) is applied as a gate high voltage (VGH) during the active period (ACT) of the Nth frame period, the 19th transistor (T19) can be turned off during the active period (ACT) of the Nth frame period.

[0239] Meanwhile, since the second subpixel (GP) and the third subpixel (BP) can operate substantially the same as the first subpixel (RP) as described in conjunction with FIGS. 9 to 17, the description of the operation of the second subpixel (GP) and the third subpixel (BP) is omitted.

[0240] FIG. 18 is a layout diagram showing a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one embodiment. FIG. 19 is an enlarged layout diagram showing region I of FIG. 18 in detail. FIG. 20 is an enlarged layout diagram showing region II of FIG. 18 in detail. FIG. 21 is an enlarged layout diagram showing region III of FIG. 18 in detail.

[0241] Referring to FIGS. 18 to 21, the initialization voltage wires (VIL), the k-th scan initialization wire (GILk), the k-th scan write wire (GWLk), the k-th PWM light emission wire (PWELk), the first horizontal power wire (VDL1), the gate off voltage wire (VGHL), the k-th sweep signal wire (SWPLk), the k-th scan control wire (GCLk), the k-th PAM light emission wire (PAELk), the test signal wire (TSTL), and the third power auxiliary wire (AVSL) can be extended in the first direction (DR1). The initialization voltage wires (VIL), the k-th scan initialization wire (GILk), the k-th scan write wire (GWLk), the k-th PWM light emission wire (PWELk), the first horizontal power wire (VDL1), the gate off voltage wire (VGHL), the k-th sweep signal wire (SWPLk), the k-th scan control wire (GCLk), the k-th PAM light emission wire (PAELk), the test signal wire (TSTL), and the third power auxiliary wire (AVSL) may be spaced apart in the second direction (DR2).

[0242] The j-th data line (DLj), the first vertical power line (VVDL), and the first PAM data line (RDL) may be extended in a second direction (DR2). Additionally, the second PAM data line (GDL) and the third PAM data line (BDL) shown in FIG. 5 may be extended in a second direction (DR2). The j-th data line (DLj), the first vertical power line (VVDL), the first PAM data line (RDL), the second PAM data line (GDL), and the third PAM data line (BDL) may be spaced apart in a first direction (DR1).

[0243] The first subpixel (RP) includes first to 19 transistors (T1 to T19), first to 6 capacitor electrodes (CE1 to CE6), first to 5 gate connection electrodes (GCE1 to GCE5), first and second data connection electrodes (DCE1, DCE2), first to 8 connection electrodes (CCE1 to CCE8), a first anode connection electrode (ANDE1), and a light-emitting element (EL).

[0244] The first transistor (T1) includes a first channel (CH1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1). The first channel (CH1) may extend in a first direction (DR1). The first channel (CH1) may overlap with the first gate electrode (G1) in a third direction (DR3). The first gate electrode (G1) may be connected to a first connection electrode (CCE1) through a first contact hole (CT1). The first gate electrode (G1) may be formed integrally with the first capacitor electrode (CE1). The first gate electrode (G1) may overlap with the second capacitor electrode (CE2) in a third direction (DR3). The first source electrode (S1) may be placed on one side of the first channel (CH1), and the first drain electrode (D1) may be placed on the other side of the first channel (CH1). The first source electrode (S1) can be connected to the second drain electrode (D2) and the fifth drain electrode (D5). The first drain electrode (D1) can be connected to the third sub-source electrode (S41) and the sixth source electrode (S6). The first source electrode (S1) and the first drain electrode (D1) may not overlap with the first gate electrode (G1) in the third direction (DR3). The first source electrode (S1) and the first drain electrode (D1) may overlap with the second capacitor electrode (CE2) in the third direction (DR3).

[0245] The second transistor (T2) includes a second channel (CH2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2). The second channel (CH2) may overlap with the second gate electrode (G2) in a third direction (DR3). The second gate electrode (G2) may be formed integrally with the first gate connection electrode (GCE1). The second source electrode (S2) may be placed on one side of the second channel (CH2), and the second drain electrode (D2) may be placed on the other side of the second channel (CH2). The second source electrode (S2) may be connected to the first data connection electrode (DCE1) through the first data contact hole (DCT1). The second drain electrode (D2) may be connected to the first source electrode (S1). The second source electrode (S2) and the second drain electrode (D2) may not overlap with the second gate electrode (G2) in the third direction (DR3). The second drain electrode (D2) may extend in the second direction (DR2). The second drain electrode (D2) may be connected to the first source electrode (S1).

[0246] The first sub-transistor (T31) of the third transistor (T3) includes a first sub-channel (CH31), a first sub-gate electrode (G31), a first sub-source electrode (S31), and a first sub-drain electrode (D31). The first sub-channel (CH31) may overlap with the first sub-gate electrode (G31) in the third direction (DR3). The first sub-gate electrode (G31) may be formed integrally with the second gate connection electrode (GCE2). The first sub-source electrode (S31) may be disposed on one side of the first sub-channel (CH31), and the first sub-drain electrode (D31) may be disposed on the other side of the first sub-channel (CH31). The first sub-source electrode (S31) may be connected to the fourth sub-drain electrode (D42), and the first sub-drain electrode (D31) may be connected to the second sub-source electrode (S32). The first sub-source electrode (S31) and the first sub-drain electrode (D31) may not overlap with the first sub-gate electrode (G31). The first sub-source electrode (S31) may overlap with the k-th scan write wiring (GWLk) in the third direction (DR3). The first sub-drain electrode (S32) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0247] The second sub-transistor (T32) of the third transistor (T3) includes a second sub-channel (CH32), a second sub-gate electrode (G32), a second sub-source electrode (S32), and a second sub-drain electrode (D32). The second sub-channel (CH32) may overlap with the second sub-gate electrode (G32) in the third direction (DR3). The second sub-gate electrode (G32) may be formed integrally with the second gate connection electrode (GCE2). The second sub-source electrode (S32) may be placed on one side of the second sub-channel (CH32), and the second sub-drain electrode (D32) may be placed on the other side of the second sub-channel (CH32). The second sub-source electrode (S32) is connected to the first sub-drain electrode (D31), and the second sub-drain electrode (D32) may be connected to the initialization voltage wiring (VIL) through the first power contact hole (VCT1). The second sub-source electrode (S32) and the second sub-drain electrode (D32) may not overlap with the second sub-gate electrode (G32). The second sub-source electrode (S32) and the second sub-drain electrode (D32) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0248] The third sub-transistor (T41) of the fourth transistor (T4) includes a third sub-channel (CH41), a third sub-gate electrode (G41), a third sub-source electrode (S41), and a third sub-drain electrode (D41). The third sub-channel (CH41) may overlap with the third sub-gate electrode (G41) in the third direction (DR3). The third sub-gate electrode (G41) may be formed integrally with the first gate connection electrode (GCE1). The third sub-source electrode (S41) may be disposed on one side of the third sub-channel (CH41), and the third sub-drain electrode (D31) may be disposed on the other side of the third sub-channel (CH41). The third sub-source electrode (S41) may be connected to the first drain electrode (D1), and the third sub-drain electrode (D41) may be connected to the fourth sub-source electrode (S42). The third sub-source electrode (S41) and the third sub-drain electrode (D41) may not overlap with the third sub-gate electrode (G41).

[0249] The fourth sub-transistor (T42) of the fourth transistor (T4) includes a fourth sub-channel (CH42), a fourth sub-gate electrode (G42), a fourth sub-source electrode (S42), and a fourth sub-drain electrode (D42). The fourth sub-channel (CH42) may overlap with the fourth sub-gate electrode (G42) in the third direction (DR3). The fourth sub-gate electrode (G42) may be formed integrally with the second gate connection electrode (GCE2). The fourth sub-source electrode (S42) may be disposed on one side of the fourth sub-channel (CH42), and the fourth sub-drain electrode (D42) may be disposed on the other side of the fourth sub-channel (CH42). The fourth sub-source electrode (S42) may be connected to the third sub-drain electrode (D32), and the fourth sub-drain electrode (D42) may be connected to the first sub-source electrode (S31). The fourth sub-source electrode (S42) and the fourth sub-drain electrode (D42) may not overlap with the fourth sub-gate electrode (G42).

[0250] The fifth transistor (T5) includes a fifth channel (CH5), a fifth gate electrode (G5), a fifth source electrode (S5), and a fifth drain electrode (D5). The fifth channel (CH5) may overlap with the fifth gate electrode (G5) in the third direction (DR3). The fifth gate electrode (G5) may be formed integrally with the third gate connection electrode (GCE3). The fifth source electrode (S5) may be placed on one side of the fifth channel (CH5), and the fifth drain electrode (D5) may be placed on the other side of the fifth channel (CH5). The fifth source electrode (S5) may be connected to the first horizontal power wiring (HVDL) through the second power contact hole (VCT2). The fifth drain electrode (D5) may be connected to the first source electrode (S1). The fifth source electrode (S5) and the fifth drain electrode (D5) may not overlap with the fifth gate electrode (G5) in the third direction (DR3). The fifth drain electrode (D5) may overlap with the extension (EX) of the second capacitor electrode (CE2) in the third direction (DR3).

[0251] The sixth transistor (T6) includes a sixth channel (CH6), a sixth gate electrode (G6), a sixth source electrode (S6), and a sixth drain electrode (D6). The sixth channel (CH6) may overlap with the sixth gate electrode (G6) in the third direction (DR3). The sixth gate electrode (G6) may be formed integrally with the third gate connection electrode (GCE3). The sixth source electrode (S6) may be placed on one side of the sixth channel (CH6), and the sixth drain electrode (D6) may be placed on the other side of the sixth channel (CH6). The sixth source electrode (S6) may be connected to the first drain electrode (D1). The sixth drain electrode (D6) may be connected to the fourth connection electrode (CCE4) through the tenth contact hole (CT10). The sixth source electrode (S6) and the sixth drain electrode (D6) may not overlap with the sixth gate electrode (G6) in the third direction (DR3). The sixth drain electrode (D6) may overlap with the second connection electrode (CCE2) and the first horizontal power wiring (HVDL) in the third direction (DR3).

[0252] The seventh transistor (T7) includes a seventh channel (CH7), a seventh gate electrode (G7), a seventh source electrode (S7), and a seventh drain electrode (D7). The seventh channel (CH7) may overlap with the seventh gate electrode (G7) in the third direction (DR3). The seventh gate electrode (G7) may be formed integrally with the third gate connection electrode (GCE3). The seventh gate electrode (G7) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3). The seventh source electrode (S7) may be placed on one side of the seventh channel (CH7), and the seventh drain electrode (D7) may be placed on the other side of the seventh channel (CH7). The seventh source electrode (S7) may be connected to the gate off voltage wiring (VGHL) through the seventh contact hole (CT7). The seventh drain electrode (D7) can be connected to the k-th sweep signal wiring (SWPLk) through the sixth contact hole (CT6). The seventh source electrode (S7) and the seventh drain electrode (D7) may not overlap with the seventh gate electrode (G7) in the third direction (DR3).

[0253] The eighth transistor (T8) includes an eighth channel (CH8), an eighth gate electrode (G8), an eighth source electrode (S8), and an eighth drain electrode (D8). The eighth channel (CH8) may overlap with the eighth gate electrode (G8) in the third direction (DR3). The eighth gate electrode (G8) may extend in the second direction (DR2). The eighth gate electrode (G8) may be formed integrally with the third capacitor electrode (CE3). The eighth source electrode (S8) may be placed on one side of the eighth channel (CH8), and the eighth drain electrode (D8) may be placed on the other side of the eighth channel (CH8). The eighth source electrode (S8) may be connected to the ninth drain electrode (D9) and the twelfth drain electrode (D12). The eighth drain electrode (D8) may be connected to the seventh sub-source electrode (S111). The 8th source electrode (S8) and the 8th drain electrode (D8) may not overlap with the 8th gate electrode (G8) in the 3rd direction (DR3).

[0254] The ninth transistor (T9) includes a ninth channel (CH9), a ninth gate electrode (G9), a ninth source electrode (S9), and a ninth drain electrode (D9). The ninth channel (CH9) may overlap with the ninth gate electrode (G9) in the third direction (DR3). The ninth gate electrode (G9) may extend in the second direction (DR2). The ninth gate electrode (G9) may be formed integrally with the first gate connection electrode (GCE1). The ninth source electrode (S9) may be placed on one side of the ninth channel (CH9), and the ninth drain electrode (D9) may be placed on the other side of the ninth channel (CH9). The ninth source electrode (S9) may be connected to the second data connection electrode (DCE2) through the third data contact hole (DCT3). The ninth drain electrode (D9) may be connected to the eighth source electrode (D8). The ninth source electrode (S9) and the ninth drain electrode (D9) may not overlap with the ninth gate electrode (G9) in the third direction (DR3).

[0255] The fifth sub-transistor (T101) of the tenth transistor (T10) includes a fifth sub-channel (CH101), a fifth sub-gate electrode (G101), a fifth sub-source electrode (S101), and a fifth sub-drain electrode (D101). The fifth sub-channel (CH101) may overlap with the fifth sub-gate electrode (G101) in the third direction (DR3). The fifth sub-gate electrode (G101) may be formed integrally with the second gate connection electrode (GCE2). The fifth sub-source electrode (S101) may be disposed on one side of the fifth sub-channel (CH101), and the fifth sub-drain electrode (D101) may be disposed on the other side of the fifth sub-channel (CH101). The fifth sub-source electrode (S101) is connected to the eighth sub-drain electrode (D112), and the fifth sub-drain electrode (D101) may be connected to the sixth sub-source electrode (S102). The fifth sub-source electrode (S101) and the fifth sub-drain electrode (D101) may not overlap with the fifth sub-gate electrode (G101). The fifth sub-source electrode (S101) may overlap with the k-th scan write wiring (GWLk) in the third direction (DR3). The fifth sub-drain electrode (S102) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0256] The sixth sub-transistor (T102) of the tenth transistor (T10) includes a sixth sub-channel (CH102), a sixth sub-gate electrode (G102), a sixth sub-source electrode (S102), and a sixth sub-drain electrode (D102). The sixth sub-channel (CH102) may overlap with the sixth sub-gate electrode (G102) in the third direction (DR3). The sixth sub-gate electrode (G102) may be formed integrally with the second gate connection electrode (GCE2). The sixth sub-source electrode (S102) may be disposed on one side of the sixth sub-channel (CH102), and the sixth sub-drain electrode (D102) may be disposed on the other side of the sixth sub-channel (CH102). The sixth sub-source electrode (S102) is connected to the fifth sub-drain electrode (D101), and the sixth sub-drain electrode (D102) can be connected to the initialization voltage wiring (VIL) through the first power contact hole (VCT1). The sixth sub-source electrode (S102) and the sixth sub-drain electrode (D102) may not overlap with the sixth sub-gate electrode (G102). The sixth sub-source electrode (S102) and the sixth sub-drain electrode (D102) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0257] The seventh sub-transistor (T111) of the eleventh transistor (T11) includes a seventh sub-channel (CH111), a seventh sub-gate electrode (G111), a seventh sub-source electrode (S111), and a seventh sub-drain electrode (D111). The seventh sub-channel (CH111) may overlap with the seventh sub-gate electrode (G111) in the third direction (DR3). The seventh sub-gate electrode (G111) may be formed integrally with the first gate connection electrode (GCE1). The seventh sub-source electrode (S111) may be disposed on one side of the seventh sub-channel (CH111), and the seventh sub-drain electrode (D111) may be disposed on the other side of the seventh sub-channel (CH111). The seventh sub-source electrode (S111) is connected to the eighth drain electrode (D8), and the seventh sub-drain electrode (D111) can be connected to the eighth sub-source electrode (S112). The seventh sub-source electrode (S111) and the seventh sub-drain electrode (D111) may not overlap with the seventh sub-gate electrode (G111).

[0258] The eighth sub-transistor (T112) of the eleventh transistor (T11) includes an eighth sub-channel (CH112), an eighth sub-gate electrode (G112), an eighth sub-source electrode (S112), and an eighth sub-drain electrode (D112). The eighth sub-channel (CH112) may overlap with the eighth sub-gate electrode (G112) in the third direction (DR3). The eighth sub-gate electrode (G112) may be formed integrally with the second gate connection electrode (GCE2). The eighth sub-source electrode (S112) may be disposed on one side of the eighth sub-channel (CH112), and the eighth sub-drain electrode (D112) may be disposed on the other side of the eighth sub-channel (CH112). The eighth sub-source electrode (S112) is connected to the seventh sub-drain electrode (D111), and the eighth sub-drain electrode (D112) can be connected to the fifth sub-source electrode (S101). The eighth sub-source electrode (S112) and the eighth sub-drain electrode (D112) may not overlap with the eighth sub-gate electrode (G112).

[0259] The 12th transistor (T12) includes a 12th channel (CH12), a 12th gate electrode (G12), a 12th source electrode (S12), and a 12th drain electrode (D12). The 12th channel (CH12) may overlap with the 12th gate electrode (G12) in a third direction (DR3). The 12th gate electrode (G12) may be formed integrally with the 3rd gate connection electrode (GCE3). The 12th source electrode (S12) may be disposed on one side of the 12th channel (CH12), and the 12th drain electrode (D12) may be disposed on the other side of the 12th channel (CH12). The 12th source electrode (S12) may be connected to the 5th connection electrode (CCE5) through the 11th contact holes (CT11). The 12th source electrode (S12) and the 12th drain electrode (D12) may not overlap with the 12th gate electrode (G12) in the 3rd direction (DR3).

[0260] The 13th transistor (T13) includes a 13th channel (CH13), a 13th gate electrode (G13), a 13th source electrode (S13), and a 13th drain electrode (D13). The 13th channel (CH13) may overlap with the 13th gate electrode (G13) in the 3rd direction (DR3). The 13th gate electrode (G13) may be formed integrally with the 3rd gate connection electrode (GCE3). The 13th source electrode (S13) may be placed on one side of the 13th channel (CH13), and the 13th drain electrode (D13) may be placed on the other side of the 13th channel (CH13). The 13th source electrode (S13) may be connected to the 1st horizontal power wiring (HVDL) through the 2nd power contact hole (VCT2). The 13th drain electrode (D13) can be connected to the 2nd connection electrode (CCE2) through the 3rd contact hole (CT3). The 13th source electrode (S13) and the 13th drain electrode (D13) may not overlap with the 13th gate electrode (G13) in the 3rd direction (DR3).

[0261] The 14th transistor (T14) includes a 14th channel (CH14), a 14th gate electrode (G14), a 14th source electrode (S14), and a 14th drain electrode (D14). The 14th channel (CH14) may overlap with the 14th gate electrode (G14) in a third direction (DR3). The 14th gate electrode (G14) may be formed integrally with the third gate connection electrode (GCE3). The 14th source electrode (S14) may be disposed on one side of the 14th channel (CH14), and the 14th drain electrode (D14) may be disposed on the other side of the 14th channel (CH14). The 14th source electrode (S14) may be connected to the 5th connection electrode (CCE5) through the 11th contact holes (CT11). The 14th drain electrode (D14) can be connected to the 2nd connection electrode (CCE2) through the 4th contact hole (CT4). The 14th source electrode (S14) and the 14th drain electrode (D14) may not overlap with the 14th gate electrode (G14) in the 3rd direction (DR3).

[0262] The 15th transistor (T15) includes a 15th channel (CH15), a 15th gate electrode (G15), a 15th source electrode (S15), and a 15th drain electrode (D15). The 15th channel (CH15) may overlap with the 15th gate electrode (G15) in the third direction (DR3). The 15th gate electrode (G15) may be formed integrally with the 5th capacitor electrode (CE5). The 15th source electrode (S15) may be placed on one side of the 15th channel (CH15), and the 15th drain electrode (D15) may be placed on the other side of the 15th channel (CH15). The 15th source electrode (S15) may be connected to the 9th drain electrode (D5). The 15th drain electrode (D15) may be connected to the 17th source electrode (S17). The 15th source electrode (S15) and the 15th drain electrode (D15) may not overlap with the 15th gate electrode (G15) in the 3rd direction (DR3).

[0263] The ninth sub-transistor (T161) of the 16th transistor (T16) includes a ninth sub-channel (CH161), a ninth sub-gate electrode (G161), a ninth sub-source electrode (S161), and a ninth sub-drain electrode (D161). The ninth sub-channel (CH161) may overlap with the ninth sub-gate electrode (G161) in the third direction (DR3). The ninth sub-gate electrode (G161) may be formed integrally with the third gate connection electrode (GCE3). The ninth sub-source electrode (S161) may be disposed on one side of the ninth sub-channel (CH161), and the ninth sub-drain electrode (D161) may be disposed on the other side of the ninth sub-channel (CH161). The ninth sub-source electrode (S161) is connected to the fourth connecting electrode (CCE4) through the tenth contact hole (CT10), and the ninth sub-drain electrode (D161) can be connected to the tenth sub-source electrode (S162). The ninth sub-source electrode (S161) and the ninth sub-drain electrode (D161) may not overlap with the ninth sub-gate electrode (G161).

[0264] The 10th sub-transistor (T162) of the 16th transistor (T16) includes a 10th sub-channel (CH162), a 10th sub-gate electrode (G162), a 10th sub-source electrode (S162), and a 10th sub-drain electrode (D162). The 10th sub-channel (CH162) may overlap with the 10th sub-gate electrode (G162) in the third direction (DR3). The 10th sub-gate electrode (G162) may be formed integrally with the third gate connection electrode (GCE3). The 10th sub-source electrode (S162) may be disposed on one side of the 10th sub-channel (CH162), and the 10th sub-drain electrode (D162) may be disposed on the other side of the 10th sub-channel (CH162). The 10th sub-source electrode (S162) is connected to the 9th sub-drain electrode (D161), and the 10th sub-drain electrode (D162) can be connected to the initialization voltage wiring (VIL) through the 9th contact hole (CT9). The 10th sub-source electrode (S162) and the 10th sub-drain electrode (D162) may not overlap with the 10th sub-gate electrode (G162).

[0265] The 17th transistor (T17) includes a 17th channel (CH17), a 17th gate electrode (G17), a 17th source electrode (S17), and a 17th drain electrode (D17). The 17th channel (CH17) may overlap with the 17th gate electrode (G17) in the third direction (DR3). The 17th gate electrode (G17) may be formed integrally with the 5th gate connection electrode (GCE5). The 17th source electrode (S17) may be placed on one side of the 17th channel (CH17), and the 17th drain electrode (D17) may be placed on the other side of the 17th channel (CH17). The 17th source electrode (S17) may be connected to the 15th drain electrode (D15). The 17th drain electrode (D17) may be connected to the 7th connection electrode (CCE7) through the 16th contact holes (CT16). The 17th source electrode (S17) and the 17th drain electrode (D17) may not overlap with the 17th gate electrode (G17) in the 3rd direction (DR3).

[0266] The 18th transistor (T18) includes an 18th channel (CH18), an 18th gate electrode (G18), an 18th source electrode (S18), and an 18th drain electrode (D18). The 18th channel (CH18) may overlap with the 18th gate electrode (G18) in a third direction (DR3). The 18th gate electrode (G18) may be formed integrally with the third gate connection electrode (GCE3). The 18th source electrode (S18) may be placed on one side of the 18th channel (CH18), and the 18th drain electrode (D18) may be placed on the other side of the 18th channel (CH18). The 18th source electrode (S18) may be connected to the initialization voltage wiring (VIL) through the 9th contact hole (CT9). The 18th drain electrode (D18) can be connected to the 7th connecting electrode (CCE7) through the 16th contact holes (CT16). The 18th source electrode (S18) and the 18th drain electrode (D18) may not overlap with the 18th gate electrode (G18) in the 3rd direction (DR3).

[0267] The 19th transistor (T19) includes a 19th channel (CH19), a 19th gate electrode (G19), a 19th source electrode (S19), and a 19th drain electrode (D19). The 19th channel (CH19) may overlap with the 19th gate electrode (G19) in the third direction (DR3). The 19th gate electrode (G19) may be connected to the test signal wiring (TSTL) through the 23rd contact hole (CT23). The 19th source electrode (S19) may be placed on one side of the 19th channel (CH19), and the 19th drain electrode (D19) may be placed on the other side of the 19th channel (CH19). The 19th source electrode (S19) may be connected to the 8th connection electrode (CCE8) through the 21st contact hole (CT21). The 19th drain electrode (D19) can be connected to the 3rd power auxiliary wiring (AVSL) through the 24th contact hole (CT24). The 19th source electrode (S19) and the 19th drain electrode (D19) may not overlap with the 19th gate electrode (G19) in the 3rd direction (DR3).

[0268] The first capacitor electrode (CE1) can be formed integrally with the first gate electrode (G1). The second capacitor electrode (CE2) can overlap with the first capacitor electrode (CE1) in the third direction (DR3). The first capacitor electrode (CE1) may be one electrode of the first capacitor (C1), and the second capacitor electrode (CE2) may be the other electrode of the first capacitor (C1).

[0269] The second capacitor electrode (CE2) includes a hole that exposes the first gate electrode (G1), and the first connection electrode (CCE1) can be connected to the first gate electrode (G1) through the first contact hole (CT1) in the hole.

[0270] The second capacitor electrode (CE2) may include an extension (EX) extending in the second direction (DR2). The extension (EX) of the second capacitor electrode (CE2) may intersect with the k-th PWM light-emitting wiring (PWELk) and the first horizontal voltage wiring (HVDL). The extension (EX) of the second capacitor (CE2) may be connected to the k-th sweep signal wiring (SWPLk) through the fifth contact hole (CT5).

[0271] The third capacitor electrode (CE3) can be formed integrally with the eighth gate electrode (G8). The fourth capacitor electrode (CE4) can overlap with the third capacitor electrode (CE3) in the third direction (DR3). The third capacitor electrode (CE3) may be one electrode of the second capacitor (C2), and the fourth capacitor electrode (CE4) may be the other electrode of the second capacitor (C2).

[0272] The fourth capacitor electrode (CE4) includes a hole that exposes the eighth gate electrode (G8), and the sixth connecting electrode (CCE6) can be connected to the eighth gate electrode (G8) through the 12th contact hole (CT12) in the hole.

[0273] The fifth capacitor electrode (CE5) can be formed integrally with the fourth gate connection electrode (GCE4) and the fifth gate electrode (G15). The sixth capacitor electrode (CE6) can overlap with the fifth capacitor electrode (CE5) in the third direction (DR3). The fifth capacitor electrode (CE5) may be one electrode of the third capacitor (C3), and the sixth capacitor electrode (CE6) may be the other electrode of the third capacitor (C3). The sixth capacitor electrode (CE6) may be connected to the initialization voltage wiring (VIL) through the eighteenth contact hole (CT18).

[0274] The first gate connection electrode (GCE1) can be connected to the k-th scan write wire (GWLk) through the first gate contact hole (GCT1) and the third gate contact hole (GCT3). The second gate connection electrode (GCE2) can be connected to the k-th scan initialization wire (GILk) through the second gate contact hole (GCT2). The third gate connection electrode (GCE3) can be connected to the k-th PWM light emission wire (PWELk) through the 14th contact hole (CT14). The fourth gate connection electrode (GCE4) can be connected to the k-th scan control wire (GCLk) through the eighth contact hole (CT8). The fourth gate connection electrode (GCE4) can be connected to the fourth connection electrode (CCE4) through the 17th contact hole (CT17). The fifth gate connection electrode (GCE5) can be connected to the kth PAM light-emitting wiring (PAELk) through the 19th contact hole (CT19).

[0275] The first data connection electrode (DCE1) can be connected to the second source electrode (S2) through the first data contact hole (DCT1) and to the j-th data wiring (DLj) through the second data contact hole (DCT2). The second data connection electrode (DCE2) can be connected to the ninth source electrode (S9) through the third data contact hole (DCT3) and to the first PAM data wiring (RDL) through the fourth data contact hole (DCT4).

[0276] The first connecting electrode (CCE1) can be extended in a second direction (DR2). The first connecting electrode (CCE1) can be connected to the first gate electrode (G1) through the first contact hole (CT1) and to the first sub-source electrode (S31) and the fourth sub-drain electrode (D42) through the second contact hole (CT2).

[0277] The second connecting electrode (CCE2) can be extended in the first direction (DR1). The second connecting electrode (CCE2) can be connected to the 12th drain electrode (D12) through the third contact hole (CT3), connected to the 14th drain electrode (D14) through the fourth contact hole (CT4), and connected to the 4th capacitor electrode (CE4) through the 15th contact hole (CT15).

[0278] The fourth connecting electrode (CCE4) can be extended in the first direction (DR1). The fourth connecting electrode (CCE4) can be connected to the sixth drain electrode (D6) and the ninth sub-source electrode (S161) through the tenth contact hole (CT10), and can be connected to the fourth gate connecting electrode (GCE4) through the seventh contact hole (CT17).

[0279] The fifth connecting electrode (CCE5) can be extended in the first direction (DR1). The fifth connecting electrode (CCE5) is connected to the 12th source electrode (S12) and the 14th source electrode (S14) through the 11th contact holes (CT11), and can be connected to the 4th capacitor electrode (CE4) through the 4th power contact hole (VDCT4).

[0280] The sixth connecting electrode (CCE6) can be extended in the second direction (DR2). The sixth connecting electrode (CCE6) can be connected to the third capacitor electrode (CE3) through the twelfth contact hole (CT12) and to the fifth sub-source electrode (S101) and the eighth sub-drain electrode (D112) through the thirteenth contact hole (CT13).

[0281] The 7th connecting electrode (CCE7) can be connected to the 17th drain electrode (D17) and the 18th drain electrode (D18) through the 16th contact holes (CT16). The 7th connecting electrode (CCE7) can be connected to the 1st anode connecting electrode (ANDE1) through the 20th contact hole (CT20).

[0282] The 8th connecting electrode (CCE8) can be connected to the 19th source electrode (S19) through the 21st contact hole (CT21) and to the 1st anode connecting electrode (ANDE1) through the 22nd contact hole (CT22).

[0283] The first anode connecting electrode (ANDE1) can be extended in the second direction (DR2). The first anode connecting electrode (ANDE1) can be connected to the seventh connecting electrode (CCE7) through the 20th contact hole (CT20) and to the eighth connecting electrode (CCE8) through the 22nd contact hole (CT22).

[0284] The second power connection electrode (VDCE) can be extended in the second direction (DR2). It can be connected to the fifth connection electrode (CCE5) through the fourth power contact hole (VCT4).

[0285] FIG. 22 is a layout diagram showing a third source metal layer of a first subpixel according to one embodiment. FIG. 23 is a layout diagram showing a fourth source metal layer of a first subpixel according to one embodiment.

[0286] Referring to FIG. 22, the third power line (VSL) may consist of a third source metal layer disposed on an organic film covering the second source metal layer. The third power line (VSL) may be disposed entirely over the remainder of the display area (DA), excluding a portion where the light-emitting element (LE) of each of the plurality of subpixels (RP, GP, BP) is disposed.

[0287] Additionally, the third source metal layer may further include a second anode connecting electrode (ANDE2) that overlaps with the first anode connecting electrode (ANDE1).

[0288] Referring to FIG. 23, the anode electrode (AND) of each of the plurality of subpixels (RP, GP, BP) and the cathode electrode (CSD) that corresponds to the plurality of subpixels (RP, GP, BP) in common may be composed of a fourth source metal layer disposed on another organic film covering the third source metal layer.

[0289] FIG. 24 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 18. FIG. 25 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 18. FIG. 26 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 18. FIG. 27 is a cross-sectional view showing an example of a display panel cut along E-E' of FIG. 18. FIG. 28 is a cross-sectional view showing an example of a display panel cut along F-F' of FIG. 18. FIG. 29 is a cross-sectional view showing an example of a display panel cut along G-G' of FIG. 18. FIG. 30 is a cross-sectional view showing an example of a display panel cut along H-H' of FIG. 18. FIG. 31 is a cross-sectional view showing an example of a display panel cut along I-I' of FIG. 18. FIG. 32 is a cross-sectional view showing an example of a display panel cut along J-J' of FIG. 18.

[0290] Referring to FIGS. 24 to 32, a buffer film (BF) may be disposed on a substrate (SUB).

[0291] The substrate (SUB) may be made of insulating materials such as polymer resin and glass.

[0292] For example, the substrate (SUB) may be made of a polyimide polymer resin. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0293] The buffer layer (BF) is an insulating layer designed to protect the transistors of the thin-film transistor layer (TFTL) and the light-emitting elements (LE) of the light-emitting element layer (EML) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability.

[0294] The buffer film (BF) may be composed of a plurality of inorganic films that are alternately stacked. For example, the buffer film (BF) may be formed as a multilayer film in which one or more inorganic films among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0295] An active layer may be disposed on the buffer film (BF). The active layer includes first to ninth channels (CH1~CH19) of first to ninth transistors (T1~T19), first to ninth source electrodes (S1~S19), and first to ninth drain electrodes (D1~D19).

[0296] The active layer may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor.

[0297] The first to ninth channels (CH1~CH19) may each overlap with the first to ninth gate electrodes (G1~G19) in the third direction (DR3). The first to ninth source electrodes (S1~S19) and the first to ninth drain electrodes (D1~D19) may not overlap with the first to ninth gate electrodes (G1~G19) in the third direction (DR3). The first to ninth source electrodes (S1~S19) and the first to ninth drain electrodes (D1~D19) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor or an oxide semiconductor.

[0298] A gate insulating film (130) may be disposed on the active layer. The gate insulating film (130) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The gate insulating film (130) may be referred to as the first insulating film.

[0299] A first gate metal layer may be disposed on the gate insulating film (130). The first gate metal layer includes the first to ninth gate electrodes (G1 to G19) of the first to ninth transistors (T1 to T19), the first capacitor electrode (CE1), the third capacitor electrode (CE3), the fifth capacitor electrode (CE5), and the first to fifth gate connecting electrodes (GCE1 to GCE5). The first to ninth gate electrodes (G1 to G19), the first capacitor electrode (CE1), the third capacitor electrode (CE3), the fifth capacitor electrode (CE5), and the first to fifth gate connecting electrodes (GCE1 to GCE5) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0300] A first interlayer insulating film (141) may be disposed on the first gate metal layer. The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film (141) may be referred to as a second insulating film.

[0301] A second gate metal layer may be disposed on the first interlayer insulating film (141). The second gate metal layer may include a second capacitor electrode (CE2), a fourth capacitor electrode (CE4), and a sixth capacitor electrode (CE6). The second gate metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0302] The second capacitor electrode (CE2) may overlap with the first capacitor electrode (CE1) in the third direction (DR3), the fourth capacitor electrode (CE4) may overlap with the third capacitor electrode (CE3) in the third direction (DR3), and the sixth capacitor electrode (CE6) may overlap with the fifth capacitor electrode (CE5) in the third direction (DR3). Since the first interlayer insulating film (141) has a predetermined dielectric constant, the first capacitor (C1) can be formed by the first capacitor electrode (CE1), the second capacitor electrode (CE2), and the first interlayer insulating film (141) disposed between them. Additionally, the second capacitor (C2) can be formed by the third capacitor electrode (CE3), the fourth capacitor electrode (CE4), and the first interlayer insulating film (141) disposed between them. A third capacitor (C3) can be formed by a fifth capacitor electrode (CE5), a sixth capacitor electrode (CE6), and a first interlayer insulating film (141) disposed between them.

[0303] A second interlayer insulating film (142) may be disposed on the second gate metal layer. The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film (141) may be referred to as a third insulating film.

[0304] A first source metal layer may be disposed on the second interlayer insulating film (142). The first source metal layer may further include initialization voltage lines (VIL), k-th scan initialization lines (GILk), k-th scan write lines (GWLk), k-th PWM light emission lines (PWELk), a first horizontal power line (HVDL), a gate off voltage line (VGHL), a k-th sweep signal line (SWPLk), a k-th scan control line (GCLk), a k-th PAM light emission line (PAELk), a test signal line (TSTL), and a third power auxiliary line (AVSL).

[0305] Additionally, the first source metal layer may include first and second data connection electrodes (DCE1, DCE2) and first to eighth connection electrodes (CCE1~CCE8).

[0306] The first source metal layer may be formed as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0307] The k-th scan writing wiring (GWLk) can be connected to the first gate connection electrode (GCE1) through the first gate contact hole (GCT1) and the third gate contact hole (GCT3) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th scan initialization wiring (GILk) can be connected to the second gate connection electrode (GCE2) through the second gate contact hole (GCT2) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th PWM light emission wiring (PWELk) can be connected to the third gate connection electrode (GCE3) through the 14th contact hole (CT14) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th scan control wiring (GCLk) can be connected to the fourth gate connection electrode (GCE4) through an eighth contact hole (CT8) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th PAM light-emitting wiring (PAELk) can be connected to the fifth gate connection electrode (GCE5) through a ninth contact hole (CT19) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142).

[0308] The initial voltage wiring (VIL) can be connected to the second sub-drain electrode (D32) and the sixth sub-drain electrode (D102) through a first power contact hole (VCT1) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The initial voltage wiring (VIL) can be connected to the tenth sub-drain electrode (D162) and the eighteenth drain electrode (D18) through a ninth contact hole (CT9) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The initial voltage wiring (VIL) can be connected to the sixth capacitor electrode (CE6) through an eighteenth contact hole (CT18) penetrating the second interlayer insulating film (142). The first horizontal power wiring (HVDL) can be connected to the fifth source electrode (S5) and the thirteenth source electrode (S13) through a second power contact hole (VCT2) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The gate off voltage wiring (VGHL) can be connected to the seventh source electrode (S7) through a seventh contact hole (CT7) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The test signal wiring (TSTL) can be connected to the ninth gate electrode (G19) through a thirteenth contact hole (CT23) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The third power line (VSL) can be connected to the 19th drain electrode (D19) through a 24th contact hole (CT24) that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0309] The first data connection electrode (DCE1) can be connected to the second source electrode (S2) through a first data contact hole (DCT1) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The second data connection electrode (DCE2) can be connected to the ninth source electrode (S9) through a third data contact hole (DCT3) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0310] The first connecting electrode (CCE1) is connected to the first gate electrode (G1) through a first contact hole (CT1) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142), and can be connected to the first sub-source electrode (S31) and the fourth sub-drain electrode (D42) through a second contact hole (CT2) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0311] The second connecting electrode (CCE2) can be connected to the 17th drain electrode (D17) through a third contact hole (CT3) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142), connected to the 14th drain electrode (D14) through a fourth contact hole (CT4) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142), and connected to the 4th capacitor electrode (CE4) through a 15th contact hole (CT15) penetrating the second interlayer insulating film (142).

[0312] The fourth connecting electrode (CCE4) is connected to the sixth drain electrode (D6) through a tenth contact hole (CT10) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142), and can be connected to the fourth gate connecting electrode (GCE4) through a seventeenth contact hole (CT17) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142).

[0313] The fifth connecting electrode (CCE5) can be connected to the 12th source electrode (S12) and the 14th source electrode (S14) through 11th contact holes (CT11) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0314] The 6th connecting electrode (CCE6) is connected to the 8th gate electrode (G8) through a 12th contact hole (CT12) penetrating the 1st interlayer insulating film (141) and the 2nd interlayer insulating film (142), and can be connected to the 5th sub-source electrode (S101) and the 8th sub-drain electrode (D112) through a 13th contact hole (CT13) penetrating the gate insulating film (130), the 1st interlayer insulating film (141), and the 2nd interlayer insulating film (142).

[0315] The 7th connecting electrode (CCE7) can be connected to the 17th drain electrode (D17) and the 18th drain electrode (D18) through 16 contact holes (CT16) penetrating the gate insulating film (130), the 1st interlayer insulating film (141), and the 2nd interlayer insulating film (142).

[0316] The 8th connecting electrode (CCE8) can be connected to the 19th source electrode (S19) through a 21st contact hole (CT21) that penetrates the gate insulating film (130), the 1st interlayer insulating film (141), and the 2nd interlayer insulating film (142).

[0317] A first planarization film (160) may be disposed on the first source metal layer. The first planarization film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first planarization film (160) may be referred to as a fourth insulating film.

[0318] A second source metal layer may be disposed on the first planarization film (160). The second source metal layer may include a j-th data line (DLj), a first vertical power line (VVDL), and a first PAM data line (RDL). Additionally, the second source metal layer may include a first anode connection electrode (ANDE1) and a second power connection electrode (VDCE). The second source metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0319] The j data wiring (DLj) can be connected to the first data connection electrode (DCE1) through a second data contact hole (DCT2) penetrating the first flattening film (160). The first PAM data wiring (RDL) can be connected to the second data connection electrode (DCE2) through a fourth data contact hole (DCT4) penetrating the first flattening film (160). The first vertical power wiring (VVDL) can be connected to the first horizontal power wiring (HVDL) through a third power contact hole (VCT3) penetrating the first flattening film (160). The third power contact hole (VCT3) can overlap with the second power contact hole (VCT2) in the third direction (DR3). The area of ​​the third power contact hole (VCT3) can be larger than the area of ​​the second power contact hole (VCT2).

[0320] The first anode connection electrode (ANDE1) can be connected to the seventh connection electrode (CCE7) through the 20th contact hole (CT20) penetrating the first flattening film (160), and can be connected to the eighth connection electrode (CCE8) through the 22nd contact hole (CT22) penetrating the first flattening film (160). The second power connection electrode (VDCE) can be connected to the fifth connection electrode (CCE5) through the fourth power contact hole (VCT4) penetrating the first flattening film (160).

[0321] A second planarization film (170) may be disposed on the second source metal layer. The second planarization film (170) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second planarization film (170) may be referred to as a fifth insulating film.

[0322] A third source metal layer may be disposed on the second flattening film (170). The third source metal layer may include a third power wiring (VSL).

[0323] It may include a third power wiring (VSL). The third power wiring (VSL) may be connected to a second power connection electrode (VDCE) through a fifth power contact hole (VCT5) penetrating the second flattening film (170). The third source metal layer may be formed as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0324] A third planarization film (180) may be disposed on the third source metal layer. The third planarization film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The third planarization film (180) may be referred to as a fifth insulating film.

[0325] A fourth source metal layer including an anode electrode (AND) and a cathode electrode (CSD) may be disposed on the third planarization film (180).

[0326] Although not separately described, the fourth source metal layer may further include a second sub-power wiring and a third sub-power wiring.

[0327] The fourth source metal layer may be formed as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0328] The anode electrode (AND) can correspond to each of the multiple subpixels (RP, GP, BP).

[0329] The cathode electrode (CSD) is spaced apart from each anode electrode (AND) and can correspond to a plurality of subpixels (RP, GP, BP) in total.

[0330] A pad layer may be disposed on a portion of the fourth source metal layer. The pad layer may be made of a transparent conductive material (TCO) such as ITO or IZO.

[0331] The pad layer may include an anode pad (ANDP) on an anode electrode (AND) and a cathode pad (CSDP) disposed on a portion adjacent to the anode electrode (AND) among the cathode electrode (CSD).

[0332] A protective film (PAS) may be disposed on the pad layer. The protective film (PAS) may be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The protective film (PAS) may be exposed without covering a portion of the upper surface of the pixel electrode (AND).

[0333] A light-emitting element (LE) can be placed on an anode pad (ANDP) and a cathode pad (CSDP) that are not covered by a protective film (PAS).

[0334] An anode contact electrode (ANDC) made of a conductive adhesive material can be placed between the anode pad (ANDP) and the light-emitting element (LE).

[0335] Meanwhile, as previously explained in conjunction with Fig. 4, when the light-emitting element (LE) is of the flip-chip type, a step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) inevitably occurs due to the mesa structure.

[0336] Due to the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2), defects such as the light-emitting element (LE) being placed in a tilted state and connection failures such as the connection between at least one of the anode electrode (AND) and the cathode electrode (CSD) and the light-emitting element (LE) being severed can easily occur during placement of the light-emitting element (LE). Furthermore, since it is difficult to place the anode contact electrode (ANDC) between the first contact electrode (CTE1) and the anode pad (ANDP), and the cathode contact electrode (CSDC) between the second contact electrode (CTE2) and the cathode pad (CSDP) flatly, placement defects of the light-emitting element (LE) may be exacerbated.

[0337] To prevent this, a display panel (100) of one embodiment includes a step correction structure corresponding to at least one of an anode electrode (AND) and a cathode electrode (CSD).

[0338] The step correction structure is intended to position the anode electrode (AND) closer to the substrate (SUB) than the cathode electrode (CSD). Due to this step correction structure, the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) can be compensated, thereby reducing placement defects of the light-emitting element (LE).

[0339] Examples of step correction structures are described below with reference to FIGS. 33 to 39.

[0340] FIG. 33 is a cross-sectional view showing a first embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23.

[0341] Referring to FIG. 33, the step correction structure (SHC) according to the first embodiment includes a correction hole (CRH) that corresponds to the anode electrode (AND) and penetrates the third flattening film (180).

[0342] In this case, the anode electrode (AND) is placed on the second planarization film (170) exposed by the correction hole (CRH). Therefore, by the correction hole (CRH), the anode electrode (AND) can be placed closer to the substrate (SUB) than the cathode electrode (CSD) by the thickness of the third planarization film (180).

[0343] That is, by means of the correction hole (CRH), the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) can be compensated by the thickness of the third planarization film (180). As a result, the placement defect of the light-emitting element (LE) can be reduced.

[0344] FIG. 34 is a cross-sectional view showing a second embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23. FIG. 35 is a layout diagram showing a third source metal layer of a first subpixel according to the second embodiment.

[0345] Referring to FIG. 34, the step correction structure (SHC) according to the second embodiment includes a dummy pattern (DMP) that corresponds to the cathode electrode (CSD) and is composed of a second source metal layer on the second planarization film (170).

[0346] The cathode electrode (CSD) can be entirely overlapped with the dummy pattern (DMP) with the third planarization film (180) in between.

[0347] Referring to FIG. 35, the dummy pattern (DMP) may be an island-shaped pattern spaced apart from the third power line (VSL) and the second anode connection electrode (ANDE2). The dummy pattern (DMP) may be maintained in a floating state.

[0348] In this way, the cathode electrode (CSD) can be spaced further away from the substrate (SUB) than the anode electrode (AND) by the thickness of the dummy pattern (DMP) made of the second source metal layer.

[0349] That is, by means of a dummy pattern (DMP), the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) can be compensated by the thickness of the second source metal layer. As a result, placement defects of the light-emitting element (LE) can be reduced.

[0350] FIG. 36 is a cross-sectional view showing a third embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23.

[0351] Referring to FIG. 36, the step correction structure (SHC) according to the third embodiment includes the correction hole (CRH) of the first embodiment shown in FIG. 33 and the dummy pattern (DMP) of the second embodiment shown in FIG. 34.

[0352] The explanation of Correction Hole (CRH) and Dummy Pattern (DMP) is omitted as it is redundant.

[0353] According to this third embodiment, the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) can be compensated by the thickness of the third planarization film (180) and the thickness of the second source metal layer. As a result, the placement defect of the light-emitting element (LE) can be further reduced.

[0354] FIG. 37 is a cross-sectional view showing a fourth embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23.

[0355] Referring to FIG. 37, the display panel (100) according to the fourth embodiment is identical to the first embodiment shown in FIG. 33 except that it further includes a first auxiliary inorganic insulating film (171) disposed on the second flattening film (170), so a redundant description is omitted below.

[0356] Since the second source metal layer on the second planarization film (170) does not include a pattern that overlaps with the anode electrode (AND), the second planarization film (170) can be patterned together during the process of placing the correction hole (CRH) penetrating the third planarization film (180). As a result, a short circuit defect may occur in which the first source metal layer on the first planarization film (160) is electrically connected to the anode electrode (AND) through the correction hole (CRH).

[0357] To prevent this, the display panel of the fourth embodiment includes a first auxiliary inorganic insulating film (171) covering the second flattening film (170).

[0358] In this case, a third source metal layer including a third power wiring (VSL) and a second anode connection electrode (ANDE2) is placed on the first auxiliary inorganic insulating film (171).

[0359] And, a portion of the first auxiliary inorganic insulating film (171) is exposed by the correction hole (CRH), and the anode electrode (AND) can be placed on the first auxiliary inorganic insulating film (171) exposed through the correction hole (CRH).

[0360] According to this fourth embodiment, a short circuit defect between the anode electrode (AND) and the second source metal layer due to the arrangement of the correction hole (CRH) can be prevented.

[0361] FIG. 38 is a cross-sectional view showing a fifth embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23.

[0362] Referring to FIG. 38, the display panel according to the fifth embodiment is identical to the first embodiment shown in FIG. 33 except that it is placed on the first flattening film (160) and further includes a second auxiliary inorganic insulating film (172) covering a second source metal layer including a j-th data line (DLj), a first vertical power line (VVDL), a first PAM data line (RDL), and a first anode connection electrode (ANDE1), and that a correction hole (CRH') penetrates the third flattening film (180) and the second flattening film (170), so a redundant description is omitted below.

[0363] According to the fifth embodiment, a second auxiliary inorganic insulating film (172) is disposed between the second source metal layer and the second flattening film (170) on the first flattening film (160).

[0364] According to the fifth embodiment, the correction hole (CRH') penetrates the third flattening film (180) and the second flattening film (170) and exposes a portion of the second auxiliary inorganic insulating film (172). In this case, the anode electrode (AND) is placed on the second auxiliary inorganic insulating film (172) exposed by the correction hole (CRH').

[0365] Here, since the second source metal layer is covered with the second auxiliary inorganic insulating film (172), even if the correction hole (CRH') penetrates not only the third flattening film (180) but also the second flattening film (170), the short circuit defect between the anode electrode (AND) and the second source metal layer due to the arrangement of the correction hole (CRH') can be blocked.

[0366] In addition, since the second auxiliary inorganic insulating film (172) is not significantly affected by the patterning process of the second planarization film (170), the possibility of process errors occurring when placing the correction hole (CRH') can be reduced.

[0367] In addition, by means of a correction hole (CRH') penetrating the third planarization film (180) and the second planarization film (170), the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) can be compensated by the thickness of the third planarization film (180) and the thickness of the second planarization film (170). As a result, the placement defect of the light-emitting element (LE) can be further reduced.

[0368] FIG. 39 is a cross-sectional view showing a sixth embodiment of a display panel cut along K-K' of FIG. 18, FIG. 22, and FIG. 23.

[0369] Referring to FIG. 39, the display panel according to the 6th embodiment is identical to the 5th embodiment shown in FIG. 38 except that the correction hole (CRH) penetrates only a part of the second flattening film (170), so a redundant description is omitted below.

[0370] In the case of the fifth embodiment illustrated in FIG. 38, the correction hole (CRH') penetrates both the third flattening film (180) and the second flattening film (170) to expose the second auxiliary inorganic insulating film (172).

[0371] Since the surface of the second auxiliary inorganic insulating film (172) includes irregularities corresponding to the second source metal layer, the surface of the anode electrode (AND) disposed on the second auxiliary inorganic insulating film (172) may also include irregularities. In this case, contact failure between the anode contact electrode (ANDC) and the anode electrode (AND) may be caused by the irregularities on the surface of the anode electrode (AND).

[0372] On the other hand, according to the sixth embodiment illustrated in FIG. 39, since the correction hole (CRH) penetrates only a part of the second flattening film (180), the anode electrode (AND) can be placed on the other part of the second flattening film (180) exposed through the correction hole (CRH).

[0373] Since patterning is performed on the second flattening film (180) of the flat surface, the other part of the second flattening film (180) exposed through the correction hole (CRH) can also be made of a flat surface.

[0374] Accordingly, the anode electrode (AND) can be positioned to have a flat surface by being placed on another part of the flat second planarization film (180), so that contact failure between the anode contact electrode (ANDC) and the anode electrode (AND) can be prevented.

[0375] In addition, according to the 6th embodiment, by adjusting the depth of the correction hole (CRH) to correspond to the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE), the effect as a step difference correction structure (SCH) can be further improved.

[0376] Meanwhile, although not separately illustrated, the fourth embodiment illustrated in FIG. 37, the fifth embodiment illustrated in FIG. 38, and the sixth embodiment illustrated in FIG. 39 can be modified into a structure that further includes the dummy pattern (DMP) of the second embodiment illustrated in FIG. 34 and FIG. 35.

[0377] In this way, the step difference between the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light-emitting element (LE) can be compensated by the depth of the correction hole (SHC, SHC', SCH") plus the thickness of the second source metal layer, so that the placement defect of the light-emitting element (LE) can be further reduced.

[0378] FIG. 40 is a perspective view showing a tile-type display device including a plurality of display devices according to one embodiment.

[0379] Referring to FIG. 40, a tile-type display device (TD) according to one embodiment may include a plurality of display devices (11, 12, 13, 14) arranged side by side in a first direction (DR1) and a second direction (DR2), and a joint (SM) between the plurality of display devices (11, 12, 13, 14).

[0380] For example, the tile-type display device (TD) may include a first display device (11), a second display device (12), a third display device (13), and a fourth display device (14).

[0381] Multiple display devices (11, 12, 13, 14) may be arranged in a grid form. Multiple display devices (11, 12, 13, 14) may be arranged in a matrix form with m (m is a positive integer) rows and n (n is a positive integer) columns. For example, the first display device (11) and the second display device (12) may be adjacent to each other in the first direction (DR1). The first display device (11) and the third display device (13) may be adjacent to each other in the second direction (DR2). The third display device (13) and the fourth display device (14) may be adjacent to each other in the first direction (DR1). The second display device (12) and the fourth display device (14) may be adjacent to each other in the second direction (DR2).

[0382] However, the number and arrangement of multiple display devices (11, 12, 13, 14) in the tile-type display device (TD) are not limited to those shown in FIG. 40. The number and arrangement of display devices (11, 12, 13, 14) in the tile-type display device (TD) may be determined according to the size of each of the display device (10) and the tile-type display device (TD) and the shape of the tile-type display device (TD).

[0383] Multiple display devices (11, 12, 13, 14) may have the same size as each other, but are not limited thereto. For example, multiple display devices (11, 12, 13, 14) may have different sizes.

[0384] Each of the plurality of display devices (11, 12, 13, 14) may have a rectangular shape including a long side and a short side. The plurality of display devices (11, 12, 13, 14) may be arranged such that their long sides or short sides are connected to one another. Some or all of the plurality of display devices (11, 12, 13, 14) may be placed at the edge of the tile-type display device (TD) and may form one side of the tile-type display device (TD). At least one of the plurality of display devices (11, 12, 13, 14) may be placed at at least one corner of the tile-type display device (TD) and may form two adjacent sides of the tile-type display device (TD). At least one of the plurality of display devices (11, 12, 13, 14) may be surrounded by other display devices.

[0385] Each of the plurality of display devices (11, 12, 13, 14) may be substantially identical to the display device (10) of each embodiment described in conjunction with FIGS. 1 to 39. Therefore, a description of each of the plurality of display devices (11, 12, 13, 14) is omitted.

[0386] The joint (SM) may include a connecting member or an adhesive member. In this case, a plurality of display devices (11, 12, 13, 14) may be connected to each other through the connecting member or adhesive member of the joint (SM). The joint (SM) may be positioned between the first display device (11) and the second display device (12), between the first display device (11) and the third display device (13), between the second display device (12) and the fourth display device (14), and between the third display device (13) and the fourth display device (14).

[0387] Figure 41 is an enlarged layout diagram showing the L region of Figure 40 in detail.

[0388] Referring to FIG. 41, the joint (SM) may have a planar shape of a column cross, a cross, or an addition sign in the central area of ​​a tiled display device (TD) where the first display device (11), the second display device (12), the third display device (13), and the fourth display device (14) are adjacent. The joint (SM) may be positioned between the first display device (11) and the second display device (12), between the first display device (11) and the third display device (13), between the second display device (12) and the fourth display device (14), and between the third display device (13) and the fourth display device (14).

[0389] The first display device (11) may include first pixels (PX1) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The second display device (12) may include second pixels (PX2) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The third display device (13) may include third pixels (PX3) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The fourth display device (14) may include fourth pixels (PX4) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image.

[0390] The minimum distance between adjacent first pixels (PX1) in the first direction (DR1) is defined as the first horizontal separation distance (GH1), and the minimum distance between adjacent second pixels (PX2) in the first direction (DR1) can be defined as the second horizontal separation distance (GH2). The first horizontal separation distance (GH1) and the second horizontal separation distance (GH2) may be substantially the same.

[0391] A joint (SM) may be disposed between adjacent first pixel (PX1) and second pixel (PX2) in the first direction (DR1). The minimum distance (G12) between adjacent first pixel (PX1) and second pixel (PX2) in the first direction (DR1) may be the sum of the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) in the first direction (DR1), the minimum distance (GHS2) between the second pixel (PX2) and the joint (SM) in the first direction (DR1), and the width (GSM1) of the joint (SM) in the first direction (DR1).

[0392] In the first direction (DR1), the minimum distance (G12), the first horizontal separation distance (GH1), and the second horizontal separation distance (GH2) between adjacent first pixels (PX1) and second pixels (PX2) may be substantially the same. To this end, in the first direction (DR1), the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) may be smaller than the first horizontal separation distance (GH1), and the minimum distance (GHS2) between the second pixel (PX2) and the joint (SM) in the first direction (DR1) may be smaller than the second horizontal separation distance (GH2). Additionally, in the first direction (DR1), the width (GSM1) of the joint (SM) may be smaller than the first horizontal separation distance (GH1) or the second horizontal separation distance (GH2).

[0393] The minimum distance between adjacent third pixels (PX3) in the first direction (DR1) is defined as the third horizontal separation distance (GH3), and the minimum distance between adjacent fourth pixels (PX4) in the first direction (DR1) can be defined as the fourth horizontal separation distance (GH4). The third horizontal separation distance (GH3) and the fourth horizontal separation distance (GH4) may be substantially the same.

[0394] A joint (SM) may be disposed between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1). The minimum distance (G34) between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1) may be the sum of the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) in the first direction (DR1), the minimum distance (GHS4) between the fourth pixel (PX4) and the joint (SM) in the first direction (DR1), and the width (GSM1) of the joint (SM) in the first direction (DR1).

[0395] In the first direction (DR1), the minimum distance (G34), the third horizontal separation distance (GH3), and the fourth horizontal separation distance (GH4) between adjacent third pixels (PX3) and fourth pixels (PX4) may be substantially the same. To this end, in the first direction (DR1), the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) may be smaller than the third horizontal separation distance (GH3), and the minimum distance (GHS4) between the fourth pixel (PX4) and the joint (SM) in the first direction (DR1) may be smaller than the fourth horizontal separation distance (GH4). Additionally, in the first direction (DR1), the width (GSM1) of the joint (SM) may be smaller than the third horizontal separation distance (GH3) or the fourth horizontal separation distance (GH4).

[0396] The minimum distance between neighboring first pixels (PX1) in the second direction (DR2) is defined as the first vertical separation distance (GV1), and the minimum distance between neighboring third pixels (PX3) in the second direction (DR2) can be defined as the third vertical separation distance (GV3). The first vertical separation distance (GV1) and the third vertical separation distance (GV3) may be substantially the same.

[0397] A joint (SM) may be disposed between adjacent first pixel (PX1) and third pixel (PX3) in the second direction (DR2). The minimum distance (G13) between adjacent first pixel (PX1) and third pixel (PX3) in the second direction (DR2) may be the sum of the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) in the second direction (DR2), the minimum distance (GVS3) between the third pixel (PX3) and the joint (SM) in the second direction (DR2), and the width (GSM2) of the joint (SM) in the second direction (DR2).

[0398] In the second direction (DR2), the minimum distance (G13), the first vertical separation distance (GV1), and the third vertical separation distance (GV3) between adjacent first pixel (PX1) and third pixel (PX3) may be substantially the same. To this end, in the second direction (DR2), the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) may be smaller than the first vertical separation distance (GV1), and the minimum distance (GVS3) between the third pixel (PX3) and the joint (SM) in the second direction (DR2) may be smaller than the third vertical separation distance (GV3). Additionally, in the second direction (DR2), the width (GSM2) of the joint (SM) may be smaller than the first vertical separation distance (GV1) or the third vertical separation distance (GV3).

[0399] The minimum distance between adjacent second pixels (PX2) in the second direction (DR2) is defined as the second vertical separation distance (GV2), and the minimum distance between adjacent fourth pixels (PX4) in the second direction (DR2) can be defined as the fourth vertical separation distance (GV4). The second vertical separation distance (GV2) and the fourth vertical separation distance (GV4) may be substantially the same.

[0400] A joint (SM) may be disposed between adjacent second pixels (PX2) and fourth pixels (PX4) in the second direction (DR2). The minimum distance (G24) between adjacent second pixels (PX2) and fourth pixels (PX4) in the second direction (DR2) may be the sum of the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) in the second direction (DR2), the minimum distance (GVS4) between the fourth pixel (PX4) and the joint (SM) in the second direction (DR2), and the distance (GSM4) of the joint (SM) in the second direction (DR2).

[0401] In the second direction (DR2), the minimum distance (G24), the second vertical separation distance (GV2), and the fourth vertical separation distance (GV4) between adjacent second pixels (PX2) and fourth pixels (PX4) may be substantially the same. To this end, in the second direction (DR2), the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) may be smaller than the second vertical separation distance (GV2), and the minimum distance (GVS4) between the fourth pixel (PX4) and the joint (SM) in the second direction (DR2) may be smaller than the fourth vertical separation distance (GV4). Additionally, in the second direction (DR2), the width (GSM2) of the joint (SM) may be smaller than the second vertical separation distance (GV2) or the fourth vertical separation distance (GV4).

[0402] As shown in FIG. 41, in order to prevent a seam (SM) from being visible between images displayed by a plurality of display devices (11, 12, 13, 14), the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between pixels of each display device.

[0403] FIG. 42 is a cross-sectional view showing an example of a tile-type display device cut along N-N' of FIG. 41.

[0404] Referring to FIG. 42, the first display device (11) includes a first display module (DPM1) and a first front cover (COV1). The second display device (12) includes a second display module (DPM2) and a second front cover (COV2).

[0405] Each of the first display module (DPM1) and the second display module (DPM2) includes a substrate (SUB), a thin-film transistor layer (TFTL), and a light-emitting element layer (EML). Since the thin-film transistor layer (TFTL) and the light-emitting element layer (EML) have already been described in detail in conjunction with FIGS. 4, FIGS. 23 to 27, etc., a redundant description is omitted.

[0406] A substrate (SUB) may include a first surface on which a thin-film transistor layer (TFTL) is disposed, a second surface facing the first surface, and a first side surface disposed between the first surface and the second surface. The first surface may be the front or top surface of the substrate (SUB), and the second surface may be the back or bottom surface of the substrate (SUB).

[0407] In addition, the substrate (SUB) may further include a chamfer surface formed of an inclined surface that is positioned between the first surface and the first side and between the second surface and the first side.

[0408] A thin-film transistor layer (TFTL) and a light-emitting element layer (EML) may not be placed on the chamfered surface. Since the width of the first side is reduced due to the chamfered surface, the collision and damage between the substrate (SUB) of the first display device (11) and the substrate of the second display device (12) can be reduced.

[0409] A chamfered surface may also be positioned between each of the other sides excluding the first side and between each of the other sides excluding the first side and between the second side and between each of the other sides excluding the first side. For example, if the first display device (11) and the second display device (12) have a rectangular planar shape as in FIG. 41, the substrate (SUB) may include a chamfered surface positioned between each of the first side and the second side, the third side, and the fourth side, and between each of the second side and the second side, the third side, and the fourth side.

[0410] The first front cover (COV1) may overlap the chamfered surface of the substrate (SUB). That is, the first front cover (COV1) may protrude beyond the substrate (SUB) in the first direction (DR1) and the second direction (DR2). Therefore, the distance (GSUB) between the substrate (SUB) of the first display device (11) and the substrate (SUB) of the second display device (12) may be greater than the distance (GCOV) between the first front cover (COV1) and the second front cover (COV2).

[0411] Each of the first front cover (COV1) and the second front cover (COV2) may include an adhesive member (51), a light transmittance control layer (52) disposed on the adhesive member (51), and an anti-glare layer (53) disposed on the light transmittance control layer (52).

[0412] The adhesive member (51) of the first front cover (COV1) serves to attach the light-emitting element layer (EML) of the first display module (DPM1) to the first front cover (COV1).

[0413] The adhesive member (51) of the second front cover (COV2) serves to attach the light-emitting element layer (EML2) of the second display module (DPM2) to the second front cover (COV2).

[0414] The adhesive member (51) may be a transparent adhesive member capable of transmitting light. For example, the adhesive member (51) may be an optically clear adhesive film or an optically clear resin.

[0415] The anti-glare layer (53) can be designed to diffusely reflect external light to prevent the external light from being reflected as is and to prevent a decrease in the visibility of the image. Accordingly, due to the anti-glare layer (53), the contrast ratio of the image displayed by the first display device (11) and the second display device (12) can be increased.

[0416] The light transmittance control layer (52) can be designed to reduce the transmittance of external light or light reflected from the first display module (DPM1) and the second display module (DPM2). As a result, the gap (GSUB) between the substrate (SUB) of the first display module (DPM1) and the substrate (SUB) of the second display module (DPM2) can be prevented from being visible from the outside.

[0417] The anti-glare layer (53) may be implemented as a polarizing plate, and the light transmittance control layer (52) may be implemented as a phase delay layer, but the embodiments of the present specification are not limited thereto.

[0418] Figure 43 is an enlarged layout diagram showing the M area of ​​Figure 40 in detail.

[0419] FIG. 43 shows pads (PADs) and first pixels (PX1) placed on the upper side of the first display device (10).

[0420] Referring to FIG. 43, pads (PADs) may be placed on the upper edge of the first display device (11). When the data lines (DL) of the first display device (11) extend in a second direction (DR2), pads (PADs) may be placed on the upper and lower edges of the first display device (11). Alternatively, when the data lines (DL) of the first display device (11) extend in a first direction (DR1), pads (PADs) may be placed on the left and right edges of the first display device (11).

[0421] Each of the pads (PAD) can be connected to the data line (DL). Alternatively, the pad (PAD) can be formed as part of the data line (DL).

[0422] Additionally, each of the pads (PAD) can be connected to a side wiring (SSL). The side wiring (SSL) can be placed on one side and the bottom (or back) of the substrate (SUB). The side wiring (SSL) can be connected to a connecting wire (CCL in FIG. 44) on the bottom of the substrate (SUB).

[0423] FIG. 44 is a cross-sectional view showing an example of a tile-type display device cut along O-O' of FIG. 43.

[0424] Referring to FIG. 44, the pad may be formed as part of the data wiring (DL) on the second interlayer insulating film (142).

[0425] Alternatively, although not separately described, the pad may be composed of a conductive pattern placed on a part of the data wiring (DL).

[0426] Alternatively, although not separately illustrated, the pad may be formed as a conductive pattern that is placed on an insulating film (not illustrated) covering the data wiring (DL) and contacts a part of the data wiring (DL) through a hole penetrating the insulating film.

[0427] When a pad consisting of a separate conductive pattern is disposed, the pad may be exposed without being covered by a planarization film or other insulating film. The pad may comprise the same material as the anode electrodes (AND) and cathode electrodes (CSD). The pad may comprise a highly reflective metallic material such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a laminated structure of APC alloy and ITO (ITO / APC / ITO).

[0428] The first data metal layer (DTL1) may include a data wiring (DL). The data wiring (DL) may be placed on the second interlayer insulating film (142). That is, the data wiring (DL) may be placed on the same layer as the first connecting electrode (CE1) and may include the same material.

[0429] The connecting wiring (CCL) may be disposed on the lower surface of the substrate (SUB). The connecting wiring (CCL) may be a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0430] The lower flattening film (INS1) can be placed on a part of the connecting wiring (CCL). The lower flattening film (INS1) can be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0431] The lower insulating film (INS2) can be placed on the lower planarization film (INS1). The lower insulating film (INS2) can be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0432] Side wiring (SSL) can be placed on the bottom edge, side, and top edge of the substrate (SUB). One end of the side wiring (SSL) can be connected to the connection wiring (CCL). One end of the side wiring (SSL) can be in contact with the side and bottom of the connection wiring (CCL). The other end of the side wiring (SSL) can be connected to a pad or data wiring (DL). The other end of the side wiring (SSL) can be connected to the pad or data wiring (DL) through a contact hole penetrating the protective film (PAS).

[0433] Side wiring (SSL) can be placed on the side of the substrate (SUB), the side of the buffer film (BF), the side of the gate insulating film (130), the side of the first interlayer insulating film (141), and the side of the second interlayer insulating film (142).

[0434] A flexible film (FPCB) can be placed on the lower surface of a lower insulating film (INS2). The flexible film (FPCB) can be connected to a connecting wire (CCL) through a hole penetrating the lower planarization film (INS1) and the lower insulating film (INS2) and a conductive adhesive member (CAM). A source driving circuit (SIC) for supplying data voltages to data wires (DL) can be placed on the lower surface of the flexible film (FPCB). The conductive adhesive member (CAM) can be an anisotropic conductive film or anisotropic conductive paste.

[0435] As shown in FIGS. 43 and 44, the source driving circuit (SIC) of the flexible film (FPCB) of the first display device (11) placed on the lower part of the substrate (SUB) can be connected to the data wiring (DL) through the connection wiring (CCL), side wiring (SSL), and pad (PAD). That is, since the source driving circuit (SIC) is placed on the lower part of the substrate (SUB), the non-display area (NDA) on the upper part of the substrate (SUB) can be eliminated, so pixels (PX) can also be formed on the edges of the substrate (SUB).

[0436] FIG. 45 is a block diagram showing a tile-type display device according to one embodiment.

[0437] Figure 45 illustrates the first display device (11) and the host system (HOST).

[0438] Referring to FIG. 45, a tile-type display device (TD) according to one embodiment is connected to a host system (HOST).

[0439] The host system (HOST) can be implemented as any one of a television system, home theater system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), mobile phone system, or tablet.

[0440] User commands can be input to the host system in various formats. For example, the host system may receive commands via user touch input. Alternatively, the host system may receive user commands via keyboard input or button input from a remote controller.

[0441] The host system (HOST) can receive original video data (ODATA) corresponding to the original image from an external source. The host system (HOST) can divide the original video data (ODATA) according to the number of display devices. For example, the host system (HOST) can divide the original video data (ODATA) into first video data (DATA1) corresponding to the first image, second video data (DATA2) corresponding to the second image, third video data (DATA3) corresponding to the third image, and fourth video data (DATA4) corresponding to the fourth image, corresponding to the first display device (11), second display device (12), third display device (13), and fourth display device (14). The host system (HOST) can transmit the first video data (DATA1) to the first display device (11), transmit the second video data (DATA2) to the second display device (12), transmit the third video data (DATA3) to the third display device (13), and transmit the fourth video data (DATA4) to the fourth display device (14).

[0442] The first display device (11) can display a first image according to the first video data (DATA1), the second display device (12) can display a second image according to the second video data (DATA2), the third display device (13) can display a third image according to the third video data (DATA3), and the fourth display device (14) can display a fourth image according to the fourth video data (DATA4). Accordingly, the user can view an original image in which the first to fourth images displayed on the first to fourth display devices (11, 12, 13, 14) are combined.

[0443] The first display device (11) may include a broadcast tuning unit (510), a signal processing unit (520), a display unit (530), a speaker (540), a user input unit (550), an HDD (560), a network communication unit (570), a UI generation unit (580), and a control unit (590).

[0444] The broadcast tuning unit (510) can receive a broadcast signal of a corresponding channel by tuning a predetermined channel frequency according to the control of the control unit (590). The broadcast tuning unit (510) may include a channel detection module and an RF demodulation module.

[0445] The broadcast signal demodulated by the broadcast tuning unit (510) is processed by the signal processing unit (520) and output to the display unit (530) and speaker (540). Here, the signal processing unit (520) may include a demultiplexer (521), a video decoder (522), a video processing unit (523), an audio decoder (524), and an additional data processing unit (525).

[0446] The demultiplexer (521) separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by a video decoder (522), an audio decoder (524), and an additional data processing unit (525), respectively. At this time, the video decoder (522), the audio decoder (524), and the additional data processing unit (525) restore the signal into a decoding format corresponding to the encoding format used during broadcast signal transmission.

[0447] Meanwhile, the decoded video signal is converted by the video processing unit (523) to match the vertical frequency, resolution, aspect ratio, etc., that match the output specifications of the display unit (530), and the decoded audio signal is output to the speaker (540).

[0448] The display unit (530) includes a display panel (100) on which an image is displayed and a panel driving unit that controls the operation of the display panel (100). Since detailed block diagrams of the display panel (100) and the panel driving unit have been described in FIG. 4 and others, redundant descriptions are omitted.

[0449] The user input unit (550) can receive signals transmitted by the host system (HOST). The user input unit (550) can be configured to receive data regarding the selection and operation of the channel transmitted by the host system (HOST), as well as commands regarding communication with other display devices (DV2~DV4), which the user selects and inputs.

[0450] The storage unit (560) stores various software programs including OS programs, recorded broadcast programs, videos, photos, and other data, and may be made of a storage medium such as a hard disk or non-volatile memory.

[0451] The network communication unit (570) is for short-range communication with the host system (HOST) and other display devices (DV2~DV4), and can be implemented as a communication module including an antenna pattern capable of implementing mobile communication, data communication, Bluetooth, RF, Ethernet, etc.

[0452] The network communication unit (570) may transmit and receive wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network built according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), 5G, etc.) through an antenna pattern described later.

[0453] The network communication unit (570) may transmit and receive wireless signals in a communication network according to wireless internet technologies through an antenna pattern described later. Examples of wireless internet technologies include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc., and the antenna pattern transmits and receives data according to at least one wireless internet technology within a range that includes internet technologies not listed above.

[0454] The UI generation unit (580) generates a UI menu for communication with the host system (HOST) and other display devices (DV2~DV4), and can be implemented by algorithm code and OSD IC. The UI menu for communication with the host system (HOST) and other display devices (DV2~DV4) may be a menu for specifying the corresponding digital TV to communicate with and selecting the desired function.

[0455] The control unit (590) is responsible for overall control of the first display device (11) and for communication control of the host system (HOST) and the second to fourth display devices (12, 13, 14), and can be implemented by an MCU (Micro Controller Unit) in which the corresponding algorithm code for control is stored and the stored algorithm code is executed.

[0456] The control unit (590) controls the transmission of corresponding control commands and data to the host system (HOST) and the second to fourth display devices (12, 13, 14) via the network communication unit (570) according to the input and selection of the user input unit (550). Of course, when a predetermined control command and data are input from the host system (HOST) and the second to fourth display devices (12, 13, 14), an operation is performed according to the corresponding control command.

[0457] Meanwhile, the block diagram of the second display device (12), the block diagram of the third display device (13), and the block diagram of the fourth display device (14) are substantially identical to the block diagram of the first display device (11) described in conjunction with FIG. 45, so the description of these is omitted.

[0458] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0459] 100: Display panel PX: Pixel RP, GP, BP: 1st, 2nd, and 3rd subpixels SUB: Substrate TFTL: Thin-film transistor layer EML: Light-emitting diode layer CRH: Correction hole AND: Anode electrode CSD: Cathode electrode ANDC: Anode contact electrode CSDC: Cathode contact electrode PAS: Protective layer LE: Light-emitting element SPUB: Base substrate NSEM: n-type semiconductor MQW: Active layer PSEM: p-type semiconductor CTE1, 2: 1st and 2nd contact electrodes 10: Display device DA: Display area NDA: Non-display area 110: Scan drive unit 200: Source driver 300: Timing controller 400: Power supply GWL: Scan entry wiring GIL: Scan initialization wiring GCL: Scan control wiring SWL: Sweep signal wiring PWEL: PWM light-emitting wiring PAEL: PAM light-emitting wiring DL: PWM data wiring RDL, GDL, BDL: 1st, 2nd, and 3rd PAM data wiring DATA: Digital video data TS: Timing signal DCS: PWM control signal VDD1, 2: 1st and 2nd power supply voltages VSS: Third power supply voltage VINT: Initialization voltage VGL: Gate-on voltage VGH: Gate-off voltage PDU1, PDU2, PDU3: 1st, 2nd, and 3rd pixel drivers AVSL: 3rd Power Auxiliary Wiring VSL: 3rd Power Wiring ANDE1, 2: First and second anode connecting electrodes SHC: Step correction structure DMP: Dummy pattern CRH', CRH": Correction hole 171, 172: 1st and 2nd auxiliary inorganic insulating films TD: Tile display 11, 12, 13, 14: 1st, 2nd, 3rd, and 4th display devices

Claims

Claim 1 A substrate including a display area in which a plurality of subpixels are arranged; an active layer disposed on the substrate; and a gate insulating film covering the active layer. A first interlayer insulating film covering a first gate metal layer disposed on the gate insulating film; a second interlayer insulating film covering a second gate metal layer disposed on the first interlayer insulating film; a first planarization film covering a first source metal layer disposed on the second interlayer insulating film; a second planarization film covering a second source metal layer disposed on the first planarization film; a third planarization film covering a third source metal layer disposed on the second planarization film; and a fourth source metal layer disposed on the third planarization film, wherein the fourth source metal layer comprises a plurality of anode electrodes corresponding to each of the plurality of subpixels, and a cathode electrode corresponding to the plurality of subpixels and spaced apart from each of the plurality of anode electrodes, wherein the anode electrode is disposed closer to the substrate than the cathode electrode by a step correction structure corresponding to at least one of the anode electrode or the cathode electrode, and the step correction structure corresponds to the anode electrode and the third planarization film A display device including a penetrating correction hole. Claim 2 A display device according to claim 1, further comprising a plurality of light-emitting elements disposed on each of the plurality of anode electrodes and the cathode electrode and corresponding to each of the plurality of subpixels, wherein the plurality of light-emitting elements are flip-chip type micro light-emitting diode elements. Claim 3 In claim 2, the anode electrode is a display device disposed on the second planarization film exposed through the correction hole. Claim 4 In claim 3, the step correction structure further comprises an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode is a display device superimposed on the dummy pattern. Claim 5 A display device according to claim 3, further comprising a first auxiliary inorganic insulating film covering the second planarization film, wherein the third source metal layer is disposed on the first auxiliary inorganic insulating film. Claim 6 In claim 3, the display device further comprises a second auxiliary inorganic insulating film covering the second source metal layer, wherein the second planarization film is disposed on the second auxiliary inorganic insulating film. Claim 7 A display device according to claim 6, wherein the correction hole further penetrates the second planarization film and exposes a portion of the second auxiliary inorganic insulating film, and the anode electrode is disposed on the exposed second auxiliary inorganic insulating film. Claim 8 In claim 7, the step correction structure further comprises an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode is a display device superimposed on the dummy pattern. Claim 9 A display device according to claim 6, wherein the correction hole further penetrates a portion of the second planarization film, and the anode electrode is disposed on another portion of the second planarization film. Claim 10 In claim 9, the step correction structure further comprises an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode is a display device superimposed on the dummy pattern. Claim 11 In claim 2, further comprising: a scan write wiring to which a scan write signal is applied; a scan initialization wiring to which a scan initialization signal is applied; a sweep signal wiring to which a sweep signal is applied; a first data wiring to which a first data voltage is applied; and a second data wiring to which a second data voltage is applied, wherein each of the plurality of sub-pixels is connected to the scan write wiring, the scan initialization wiring, the sweep signal wiring, the first data wiring, and the second data wiring, and each of the plurality of sub-pixels comprises: a first pixel driver that generates a control current according to the first data voltage of the first data wiring; and a second pixel driver that generates a driving current applied to the anode electrode according to the second data voltage of the second data wiring. A display device comprising a third pixel driver that controls the period for applying the driving current to the light-emitting element according to the control current of the first pixel driver, wherein the first pixel driver comprises: a first transistor that generates the control current according to the first data voltage; a second transistor that applies the first data voltage of the first data wiring to the first electrode of the first transistor according to the scan write signal; a third transistor that applies the initial voltage of the initial voltage wiring to the gate electrode of the first transistor according to the scan initialization signal; a fourth transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal; and a first capacitor disposed between the sweep signal wiring and the gate electrode of the first transistor. Claim 12 A display device according to claim 11, further comprising: a first power wiring to which a first power supply voltage is applied; a second power wiring to which a second power supply voltage is applied; a first light-emitting wiring to which a first light-emitting signal is applied; and a scan control wiring to which a scan control signal is applied, wherein the first pixel driving unit further comprises: a fifth transistor that connects the first power wiring to a first electrode of the first transistor according to the first light-emitting signal; a sixth transistor that connects the second electrode of the first transistor to a first node according to the first light-emitting signal; and a seventh transistor that connects the sweep signal wiring to a gate-off voltage wiring to which a gate-off voltage is applied according to the scan control signal. Claim 13 In claim 12, the second pixel driving unit comprises: an eighth transistor that generates the driving current according to the second data voltage; a ninth transistor that applies the second data voltage of the second data wiring to the first electrode of the eighth transistor according to the scan write signal; a tenth transistor that applies the initialization voltage of the initialization voltage wiring to the gate electrode of the eighth transistor according to the scan initialization signal; and an eleventh transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal. Claim 14 In claim 13, the second pixel driving unit further comprises: a 12th transistor that connects the first power wiring to a second node according to the scan control signal; a 13th transistor that connects the second power wiring to the first electrode of the 9th transistor according to the first light emission signal; a 14th transistor that connects the second power wiring to the second node according to the first light emission signal; and a second capacitor disposed between the gate electrode of the 9th transistor and the second node. Claim 15 In claim 14, the third pixel driver comprises: a 15th transistor having a gate electrode electrically connected to the 6th transistor through a third node; a 16th transistor connecting the 1st node to the initialization voltage wiring according to the scan control signal; a 17th transistor connecting the 2nd electrode of the 15th transistor to the 1st electrode of the light-emitting element according to the 2nd light-emitting signal; an 18th transistor connecting the 1st electrode of the light-emitting element to the initialization voltage wiring according to the scan control signal; and a third capacitor disposed between the third node and the initialization voltage wiring. Claim 16 In claim 15, the display device further comprises a test signal wiring to which a test signal is applied; and a third power wiring to which a third power supply voltage is applied, wherein the third pixel driving unit further comprises a 19 transistor that connects the first electrode of the light-emitting element to the third power wiring according to the test signal, and the cathode electrode is connected to the third power wiring. Claim 17 In claim 16, the active layer comprises a channel, source electrode, and drain electrode for each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, twelfth, thirteenth, eleventh, twelfth, twelfth, twelfth, twelfth, twelfth, twelfth, and twelfth transistors, and the first gate metal layer comprises a gate electrode for each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, eleventh, twelfth, twelfth, twelfth, twelfth, twelfth, and twelfth transistors, and first, third, and fifth capacitor electrodes which are one end of each of the first, second, and third capacitors, and the second gate metal layer comprises second, fourth, and sixth capacitor electrodes which are the other end of each of the first, second, and third capacitors, respectively, in a display device. Claim 18 In claim 17, the first source metal layer comprises the initialization voltage wiring, the scan initialization wiring, the scan write wiring, the first light-emitting wiring, the second light-emitting wiring, the first horizontal power wiring to which the first power supply voltage is applied, the sweep signal wiring, the gate off voltage wiring, the scan control wiring, the test signal wiring, and the third power auxiliary wiring to which the third power supply voltage is applied, and the second source metal layer comprises the first data wiring, the first vertical power wiring to which the first power supply voltage is applied, the second data wiring, and the first anode connection electrode, and the first anode connection electrode is connected to the drain electrode of the 17th transistor and the drain electrode of the 18th transistor. Claim 19 In claim 18, the display device comprising a third source metal layer to which the third power supply voltage is applied, a third power wiring to which the third power supply voltage is applied, and a second anode connecting electrode connected to the first anode connecting electrode. Claim 20 A display device according to claim 2, further comprising: an anode pad corresponding to each of the plurality of subpixels and disposed on the anode electrode; and a cathode pad corresponding to each of the plurality of subpixels and disposed on the cathode electrode, wherein each of the plurality of light-emitting elements comprises a base substrate, an n-type semiconductor disposed on one surface of the base substrate facing the substrate, an active layer disposed on a part of the n-type semiconductor, a p-type semiconductor disposed on the active layer, a first contact electrode disposed on the p-type semiconductor and facing the anode electrode, and a second contact electrode disposed on another part of the n-type semiconductor and facing the cathode electrode, wherein the first contact electrode is attached to the anode pad through an anode contact electrode, and the second contact electrode is attached to the cathode pad through a cathode contact electrode. Claim 21 A plurality of display devices and a joint disposed between the plurality of display devices, wherein any one of the plurality of display devices comprises: a substrate including a display area in which a plurality of subpixels are arranged; an active layer disposed on a first surface of the substrate; and a gate insulating film covering the active layer. A first interlayer insulating film covering a first gate metal layer disposed on the gate insulating film; a second interlayer insulating film covering a second gate metal layer disposed on the first interlayer insulating film; a first planarization film covering a first source metal layer disposed on the second interlayer insulating film; a second planarization film covering a second source metal layer disposed on the first planarization film; a third planarization film covering a third source metal layer disposed on the second planarization film; and a fourth source metal layer disposed on the third planarization film, wherein the fourth source metal layer comprises a plurality of anode electrodes corresponding to each of the plurality of subpixels, and a cathode electrode corresponding to the plurality of subpixels and spaced apart from each of the plurality of anode electrodes, wherein the anode electrode is disposed closer to the substrate than the cathode electrode by a step correction structure corresponding to at least one of the anode electrode or the cathode electrode, and the step correction structure corresponds to the anode electrode and the third planarization film Tile-type display device including a penetrating correction hole. Claim 22 In claim 21, the substrate is a tile-type display device made of glass. Claim 23 A tile-type display device according to claim 21, wherein any one of the display devices comprises: a pad disposed on a first surface of the substrate; and a side wiring disposed on a first surface of the substrate, a second surface opposite to the first surface, and a side wiring connected to the pad, the side wiring being disposed on a side between the first surface and the second surface. Claim 24 In claim 23, any one of the display devices further comprises a connecting wire disposed on a second surface of the substrate; and a flexible film connected to the connecting wire through a conductive adhesive member, wherein the side wiring is connected to the connecting wire, forming a tile-type display device. Claim 25 In claim 21, the plurality of display devices are tile-type display devices arranged in a matrix form with M rows and N columns. Claim 26 In claim 21, the tile-type display device further comprises a plurality of light-emitting elements corresponding to each of the plurality of subpixels and disposed on each of the plurality of anode electrodes and the cathode electrode, wherein the plurality of light-emitting elements are flip-chip type micro light-emitting diode elements. Claim 27 In claim 26, the anode electrode is a tile-type display device disposed on the second flattening film exposed through the correction hole. Claim 28 In claim 27, the step correction structure further comprises an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode is a tile-type display device superimposed on the dummy pattern. Claim 29 In claim 27, any one of the above display devices further comprises a first auxiliary inorganic insulating film covering the second planarization film, and the third source metal layer is disposed on the first auxiliary inorganic insulating film, forming a tile-type display device. Claim 30 In claim 27, any one of the above display devices further comprises a second auxiliary inorganic insulating film covering the second source metal layer, and the second planarizing film is a tile-type display device disposed on the second auxiliary inorganic insulating film. Claim 31 A tile-type display device according to claim 30, wherein the correction hole further penetrates the second planarization film and exposes a portion of the auxiliary inorganic insulating film, and the anode electrode is disposed on the exposed auxiliary inorganic insulating film. Claim 32 In claim 31, the step correction structure further comprises an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode is a tile-type display device superimposed on the dummy pattern. Claim 33 A tile-type display device according to claim 30, wherein the correction hole further penetrates a portion of the second planarization film, and the anode electrode is disposed on another portion of the second planarization film. Claim 34 In claim 33, the step correction structure further comprises an island-shaped dummy pattern corresponding to the cathode electrode and composed of the second source metal layer, and the cathode electrode is a tile-type display device superimposed on the dummy pattern. Claim 35 In claim 26, the above-mentioned display device further comprises an anode pad corresponding to each of the plurality of subpixels and disposed on the anode electrode; and a cathode pad corresponding to each of the plurality of subpixels and disposed on the cathode electrode, wherein each of the plurality of light-emitting elements comprises a base substrate, an n-type semiconductor disposed on one side of the base substrate facing the substrate, an active layer disposed on a part of the n-type semiconductor, a p-type semiconductor disposed on the active layer, a first contact electrode disposed on the p-type semiconductor and facing the anode electrode, and a second contact electrode disposed on another part of the n-type semiconductor and facing the cathode electrode, wherein the first contact electrode is attached to the anode pad through an anode contact electrode, and the second contact electrode is attached to the cathode pad through a cathode contact electrode.

Images