Semiconductor package

Abstract

A semiconductor package is provided having a package substrate having a mounting area and a peripheral area surrounding the mounting area, a semiconductor device disposed on the mounting area of ​​the package substrate, a package cap disposed on the peripheral area of ​​the package substrate, wherein the package cap includes a partition portion surrounding the semiconductor device and an extension portion covering the semiconductor device, and an adhesive layer between the lower surface of the package cap and the package substrate, wherein the lower surface of the package cap has a trench, and the trench has a trapezoidal cross-section whose width decreases as it moves away from the lower surface of the package cap, and the adhesive layer is in contact with the upper surface of the package substrate and the lower surface of the package cap, and the adhesive layer can fill the interior of the trench.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0002] In line with the trend of electronic products becoming smaller, slimmer, and more dense, printed circuit boards (PCBs) are also undergoing simultaneous miniaturization and slimming. Furthermore, along with the increasing portability of electronic devices and the demand for multi-functional and high-capacity data transmission, the design of PCBs is becoming more complex, requiring advanced technology. Consequently, there is a growing demand for multilayer PCBs that house power circuits, grounding circuits, and signal circuits.

[0003] Various semiconductor chips, such as central processing units or power integrated circuits, are mounted on multilayer printed circuit boards. High temperatures can be generated in these semiconductor chips during operation. These high temperatures can cause an overload on the semiconductor chips, leading to malfunctions.

[0004] Meanwhile, as multiple semiconductor chips and semiconductor devices are embedded on a printed circuit board, electromagnetic interference (EMI) may occur between them. This electromagnetic interference may also cause malfunctions in adjacent semiconductor chips and semiconductor devices. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor package with improved structural stability.

[0006] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor package with a low occurrence of defects and a semiconductor package manufactured thereby.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems comprises a package substrate having a mounting region and a peripheral region surrounding the mounting region, a semiconductor device disposed on the mounting region of the package substrate, a package cap disposed on the peripheral region of the package substrate, wherein the package cap includes a partition portion surrounding the semiconductor device and an extension portion covering the semiconductor device, and may include an adhesive layer between the lower surface of the package cap and the package substrate. The lower surface of the package cap may have a trench. The trench may have a trapezoidal cross-section in which the width decreases as it moves away from the lower surface of the package cap. The adhesive layer may be in contact with the upper surface of the package substrate and the lower surface of the package cap, and the adhesive layer may fill the interior of the trench.

[0009] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems may include a package substrate, an interposer disposed on the package substrate, a chip stack comprising first semiconductor chips disposed on the interposer and vertically stacked, a second semiconductor chip disposed on the interposer and spaced horizontally apart from the chip stack, and a package cap disposed on the package substrate and surrounding the interposer. The package cap may be adhered to the package substrate using an adhesive layer provided on the lower surface of the package cap. The package cap may have a trench provided on the lower surface of the package cap. The width of the trench may decrease as it moves away from the lower surface of the package cap.

[0010] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems may include a package substrate, a semiconductor device on the package substrate, and a package cap surrounding the semiconductor device on the package substrate. The package cap may be adhered to the package substrate using an adhesive layer provided on the lower surface of the package cap. A trench having a trapezoidal cross-sectional shape, with a width that decreases as it moves away from the lower surface, may be provided on the lower surface of the package cap. Protrusions extending from the bottom surface of the trench of the package cap toward the package substrate may be provided on the bottom surface of the trench. The height of the protrusions may be smaller than the depth of the trench. Effects of the invention

[0011] In the semiconductor package according to the embodiments of the present invention, as a trench is formed on the lower surface of the package cap, the contact area between the adhesive layer and the package cap may be large, and the adhesion strength between the adhesive layer and the package cap may be high. Accordingly, the package cap can be more firmly adhered to the package substrate, and a semiconductor package with improved structural stability can be provided.

[0012] As the trench has a trapezoidal shape, in the process of attaching the adhesive layer to the bottom surface of the package cap, the adhesive layer can be easily inserted into the trench, and an air gap can be prevented from forming inside the trench. Therefore, it is possible to prevent the adhesive layer from peeling off from the package cap due to the air gap. In other words, a method for manufacturing a semiconductor package with fewer defects and a semiconductor package with improved structural stability can be provided.

[0013] Furthermore, during the manufacturing process of a semiconductor package, in the process of attaching an adhesive layer to the lower surface of a package cap, the adhesive layer flows into the trench, and it is possible to prevent residual portions of the adhesive layer from protruding excessively from the inner or outer surface of the package cap. Accordingly, it is possible to prevent the package substrate from being contaminated by residual portions of the adhesive layer or the semiconductor package from bending caused by said residual portions of the adhesive layer. Brief explanation of the drawing

[0014] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a plan view for illustrating a semiconductor package according to embodiments of the present invention. FIG. 3 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIGS. 4 to 13 are enlarged drawings illustrating area A of FIG. 1. FIGS. 14 and FIGS. 15 are cross-sectional views illustrating a semiconductor package according to embodiments of the present invention. Specific details for implementing the invention

[0015] A semiconductor package according to the concept of the present invention is described with reference to the drawings.

[0016] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a plan view illustrating a semiconductor package according to embodiments of the present invention, where FIG. 1 corresponds to a cross-section cut along line A-A' of FIG. 2. FIG. 3 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention, corresponding to a cross-section cut along line A-A' of FIG. 2. FIG. 4 to 6 are enlarged drawings illustrating region A of FIG. 1.

[0017] Referring to FIG. 1, a semiconductor package (100) according to the present embodiment may include at least one semiconductor device (300) mounted on a package substrate (200). The semiconductor device (300) on the package substrate (200) may be covered by a package cap (400).

[0018] The package substrate (200) may be a printed circuit board (PCB) having signal patterns on its upper surface. Alternatively, the package substrate (200) may have a structure in which an insulating film and a wiring layer are stacked alternately. The package substrate (200) may have first substrate pads (202) provided on the upper surface of the package substrate (200) and second substrate pads (204) disposed on the lower surface of the package substrate (200).

[0019] The package substrate (200) may have a chip mounting area (200a) and a peripheral area (200b). The peripheral area (200b) may surround the chip mounting area (200a) in a planar view. Alternatively, the chip mounting area (200a) may be located inside the peripheral area (200b). The chip mounting area (200a) may be an area where a semiconductor device (300) is mounted, and the peripheral area (200b) may be an area where a package cap (400) contacts the package substrate (200).

[0020] External terminals (210) may be disposed below the package substrate (200). In detail, the external terminals (210) may be disposed on the second substrate pads (204) on the lower surface of the package substrate (200). The external terminals (210) may include solder balls or solder bumps, and depending on the type of the external terminals (210), the semiconductor package (100) may include a ball grid array (BGA), a fine ball-grid array (FBGA), or a land grid array (LGA) form. The external terminals (210) may be electrically connected to the package substrate (200) through the second substrate pads (204). In the following, being electrically connected may include being connected directly or indirectly.

[0021] A semiconductor device (300) may be disposed on a package substrate (200). The semiconductor device (300) may be disposed on a chip mounting area (200a) of the package substrate (200). The semiconductor device (300) may be, for example, a type of package in which a semiconductor chip (320) is packaged so as to be mounted on the package substrate (200). For example, the semiconductor device (300) may include a semiconductor chip (320) mounted on an interposer substrate (310).

[0022] The interposer substrate (310) may have a structure in which an insulating pattern and a redistribution pattern are stacked alternately. The interposer substrate (310) may have third substrate pads provided on the upper surface of the interposer substrate (310) and fourth substrate pads (312) provided on the lower surface of the interposer substrate (310).

[0023] A semiconductor chip (320) is formed on an interposer substrate (310) and may have a width narrower than that of the interposer substrate (310). The semiconductor chip (320) may have internal solder balls (not shown) provided on the lower surface of the semiconductor chip (320), and may be electrically connected to the third substrate pads of the interposer substrate (310) on the upper surface of the interposer substrate (310) by the internal solder balls. At this time, the space between the internal solder balls between the interposer substrate (310) and the semiconductor chip (320) may be filled with an underfill resin film (corresponding to 322). That is, the semiconductor chip (320) may be mounted on the interposer substrate (310) by a flip chip bonding method. However, embodiments of the present invention are not limited thereto, and the semiconductor chip (320) may be electrically connected to the interposer substrate (310) by a bonding wire (not shown). At this time, the semiconductor chip (320) may be bonded to the interposer substrate (310) using an adhesive layer (corresponding to 322) provided on the lower surface of the semiconductor chip (320). The semiconductor chip (320) may be, for example, a logic chip or a memory chip. The logic chip may include a logic portion and a memory portion. For example, the memory chip may be a DRAM, NAND flash, NOR flash, PRAM, ReRAM, or MRAM.

[0024] According to other embodiments, a redistribution layer may be provided in place of the interposer substrate (310). The redistribution layer may correspond to a wiring layer for fan-out redistribution of the semiconductor chip (320) and may be in direct contact with the bottom surface of the semiconductor chip (320). Accordingly, the redistribution layer may be directly connected to the semiconductor chip (320) without the aforementioned internal solder balls.

[0025] A molding film (330) may be disposed on an interposer substrate (310). The molding film (330) may surround a semiconductor chip (320) on the interposer substrate (310). For example, the molding film (330) may expose the upper surface of the semiconductor chip (320), or, as not illustrated, the molding film (330) may be provided to cover the upper surface of the semiconductor chip (320). The molding film (330) may comprise an insulating polymer material such as an epoxy molding compound (EMC).

[0026] Although FIG. 1 illustrates the inclusion of a single semiconductor chip (320), the semiconductor chip (320) may be provided in multiple numbers. The semiconductor device (300) may be formed by stacking multiple semiconductor chips in sequence. For example, a base semiconductor chip may be provided instead of an interposer substrate (310). The semiconductor device (300) may include the base semiconductor chip and the semiconductor chip (320). The semiconductor chip (320) may be formed on the base semiconductor chip and may have a narrower width than the base semiconductor chip. The boundary region between the semiconductor chip (320) and the base semiconductor chip may be electrically connected by internal solder balls (not shown), and the space between the internal solder balls may be filled with an underfill resin film (322). The base semiconductor chip may be a logic chip, and the semiconductor chip (320) may be a memory chip.

[0027] A semiconductor device (300) can be mounted on a package substrate (200) by a flip-chip bonding method. Fourth substrate pads (312) of an interposer substrate (310) are formed on the lower surface of the interposer substrate (310) and can be electrically connected to the first substrate pads (202) of the package substrate (200). Solder balls (340) can be formed between the fourth substrate pads (312) and the first substrate pads (202). The semiconductor device (300) can be electrically connected to the package substrate (200) by the solder balls (340). The space between the solder balls (340) can be filled with an underfill resin film (342).

[0028] According to other embodiments, the semiconductor device (300) may be a single semiconductor chip. For example, the single semiconductor chip may be directly mounted on a package substrate (200) using solder balls (340) provided on its lower surface. However, the semiconductor device (300) is not limited to the examples described above, and the semiconductor device (300) may be provided in various forms of devices or packages as needed. The following description will continue based on the embodiment of FIG. 1.

[0029] Referring to FIGS. 1 and 2, a package cap (400) may be provided on a package substrate (200). The package cap (400) may cover a semiconductor device (300) on the package substrate (200). For example, the package cap (400) may have a partition portion (410) on one side of the semiconductor device (300) and an extension portion (420) on the semiconductor device (300).

[0030] The partition portion (410) of the package cap (400) may be disposed on the package substrate (200) on one side of the semiconductor device (300). The partition portion (410) may be disposed on the peripheral region (200b) of the package substrate (200). For example, the partition portion (410) may have a partition shape extending along the peripheral region (200b). In a planar view, the partition portion (410) may surround the semiconductor device (300). For example, the planar shape of the partition portion (410) may have a ring shape surrounding the semiconductor device (300). The partition portion (410) may have an inner surface (400a) facing the semiconductor device (300) and an outer surface (400b) facing the inner surface (400a).

[0031] The extension portion (420) of the package cap (400) may be positioned above the semiconductor device (300). For example, the extension portion (420) may be positioned on the partition portion (410). More specifically, the top of the partition portion (410) may be located at a level equal to or higher than the upper surface of the semiconductor device (300), and the extension portion (420) may be connected to the top of the partition portion (410) and spaced apart from the package substrate (200). The extension portion (420) may extend from the top of the partition portion (410) onto the semiconductor device (300). The extension portion (420) may cover the entire semiconductor device (300).

[0032] A package cap (400) having a partition portion (410) and an extension portion (420) may have a cap shape that covers a semiconductor device (300). The package cap (400) may include a metal material with high thermal conductivity. The package cap (400) may be configured to protect the semiconductor device (300) of the semiconductor package from external shocks, to release heat generated from the semiconductor device (300) to the outside, or to shield electromagnetic interference (EMI) generated between the outside of the semiconductor package and the semiconductor device (300).

[0033] A thermal interface material (TIM) film (350) may be interposed between the package cap (400) and the semiconductor device (300). More specifically, the thermal interface material film (350) may be provided between the package cap (400) and the semiconductor chip (320) and between the package cap (400) and the molding film (330). The thermal interface material film (350) may be a heat transfer member for transferring heat generated in the semiconductor device (300) to the package cap (400). The thermal interface material film (350) may include thermal grease, epoxy material, or metal solid particles such as indium (P). The thermal interface material film (350) may maintain a solid state at low temperatures and change into a liquid state at high temperatures. The thermal interface material film (350) may have adhesive and / or conductive properties.

[0034] According to other embodiments, the package cap (400) may not have an extension (420). As shown in FIG. 3, the package cap (400) may have only a partition (410) surrounding the semiconductor device (300). Accordingly, the upper surface of the semiconductor device (300) may be exposed, and the thermal boundary material film described above may not be provided on the upper surface of the semiconductor device (300). The following description will continue based on the embodiment of FIG. 1.

[0035] The package cap (400) can be attached to the package substrate (200) by an adhesive layer (500). For example, the adhesive layer (500) can be placed on a peripheral area (200b) of the package substrate (200). The adhesive layer (500) can be provided on the lower surface of the partition portion (410) of the package cap (400). The adhesive layer (500) can bond the lower surface of the partition portion (410) and the upper surface of the package substrate (200). The adhesive layer (500) may include a material with high thermal conductivity. As an example, the adhesive layer (500) may include a thermal interface material (TIM), such as thermal grease.

[0036] According to other embodiments, the package cap (400) may be attached to the package substrate (200) by including a conductive adhesive material or using a solder material instead of the adhesive layer (500). For example, the adhesive layer (500) may be replaced with a solder ball. In this case, the solder ball may be connected to substrate pads provided on the peripheral region (200b) of the package substrate (200), and the package cap (400) may be connected to the ground wiring pattern of the package substrate (200) through the substrate pads. By connecting the package cap (400) to the ground wiring pattern of the package substrate (200), the shielding effect against electromagnetic interference (EMI) may be further enhanced. The following description will continue based on the embodiment of FIG. 1.

[0037] A portion of the adhesive layer (500) may be inserted into the interior of the partition portion (410) of the package cap (400). For example, the partition portion (410) of the package cap (400) may have a trench (T) formed on the lower surface of the partition portion (410), and the adhesive layer (500) may fill the trench (T) on the lower surface of the partition portion (410). Hereinafter, the configuration of the partition portion (410) and the adhesive layer (500) will be described in more detail with reference to FIGS. 4 to 13.

[0038] Referring to FIGS. 1 to 4, a trench (T) may be provided on the lower surface (410c) of the bulkhead (410). The trench (T) may extend from the lower surface (410c) of the bulkhead (410) toward the interior of the bulkhead (410). That is, the trench (T) may extend upward from the lower surface (410c) of the bulkhead (410). The vertical cross-section of the trench (T) may have a trapezoidal shape. For example, the width of the trench (T) decreases as it moves away from the lower surface (410c) of the bulkhead (410), and the trench (T) may have a bottom surface (Ta) parallel to the lower surface (410c) of the bulkhead (410). In other words, the inner surface of the trench (T) may be inclined with respect to the bottom surface (Ta) of the trench (T) and the lower surface (410c) of the bulkhead (410). The vertical cross-section of the trench (T) is perpendicular to the package substrate (200) and refers to a cross-section in the direction from the inner surface (400a) of the bulkhead (410) toward the outer surface (400b). The bottom surface (Ta) of the trench (T) may be located at a higher level than the lower surface (410c) of the bulkhead (410). The bottom surface (Ta) of the trench (T) may be substantially flat. From a planar perspective, as illustrated in FIG. 2, the planar shape of the trench (T) may have a ring shape extending along the bulkhead (410). More specifically, the trench (T) may extend planarly along the inner surface (400a) and the outer surface (400b) of the bulkhead (410). The width (w) of the trench (T) may be greater than 200 µm. Here, the width (w) of the trench (T) refers to the maximum width of the trench (T) and corresponds to the width of the trench (T) measured on the lower surface (410c) of the bulkhead (410). The distance between the inner surface (400a) and the outer surface (400b) of the bulkhead (410) and the trench (T) may be 200 µm to 500 µm. The depth (d) of the trench (T) may be 200 µm to 500 µm.

[0039] The extension (510) of the adhesive layer (500) can fill the interior of the trench (T) on the lower surface (410c) of the partition (410). That is, the adhesive layer (500) can be interposed between the lower surface (410c) of the partition (410) and the upper surface of the package substrate (200), and at the same time, can extend into the trench (T) of the partition (410). The extension (510) of the adhesive layer (500) can come into contact with the bottom surface (Ta) and the inner surface of the trench (T). Depending on the vertical cross-sectional shape of the trench (T), the vertical cross-section of the extension (510) of the adhesive layer (500) filling the interior of the trench (T) may have a trapezoidal shape.

[0040] According to embodiments of the present invention, as a trench (T) is formed on the lower surface (410c) of the partition (410), the contact area between the adhesive layer (500) and the partition (410) may be wide, and the adhesive strength between the adhesive layer (500) and the partition (410) may be high. Accordingly, the package cap (400) can be more firmly attached to the package substrate (200), and a semiconductor package (100) with improved structural stability can be provided.

[0041] Additionally, as the trench (T) has a trapezoidal shape, during the manufacturing process of the semiconductor package (100), the adhesive layer (500) can be easily inserted into the trench (T) during the process of attaching the adhesive layer (500) to the lower surface (410c) of the partition (410), and an air gap, such as a bubble, can not occur inside the trench (T) between the adhesive layer (500) and the partition (410). Therefore, during a heat treatment process such as a process of curing the adhesive layer (500), the adhesive layer (500) can be prevented from peeling off from the package cap (400) due to the air gap. That is, a method for manufacturing a semiconductor package with fewer defects and a semiconductor package (100) with improved structural stability can be provided.

[0042] A portion of the adhesive layer (500) located between the lower surface (410c) of the partition (410) and the upper surface of the package substrate (200) may protrude from the inner surface (410a) and the outer surface (410b) of the partition (410). For example, the distance at which the portion of the adhesive layer (500) protrudes may be 0 µm to 100 µm from the inner surface (410a) or the outer surface (410b) of the partition (410). During the manufacturing process of the semiconductor package (100), in the process of attaching the adhesive layer (500) to the lower surface (410c) of the partition (410), the adhesive layer (500) is introduced into the trench (T), and the remaining portions of the adhesive layer (500) may be prevented from protruding excessively from the inner surface (410a) or the outer surface (410b) of the partition (410). Accordingly, it is possible to prevent the package substrate (200) from being contaminated by the remaining portions of the adhesive layer (500) or warpage from occurring in the semiconductor package (100) by the remaining portions of the adhesive layer (500).

[0043] Figure 4 illustrates that a trench (T) having a vertical cross-section in the shape of a trapezoid is provided on the lower surface (410c) of the bulkhead (410), but the present invention is not limited thereto.

[0044] According to other embodiments, as illustrated in FIG. 5, the trench (T) may extend from the lower surface (410c) of the bulkhead (410) toward the interior of the bulkhead (410). That is, the trench (T) may extend upward from the lower surface (410c) of the bulkhead (410). The vertical cross-section of the trench (T) may have a semicircular shape. For example, the width of the trench (T) may decrease as it moves away from the lower surface (410c) of the bulkhead (410). The bottom surface (Ta) of the trench (T) may be curved from the inner surface (400a) toward the outer surface (400b), and both ends of the bottom surface (Ta) may be connected to the lower surface (410c) of the bulkhead (410). The bottom surface (Ta) of the trench (T) may be located at a higher level than the lower surface (410c) of the bulkhead (410). From a planar perspective, the planar shape of the trench (T) may have a ring shape extending along the bulkhead (410). The width of the trench (T) may be greater than 200 µm. The gap between the inner surface (400a) and the outer surface (400b) of the bulkhead (410) and the trench (T) may be 200 µm to 500 µm. The depth of the trench (T) may be 200 µm to 500 µm.

[0045] According to other embodiments, as illustrated in FIG. 6, the trench (T) may extend from the lower surface (410c) of the bulkhead (410) toward the interior of the bulkhead (410). That is, the trench (T) may extend upward from the lower surface (410c) of the bulkhead (410). The vertical cross-section of the trench (T) may have a triangular shape. For example, the width of the trench (T) may decrease as it moves away from the lower surface (410c) of the bulkhead (410). The trench (T) may have side walls (Tb) that are inclined with respect to the lower surface (410c) of the bulkhead (410) and adjacent to the inner surface (400a) and outer surface (400b) of the bulkhead (410), respectively. The side walls (Tb) of the trench (T) may be connected to each other on the center of the trench (T). The top of the trench (T) where the side walls (Tb) meet may be located at a higher level than the lower surface (410c) of the bulkhead (410). From a planar perspective, the planar shape of the trench (T) may have a ring shape extending along the bulkhead (410). The width of the trench (T) may be greater than 200 µm. The gap between the inner surface (400a) and the outer surface (400b) of the bulkhead (410) and the trench (T) may be 200 µm to 500 µm. The depth of the trench (T) may be 200 µm to 500 µm.

[0047] FIGS. 1 to 4 illustrate that a trench (T) is provided between the inner surface (400a) and the outer surface (400b) of the bulkhead (410), but the present invention is not limited thereto. FIGS. 7 and 8 are enlarged drawings corresponding to area A of FIG. 1.

[0048] Referring to FIG. 7, a plurality of trenches (T) may be provided on the lower surface (410c) of the bulkhead (410). The trenches (T) may extend from the lower surface (410c) of the bulkhead (410) toward the interior of the bulkhead (410). That is, the trenches (T) may extend upward from the lower surface (410c) of the bulkhead (410). The vertical cross-section of each trench (T) may have a trapezoidal shape. For example, the width of the trenches (T) decreases as it moves away from the lower surface (410c) of the bulkhead (410), and each trench (T) may have a bottom surface (Ta) parallel to the lower surface (410c) of the bulkhead (410). The bottom surface (Ta) of the trenches (T) may be located at a higher level than the lower surface (410c) of the bulkhead (410). The bottom surface (Ta) of the trenches (T) may be substantially flat. In terms of planar view, the planar shape of the trenches (T) may have a ring shape extending along the bulkhead (410). More specifically, the trenches (T) may extend planarly along the inner surface (400a) and the outer surface (400b) of the bulkhead (410). The trenches (T) may be arranged from the inner surface (400a) toward the outer surface (400b) of the bulkhead (410). For example, in terms of planar view, the trenches (T) may have the form of rings that surround each other. The width of the trenches (T) may be 200 µm to 500 µm. The spacing between the trenches (T) may be 200 µm to 500 µm. The spacing between the trenches (T) refers to the spacing between the trenches (T) on the lower surface (410c) of the bulkhead (410). The spacing between the inner surface (400a) of the bulkhead (410) and the trench (T) adjacent to the inner surface (400a), and the spacing between the outer surface (400b) and the trench (T) adjacent to the outer surface (400b) may be 200 µm to 500 µm. The depth of the trenches (T) may be 200 µm to 500 µm.

[0049] According to other embodiments, as illustrated in FIG. 8, the depth of the trenches (T) may increase as they approach the inner surface (410a) and outer surface (410b) of the bulkhead (410). More specifically, the lower surface (410c) of the bulkhead (410) may include outer regions adjacent to the inner surface (410a) and outer surface (410b) of the bulkhead (410) and an inner region between the outer regions. The trenches (T) may have first trenches (T1) provided in the inner region and second trenches (T2) provided in the outer regions. That is, the second trenches (T2) may be positioned to be closer to the inner surface (410a) and outer surface (410b) of the bulkhead (410) than the first trenches (T1). The first depth of the first trenches (T1) may be shallower than the second depth of the second trenches (T2). In other words, the first bottom surface (T1a) of the first trenches (T1) may be located at a lower level than the second bottom surface (T2a) of the second trenches (T2). Alternatively, depending on the number of trenches (T), the depth of the trenches (T) may gradually decrease according to the distance between the inner surface (410a) and the outer surface (410b) of the bulkhead (410).

[0051] In FIGS. 1 to 4, the bottom surface (Ta) of the trench (T) is shown as flat, but the present invention is not limited thereto. FIGS. 9 to 13 are enlarged drawings corresponding to area A of FIG. 1.

[0052] Referring to FIG. 9, at least one protrusion (TP) may be provided within the trench (T). The protrusions (TP) may protrude from the bottom surface (Ta) of the trench (T). In this case, the height at which the protrusions (TP) protrude from the bottom surface (Ta) of the trench (T) may be less than the depth of the trench (T). In a planar view, the planar shape of the protrusions (TP) may have a ring shape extending along the bulkhead (410). More specifically, the protrusions (TP) may extend planarly along the inner surface (400a) and the outer surface (400b) of the bulkhead (410). Alternatively, the protrusions (TP) may have an island shape spaced apart from each other on the bottom surface (Ta) of the trench (T).

[0053] The width of the protrusions (TP) may decrease as they move away from the bottom surface (Ta) of the trench (T). For example, the vertical cross-section of the protrusions (TP) may have a trapezoidal shape. For example, the width of the protrusions (TP) decreases as they move away from the bottom surface (Ta) of the trench (T), but the protrusions (TP) may have a flat surface (TPa) parallel to the bottom surface (Ta) of the trench (T). Alternatively, the outer surface of the protrusions (TP) may be inclined with respect to the bottom surface (Ta) of the trench (T) and the flat surface (TPa) of the protrusions (TP). The vertical cross-section of the protrusions (TP) is perpendicular to the package substrate (200) and refers to a cross-section in the direction from the inner surface (400a) of the bulkhead (410) toward the outer surface (400b). The flat surface (TPa) of the protrusions (TP) may be located at a lower level than the bottom surface (Ta) of the trench (T) and at a higher level than the bottom surface (410c) of the bulkhead (410). The flat surface (TPa) of the protrusions (TP) may be substantially flat.

[0054] The width of the protrusions (TP) may be 200 µm to 500 µm. Here, the width of the protrusions (TP) refers to the maximum width of the protrusions (TP) and corresponds to the width of the protrusions (TP) measured on the bottom surface (Ta) of the trench (T). The protrusion height of the protrusions (TP) may be 200 µm to 500 µm. The spacing between the protrusions (TP) may be 0 µm to 500 µm.

[0055] According to embodiments of the present invention, as protrusions (TP) are provided within the trench (T), the contact area between the adhesive layer (500) and the partition (410) may be wider, and the adhesive strength between the adhesive layer (500) and the partition (410) may be higher. Accordingly, the package cap (400) may be more firmly attached to the package substrate (200), and a semiconductor package (100) with improved structural stability may be provided.

[0056] Additionally, as the protrusions (TP) have a trapezoidal shape, during the manufacturing process of the semiconductor package (100), the adhesive layer (500) can be easily introduced between the protrusions (TP) in the process of attaching the adhesive layer (500) to the lower surface (410c) of the partition (410), and an air gap, such as a bubble, can not occur inside the trench (T) between the adhesive layer (500) and the partition (410). Therefore, in a heat treatment process such as a process of curing the adhesive layer (500), the adhesive layer (500) can be prevented from peeling off from the package cap (400) due to the air gap. That is, a method for manufacturing a semiconductor package with fewer defects and a semiconductor package (100) with improved structural stability can be provided.

[0057] Figure 9 illustrates that protrusions (TP) having a vertical cross-section in the shape of a trapezoid are provided on the bottom surface (Ta) of the trench (T), but the present invention is not limited thereto.

[0058] According to other embodiments, as illustrated in FIG. 10, the protrusions (TP) may be directed downward from the bottom surface (Ta) of the trench (T). The vertical cross-section of the protrusions (TP) may have a semicircular shape. For example, the width of the protrusions (TP) may decrease as it moves away from the bottom surface (Ta) of the trench (T). The lower surface of the protrusions (TP) may have a rounded shape protruding from the bottom surface (Ta) of the trench (T). The lowest end of the protrusions (TP) may be located at a level lower than the bottom surface (Ta) of the trench (T) and higher than the lower surface (410c) of the bulkhead (410). Alternatively, as illustrated in FIG. 11, the lower surface of the protrusions (TP) may have a rounded shape, but the lower surface of the protrusions (TP) may be connected to the bottom surface (Ta) of the trench (T). At this time, the lower surface of the protrusions (TP) and the bottom surface (Ta) of the trench (T) can form a wave-shaped cross-section.

[0059] According to other embodiments, as illustrated in FIG. 12, the protrusions (TP) may be directed downward from the bottom surface (Ta) of the trench (T). The vertical cross-section of the protrusions (TP) may have a triangular shape. For example, the width of the protrusions (TP) may decrease as it moves away from the bottom surface (Ta) of the trench (T). The protrusions (TP) may have sides inclined with respect to the bottom surface (Ta) of the trench (T). The lowest point of the protrusions (TP) where the sides meet may be lower than the bottom surface (Ta) of the trench (T) and higher than the lower surface (410c) of the bulkhead (410).

[0060] According to other embodiments, as illustrated in FIG. 13, the protrusion height of the protrusions (TP) may decrease as they approach the inner surface (410a) and outer surface (410b) of the partition (410). More specifically, the lower surface (410c) of the partition (410) may include outer regions adjacent to the inner surface (410a) and outer surface (410b) of the partition (410) and an inner region between said outer regions. The protrusions (TP) may have first protrusions (TP1) provided in said inner region and second protrusions (TP2) provided in said outer regions. That is, the second protrusions (TP2) may be positioned to be closer to the inner surface (410a) and outer surface (410b) of the partition (410) than the first protrusions (TP1). The first protrusion height of the first protrusions (TP1) may be greater than the second protrusion height of the second protrusions (TP2). In other words, the first flat surface (TP1a) of the first protrusions (TP1) may be located at a lower level than the second flat surface (TP2a) of the second protrusions (TP2). Alternatively, depending on the number of protrusions (TP), the protrusion height of the protrusions (TP) may gradually increase according to the distance between the inner surface (410a) and the outer surface (410b) of the bulkhead (410).

[0062] FIG. 14 is a cross-sectional view illustrating an application example of a semiconductor package according to embodiments of the present invention.

[0063] Referring to FIG. 14, the semiconductor package (1000) may be an image sensor. The semiconductor package (1000) described with reference to FIG. 14 is merely one example of semiconductor packages according to embodiments of the present invention, and semiconductor packages according to the concept of the present invention are not limited thereto.

[0064] A substrate (1200) may be provided. The substrate (1200) may correspond to the package substrate (200) described with reference to FIGS. 1 to 13. For example, the substrate (1200) may include a printed circuit board (PCB). The substrate (1200) may include substrate pads (1202, 1204) and an external terminal (1210). The first substrate pads (1202) may be provided on the upper surface of the substrate (1200). The second substrate pads (1204) may be provided on the lower surface of the substrate (1200). The external terminal (1210) may be provided on the second substrate pads (1204) on the lower surface of the substrate (1200). The external terminal (1210) may have the shape of a solder ball or a solder bump. The external terminal (1210) can be electrically connected to the first substrate pads (1202) through the substrate (1200) as shown by the dotted line.

[0065] An image sensor element (1300) may be disposed on a substrate (1200). The image sensor element (1300) may be an example of a semiconductor element (300) described with reference to FIGS. 1 to 13. Hereinafter, the configuration of the image sensor element (1300) will be described in detail.

[0066] A first semiconductor chip (1320) may be provided on a substrate (1200). The first semiconductor chip (1320) may include a memory chip such as DRAM, SRAM, MRAM, or flash memory. The first semiconductor chip (1320) may include a silicon material. The upper surface of the first semiconductor chip (1320) may be an active surface. For example, the first semiconductor chip (1320) may include a first circuit layer (1321) and a first chip pad (1322) on its upper surface. The first chip pad (1322) may be electrically connected to an integrated element or integrated circuit within the first circuit layer (1321).

[0067] A second semiconductor chip (1330) may be provided on a substrate (1200). The second semiconductor chip (1330) may be spaced apart from the first semiconductor chip (1320). The second semiconductor chip (1330) may include the same chip as the first semiconductor chip (1320). Alternatively, the second semiconductor chip (1330) may include a chip different from the first semiconductor chip (1320) or may be a dummy chip. The second semiconductor chip (1330) may include a memory chip such as DRAM, SRAM, MRAM, or flash memory. The second semiconductor chip (1330) may include a silicon material. The upper surface of the second semiconductor chip (1330) may be an active surface. For example, the second semiconductor chip (1330) may include a second circuit layer (1331) and a second chip pad (1332) on its upper surface. The second chip pad (1332) may be electrically connected to an integrated element or integrated circuit within the second circuit layer (1331). Alternatively, if the second semiconductor chip (1330) is a dummy chip, the second circuit layer (1331) and the second chip pad (1332) may be omitted.

[0068] The first and second semiconductor chips (1320, 1330) can be bonded to a substrate (1200). For example, a substrate adhesive layer (1310) may be further interposed between the first and second semiconductor chips (1320, 1330) and the substrate (2100).

[0069] A molding film (1340) may be provided on a substrate (1200). The molding film (1340) may cover the first and second semiconductor chips (1320, 1330). At this time, the sides of the first and second semiconductor chips (200, 300) may not be exposed by the molding film (1340). The molding film (1340) may fill the space between the first semiconductor chip (1320) and the second semiconductor chip (1330). The molding film (1340) may not cover the lower surfaces of the first and second semiconductor chips (1320, 1330). The molding film (1340) can expose the first chip pad (1322) of the first semiconductor chip (1320) and the second chip pad (1332) of the second semiconductor chip (1330). The molding film (1340) can prevent the first and second semiconductor chips (1320, 1330) from being damaged by external shocks and moisture, etc. The molding film (1340) may include an insulating polymer such as an epoxy molding compound (EMC).

[0070] An image sensor unit (1360) may be disposed on a molding film (1340). In a planar view, the image sensor unit (1360) may overlap with the first semiconductor chip (1320) and the second semiconductor chip (1330). The upper surface of the image sensor unit (1360) may be the front surface where light is incident. The lower surface of the image sensor unit (1360) may face the first and second semiconductor chips (1320, 1330). The side surface of the image sensor unit (1360) may be coplanar with the side surface of the molding film (1340). The image sensor unit (1360) may be supported by the molding film (1340). Accordingly, the image sensor unit (1360) can be stably placed on the first and second semiconductor chips (1320, 1330) and the molding film (1340). The image sensor unit (1360) can sense light incident on the upper surface and output it as an electrical signal.

[0071] The image sensor unit (1360) may include a third semiconductor chip (1361) and a sensing chip (1365). The sensing chip (1365) may include a photodiode that detects light. The third semiconductor chip (1361) may include a logic chip that converts light detected from the sensing chip (1365) into an electrical signal.

[0072] A third semiconductor chip (1361) may be disposed on a molding film (1340). The third semiconductor chip (1361) may include a first base layer (1362), a third circuit layer (1363), and a first via (1364). The first base layer (1362) may include a silicon substrate. The third circuit layer (1363) may be provided on the first base layer (1362). The third circuit layer (1363) may include direct circuits (e.g., transistors) and wiring patterns. Some of the wiring patterns of the third circuit layer (1363) may be first bonding pads exposed on the upper surface of the third semiconductor chip (1361). Thus, the upper surface of the third semiconductor chip (1361) may function as an active surface. The first via (1364) penetrates the first base layer (1362) to electrically connect the third circuit layer (1363) and the first or second semiconductor chips (1320, 1330). Accordingly, the electrical connection path between the first and second semiconductor chips (1320, 1330) and the third semiconductor chip (1361) may be short.

[0073] A sensing chip (1365) may be disposed on a third semiconductor chip (1361). The sensing chip (1365) may include a second base layer (1367), a fourth circuit layer (1366), and a second via (1368). The second base layer (1367) may include a silicon substrate. The fourth circuit layer (1366) may be disposed on the underside of the sensing chip (1365) so as to be adjacent to the third semiconductor chip (1361). The fourth circuit layer (1366) may include a photodiode, an integrated circuit (e.g., a sensing transistor), and a wiring pattern. Some of the wiring patterns of the fourth circuit layer (1366) may be second bonding pads exposed on the underside of the sensing chip (1365). Thus, the underside of the sensing chip (1365) may function as an active surface. The second bonding pad may come into contact with the first bonding pad. Accordingly, the sensing chip (1365) may be electrically connected to the third semiconductor chip (1361) by the first and second bonding pads. The second via (1368) may penetrate at least a portion of the sensing chip (1365). The second via (1368) may penetrate the sensing chip (1365) and be electrically connected to the third semiconductor chip (1361). Alternatively, the second via (1368) may penetrate a portion of the sensing chip (1365) and be electrically connected to the sensing chip (1365).

[0074] A pixel array may be provided on the upper part of the image sensor unit. The pixel array may include pixels (P) provided on the sensing chip (1365). In a planar view, the pixels (P) may be provided in the central region of the image sensor unit (1360). Color filters (1381) and micro-lenses (1382) may each be provided on the pixels (P) on the upper surface of the image sensor unit (1360).

[0075] Connection pads (1371) may be disposed on the upper surface of the image sensor unit (1360). At this time, the connection pads (1371) may be disposed on the outer edge of the upper surface of the image sensor unit (1360). The connection pads (1371) may be spaced apart from the pixel array. The connection pads (1371) may be electrically connected to the second via (1368) of the sensing chip (1365). The connection pads (1371) may be connected to the first substrate pads (1202) through bonding wires (1372). The image sensor unit (1360) may be electrically connected to the substrate (1200) through bonding wires (1372).

[0076] A redistribution layer (1350) may be provided between the first and second semiconductor chips (1320, 1330) and the image sensor unit (1360). The redistribution layer (1350) may extend between the molding film (1340) and the image sensor unit (1360). The redistribution layer (1350) may include insulating films (1351) and a redistribution pattern (1352). The redistribution pattern (1352) may include a conductive layer and conductive vias. The redistribution layer (1350) may be electrically connected to the third semiconductor chip (1361). The first semiconductor chip (1320) may be electrically connected to the redistribution layer (1350) by a first connection terminal (1323). For example, a first connection terminal (1323) may be provided between the redistribution layer (1350) and the first semiconductor chip (1320). The second semiconductor chip (1330) may be electrically connected to the redistribution layer (1350) by a second connection terminal (1333). For example, a second connection terminal (1333) may be provided between the redistribution layer (1350) and the second semiconductor chip (1330). The degree of freedom for the placement of the first and second semiconductor chips (1320, 1330) may be increased by the redistribution layer (1350).

[0077] A holder (1400) is provided on a substrate (1200) to support a lens (1390). The lens (1390) may be placed on the holder (1400). The lens (1390) may be spaced apart from and face the image sensor portion (1360). The lens (1390) may transmit light. The holder (1400) may correspond to the package cap (400) described with reference to FIGS. 1 to 13. For example, the holder (1400) may cover an image sensor element (1300) on the substrate (1200). For example, the holder (1400) may have a partition portion (1410) on one side of the image sensor element (1300) and an extension portion (1420) on the image sensor element (1300).

[0078] The partition portion (1410) of the holder (1400) may be disposed on the substrate (1200) on one side of the image sensor element (1300). The partition portion (1410) may have a partition shape that surrounds the image sensor element (1300).

[0079] The extension portion (1420) of the holder (1400) may be positioned above the image sensor element (1300). For example, the extension portion (1420) may be positioned on the partition portion (1410). The extension portion (1420) may be connected to the top of the partition portion (1410) and spaced apart from the substrate (1200). The extension portion (1420) may extend from the top of the partition portion (1410) onto the image sensor element (1300). The extension portion (1420) may cover the entire image sensor element (1300). A lens (1390) may be fixed to the extension portion (1420).

[0080] The holder (1400) can be attached to the substrate (1200) by an adhesive layer (1500). For example, the adhesive layer (1500) can be provided on the lower surface of the partition portion (1410) of the holder (1400). The adhesive layer (1500) can bond the lower surface of the partition portion (1410) and the upper surface of the substrate (1200).

[0081] A portion of the adhesive layer (1500) may be inserted into the interior of the partition (1410) of the holder (1400). For example, the partition (1410) of the holder (1400) may have a trench (T) formed on the lower surface of the partition (1410), and the adhesive layer (1500) may fill the trench (T) on the lower surface of the partition (1410). The shape and arrangement of the trench (T), and the configuration of the protrusion provided within the trench (T) may be the same or similar as described with reference to FIGS. 4 to 13.

[0083] FIG. 15 is a cross-sectional view illustrating an application example of a semiconductor package according to embodiments of the present invention.

[0084] Referring to FIG. 15, the semiconductor package (2000) may be a stacked package. The semiconductor package (2000) described with reference to FIG. 15 is merely one example among semiconductor packages according to embodiments of the present invention, and semiconductor packages according to the concept of the present invention are not limited thereto.

[0085] A package substrate (2200) may be provided. The package substrate (2200) may include a printed circuit board (PCB) having a signal pattern on its upper surface. Alternatively, the package substrate (2200) may have a structure in which an insulating film and a wiring layer are stacked alternately. The package substrate (2200) may have pads disposed on its upper surface.

[0086] External terminals (2210) may be disposed below the package substrate (2200). In detail, the external terminals (2210) may be disposed on terminal pads disposed on the lower surface of the package substrate (2200). The external terminals (2210) may include solder balls or solder bumps, and depending on the type and placement of the external terminals (2210), the semiconductor package (2000) may be provided in the form of a ball grid array (BGA), a fine ball grid array (FBGA), or a land grid array (LGA).

[0087] A stacked semiconductor device (2300) may be disposed on a package substrate (2200). The stacked semiconductor device (2300) may be an example of a semiconductor device (300) described with reference to FIGS. 1 to 13. Hereinafter, the configuration of the stacked semiconductor device (2300) will be described in detail.

[0088] An interposer substrate (2310) may be provided on a package substrate (2200). The interposer substrate (2310) may include at least two wiring layers. More specifically, wiring layers that are stacked on top of each other may be provided. Each of the wiring layers may include an insulating pattern and a wiring pattern embedded within the insulating pattern. The bottom wiring layer among the wiring layers may have first substrate pads (2312) electrically connected to the wiring layers. The first substrate pads (2312) may be exposed on the bottom surface of the interposer substrate (2310). The top wiring layer among the wiring layers may have second substrate pads (2314) and third substrate pads (2316) electrically connected to the wiring layers. The second substrate pads (2314) and third substrate pads (2316) may be exposed on the top surface of the interposer substrate (2310). The second substrate pads (2314) may be pads for mounting the chip stack (CS) described later, and the third substrate pads (2316) may be pads for mounting the second semiconductor chip (2330).

[0089] An interposer substrate (2310) may be mounted on the upper surface of a package substrate (2200). Substrate terminals (2340) may be disposed on the lower surface of the interposer substrate (2310). Substrate terminals (2340) may be provided between the pads of the package substrate (2200) and the first substrate pads (2312) of the interposer substrate (2310). Substrate terminals (2340) may electrically connect the interposer substrate (2310) to the package substrate (2200). For example, the interposer substrate (2310) may be mounted on the package substrate (2200) in a flip-chip manner. Substrate terminals (2340) may include solder balls or solder bumps, etc.

[0090] A first underfill film (2342) may be provided between the package substrate (2200) and the interposer substrate (2310). The first underfill film (2342) may fill the space between the package substrate (2200) and the interposer substrate (2310) and surround the substrate terminals (2340).

[0091] A chip stack (CS) may be disposed on an interposer substrate (2310). The chip stack (CS) may include a base substrate, first semiconductor chips (2324) stacked on the base substrate, and a first molding film (2326) surrounding the first semiconductor chips (2324). The configuration of the chip stack (CS) will be described in detail below.

[0092] The base substrate may be a base semiconductor chip (2322). For example, the base substrate may be a wafer-level semiconductor substrate made of a semiconductor such as silicon (Si). Hereinafter, the base semiconductor chip (2322) refers to a component identical to the base substrate, and the same reference number may be used for the base semiconductor chip and the base substrate.

[0093] The base semiconductor chip (2322) may include a base circuit layer (2322c) and base through-electrodes (2322t). The base circuit layer (2322c) may be provided on the lower surface of the base semiconductor chip (2322). The base circuit layer (2322c) may include an integrated circuit. For example, the base circuit layer (2322c) may be a memory circuit. That is, the base semiconductor chip (2322) may be a memory chip such as DRAM, SRAM, MRAM, or flash memory. The base through-electrodes (2322t) may penetrate the base semiconductor chip (2322) in a direction perpendicular to the upper surface of the interposer substrate (2310). The base through-electrodes (2322t) and the base circuit layer (2322c) may be electrically connected. The lower surface of the base semiconductor chip (2322) may be an active surface. Although FIG. 15 illustrates that the base substrate includes a base semiconductor chip (2322), the present invention is not limited thereto. According to embodiments of the present invention, the base substrate may not include a base semiconductor chip (2322).

[0094] The base semiconductor chip (2322) may further include a protective film and first connection terminals (2322s). The protective film may be disposed on the lower surface of the base semiconductor chip (2322) to cover the base circuit layer (2322c). The protective film may include silicon nitride (SiN). The first connection terminals (2322s) may be provided on the lower surface of the base semiconductor chip (2322). The first connection terminals (2322s) may be electrically connected to the integrated circuit of the base circuit layer (2322c). The first connection terminals (2323s) may be exposed from the protective film.

[0095] The first semiconductor chip (2324) can be mounted on the base semiconductor chip (2322). That is, the first semiconductor chip (2324) can form a chip-on-wafer (COW) structure with the base semiconductor chip (2322). The width of the first semiconductor chip (2324) may be smaller than the width of the base semiconductor chip (2322).

[0096] The first semiconductor chip (2324) may include a first circuit layer (2324c) and first through electrodes (2324t). The first circuit layer (2324c) may include a memory circuit. That is, the first semiconductor chip (2324) may be a memory chip such as DRAM, SRAM, MRAM, or flash memory. The first circuit layer (2324c) may include the same circuit as the base circuit layer (2322c), but the present invention is not limited thereto. The first through electrodes (2324t) may penetrate the first semiconductor chip (2324) in a direction perpendicular to the upper surface of the interposer substrate (2310). The first through electrodes (2324t) and the first circuit layer (2324c) may be electrically connected. The bottom surface of the first semiconductor chip (2324) may be an active surface. First chip bumps (2324s) may be provided on the bottom surface of the first semiconductor chip (2324). The first chip bumps (2324s) may electrically connect the base semiconductor chip (2322) and the first semiconductor chip (2324) between the base semiconductor chip (2322) and the first semiconductor chip (2324).

[0097] The first semiconductor chip (2324) may be provided in multiple numbers. For example, multiple first semiconductor chips (2324) may be stacked on a base semiconductor chip (2322). From 8 to 32 first semiconductor chips (2324) may be stacked. First chip bumps (2324s) may be provided between each of the first semiconductor chips (2324). In this case, the first semiconductor chip (2324) placed at the top may not include a first through electrode (2324t). Additionally, the thickness of the first semiconductor chip (2324) placed at the top may be thicker than the thickness of the first semiconductor chips (2324) placed below it.

[0098] Although not illustrated, an adhesive layer may be provided between the first semiconductor chips (2324). The adhesive layer may include a non-conductive film (NCF). The adhesive layer may be interposed between the first chip bumps (2324s) between the first semiconductor chips (2324) to prevent the occurrence of an electrical short circuit between the first chip bumps (2324s).

[0099] A first molding film (2326) may be disposed on the upper surface of a base semiconductor chip (2322). The first molding film (2326) may cover the base semiconductor chip (2322) and may surround the first semiconductor chips (2324). The upper surface of the first molding film (2326) may co-plane with the upper surface of the uppermost first semiconductor chip (2324), and the uppermost first semiconductor chip (2324) may be exposed from the first molding film (2326). The first molding film (2326) may comprise an insulating polymer material. For example, the first molding film (2326) may comprise an epoxy molding compound (EMC).

[0100] A chip stack (CS) may be provided as described above. The chip stack (CS) may be mounted on an interposer substrate (2310). For example, the chip stack (CS) may be connected to the second substrate pads (2314) of the interposer substrate (2310) through the first connection terminals (2322s) of the base semiconductor chip (2322). The first connection terminals (2322s) may be provided between the second substrate pads (2314) of the interposer substrate (2310) and the base circuit layer (2322c).

[0101] A second underfill film (2328) may be provided between the interposer substrate (2310) and the chip stack (CS). The second underfill film (2328) may fill the space between the interposer substrate (2310) and the base semiconductor chip (2322) and surround the first connection terminals (2322s).

[0102] A second semiconductor chip (2330) may be disposed on an interposer substrate (2310). The second semiconductor chip (2330) may be disposed spaced apart from the chip stack (CS). The thickness of the second semiconductor chip (2330) may be thicker than the thickness of the first semiconductor chips (2324). The second semiconductor chip (2330) may include a semiconductor material such as silicon (Si). The second semiconductor chip (2330) may include a second circuit layer (2330c). The second circuit layer (2330c) may include a logic circuit. That is, the second semiconductor chip (2330) may be a logic chip. The lower surface of the second semiconductor chip (2330) may be an active surface, and the upper surface of the second semiconductor chip (2330) may be an inactive surface. Second connection terminals (2330s) may be provided on the lower surface of the second semiconductor chip (2330). The second connection terminals (2330s) may be electrically connected to the integrated circuit of the second circuit layer (2330c).

[0103] The second semiconductor chip (2330) may be mounted on the interposer substrate (2310). For example, the second semiconductor chip (2330) may be connected to the third substrate pads (2316) of the interposer substrate (2310) through the second connection terminals (2330s). The second connection terminals (2330s) may be provided between the third substrate pads (2316) of the interposer substrate (2310) and the second circuit layer (2330c).

[0104] A third underfill film (2332) may be provided between the interposer substrate (2310) and the second semiconductor chip (2330). The third underfill film (2332) may fill the space between the interposer substrate (2310) and the second semiconductor chip (2330) and surround the second connection terminals (2330s).

[0105] A second molding film (2350) may be provided on an interposer substrate (2310). The second molding film (2350) may cover the upper surface of the interposer substrate (2310). The second molding film (2350) may surround the chip stack (CS) and the second semiconductor chip (2330). The second molding film (2350) may include an insulating material. For example, the second molding film (2350) may include an epoxy molding compound (EMC).

[0106] A package cap (2400) may be provided on a package substrate (2200). The package cap (2400) may correspond to the package cap (400) described with reference to FIGS. 1 to 13. For example, the package cap (2400) may cover a chip stack (CS) and a second semiconductor chip (2330) on the package substrate (2200). For example, the package cap (2400) may have a partition portion (2410) on one side of the interposer substrate (2310), and an extension portion (2420) on the chip stack (CS) and the second semiconductor chip (2330).

[0107] The partition portion (2410) of the package cap (2400) may be disposed on the package substrate (2200) on one side of the interposer substrate (2310). The partition portion (2410) may have a partition shape that surrounds the interposer substrate (2310).

[0108] The extension portion (2420) of the package cap (2400) may be positioned above the chip stack (CS) and the second semiconductor chip (2330). For example, the extension portion (2420) may be positioned on the partition portion (2410). The extension portion (2420) may be connected to the top of the partition portion (2410) and spaced apart from the package substrate (2200). The extension portion (2420) may extend from the top of the partition portion (2410) onto the chip stack (CS) and the second semiconductor chip (2330). The extension portion (2420) may cover the entire chip stack (CS) and the second semiconductor chip (2330).

[0109] A thermal interface material (TIM) film (2360) may be interposed between the chip stack (CS), the second semiconductor chip (2330), the second molding film (2350), and the package cap (2400). More specifically, the thermal interface material film (2360) may be provided between the package cap (2400) and the chip stack (CS), between the package cap (2400) and the second semiconductor chip (2330), and between the package cap (2400) and the second molding film (2350). The thermal interface material film (2360) may be a heat transfer member for transferring heat generated in the chip stack (CS) and the second semiconductor chip (2330) to the package cap (2400). The thermal boundary material film (2360) may include thermal grease, epoxy material, or metal solid particles such as indium (P).

[0110] The package cap (2400) can be attached to the package substrate (2200) by an adhesive layer (2500). For example, the adhesive layer (2500) can be provided on the lower surface of the partition portion (2410) of the package cap (2400). The package cap (2400) can bond the lower surface of the partition portion (2410) and the upper surface of the package substrate (2200).

[0111] A portion of the adhesive layer (2500) may be inserted into the interior of the partition (2410) of the package cap (2400). For example, the partition (2410) of the package cap (2400) may have a trench (T) formed on the lower surface of the partition (2410), and the adhesive layer (2500) may fill the trench (T) on the lower surface of the partition (2410). The shape and arrangement of the trench (T), and the configuration of the protrusion provided within the trench (T) may be the same or similar as described with reference to FIGS. 4 through 13.

[0113] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0114] 100: Semiconductor package 200: Package substrate 300: Semiconductor device 400: Package cap 410: Bulkhead section 420: Extension section 500: Adhesive layer T: Trench TP: Protrusion

Claims

Claim 1 A semiconductor package comprising: a package substrate having a mounting area and a peripheral area surrounding the mounting area; a semiconductor device disposed on the mounting area of ​​the package substrate; a package cap disposed on the peripheral area of ​​the package substrate, wherein the package cap includes a partition portion surrounding the semiconductor device and an extension portion covering the semiconductor device; and an adhesive layer between the lower surface of the package cap and the package substrate, wherein the lower surface of the package cap has a trench, the trench has a trapezoidal cross-section, the width of the trench decreases as it moves away from the lower surface of the partition portion, and the trench has a bottom surface parallel to the lower surface of the partition portion, and the adhesive layer is in contact with the upper surface of the package substrate and the lower surface of the package cap, and the adhesive layer fills the inside of the trench. Claim 2 A semiconductor package according to claim 1, wherein the planar shape of the trench has a ring shape extending along the space between the inner surface of the partition portion of the package cap facing the semiconductor element and the outer surface opposite to the inner surface. Claim 3 A semiconductor package according to claim 1, wherein the package cap has at least one protrusion facing the package substrate from the bottom surface of the trench, and the width of the protrusion decreases as it moves away from the bottom surface of the trench. Claim 4 In claim 3, the protrusion height of the protrusion is smaller than the depth of the trench in the semiconductor package. Claim 5 In claim 3, the cross-section of the protrusion has a trapezoidal, semicircular, or triangular shape in which the width decreases as it moves away from the bottom surface of the trench. Claim 6 A semiconductor package according to claim 1, wherein the trench is provided in plurality between the inner surface of the partition portion of the package cap facing the semiconductor element and the outer surface opposite to the inner surface. Claim 7 A semiconductor package according to claim 6, wherein the depth of the trenches increases as they approach the inner surface and the outer surface. Claim 8 A semiconductor package according to claim 6, wherein the lower surface of the package cap comprises outer regions adjacent to the inner surface and the outer surface and an inner region between the outer regions, wherein the depth of the first trenches on the outer regions among the trenches is greater than the depth of the second trenches on the inner regions among the trenches. Claim 9 A semiconductor package comprising: a package substrate; an interposer disposed on the package substrate; a chip stack comprising first semiconductor chips disposed on the interposer and vertically stacked; a second semiconductor chip disposed on the interposer and spaced horizontally apart from the chip stack; and a package cap disposed on the package substrate and surrounding the interposer, wherein the package cap is adhered to the package substrate using an adhesive layer provided on the lower surface of the package cap, and the package cap has a trench provided on the lower surface of the package cap, and the trench becomes narrower as it moves away from the lower surface of the package cap. Claim 10 In claim 9, the cross-section of the trench has a trapezoidal, semicircular, or triangular shape in which the width decreases as it moves away from the lower surface of the package cap. Claim 11 In claim 9, the planar shape of the trench is a semiconductor package having a ring shape surrounding the interposer. Claim 12 A semiconductor package according to claim 9, wherein the package cap has at least one protrusion facing the package substrate from the bottom surface of the trench, and the width of the protrusion decreases as it moves away from the bottom surface of the trench. Claim 13 In claim 12, the protrusion height of the above protrusion is smaller than the depth of the above trench in a semiconductor package. Claim 14 In claim 9, the package cap comprises: a partition portion surrounding the entire interposer, the chip stack, and the second semiconductor chip; and an extension portion disposed on the partition portion and covering the chip stack and the second semiconductor chip. Claim 15 In claim 9, the adhesive layer is a semiconductor package that fills the trench. Claim 16 A semiconductor package comprising: a package substrate; a semiconductor device on the package substrate; and a package cap surrounding the semiconductor device on the package substrate, wherein the package cap comprises: a partition portion surrounding the semiconductor device; and an extension portion connected to the partition portion and covering the semiconductor device, wherein the package cap is adhered to the package substrate using an adhesive layer provided on the lower surface of the partition portion, wherein a trench having a trapezoidal cross-sectional shape is provided on the lower surface of the partition portion such that its width decreases as it moves away from the lower surface, wherein the trench is located between the inner surface and the outer surface of the partition portion, and wherein protrusions are provided on the bottom surface of the trench such that they face toward the package substrate from the bottom surface of the trench, and wherein the protrusion height of the protrusions is smaller than the depth of the trench. Claim 17 In claim 16, the cross-section of the protrusions has a trapezoidal, semicircular, or triangular shape in which the width decreases as it moves away from the bottom surface of the trench. Claim 18 In claim 16, the planar shape of the trench is a semiconductor package having a ring shape extending along the space between the inner surface of the package cap facing the semiconductor element and the outer surface opposite to the inner surface. Claim 19 A semiconductor package according to claim 16, wherein the protrusion height of the protrusions increases as they move further away from the inner surface and the outer surface between the inner surface of the package cap facing the semiconductor element and the outer surface facing the inner surface. Claim 20 In claim 16, the package cap comprises: a partition portion surrounding the semiconductor element; and an extension portion connected to the partition portion and covering the semiconductor element, wherein the trench is provided on the lower surface of the partition portion.

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