Display device and tiled display device

Abstract

A display device and a tile-type display device are provided. The display device comprises a substrate having a display area and a non-display area defined therein, a circuit element layer disposed on the substrate and including a conductive layer, an electrode layer disposed on the circuit element layer and including a first electrode and a second electrode spaced apart from each other, a light-emitting element disposed between the first electrode and the second electrode, and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer.

Description

Technology Field

[0001] The present invention relates to a display device and a tile-type display device. Background Technology

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] A device for displaying images of a display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among these, as a light-emitting display panel, it may include a light-emitting element; for example, in the case of a light-emitting diode (LED), there are organic light-emitting diodes (OLEDs) that use organic materials as light-emitting materials, and inorganic light-emitting diodes that use inorganic materials as light-emitting materials. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device that minimizes damage to a member placed in a light-emitting area caused by heat generated during a cutting process by forming a heat dissipation path by placing a dummy pattern portion having a laminated structure formed of a plurality of conductive layers (or metal layers) in a heat dissipation dummy area located between a light-emitting area and a non-display area.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a substrate having a display area and a non-display area defined therein, a circuit element layer disposed on the substrate and including a conductive layer, an electrode layer disposed on the circuit element layer and including a first electrode and a second electrode spaced apart from each other, a light-emitting element disposed between the first electrode and the second electrode, and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer.

[0007] The second layer above may be made of the same material as the electrode layer.

[0008] The first layer above may be disposed on the same layer as the conductive layer, and the second layer may be disposed on the same layer as the electrode layer.

[0009] At least one of the first layer and the second layer may include a metallic material.

[0010] The first electrode and the second electrode are each extended along a first direction and spaced apart from each other in a second direction that intersects the first direction, and the second layer may be spaced apart from the electrode layer in the second direction.

[0011] The second layer may have the same planar shape as the first electrode.

[0012] The second layer comprises a first pattern and a second pattern spaced apart from each other on the first layer, wherein the first pattern has the same planar shape as the first electrode and the second pattern may have the same planar shape as the second electrode.

[0013] The first electrode and the second electrode are extended along a first direction and are spaced apart from each other in a second direction intersecting the first direction, and the second layer may be spaced apart from the electrode layer in the first direction.

[0014] The second layer comprises a first pattern and a second pattern spaced apart from each other on the first layer, wherein the first pattern is disposed on the extension line of the first electrode in a planar plane, and the second pattern is disposed on the extension line of the second electrode in a planar plane.

[0015] It further includes a first contact electrode that contacts the first electrode and one end of the light-emitting element, respectively, and a second contact electrode that contacts the second electrode and the other end of the light-emitting element, respectively, wherein the second layer may be made of the same material as any one of the electrode layer, the first contact electrode, and the second contact electrode.

[0016] The apparatus further includes a first contact electrode that contacts the first electrode and one end of the light-emitting element, respectively, and a second contact electrode that contacts the second electrode and the other end of the light-emitting element, respectively, and the dummy pattern portion further includes a third layer disposed on the second layer, wherein the second layer is made of the same material as the electrode layer, and the third layer may be made of the same material as either the first contact electrode or the second contact electrode.

[0017] The circuit element layer further comprises a via layer disposed on the conductive layer and the first layer, wherein the electrode layer and the second layer are disposed on the via layer, the first electrode contacts the conductive layer through a first contact hole penetrating the via layer, and the second layer contacts the first layer through a second contact hole penetrating the via layer.

[0018] The above display area includes a light-emitting area and a light-shielding area surrounding the light-emitting area, wherein the light-emitting area is located inside the heat dissipation dummy area in the above display area, the dummy pattern portion is disposed in the light-shielding area located between the light-emitting area and the non-display area, and the light-emitting element may be disposed between the first electrode and the second electrode in the light-emitting area.

[0019] The apparatus further includes a wavelength control layer disposed on the light-emitting element in the light-emitting region and a light-blocking member disposed on the via layer in the light-blocking region, wherein the light-blocking member can cover the dummy pattern portion.

[0020] The above-mentioned light emission region further includes a bank disposed between the via layer and the electrode layer, and the dummy pattern portion further includes a third layer disposed between the via layer and the second layer in the heat dissipation dummy region, wherein the third layer may be made of the same material as the bank.

[0021] The device further includes a fixed pattern disposed on the light-emitting element to expose both ends of the light-emitting element, and the dummy pattern portion further includes a third layer disposed on the second layer, wherein the fixed pattern and the third layer may be made of the same material.

[0022] A display device according to another embodiment for solving the above problem comprises: a substrate having a display area including a light-emitting area and a heat dissipation dummy area, and a non-display area defined therein; a semiconductor layer disposed on the substrate and located in the display area; a gate insulating film disposed on the semiconductor layer; a first conductive layer disposed on the gate insulating film, comprising a gate electrode located in the display area; an interlayer insulating film disposed on the first conductive layer; a second conductive layer disposed on the interlayer insulating film, comprising a source electrode and a drain electrode located in the display area, and a first heat dissipation pattern located in the heat dissipation dummy area; a via layer disposed on the second conductive layer and located in the display area; a third conductive layer disposed on the via layer, comprising a first electrode and a second electrode, at least a portion of which is located in the light-emitting area, and a second heat dissipation pattern located in the heat dissipation dummy area; and a plurality of light-emitting elements disposed in the light-emitting area, wherein the heat dissipation dummy area is located between the light-emitting area and the non-display area, and the first electrode and the second electrode are mutually The plurality of light-emitting elements are spaced apart, and the plurality of light-emitting elements are disposed between the first electrode and the second electrode, the first electrode is electrically connected to the source electrode through a first contact hole penetrating the via layer, and the second heat dissipation pattern is in direct contact with the first heat dissipation pattern through a second contact hole penetrating the via layer.

[0023] A tile-type display device according to one embodiment for solving the above other problems comprises a plurality of display devices, each of the plurality of display devices comprising a substrate having a display area and a non-display area defined therein, a circuit element layer disposed on the substrate and including a conductive layer, an electrode layer disposed on the circuit element layer and including a first electrode and a second electrode spaced apart from each other, a light-emitting element disposed between the first electrode and the second electrode, and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer.

[0024] The second layer above may be made of the same material as the electrode layer.

[0025] The first layer above may be disposed on the same layer as the conductive layer, and the second layer may be disposed on the same layer as the electrode layer.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] A display device according to one embodiment may include a dummy pattern portion having a laminated structure formed of a plurality of conductive layers (or metal layers) in a heat dissipation dummy portion located between a light-emitting area and a non-display area. The dummy pattern portion includes at least one metal layer containing a metal material, and the plurality of layers constituting the dummy pattern portion may have a heat dissipation path through which heat is conducted from top to bottom by contacting each other through at least one contact portion. Accordingly, damage to a member placed in the light-emitting area due to heat generated during the cutting process in the manufacturing process of the display device can be minimized.

[0028] In addition, by simultaneously forming some of the plurality of heat dissipation patterns constituting the dummy pattern portion as patterns identical or similar to the electrode layer and contact electrode constituting the light-emitting element layer without an additional mask process, it is possible to prevent a decrease in the efficiency of the manufacturing process of the display device.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0030] FIG. 1 is a schematic perspective view of a tile-type display device according to one embodiment. FIG. 2 is a schematic plan view of a tile-type display device according to one embodiment. FIG. 3 is a schematic cross-sectional view of a tile-type display device according to one embodiment. FIG. 4 is a schematic plan view showing a plurality of regions of a tile-type display device according to one embodiment. FIG. 5 is a schematic plan view showing a plurality of regions of a display device according to one embodiment. Figure 6 is an enlarged plan view showing an example of an enlarged area A of Figure 4. Figure 7 is a planar layout showing an example of an enlarged area B of Figure 6. FIG. 8 is a plan view illustrating a wavelength control layer and a first light-blocking member disposed in a pixel as illustrated in FIG. 7. Figure 9 is a cross-sectional view showing an example of cutting along the line I-I' of Figure 6. Figure 10 is a planar layout showing an example of an enlarged view of area C of Figure 6. FIG. 11 is a plan view illustrating a wavelength control layer and a first light-blocking member disposed in a pixel as illustrated in FIG. 10. FIG. 12 is a schematic diagram of a light-emitting element according to one embodiment. FIG. 13 is a cross-sectional view showing an example cut along the line II-II' of FIG. 6. FIG. 14 is a cross-sectional view showing an example cut along the line III-III' of FIG. 6. Fig. 15 is a cross-sectional view showing another example cut along the line II-II' of Fig. 6. Figure 16 is a cross-sectional view showing another example cut along the line II-II' of Figure 6. Figure 17 is a cross-sectional view showing another example cut along the line II-II' of Figure 6. FIG. 18 is a cross-sectional view showing another example cut along the line I-I' of FIG. 6. FIG. 19 is a planar layout showing another example of an enlarged area C of FIG. 6. FIG. 20 is a plan view illustrating a wavelength control layer and a first light-blocking member disposed in a pixel as illustrated in FIG. 19. FIGS. 21 to 25 are process plan views and cross-sectional views for explaining the cutting process during the manufacturing process of a display device. FIGS. 26 and FIGS. 27 are cross-sectional views showing other examples of display boards. Specific details for implementing the invention

[0031] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] Elements or layers referred to as "on" another element or layer include cases where another layer or element is interposed directly above or in the middle of another element. Likewise, "below," "left," and "right" refer to cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0033] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0034] Hereinafter, embodiments will be described with reference to the attached drawings.

[0035] FIG. 1 is a schematic perspective view of a tile-type display device according to one embodiment. FIG. 2 is a schematic plan view of a tile-type display device according to one embodiment. FIG. 3 is a schematic cross-sectional view of a tile-type display device according to one embodiment.

[0036] Referring to FIGS. 1 to 3, a tile-type display device (TD) displays video or still images. The tile-type display device (TD) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, e-book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the tile-type display device (TD).

[0037] A tile-type display device (TD) according to one embodiment may include a plurality of display devices (10). The tile-type display device (TD) may further include a lower plate (20).

[0038] In the drawings describing the tile-type display device (TD) or display device (10), a first direction (DR1), a second direction (DR2), and a third direction (DR3) are defined. The first direction (DR1) and the second direction (DR2) may be directions perpendicular to each other within a single plane. The third direction (DR3) may be a direction perpendicular to the plane where the first direction (DR1) and the second direction (DR2) are located. The third direction (DR3) is perpendicular to each of the first direction (DR1) and the second direction (DR2). In the embodiment describing the tile-type display device (TD) or display device (10) below, the third direction (DR3) represents the thickness direction (or display direction) of the tile-type display device (TD) or display device (10).

[0039] The display surface of the tile-type display device (TD) may be positioned on one side of the third direction (DR3), which is the thickness direction. Unless otherwise noted in the embodiments describing the tile-type display device (TD) or the display device (10), "top" indicates the display direction toward one side of the third direction (DR3), and "top surface" indicates the surface facing one side of the third direction (DR3). Additionally, "bottom" indicates the direction opposite to the display direction toward the other side of the third direction (DR3), and "bottom surface" refers to the surface facing the other side of the third direction (DR3). Additionally, "left," "right," "top," and "bottom" indicate the direction when viewing the tile-type display device (TD) or the display device (10) from a plane. For example, "right" indicates one side of the first direction (DR1), "left" indicates the other side of the first direction (DR1), "top" indicates one side of the second direction (DR2), and "bottom" indicates the other side of the second direction (DR2).

[0040] The tile-type display device (TD) may have a rectangular shape including a short side in the first direction (DR1) and a long side in the second direction (DR2) on a plane. The tile-type display device (TD) may have a planar shape overall, but is not limited thereto. The tile-type display device (TD) may have a three-dimensional shape to provide a sense of depth to the user. For example, if the tile-type display device (TD) has a three-dimensional shape, at least some of the display devices (10) among the plurality of display devices (10) described below may have a curved shape. As another example, the tile-type display device (TD) may have a three-dimensional shape by having each of the plurality of display devices (10) have a planar shape and being arranged to have a predetermined angle with respect to each other. By including the plurality of display devices (10), the display area where the image is displayed can be enlarged.

[0041] The lower plate (20) can serve to provide and support an area where a plurality of display devices (10) are arranged. The planar shape of the lower plate (20) can follow the planar shape of the tile-type display device (TD). In an exemplary embodiment where the tile-type display device (TD) has a rectangular shape including a short side in the first direction (DR1) and a long side in the second direction (DR2) on the plane, the lower plate (20) may have a rectangular shape including a short side in the first direction (DR1) and a long side in the second direction (DR2) on the plane. Although not shown in the drawing, various wiring and cables that electrically connect each of the plurality of display devices (10) may be arranged on the lower plate (20), and a fastening member capable of fixing the plurality of display devices (10) may be further arranged.

[0042] A plurality of display devices (10) may be disposed on a lower plate (20). A plurality of display devices (10) may be fixed on one side of the lower plate (20) through a fastening member, but are not limited thereto.

[0043] A plurality of display devices (10) may be arranged in a matrix shape on a lower plate (20). A plurality of display devices (10) may be spaced apart from each other along a first direction (DR1) and a second direction (DR2) in a plane and arranged at a predetermined interval. Display devices (10) arranged adjacent to each other may be spaced apart so that their long sides and / or short sides face each other. By arranging a plurality of display devices (10) spaced apart at a predetermined interval on the lower plate (20), damage to the display device (10) by adjacent display devices (10) can be prevented even when the display device (10) expands due to heat generated by the display device (10). Although the drawing illustrates a case where a plurality of display devices (10) are arranged in a 3x3 matrix shape, the number and arrangement of the plurality of display devices (10) are not limited thereto.

[0044] In the drawing, an example is shown where the arrangement direction of the plurality of display devices (10) coincides with the first direction (DR1) and the second direction (DR2), which are the extension directions of the long and short sides of the tile-type display device (TD), but this is not limited thereto. For example, the arrangement direction of the plurality of display devices (10) and the extension directions of the long and short sides of the tile-type display device (TD) may be inclined with a predetermined slope.

[0045] Each of the plurality of display devices (10) may have a rectangular shape including a short side in the first direction (DR1) and a long side in the second direction (DR2) on a plane. However, not limited thereto, each of the plurality of display devices (10) may have a rectangular shape including a long side in the first direction (DR1) and a short side in the second direction (DR2). The plurality of display devices (10) may have the same planar shape. In addition, the plurality of display devices (10) may have the same size. However, not limited thereto, the plurality of display devices (10) may have different planar shapes and different sizes.

[0046] Each of the plurality of display devices (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following, an example of a display panel is provided in which an inorganic light-emitting diode display panel is applied, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0047] Each of the plurality of display devices (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) is an area where a screen can be displayed, and the non-display area (NDA) is an area where a screen is not displayed.

[0048] The shape of the display area (DA) can follow the shape of the display device (10). For example, the shape of the display area (DA) may have a planar rectangular shape similar to the overall shape of the display device (10). The display area (DA) may generally occupy the center of the display device (10).

[0049] A display area (DA) may include a plurality of pixels (PX). A pixel (PX) refers to a repeating minimum unit for display. To display full color, each pixel (PX) may include a plurality of subpixels emitting different colors. The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square. In an exemplary embodiment, each pixel (PX) may include a plurality of light-emitting elements made of inorganic particles, but is not limited thereto.

[0050] A non-display area (NDA) may be placed around a display area (DA). The non-display area (NDA) may surround the display area (DA) in whole or in part.

[0051] A tile-type display device (TD) may further include a boundary area (SA, or a separation area) between adjacent display devices (10). As described above, a plurality of display devices (10) may be spaced apart from each other and arranged at a predetermined interval, and the boundary area (SA) may be a separation area between display devices (10) arranged adjacently. The boundary area (SA) may also be referred to as a seam. The boundary area (SA) may be an area between the non-display areas (NDA) of display devices (10) arranged adjacently. The boundary area (SA) may be surrounded by the non-display areas (NDA) of display devices (10) arranged adjacently.

[0052] Meanwhile, the boundary area (SA) of the tile-type display device (TD) and the non-display area (NDA) of each of the multiple display devices (10) may not display a screen. Therefore, if the width of the boundary area (SA) where the screen is not displayed or the width of the non-display area (NDA) is large, the user may perceive the boundary area (SA) or the non-display area (NDA), which may reduce the immersion of the image of the tile-type display device (TD). Therefore, in order for the multiple display devices (10) to be displayed as a single display device, the distance between adjacent display devices (10) may be close enough so that the boundary area (SA) where the screen is not displayed is not perceived by the user. Additionally, the width of the non-display area (NDA) of each display device (10) may be minimized so that the non-display area (NDA) where the screen is not displayed is not perceived by the user. That is, the tile-type display device (TD) can eliminate the sense of disconnection between the multiple display devices (10) and improve the immersion of the image by preventing the non-display area (NDA) or boundary portion between the multiple display devices (10) from being perceived.

[0053] FIG. 4 is a schematic plan view showing a plurality of regions of a tile-type display device according to one embodiment. FIG. 5 is a schematic plan view showing a plurality of regions of a display device according to one embodiment.

[0054] Referring to FIG. 4, the tile-type display device (TD) may include a plurality of display devices (10: 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 10_9) spaced apart at a predetermined interval. For example, the plurality of display devices (10) may include first to ninth display devices (10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 10_9). Hereinafter, when referring to a specific display device among the first to ninth display devices (10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 10_9), the display device shall be referred to as "first display device (10_1)", "second display device (10_2)", etc. In addition, when referring to at least one of the first to ninth display devices (10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 10_9) or when referring to the first to ninth display devices (10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 10_9) collectively, it shall be referred to as "display device (10)", "multiple display devices (10)", or "display devices (10)".

[0055] The first to ninth display devices (10: 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 10_9) may be spaced apart from each other in a first direction (DR1) and / or a second direction (DR2). Although the drawing shows nine display devices (10) arranged in a 3x3 matrix structure, the number and arrangement of the display devices (10) are not limited to FIG. 4. The number of display devices (10) may be determined according to the size of the display device (10) and the tile-type display device (TD).

[0056] Some of the display devices (10_2, 10_4, 10_6, 10_8) among the plurality of display devices (10) included in the tile-type display device (TD) may be placed at the edge of the tile-type display device (TD) and may be placed adjacent to one side of the tile-type display device (TD). Other display devices (10_1, 10_3, 10_7, 10_9) among the plurality of display devices (10) included in the tile-type display device (TD) may be placed adjacent to each corner of the tile-type display device (TD). Another part of the display device (10_5) among the plurality of display devices (10) included in the tile-type display device (TD) may be placed inside the tile-type display device (TD) and may be surrounded by other display devices (10_1, 10_2, 10_3, 10_4, 10_6, 10_7, 10_8, 10_9).

[0057] Referring to FIGS. 4 and 5, a display area (DA) of a display device (10) may include a light-emitting area (LA) and a light-blocking area (BA) surrounding the light-emitting area (LA). The light-emitting area (LA) may be positioned to correspond to each of a plurality of sub-pixels included in a pixel (PX). The light-emitting area (LA) and the light-blocking area (BA) may be defined by a first light-blocking member (BM1) described later.

[0058] The light-emitting region (LA) is a region where light emitted from the light-emitting element layer of the display device (10) is provided to the outside, and the light-blocking region (BA) may be a region where light emitted from the light-emitting element layer is not transmitted.

[0059] The light emission area (LA) may include a first light emission area (LA1), a second light emission area (LA2), and a third light emission area (LA3). The first to third light emission areas (LA1, LA2, LA3) may be areas where light having a predetermined peak wavelength is emitted to the outside of the display device (10). The first light emission area (LA1) may emit light of a first color, the second light emission area (LA2) may emit light of a second color, and the third light emission area (LA3) may emit light of a third color. For example, the first color light may be red light having a peak wavelength in the range of 610 nm to 650 nm, the second color light may be green light having a peak wavelength in the range of 510 nm to 550 nm, and the third color light may be blue light having a peak wavelength in the range of 440 nm to 480 nm, but is not limited thereto.

[0060] The first to third light-emitting regions (LA1, LA2, LA3) may be sequentially and repeatedly arranged along the first direction (DR1) in the display area (DA) of the display device (10). The planar shape of the first to third light-emitting regions (LA1, LA2, LA3) may be a rectangle in which the width of the second direction (DR2) is longer than the width of the first direction (DR1), but is not limited thereto.

[0061] A light-blocking region (BA) may be positioned to surround a light-emitting region (LA). Specifically, the light-blocking region (BA) may be positioned to surround the first to third light-emitting regions (LA1, LA2, LA3). The light-blocking regions (BA) of adjacent pixels (PX) may be connected as one, and furthermore, the light-blocking regions (BA) of all pixels (PX) may be connected as one, but are not limited thereto. Each adjacent light-emitting region (LA) may be separated by a light-blocking region (BA). The light-blocking region (BA) may prevent color mixing of the light emitted from the first to third light-emitting regions (LA1, LA2, LA3).

[0062] A non-display area (NDA) of a display device (10) may be arranged to surround a display area (DA). The non-display area (NDA) may be arranged adjacent to each side of the planar display device (10). For example, the display area (DA) may have a planar rectangular shape, and the non-display area (NDA) may be arranged adjacent to four sides of the display area (DA). Specifically, the non-display area (NDA) may include a first non-display area arranged adjacent to the first long side (right side in FIG. 5) of the planar display device (10), a second non-display area arranged adjacent to the second long side (left side in FIG. 5) of the display device (10), a third non-display area arranged adjacent to the first short side (upper side in FIG. 5) of the display device (10), and a fourth non-display area arranged adjacent to the second short side (lower side in FIG. 5) of the display device (10).

[0063] In one embodiment, the display device (10) may further include a heat dissipation dummy area (DMA) located at the edge of the display area (DA). The heat dissipation dummy area (DMA) may be an area where a dummy pattern portion (DP) is placed to prevent damage or deformation of a component of the display device (10) by heat generated by a laser during the process of cutting the display base plate using a laser (hereinafter referred to as the 'cutting process') in the manufacturing process of the display device (10) described later.

[0064] The heat dissipation dummy area (DMA) may be placed at the edge of the display area (DA). The heat dissipation dummy area (DMA) may be placed between the outermost light-emitting area (LA) and the non-display area (NDA). The heat dissipation dummy area (DMA) may overlap with a portion of the light-blocking area (BA) located between the outermost light-emitting area (LA) and the non-display area (NDA).

[0065] In an exemplary embodiment where the planar shape of the display area (DA) is rectangular, the heat dissipation dummy area (DMA) may include a first heat dissipation dummy area (DMA1), a second heat dissipation dummy area (DMA2), a third heat dissipation dummy area (DMA3), and a fourth heat dissipation dummy area (DMA4).

[0066] A first heat dissipation dummy area (DMA1) may be positioned between a light-emitting area (LA) (or a third light-emitting area (LA3)) located at the outermost right edge of the display area (DA) and an adjacent non-display area (NDA). A second heat dissipation dummy area (DMA2) may be positioned between a light-emitting area (LA) (or a first light-emitting area (LA1)) located at the outermost left edge of the display area (DA) and an adjacent non-display area (NDA). The first heat dissipation dummy area (DMA1) and the second heat dissipation dummy area (DMA2) may extend along a second direction (DR2) in a plane.

[0067] A third heat dissipation dummy area (DMA3) may be positioned between a light-emitting area (LA) (or first to third light-emitting areas (LA1, LA2, LA3)) positioned at the upper outermost edge of a display area (DA) and an adjacent non-display area (NDA). A fourth heat dissipation dummy area (DMA4) may be positioned between a light-emitting area (LA) (or first to third light-emitting areas (LA1, LA2, LA3)) positioned at the lower outermost edge of a display area (DA) and an adjacent non-display area (NDA). The third heat dissipation dummy area (DMA3) and the fourth heat dissipation dummy area (DMA4) may extend along a first direction (DR1) in a plane.

[0068] In one embodiment, the display device (10) may include a dummy pattern portion (DP). The dummy pattern portion (DP) may be placed in a heat dissipation dummy region (DMA). The dummy pattern portion (DP) may have a stacked structure of a metal layer (or a conductive layer). By having a structure in which the dummy pattern portion (DP) is placed between the light-emitting region (LA) and the non-display region (NDA) which are placed at the outermost edge and has a stacked structure of multiple layers including a metal material, a heat dissipation path may be provided through which heat generated by a laser during the cutting process in the manufacturing process of the display device (10) diffuses to the dummy pattern portion (DP) formed by the multiple layers. The heat dissipation path of the heat diffused by the dummy pattern portion (DP) will be described later after explaining the cross-sectional structure of the display device (10).

[0069] A dummy pattern section (DP) may include a plurality of dummy pattern sections (DP1, DP2, DP3, DP4). For example, a dummy pattern section (DP) may include a first dummy pattern section (DP1), a second dummy pattern section (DP2), a third dummy pattern section (DP3), and a fourth dummy pattern section (DP4).

[0070] A first dummy pattern section (DP1) may be placed in a first heat dissipation dummy area (DMA1). A plurality of first dummy pattern sections (DP1) may be provided within the first heat dissipation dummy area (DMA1). A plurality of first dummy pattern sections (DP1) may be arranged along a second direction (DR2) in the first heat dissipation dummy area (DMA1). A plurality of first dummy pattern sections (DP1) may be spaced apart from each other in the second direction (DR2), but are not limited thereto. A plurality of first dummy pattern sections (DP1) may be placed adjacent to the right of a plurality of light emission areas (LA) located at the outermost right edge.

[0071] The second dummy pattern section (DP2) may be placed in the second heat dissipation dummy area (DMA2). The second dummy pattern section (DP2) may be provided in multiple numbers within the second heat dissipation dummy area (DMA2). Multiple second dummy pattern sections (DP2) may be arranged along the second direction (DR2) in the second heat dissipation dummy area (DMA2). Multiple second dummy pattern sections (DP2) may be spaced apart from each other in the second direction (DR2), but are not limited thereto. Multiple second dummy pattern sections (DP2) may be placed adjacent to the left side of each of the multiple light emission areas (LA) located at the outermost left edge.

[0072] A third dummy pattern section (DP3) may be placed in a third heat dissipation dummy area (DMA3). A plurality of third dummy pattern sections (DP3) may be provided within the third heat dissipation dummy area (DMA3). A plurality of third dummy pattern sections (DP3) may be arranged along a first direction (DR1) in the third heat dissipation dummy area (DMA3). A plurality of third dummy pattern sections (DP3) may be spaced apart from each other in the first direction (DR1), but are not limited thereto. A plurality of third dummy pattern sections (DP3) may each be placed adjacently to the upper side of a plurality of light emission areas (LA) placed at the upper outermost edge.

[0073] The fourth dummy pattern section (DP4) may be placed in the fourth heat dissipation dummy area (DMA4). The fourth dummy pattern section (DP4) may be provided in multiple numbers within the fourth heat dissipation dummy area (DMA4). Multiple fourth dummy pattern sections (DP4) may be arranged along the first direction (DR1) in the fourth heat dissipation dummy area (DMA4). Multiple fourth dummy pattern sections (DP4) may be spaced apart from each other in the first direction (DR1), but are not limited thereto. Multiple fourth dummy pattern sections (DP4) may be placed adjacent to each other on the lower side of a plurality of light emission areas (LA) located at the lower outermost edge.

[0074] Figure 6 is an enlarged plan view showing an example of an enlarged area A of Figure 4.

[0075] Referring to FIGS. 4 through 6, the first gap (d1) between the first light-emitting area (LA1) and the third light-emitting area (LA3) of pixels (PX) arranged adjacently in the same row in the first display device (10_1) may be the same. Likewise, the first gap (d1) between the first light-emitting area (LA1) and the third light-emitting area (LA3) of pixels (PX) arranged adjacently in the same row in the second display device (10_2) may be the same. Meanwhile, the second gap (d2) between the third light-emitting area (LA3) of a pixel (PX) formed at the outermost edge of the first display device (10_1) and the first light-emitting area (LA1) of a pixel (PX) of the second display device (10_2) formed at the outermost edge of the second display device (10_2) and facing the third light-emitting area (LA3) of the first display device (10_1) in the first direction (DR1) may be different from the first gap (d1).

[0076] Meanwhile, a plurality of display devices (10) included in the tile-type display device (TD) may be spaced apart from each other with a spacing area (SA) in between. For example, the first display device (10_1) and the second display device (10_2) may be spaced apart by a certain distance (d4) with the spacing area (SA) in between. The first display device (10_1) and the second display device (10_2) that are adjacently arranged may have a non-display area (NDA) located in a spaced-apart area facing each other. In this way, the first gap (d1) and the second gap (d2) described above may differ from each other by the gap (d4) of the separation area (SA) between the first display device (10_1) and the second display device (10_2), the width (d3_1) of the non-display area (NDA) of the first display device (10_1), and the width (d3_2) of the non-display area (NDA) of the second display device (10_2).

[0077] Meanwhile, if the difference between the first gap (d1) between the first light-emitting area (LA1) and the third light-emitting area (LA3) that are spaced apart in the same display device (10) and the second gap (d2) between the first light-emitting area (LA1) and the third light-emitting area (LA3) that are spaced apart in different display devices (10) is large, the boundary area (SA) or non-display area (NDA) may be perceived by the user, and the immersion of the image of the tile-type display device (TD) may be reduced. Therefore, by adjusting the width (d3_1, d3_2) of the non-display area (NDA) of each display device (10) to be minimized, the boundary area (SA) of the tile-type display device (TD) may not be perceived by the user.

[0078] Meanwhile, as described below, in order to minimize the width of the non-display area (NDA) of each display device (10), when a laser beam is irradiated onto an area adjacent to the display area (DA) of the display device (10) during a cutting process in which a display substrate is cut using a laser, the heat generated by the laser beam may be easily transferred (or diffused) to the light-emitting area (LA). The display device (10) according to the present embodiment may include a dummy pattern portion (DP) disposed between the light-emitting area (LA) and the non-display area (NDA), thereby having a heat dissipation path through which the heat generated by the laser beam and transferred to the light-emitting area (LA) is conducted to the dummy pattern portion (DP). Accordingly, a heat dissipation path is formed through which at least a portion of the heat generated by the laser beam and transferred to the light-emitting area (LA) is conducted along the dummy pattern portion (DP), thereby blocking the heat from being transferred to the light-emitting area (LA).

[0079] FIG. 7 is a planar layout showing an example of an enlarged region B of FIG. 6. FIG. 8 is a planar view showing a wavelength control layer and a first light-blocking member disposed in a pixel shown in FIG. 7. FIG. 9 is a cross-sectional view showing an example cut along the line I-I' of FIG. 6.

[0080] FIGS. 7 to 9 illustrate the planar structure and cross-sectional structure of a pixel (PX) placed inside the display area (DA) of a display device (10). Hereinafter, the planar structure and cross-sectional structure of a pixel (PX) placed inside the display area (DA) will be described with reference to FIGS. 7 to 9.

[0081] Referring to FIGS. 7 through 9, a pixel (PX) may include a plurality of subpixels (SPXn, where n is a natural number less than or equal to 3). For example, a pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). Each subpixel (SPXn) of the display device (10) may include a light-emitting region (LA) and a light-blocking region (BA).

[0082] The first to third light-emitting regions (LA1, LA2, LA3) may each be a light-emitting region (LA) of the first to third subpixels (SPX1, SPX2, SPX3). For example, the first light-emitting region (LA1) may be the light-emitting region (LA) of the first subpixel (SPX1), the second light-emitting region (LA2) may be the light-emitting region (LA) of the second subpixel (SPX2), and the third light-emitting region (LA3) may be the light-emitting region (LA) of the third subpixel (SPX3).

[0083] A light-blocking region (BA) may be arranged to surround the first to third light-emitting regions (LA1, LA2, LA3). The light-blocking region (BA) of one subpixel (SPXn) abuts the light-blocking region (BA) of an adjacent subpixel (SPXn) (regardless of whether the subpixel (SPXn) is within the same pixel (PX). The light-blocking regions (BA) of adjacent subpixels (SPXn) may be connected as one, and furthermore, the light-blocking regions (BA) of all subpixels (SPXn) may be connected as one, but are not limited thereto. The light-emitting regions (LA) of each adjacent subpixel (SPXn) may be separated by the light-blocking region (BA).

[0084] The display device (10) may include a substrate (SUB), a circuit element layer (CCL), a light-emitting element layer, a wavelength control layer (800), a first light-blocking member (BM1), and a color filter layer (CF). The display device (10) may further include a first capping layer (CAP1), a first flattening layer (OC1), and a protection layer (OC2).

[0085] The substrate (SUB) may be a base substrate or a base member and may be made of an insulating material such as a polymer resin. The substrate (SUB) may be made of glass, quartz, or an insulating material such as a polymer resin. The substrate (SUB) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. In one embodiment, the substrate (SUB) may include a glass substrate, but is not limited thereto.

[0086] The circuit element layer (CCL) can be disposed on a substrate (SUB). The circuit element layer (CCL) is disposed on one side of the substrate (SUB) and can drive a pixel (PX) (or a plurality of sub-pixels (SPXn)). The circuit element layer (CCL) can drive a light-emitting element layer by including at least one transistor, etc.

[0087] The light-emitting element layer may be disposed on one side of the circuit element layer (CCL). The light-emitting element layer may include an electrode layer (200A), a light-emitting element (ED), a contact electrode (700A), and a first insulating layer (520).

[0088] The electrode layer (200A) may be disposed on the circuit element layer (CCL). The electrode layer (200A) may be disposed on the display area (DA). The electrode layer (200A) may include a first electrode (210) and a second electrode (220) spaced apart from each other.

[0089] The first electrode (210) and the second electrode (220) may each have a shape extending in a second direction (DR2) in a plane. The first electrode (210) and the second electrode (220) may be arranged to be spaced apart and facing each other in a first direction (DR1). The first electrode (210) and the second electrode (220) may be arranged such that at least a portion of the first electrode (210) and the second electrode (220) is located in the light-emitting area (LA) of each subpixel (SPXn).

[0090] The first electrode (210) is electrically connected to the circuit element layer (CCL) through the first electrode contact hole (CTD), and the second electrode (220) can be electrically connected to the circuit element layer (CCL) through the second electrode contact hole (CTS).

[0091] The first and second electrodes (210, 220) are each electrically connected to light-emitting elements (EDs), and a predetermined voltage may be applied so that the light-emitting elements (EDs) emit light. For example, the first and second electrodes (210, 220) are electrically connected to a light-emitting element (ED) placed between the first electrode (210) and the second electrode (220) through a contact electrode (700A), and an electrical signal applied to the first and second electrodes (210, 220) can be transmitted to the light-emitting element (ED) through the contact electrode (700A).

[0092] The first electrode (210) and the second electrode (220) can be separated from each other in the separation section (ROP) within the subpixel (SPXn) adjacent to the first electrode (210) and the second electrode (220) in the second direction (DR2). Such shapes of the first electrode (210) and the second electrode (220) can be formed through a process of disconnecting each electrode placed in the separation section (ROP) after the process of placing the light-emitting element (ED) during the manufacturing process of the display device (10). However, not limited thereto, the first and second electrodes (210, 220) may be extended to the subpixel (SPXn) adjacent to the second direction (DR2) and arranged as an integrated unit, or only one of the first electrode (210) or the second electrode (220) may be separated. The shape and arrangement of the first electrode (210) and the second electrode (220) arranged for each subpixel (SPXn) are not particularly limited as long as at least a portion of the first electrode (210) and the second electrode (220) are arranged facing each other so that a space for the light-emitting element (ED) to be arranged is formed.

[0093] The first and second electrodes (210, 220) may be used to form an electric field within a subpixel (SPXn) to align a light-emitting element (ED). The light-emitting element (ED) may be positioned between the first electrode (210) and the second electrode (220) by the electric field formed on the first electrode (210) and the second electrode (220).

[0094] Multiple light-emitting elements (ED) may be placed in the light-emitting region (LA). Multiple light-emitting elements (ED) may not be placed in the light-blocking region (BA).

[0095] A plurality of light-emitting elements (ED) may be disposed on the electrode layer (200A) in the light-emitting region (LA). A plurality of light-emitting elements (ED) may be disposed between the first electrode (210) and the second electrode (220) in the light-emitting region (LA).

[0096] Each of the plurality of light-emitting elements (ED) may have a shape that extends in one direction, and the direction in which the first and second electrodes (210, 220) extend and the direction in which the light-emitting element (ED) extends may be substantially perpendicular. The plurality of light-emitting elements (ED) may be aligned between the first electrode (210) and the second electrode (220) such that one end of the ED is placed on the first electrode (210) and the other end is placed on the second electrode (220).

[0097] The first insulating layer (520) may be disposed on a plurality of light-emitting elements (ED). The first insulating layer (520) may include a fixed pattern (521) disposed in a light-emitting region (LA).

[0098] A fixed pattern (521) may be partially disposed on a light-emitting element (ED) disposed between the first electrode (210) and the second electrode (220). The fixed pattern (521) may be disposed on the light-emitting element (ED), but may expose both ends of the light-emitting element (ED).

[0099] The contact electrode (700A) may be placed on a fixed pattern (521). The contact electrode (700A) may be placed in a light-emitting area (LA). The contact electrode (700A) may include a first contact electrode (710) and a second contact electrode (720) spaced apart from each other.

[0100] The first contact electrode (710) and the second contact electrode (720) may each have a shape extending in a second direction (DR2) in a plane. The first contact electrode (710) and the second contact electrode (720) may be arranged to be spaced apart and facing each other in a first direction (DR1).

[0101] A first contact electrode (710) may be placed on the first electrode (210). The first contact electrode (710) may be in contact with one end of the light-emitting element (ED) exposed by the fixed pattern (521). The first contact electrode (710) may be in contact with a portion of the first electrode (210) through the first contact portion (OP1). One end of the light-emitting element (ED) and the first electrode (210) may be electrically connected through the first contact electrode (710).

[0102] A second contact electrode (720) may be placed on the second electrode (220). The second contact electrode (720) may contact the other end of the light-emitting element (ED) exposed by the fixed pattern (521). The second contact electrode (720) may contact a portion of the second electrode (220) through the second contact portion (OP2). The other end of the light-emitting element (ED) and the second electrode (220) may be electrically connected through the second contact electrode (720).

[0103] The wavelength control layer (800) may be placed on the light-emitting element (ED). The wavelength control layer (800) may be placed in the light-emitting region (LA). The wavelength control layer (800) may be placed in the light-emitting regions (LA1, LA2, LA3) of each subpixel (SPXn), but may not be placed in the light-blocking region (BA).

[0104] The wavelength control layer (800) may include a wavelength conversion layer (WCL) that converts the wavelength of light emitted from a light-emitting element (ED) and a light transmission pattern (TPL) that maintains and passes the wavelength of light emitted from a light-emitting element (ED).

[0105] The wavelength conversion layer (WCL) or light transmission pattern (TPL) may be arranged so as to be separated for each subpixel (SPXn). The wavelength conversion layer (WCL) or light transmission pattern (TPL) is placed in the light-emitting area (LA) of the display area (DA), and adjacent wavelength conversion layers (WCL) and / or light transmission patterns (TPL) may be spaced apart from each other with a first light-blocking member (BM1) placed in the light-blocking area (BA) in between.

[0106] The wavelength conversion layer (WCL) and the light transmission pattern (TPL) may be disposed on the light-emitting device (ED). In some embodiments, the wavelength conversion layer (WCL) and the light transmission pattern (TPL) may be formed by applying a photosensitive material, exposing it to light, and developing it to form a pattern. However, this is not limited thereto, and the wavelength conversion layer (WCL) and the light transmission pattern (TPL) may also be formed by an inkjet method. Below, examples will be provided for cases where the wavelength conversion layer (WCL) and the light transmission pattern (TPL) are formed using a photosensitive material.

[0107] A wavelength conversion layer (WCL) may be disposed in a subpixel (SPXn) where the wavelength of light emitted from a light-emitting element (ED) differs from the color of the corresponding subpixel (SPXn) and thus requires wavelength conversion. A light transmission pattern (TPL) may be disposed in a subpixel (SPXn) where the wavelength of light emitted from a light-emitting element (ED) is the same as the color of the corresponding subpixel (SPXn). An exemplified embodiment corresponds to a case where the light-emitting element (ED) disposed in each subpixel (SPXn) emits light of a third color, wherein a wavelength conversion layer (WCL) is disposed in the first subpixel (SPX1) and the second subpixel (SPX2), respectively, and a light transmission pattern (TPL) is disposed in the third subpixel (SPX3).

[0108] In an exemplary embodiment, the wavelength conversion layer (WCL) may include a first wavelength conversion pattern (WCL1) disposed in a first subpixel (SPX1) and a second wavelength conversion pattern (WCL2) disposed in a second subpixel (SPX2).

[0109] The first wavelength conversion pattern (WCL1) may be placed within a first light-emitting area (LA1) partitioned by a first light-blocking member (BM1) in the first subpixel (SPX1). The first wavelength conversion pattern (WCL1) is placed in the first light-emitting area (LA1) of the first subpixel (SPX1) and may cover a portion of the electrode layer (200A), the light-emitting element (ED), and the contact electrode (700A) placed in the first light-emitting area (LA1).

[0110] The first wavelength conversion pattern (WCL1) can convert light of a third color wavelength emitted from a light-emitting element (ED) into light of a first color wavelength different from the third color and emit it. For example, the first wavelength conversion pattern (WCL1) can convert blue light emitted from a light-emitting element (ED) into red light and emit it.

[0111] The first wavelength conversion pattern (WCL1) may include a first base resin (BRS1) and a first wavelength conversion material (WCP1) dispersed within the first base resin (BRS1). The first wavelength conversion pattern (WCL1) may further include a first scatterer (SCP1) dispersed within the first base resin (BRS1).

[0112] The second wavelength conversion pattern (WCL2) may be placed within the second light-emitting region (LA2) partitioned by the first light-blocking member (BM1) in the second subpixel (SPX2). The second wavelength conversion pattern (WCL2) is placed in the second light-emitting region (LA2) of the second subpixel (SPX2) and may cover a portion of the electrode layer (200A), the light-emitting element (ED), and the contact electrode (700A) placed in the second light-emitting region (LA2).

[0113] The second wavelength conversion pattern (WCL2) can convert light of a third color wavelength emitted from the light-emitting element (ED) into light of a second color wavelength different from the third color and emit it. For example, the second wavelength conversion pattern (WCL2) can convert blue light emitted from the light-emitting element (ED) into green light and emit it.

[0114] The second wavelength conversion pattern (WCL2) may include a second base resin (BRS2) and a second wavelength conversion material (WCP2) dispersed within the second base resin (BRS2). The second wavelength conversion pattern (WCL2) may further include a second scatterer (SCP2) dispersed within the second base resin (BRS2).

[0115] The light transmission pattern (TPL) may be placed within a third light-emitting region (LA3) partitioned by a first light-blocking member (BM1) in a third subpixel (SPX3). The light transmission pattern (TPL) may be placed in the third light-emitting region (LA3) of the third subpixel (SPX3) to cover a portion of the electrode layer (200A), the light-emitting element (ED), and the contact electrode (700A) placed in the third light-emitting region (LA3).

[0116] The light transmission pattern (TPL) can emit light of a third color wavelength emitted from the light-emitting element (ED) while maintaining that wavelength. For example, the light transmission pattern (TPL) transmits blue light emitted from the light-emitting element (ED) while maintaining that wavelength.

[0117] The light transmission pattern (TPL) may include a third base resin (BRS3). The light transmission pattern (TPL) may further include a third scatterer (SCP3) dispersed within the third base resin (BRS3).

[0118] The first to third base resins (BRS1, BRS2, ​​BRS3) may include a transparent organic material. For example, the first to third base resins (BRS1, BRS2, ​​BRS3) may be composed of an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins (BRS1, BRS2, ​​BRS3) may all be composed of the same material, but are not limited thereto.

[0119] The first to third scatterers (SCP1, SCP2, SCP3) may have a refractive index different from that of the first to third base resins (BRS1, BRS2, ​​BRS3). The first to third scatterers (SCP1, SCP2, SCP3) may include metal oxide particles or organic particles. Examples of the metal oxides include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the organic particle materials include acrylic resin or urethane resin. The first to third scatterers (SCP1, SCP2, SCP3) may all be made of the same material, but are not limited thereto.

[0120] The first wavelength conversion material (WCP1) may be a material that converts a third color into a first color, and the second wavelength conversion material (WCP2) may be a material that converts a third color into a second color. For example, the first wavelength conversion material (WCP1) may be a material that converts blue light into red light, and the second wavelength conversion material (WCP2) may be a material that converts blue light into green light. The first wavelength conversion material (WCP1) and the second wavelength conversion material (WCP2) may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0121] A first capping layer (CAP1) may be placed on the wavelength control layer (800) to cover them. The first capping layer (CAP1) may seal the outer surface of the wavelength control layer (800). For example, the first capping layer (CAP1) may seal the first wavelength conversion pattern (WCL1), the second wavelength conversion pattern (WCL2), and the light transmission pattern (TPL) to prevent damage or contamination of the first wavelength conversion pattern (WCL1), the second wavelength conversion pattern (WCL2), and the light transmission pattern (TPL).

[0122] The first capping layer (CAP1) may include an inorganic material. For example, the first capping layer (CAP1) may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride.

[0123] The first light-blocking member (BM1) may be disposed on the first capping layer (CAP1). The first light-blocking member (BM1) may be disposed in the light-blocking area (BA) of the display area (DA) along the boundary of the subpixel (SPXn). The first light-blocking member (BM1) may be disposed in the area between the wavelength control layer (WCL) and the light transmission pattern (TPL) disposed in the light-emitting area (LA).

[0124] The first light-blocking member (BM1) may be formed by including an organic material. In one embodiment, the first light-blocking member (BM1) may include a light-absorbing material that absorbs a visible light wavelength band. As the first light-blocking member (BM1) includes a light-absorbing material and is positioned along the boundary of each subpixel (SPXn), the first light-blocking member (BM1) may define the light-emitting region (LA: LA1, LA2, LA3) and the light-blocking region (BA) of each subpixel (SPXn). That is, the first light-blocking member (BM1) may be a subpixel defining film that defines the light-emitting region (LA) and the light-blocking region (BA) of each subpixel (SPXn).

[0125] The first flattening layer (OC1) may be disposed on the wavelength control layer (800) and the first light-blocking member (BM1). The first flattening layer (OC1) may be disposed on the wavelength control layer (800) and the first light-blocking member (BM1) and may serve to flatten the step difference caused by the member disposed below. The first flattening layer (OC1) may include an organic material. For example, the first flattening layer (OC1) may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0126] The color filter layer (CF) can be placed on the first flattening layer (OC1) in the display area (DA).

[0127] The color filter layer (CF) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3).

[0128] The first to third color filters (CF1, CF2, CF3) may include a colorant, such as a dye or pigment, that absorbs wavelengths other than the corresponding color wavelength. The first color filter (CF1) may selectively transmit light of the first color (e.g., red light) and block or absorb light of the second color (e.g., green light) and light of the third color (e.g., blue light). The second color filter (CF2) may selectively transmit light of the second color (e.g., green light) and block or absorb light of the first color (e.g., red light) and light of the third color (e.g., blue light). The third color filter (CF3) may selectively transmit light of the third color (e.g., blue light) and block or absorb light of the first color (e.g., red light) and light of the second color (e.g., green light). For example, the first color filter (CF1) may be a red color filter, the second color filter (CF2) may be a green color filter, and the third color filter (CF3) may be a blue color filter.

[0129] The first to third color filters (CF1, CF2, CF3) can absorb a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light. Accordingly, the first to third color filters (CF1, CF2, CF3) can prevent color distortion caused by external light reflection.

[0130] A first color filter (CF1) may be placed in a first light-emitting area (LA1) of a first subpixel (SPX1). A first color filter (CF1) may be further placed in a light-blocking area (BA) surrounding the light-emitting area (LA). A first color filter (CF1) may be placed on a first flattening layer (OC1) in the first light-emitting area (LA1) and the light-blocking area (BA).

[0131] The second color filter (CF2) may be placed in the second light-emitting area (LA2) of the second subpixel (SPX2). The second color filter (CF2) may be further placed in the light-blocking area (BA) surrounding the light-emitting area (LA). The second color filter (CF2) may be placed on the first flattening layer (OC1) exposed by the first color filter (CF1) in the second light-emitting area (LA2), and on the first color filter (CF1) in the light-blocking area (BA).

[0132] The third color filter (CF3) may be placed in the third 2nd light-emitting area (LA3) of the third subpixel (SPX32). The third color filter (CF3) may be further placed in the light-blocking area (BA) surrounding the light-emitting area (LA). The third color filter (CF3) may be placed on the first flattening layer (OC1) exposed by the first and second color filters (CF1, CF2) in the third light-emitting area (LA3), and on the first and second color filters (CF1, CF2) in the light-blocking area (BA).

[0133] A protective layer (OC2) may be disposed on a color filter layer (CF). The protective layer (OC2) may include at least one organic film to protect another member disposed below the protective layer (OC2) from foreign substances such as dust.

[0134] FIG. 10 is a planar layout showing an example of an enlarged region C of FIG. 6. FIG. 11 is a planar view showing a wavelength control layer and a first light-blocking member disposed in a pixel shown in FIG. 10.

[0135] FIGS. 10 and 11 illustrate the planar structure of a pixel (PX) placed in a non-display area (NDA) and an adjacent display area (DA) of a display device (10). FIGS. 10 and 11 illustrate only the first dummy pattern part (DP1) placed in the first heat dissipation dummy area (DMA1) and the third dummy pattern part (DP3) placed in the third heat dissipation dummy area (DMA3). The second dummy pattern part (DP2) may be substantially identical to the planar structure of the first dummy pattern part (DP1) except for the location of the area where it is placed, and the fourth dummy pattern part (DP4) may be substantially identical to the planar structure of the third dummy pattern part (DP3) except for the location of the area where it is placed. Accordingly, the planar structure of the first dummy pattern section (DP1) and the third dummy pattern section (DP3) placed at the outermost edge of the display area (DA) of the display device (10) will be described below, the structure of the second dummy pattern section (DP2) will be replaced by the description of the structure of the first dummy pattern section (DP1), and the structure of the fourth dummy pattern section (DP4) will be replaced by the description of the structure of the third dummy pattern section (DP3).

[0136] Referring to FIGS. 6, 10, and 11, the first dummy pattern portion (DP1) may be placed in the first heat dissipation dummy area (DMA1). The first heat dissipation dummy area (DMA1) may be placed between the third light-emitting area (LA3) and the non-display area (NDA) of the pixel (PX) located at the outermost right edge of the display area (DA) as described above.

[0137] The first dummy pattern section (DP1) may include a first layer (230) and a second layer (730) placed on different layers.

[0138] The first layer (230) of the first dummy pattern section (DP1) may have a shape that extends in a second direction (DR2) in a planar manner. The first layer (230) of the first dummy pattern section (DP1) may be arranged to be spaced apart from the electrode layer (200A) in the first direction (DR1).

[0139] The first layer (230) of the first dummy pattern portion (DP1) may have the same planar shape as one of the first electrode (210) and the second electrode (220) of the electrode layer (200A). The first layer (230) of the first dummy pattern portion (DP1) may be formed with the same pattern as one of the first electrode (210) and the second electrode (220) of the electrode layer (200A). The first layer (230) of the first dummy pattern portion (DP1) may contact at least one of the plurality of conductive layers (or metal layers) of the dummy element layer (CCL) through the first dummy electrode contact hole (CTH1).

[0140] The second layer (730) of the first dummy pattern section (DP1) may have a shape that extends in a second direction (DR2) in a planar manner. The second layer (730) of the first dummy pattern section (DP1) may be arranged to be spaced apart from the contact electrode (700A) in the first direction (DR1).

[0141] The second layer (730) of the first dummy pattern portion (DP1) may have the same planar shape as one of the first contact electrode (710) and the second contact electrode (720) of the contact electrode (700A). The second layer (730) of the first dummy pattern portion (DP1) may be formed with the same pattern as one of the first contact electrode (710) and the second contact electrode (720) of the contact electrode (700A).

[0142] The second layer (730) of the first dummy pattern section (DP1) may be placed on the first layer (230) of the first dummy pattern section (DP1). The second layer (730) of the first dummy pattern section (DP1) may overlap with at least a portion of the first layer (230) in a third direction (DR3). The second layer (730) of the first dummy pattern section (DP1) may contact a portion of the first layer (230) of the first dummy pattern section (DP1) through a third contact section (OP3).

[0143] In one embodiment, the pattern of the first dummy pattern portion (DP1) may be similar to the pattern of the electrode layer (200A) and the contact electrode (700A) that are placed in the light-emitting area (LA) of each subpixel (SPXn) to form a pixel pattern. Specifically, the first and second electrodes (210, 220) of the electrode layer (200A) and the first and second contact electrodes (710, 720) of the contact electrode (700A) may be placed in the light-emitting area (LA) of each subpixel (SPXn) to form a pixel pattern. In this case, the first dummy pattern portion (DP1) may correspond to the first electrode (210) and the first contact electrode (710) that form the pixel pattern and may have the same pattern as the first electrode (210) and the first contact electrode (710). However, not limited thereto, the first dummy pattern part (DP1) may correspond to the second electrode (220) and the second contact electrode (720) constituting the pixel pattern and have the same pattern as the second electrode (220) and the second contact electrode (720).

[0144] The wavelength control layer (800) placed in the light-emitting area (LA) can be non-overlapping with the first layer (230) of the first dummy pattern section (DP1) and the second layer (730) of the first dummy pattern section (DP1) in the third direction (DR3). The first light-blocking member (BM1) placed in the light-blocking area (BA) can be overlapping with the first layer (230) of the first dummy pattern section (DP1) and the second layer (730) of the first dummy pattern section (DP1) in the third direction (DR3).

[0145] The third dummy pattern section (DP3) may be placed in the third heat dissipation dummy area (DMA3). The third heat dissipation dummy area (DMA3) may be placed between the first to third light-emitting areas (LA1, LA2, LA3) and the non-display area (NDA) of the pixel (PX) located at the upper outermost edge of the display area (DA) as described above.

[0146] The third dummy pattern section (DP3) may include a first layer (211, 221) and a second layer (740) placed on different layers.

[0147] The first layer (211, 221) of the third dummy pattern portion (DP3) may have a shape that extends in a second direction (DR2) in a plane. The first layer (211, 221) of the third dummy pattern portion (DP3) may not be placed in a non-display area (NDA). The first layer (211, 221) of the third dummy pattern portion (DP3) may be placed so as to be spaced apart from the electrode layer (200A) in the second direction (DR2).

[0148] The first layer (211, 221) of the third dummy pattern section (DP3) may include a first pattern (211) and a second pattern (221) that are spaced apart from each other. The first pattern (211) of the third dummy pattern section (DP3) and the second pattern (221) of the third dummy pattern section (DP3) may be spaced apart from each other in a first direction (DR1).

[0149] The first pattern (211) of the third dummy pattern section (DP3) may be located on the extension line of the first electrode (210), and the second pattern (221) of the third dummy pattern section (DP3) may be located on the extension line of the second electrode (220). Such shapes of the first pattern (211) of the third dummy pattern section (DP3) and the first electrode (210) may be formed through a process of disconnecting the aforementioned separation section (ROP) after the process of placing the light-emitting element (ED) during the manufacturing process of the display device (10). Similarly, such shapes of the second pattern (221) of the third dummy pattern section (DP3) and the second electrode (220) may be formed through a process of disconnecting the separation section (ROP) after the process of placing the light-emitting element (ED) during the manufacturing process of the display device (10).

[0150] The first pattern (211) of the third dummy pattern section (DP3) may contact at least one of the plurality of conductive layers (or metal layers) of the circuit element layer (CCL) through the second dummy electrode contact hole (CTH2), and the second pattern (221) of the third dummy pattern section (DP3) may contact at least one of the plurality of conductive layers (or metal layers) of the circuit element layer (CCL) through the third dummy electrode contact hole (CTH3). Meanwhile, although the drawing illustrates that both the first pattern (211) of the third dummy pattern section (DP3) and the second pattern (221) of the third dummy pattern section (DP3) contact the circuit element layer (CCL), it is not limited thereto. For example, one of the first pattern (211) of the third dummy pattern section (DP3) and the second pattern (221) of the third dummy pattern section (DP3) may be in contact with the circuit element layer (CCL), and the other pattern may not be in contact with the circuit element layer (CCL).

[0151] The second layer (740) of the third dummy pattern section (DP3) may have a shape that extends in a first direction (DR2) in a plane. The second layer (740) of the third dummy pattern section (DP3) may cover the first pattern (211) and the second pattern (221) of the third dummy pattern section (DP3) in the second direction (DR2). The second layer (740) of the third dummy pattern section (DP3) may be positioned to be spaced apart from the contact electrode (700A) in the second direction (DR2).

[0152] The second layer (740) of the third dummy pattern section (DP3) may be placed on the first layer (211, 221) of the third dummy pattern section (DP3). The second layer (740) of the third dummy pattern section (DP3) may overlap with at least a portion of the first layer (211, 221) of the third dummy pattern section (DP3) in the third direction (DR3). The second layer (740) of the third dummy pattern section (DP3) may contact a portion of the first layer (211, 221) of the third dummy pattern section (DP3) through the fourth contact section (OP4). In the drawing, the second layer (740) of the third dummy pattern section (DP3) is shown to contact a portion of the second pattern (221) of the third dummy pattern section (DP3) through the fourth contact section (OP4), but is not limited thereto. For example, the second layer (740) of the third dummy pattern section (DP3) may come into contact with a portion of the first pattern (211) of the third dummy pattern section (DP3), or may come into contact with both the first pattern (211) and the second pattern (221) of the third dummy pattern section (DP3).

[0153] FIG. 12 is a schematic diagram of a light-emitting element according to one embodiment.

[0154] Referring to FIG. 12, the light-emitting element (ED) is a particle-shaped element and may have a rod or cylindrical shape having a predetermined aspect ratio. The length of the light-emitting element (ED) is greater than the diameter of the light-emitting element (ED), and the aspect ratio may be 6:5 to 100:1, but is not limited thereto.

[0155] The light-emitting element (ED) may have a size ranging from a nanometer scale (1 nm or more and less than 1 µm) to a micrometer scale (1 µm or more and less than 1 mm). In one embodiment, the light-emitting element (ED) may have both a diameter and a length of the nanometer scale or both of the micrometer scale. In some other embodiments, the diameter of the light-emitting element (ED) may have a size of the nanometer scale, while the length of the light-emitting element (ED) may have a size of the micrometer scale. In some embodiments, some of the light-emitting elements (ED) may have a diameter and / or length of the nanometer scale, while others may have a diameter and / or length of the micrometer scale.

[0156] In one embodiment, the light-emitting element (ED) may be an inorganic light-emitting diode. The inorganic light-emitting diode may include a plurality of semiconductor layers. For example, the inorganic light-emitting diode may include a first conductivity type (e.g., n-type) semiconductor layer, a second conductivity type (e.g., p-type) semiconductor layer, and an active semiconductor layer interposed between them. The active semiconductor layer receives holes and electrons from the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, and the holes and electrons reaching the active semiconductor layer may combine with each other to emit light.

[0157] In one embodiment, the semiconductor layers described above may be sequentially stacked along the length direction of the light-emitting element (ED). The light-emitting element (ED) may include a first semiconductor layer (31), a device active layer (33), and a second semiconductor layer (32) that are sequentially stacked along the length direction.

[0158] The first semiconductor layer (31) may be doped with a first conductivity type dopant. The first conductivity type dopant may be Si, Ge, Sn, etc. In an exemplary embodiment, the first semiconductor layer (31) may be n-GaN doped with n-type Si.

[0159] The second semiconductor layer (32) may be spaced apart from the first semiconductor layer (31) with the device active layer (33) in between. The second semiconductor layer (32) may be doped with a second conductivity type dopant such as Mg, Zn, Ca, Se, Ba, etc. In an exemplary embodiment, the second semiconductor layer (32) may be p-GaN doped with p-type Mg.

[0160] The device active layer (33) may include a material having a single or multiple quantum well structure. As described above, the device active layer (33) may emit light by the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (31) and the second semiconductor layer (32).

[0161] In some embodiments, the device active layer (33) may have a structure in which semiconductor materials with a large band gap energy and semiconductor materials with a small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength of the light emitted.

[0162] The light emitted from the device active layer (33) can be emitted not only on the outer surface in the longitudinal direction of the light-emitting element (ED), but also on both sides. That is, the light emitted from the device active layer (33) is not limited to a single direction of emission.

[0163] The light-emitting element (ED) may further include a device electrode layer (37) disposed on the second semiconductor layer (32). The device electrode layer (37) may be in contact with the second semiconductor layer (32). The device electrode layer (37) may be an ohmic contact electrode, but is not limited thereto, and may be a Schottky contact electrode.

[0164] The device electrode layer (37) can be positioned between the second semiconductor layer (32) and the contact electrode (700A) to reduce resistance when the two ends of the light-emitting element (ED) and the contact electrode (700A) are electrically connected to apply an electrical signal to the first semiconductor layer (31) and the second semiconductor layer (32). The device electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ITZO (Indium Tin-Zinc Oxide). The device electrode layer (37) may also include an n-type or p-type doped semiconductor material.

[0165] The light-emitting element (ED) may further include a device insulating film (38) that surrounds the outer surface of the first semiconductor layer (31), the second semiconductor layer (32), the device active layer (33), and / or the device electrode layer (37). The device insulating film (38) is arranged to surround at least the outer surface of the device active layer (33) and may extend in one direction in which the light-emitting element (ED) extends. The device insulating film (38) can perform the function of protecting the above components. The device insulating film (38) is made of materials having insulating properties and can prevent an electrical short circuit that may occur when the device active layer (33) comes into direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, since the device insulating film (38) protects the outer surface of the first and second semiconductor layers (31, 32), including the device active layer (33), it can prevent a decrease in light-emitting efficiency.

[0166] FIG. 13 is a cross-sectional view showing an example cut along the line II-II' of FIG. 6.

[0167] The display device (10) illustrated in FIG. 13 illustrates a non-display area (NDA) and a display area (DA) adjacent to the non-display area (NDA). Specifically, the display area (DA) in FIG. 13 illustrates a light-emitting area (LA) and a first heat dissipation dummy area (DMA1) together.

[0168] Referring to FIG. 13, a circuit element layer (CCL) may be disposed on a substrate (SUB). The circuit element layer (CCL) may include a lower metal layer (110), a semiconductor layer (120), a first conductive layer (130), a second conductive layer (140), and a plurality of insulating films. The plurality of insulating films included in the circuit element layer (CCL) may include a buffer layer (161), a gate insulating film (162), an interlayer insulating film (163), a passivation layer (164), and a via layer (165).

[0169] The lower metal layer (110) is disposed on a substrate (SUB). The lower metal layer (110) may be located in a display area (DA). The lower metal layer (110) may include a light-blocking layer (BML) and a first heat dissipation pattern (DP11).

[0170] The light-blocking layer (BML) may be positioned to cover at least the channel region of the active layer (ACT) of the transistor (TR) from the bottom. However, it is not limited thereto, and the light-blocking layer (BML) may be omitted.

[0171] The first heat dissipation pattern (DP11) may be spaced apart from the light-blocking layer (BML). The first heat dissipation pattern (DP11) may be placed in the first heat dissipation dummy area (DMA1). The first heat dissipation pattern (DP11) may be one of a plurality of layers constituting the first dummy pattern section (DP1). Hereinafter, the same reference numeral 'DP11' may be referred to as the 'first heat dissipation pattern (DP11)' or the 'third layer (DP11) of the first dummy pattern section (DP1).' The third layer (DP11) of the first dummy pattern section (DP1) may be formed on a layer different from the first layer (230) of the first dummy pattern section (DP1) and the second layer (730) of the first dummy pattern section (DP1) described above.

[0172] The lower metal layer (110) may include a material that blocks light. For example, the lower metal layer (110) may be formed of an opaque metal material that blocks the transmission of light.

[0173] A buffer layer (161) may be placed on a lower metal layer (110). The buffer layer (161) may be placed to cover the front surface of a substrate (SUB) on which the lower metal layer (110) is placed. The buffer layer (161) may be placed across a display area (DA) and a non-display area (NDA) on the substrate (SUB). The buffer layer (161) may serve to protect multiple transistors from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability.

[0174] The semiconductor layer (120) is placed on the buffer layer (161). The semiconductor layer (120) may be located in the display area (DA). The semiconductor layer (120) may include the active layer (ACT) of the transistor (TR). The active layer (ACT) of the transistor (TR) may be placed overlapping the light-blocking layer (BML) as described above.

[0175] The semiconductor layer (120) may include polycrystalline silicon, single-crystal silicon, oxide semiconductor, etc. In an exemplary embodiment, when the semiconductor layer (120) includes polycrystalline silicon, the polycrystalline silicon may be formed by crystallizing amorphous silicon. When the semiconductor layer (120) includes polycrystalline silicon, the active layer (ACT) of the transistor (TR) may include a plurality of doped regions doped with impurities and channel regions between them. In another exemplary embodiment, the semiconductor layer (120) may include an oxide semiconductor. The oxide semiconductor may be, for example, indium-tin oxide (ITO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-zinc-tin oxide (IZTO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-gallium-zinc-tin oxide (IGZTO), etc.

[0176] A gate insulating film (162) may be disposed on a semiconductor layer (120). The gate insulating film (162) may be disposed in a display area (DA) and a non-display area (NDA). The gate insulating film (162) may function as a gate insulating film for each transistor. The gate insulating film (162) may be formed as a multilayer in which inorganic layers comprising at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy) are alternately stacked.

[0177] The first conductive layer (130) may be disposed on the gate insulating film (162). The first conductive layer (130) may be located in the display area (DA). The first conductive layer (130) may include the gate electrode (GE) of the transistor (TR) and the second heat dissipation pattern (DP12).

[0178] The gate electrode (GE) of the transistor (TR) can be positioned to overlap the channel region of the active layer (ACT) and the third direction (DR3), which is the thickness direction of the substrate (SUB).

[0179] The second heat dissipation pattern (DP12) may be spaced apart from the gate electrode (GE). The second heat dissipation pattern (DP12) may be placed in the first heat dissipation dummy region (DMA1). The second heat dissipation pattern (DP12) may be placed overlappingly with the first heat dissipation pattern (DP11). The second heat dissipation pattern (DP12) may be in direct contact with one side of the first heat dissipation pattern (DP11) through a contact hole (CNT14) penetrating the buffer layer (161) and the gate insulating film (162). The second heat dissipation pattern (DP12) may be one of a plurality of layers constituting the first dummy pattern portion (DP1). Hereinafter, the same reference numeral 'DP12' may be referred to as the 'second heat dissipation pattern (DP12)' or the 'fourth layer (DP12) of the first dummy pattern portion (DP1).' However, not limited to this, the second heat dissipation pattern (DP12) may be omitted.

[0180] The first conductive layer (130) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.

[0181] An interlayer insulating film (163) may be disposed on the first conductive layer (130). The interlayer insulating film (163) may be disposed across the display area (DA) and the non-display area (NDA). The interlayer insulating film (163) may be disposed to cover the gate electrode (GE). The interlayer insulating film (163) may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy).

[0182] The second conductive layer (140) may be disposed on the first interlayer insulating film (163). The second conductive layer (140) may be located in the display area (DA). The second conductive layer (140) may include a drain electrode (SD1) of the transistor (TR), a source electrode (SD2) of the transistor (TR), a voltage line (VL), and a third heat dissipation pattern (DP13).

[0183] The drain electrode (SD1) of the transistor (TR) can be electrically connected to one end region of the active layer (ACT) of the transistor (TR) through a contact hole (CNT12) penetrating the interlayer insulating film (163) and the gate insulating film (162).

[0184] The source electrode (SD2) of the transistor (TR) can be electrically connected to the other end region of the active layer (ACT) of the transistor (TR) through a contact hole (CNT11) penetrating the interlayer insulating film (163) and the gate insulating film (162). Additionally, the source electrode (SD2) of the transistor (TR) can be electrically connected to the light-blocking layer (BML) through another contact hole (CNT13) penetrating the interlayer insulating film (163), the gate insulating film (162), and the buffer layer (161).

[0185] A voltage line (VL) may be supplied with a low potential voltage (or a second power supply voltage) lower than the high potential voltage (or a first power supply voltage) supplied to the transistor (TR). The voltage line (VL) may be electrically connected to a second electrode (220) through a second electrode contact hole (CTS) that penetrates the passivation layer (164) and via layer (165) described later.

[0186] The third heat dissipation pattern (DP13) may be spaced apart from the drain electrode (SD1) of the transistor (TR), the source electrode (SD2) of the transistor (TR), and the voltage line (VL). The third heat dissipation pattern (DP13) may be placed in the first heat dissipation dummy area (DMA1). The third heat dissipation pattern (DP13) may be placed overlappingly with the second heat dissipation pattern (DP12) and the first heat dissipation pattern (DP11). The third heat dissipation pattern (DP13) may be in direct contact with one side of the second heat dissipation pattern (DP12) through a contact hole (CNT15) penetrating the interlayer insulating film (163).

[0187] The third heat dissipation pattern (DP13) may be one of a plurality of layers constituting the first dummy pattern portion (DP1). Hereinafter, the same reference numeral 'DP13' may be referred to as the 'third heat dissipation pattern (DP13)' or the 'fifth layer (DP13) of the first dummy pattern portion (DP1).' As described above, when the second heat dissipation pattern (DP12) is omitted, the third heat dissipation pattern (DP13) may come into direct contact with the first heat dissipation pattern (DP11) through a contact hole penetrating the interlayer insulating film (163), the gate insulating film (162), and the buffer layer (161).

[0188] The second conductive layer (140) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.

[0189] A passivation layer (164) may be disposed on the second conductive layer (140). The passivation layer (164) may be disposed across the display area (DA) and the non-display area (NDA). The passivation layer (164) serves to cover and protect the second conductive layer (140). The passivation layer (164) may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy).

[0190] The via layer (165) may be placed on the passivation layer (164). The via layer (165) may be placed in the display area (DA). The via layer (165) may not be placed in the non-display area (NDA). The via layer (165) may serve to flatten the step formed by the pattern of the lower member. The via layer (165) may include an organic insulating material, such as an organic material such as polyimide (PI).

[0191] Referring to FIGS. 10 to 13, the light-emitting element layer may be disposed on one side of the via layer (165) of the circuit element layer (CCL). The light-emitting element layer may include a third conductive layer (200), a second insulating layer (510), a light-emitting element (ED), a first insulating layer (520), and a fourth conductive layer (700).

[0192] The third conductive layer (200) may be disposed on one side of the via layer (165). The third conductive layer (200) may be located in the display area (DA). The third conductive layer (200) may include an electrode layer (200A) and a fourth heat dissipation pattern (230).

[0193] The electrode layer (200A) may be placed directly on one side of the via layer (165). As described above, the electrode layer (200A) may include a first electrode (210) and a second electrode (220), and the first electrode (210) and the second electrode (220) may be spaced apart from each other on one side of the via layer (165). The first electrode (210) and the second electrode (220) may be spaced apart from each other in a first direction (DR1) so as to expose a portion of the via layer (165).

[0194] The first electrode (210) can be connected to the transistor (TR) through a first electrode contact hole (CTD) that penetrates the via layer (165) and the passivation layer (164). Specifically, the first electrode (210) can be connected to the source electrode (SD2) of the transistor (TR) through the first electrode contact hole (CTD). The first electrode (210) can be in direct contact with one side of the source electrode (SD2) of the transistor (TR) exposed by the first electrode contact hole (CTD).

[0195] The second electrode (220) can be connected to a voltage line (VL) through a second electrode contact hole (CTS) that penetrates the via layer (165) and the passivation layer (164). The second electrode (220) can be in direct contact with one side of the voltage line (VL) exposed by the second electrode contact hole (CTS).

[0196] The fourth heat dissipation pattern (230) may be spaced apart from the first electrode (210) and the second electrode (220). The fourth heat dissipation pattern (230) may be placed in the first heat dissipation dummy area (DMA1). The fourth heat dissipation pattern (230) may be placed overlappingly with the first to third heat dissipation patterns (DP11, DP12, DP13). The fourth heat dissipation pattern (230) may be in direct contact with one side of the third heat dissipation pattern (DP13) through the first dummy electrode contact hole (CTH1) penetrating the via layer (165) and the passivation layer (164).

[0197] The fourth heat dissipation pattern (230) may be one of a plurality of layers constituting the first dummy pattern section (DP1). The fourth heat dissipation pattern (230) may be the first layer (230) of the first dummy pattern section (DP1) described above with reference to FIGS. 10 and FIGS. 11. Hereinafter, the same reference numeral '230' may be referred to as the 'fourth heat dissipation pattern (230)' or the 'first layer (230) of the first dummy pattern section (DP1)'. Meanwhile, in the drawings, the fourth heat dissipation pattern (230) disposed on the via layer (165) is shown to be in direct contact with the third heat dissipation pattern (DP13) of the second conductive layer (140) included in the circuit element layer (CCL), but is not limited thereto. For example, the fourth heat dissipation pattern (230) may be in direct contact with the second heat dissipation pattern (DP12) of the first conductive layer (130) included in the circuit element layer (CCL) with the third heat dissipation pattern (DP13) omitted, or the second and third heat dissipation patterns (DP12, DP13) may be omitted and in direct contact with the first heat dissipation pattern (DP11) of the lower metal layer (110).

[0198] The first electrode (210), the second electrode (220), and the fourth heat dissipation pattern (230) may be made of the same material. The first electrode (210), the second electrode (220), and the fourth heat dissipation pattern (230) may be formed on the same layer. That is, the first electrode (210), the second electrode (220), and the fourth heat dissipation pattern (230) may be formed simultaneously through a single mask process. As described above, the fourth heat dissipation pattern (230) may be formed with the same pattern as one of the first electrode (210) and the second electrode (220).

[0199] The third conductive layer (200) may include a transparent conductive material. For example, the third conductive layer (200) may include materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin-Zinc Oxide), etc., but is not limited thereto. In some other embodiments, the third conductive layer (200) may include a highly reflective conductive material. For example, the third conductive layer (200) may include a highly reflective metal material such as silver (Ag), copper (Cu), or aluminum (Al). The third conductive layer (200) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or it may be formed as a plurality of layers including these. In an exemplary embodiment, the third conductive layer (200) may have a stacked structure such as ITO / silver (Ag) / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO, or may be an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc.

[0200] A second insulating layer (510) may be disposed on a third conductive layer (200). The second insulating layer (510) may be disposed across a display area (DA) and a non-display area (NDA). The second insulating layer (510) may be disposed to cover the third conductive layer (200).

[0201] The second insulating layer (510) can protect the first electrode (210), the second electrode (220), and the fourth heat dissipation pattern (230) while simultaneously insulating them from one another. Additionally, it can prevent the light-emitting element (ED) placed on the second insulating layer (510) from being damaged by direct contact with other components.

[0202] The second insulating layer (510) may be disposed on the third conductive layer (200) and may be disposed to expose at least a portion of the third conductive layer (200). A plurality of contact portions (OP1, OP2, OP3) penetrating the second insulating layer (510) may be formed in the second insulating layer (510). The plurality of contact portions (OP1, OP2, OP3) may be defined by the side walls of the second insulating layer (510). The first contact portion (OP1) may expose one side of the first electrode (210), the second contact portion (OP2) may expose one side of the second electrode (220), and the third contact portion (OP3) may expose one side of the fourth heat dissipation pattern (230).

[0203] A light-emitting element (ED) may be placed on the second insulating layer (510). A light-emitting element (ED) may be placed in the light-emitting region (LA). A light-emitting element (ED) may not be placed in the light-blocking region (BA).

[0204] A light-emitting element (ED) may be positioned between the first electrode (210) and the second electrode (220) in the light-emitting region (LA). As described above, the light-emitting element (ED) has a shape that extends in one direction, and both ends of the light-emitting element (ED) may be aligned to be placed on the first electrode (210) and the second electrode (220), respectively.

[0205] The light-emitting element (ED) can be aligned such that the extension direction of the light-emitting element (ED) is substantially parallel to one side of the substrate (SUB). In the light-emitting element (ED), a first semiconductor layer (31), a device active layer (33), a second semiconductor layer (32), and a device electrode layer (37) can be sequentially formed in a direction parallel to one side of the substrate (SUB) on a cross-section spanning both ends.

[0206] The first insulating layer (520) may be disposed on the second insulating layer (510) on which the light-emitting element (ED) and the light-emitting element (ED) are disposed. The first insulating layer (520) may include a fixed pattern (521) and a fifth heat dissipation pattern (522).

[0207] A fixed pattern (521) may be placed in the light-emitting area (LA). A fixed pattern (521) may be placed on a light-emitting element (ED) in the light-emitting area (LA). A fixed pattern (521) may be placed to expose both ends of the light-emitting element (ED). The fixed pattern (521) may serve to protect the light-emitting element (ED) and, at the same time, to fix the light-emitting element (ED) during the manufacturing process of the display device (10). Although not shown in the drawing, the material forming the fixed pattern (521) may be filled in the empty space between the light-emitting element (ED) and the second insulating layer (510), which is located between the first electrode (210) and the second electrode (220) and formed by being recessed.

[0208] The fifth heat dissipation pattern (522) may be spaced apart from the fixed pattern (521). The fifth heat dissipation pattern (522) may be placed in the first heat dissipation dummy area (DMA1). The fifth heat dissipation pattern (522) may be placed overlapping with the fourth heat dissipation pattern (230) but may not overlap with the third contact part (OP3). The fifth heat dissipation pattern (522) may be formed with a predetermined thickness and placed in the first heat dissipation dummy area (DMA1) located between the non-display area (NDA) and the light-emitting area (LA) to form the first dummy pattern part (DP1). The fifth heat dissipation pattern (522) may serve as a heat dissipation barrier that blocks heat generated outside the non-display area (NDA) and spreading to the light-emitting area (LA) during the cutting process in the manufacturing process of the display device (10).

[0209] The shape of the fixed pattern (521) and the fifth heat dissipation pattern (522) may be the same. The thickness of the fixed pattern (521) and the fifth heat dissipation pattern (522) may be the same. The fixed pattern (521) and the fifth heat dissipation pattern (522) may be made of the same material. The fixed pattern (521) and the fifth heat dissipation pattern (522) may be formed on the same layer. That is, the fixed pattern (521) and the fifth heat dissipation pattern (522) may be formed simultaneously through a single mask process.

[0210] The fifth heat dissipation pattern (522) may be one of a plurality of layers constituting the first dummy pattern section (DP1). The fifth heat dissipation pattern (522) may be the sixth layer (522) of the dummy pattern section (DP1). Hereinafter, the same reference numeral '522' may be referred to as the 'fifth heat dissipation pattern (522)' or the 'sixth layer (522) of the first dummy pattern section (DP1)'.

[0211] The first insulating layer (520) may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0212] The fourth conductive layer (700) may be disposed on the first insulating layer (520). The fourth conductive layer (700) may be located in the display area (DA). The fourth conductive layer (700) may include a contact electrode (700A) and a sixth heat dissipation pattern (730).

[0213] The contact electrode (700A) may be placed in the light-emitting area (LA). The contact electrode (700A) may include a first contact electrode (710) and a second contact electrode (720) spaced apart from each other as described above. The first contact electrode (710) and the second contact electrode (720) may be spaced apart from each other on a fixed pattern (521).

[0214] The first contact electrode (710) can contact one end of the light-emitting element (ED) and the first electrode (210), respectively. The first contact electrode (710) can contact one end of the light-emitting element (ED) exposed by the fixed pattern (521). Additionally, the first contact electrode (710) can contact one surface of the first electrode (210) exposed by the first contact portion (OP1) penetrating the second insulating layer (510). By the first contact electrode (710) contacting one end of the light-emitting element (ED) and the first electrode (210), respectively, the electrical signal applied to the first electrode (210) can be transmitted to one end of the light-emitting element (ED) through the first contact electrode (710).

[0215] The second contact electrode (720) can contact the other end of the light-emitting element (ED) and the second electrode (220), respectively. The second contact electrode (720) can contact the other end of the light-emitting element (ED) exposed by the fixed pattern (521). Additionally, the second contact electrode (720) can contact one side of the second electrode (220) exposed by the second contact portion (OP2) penetrating the second insulating layer (510). By the second contact electrode (720) contacting the other end of the light-emitting element (ED) and the second electrode (220), respectively, the electrical signal applied to the second electrode (220) can be transmitted to the other end of the light-emitting element (ED) through the second contact electrode (720).

[0216] The sixth heat dissipation pattern (730) may be spaced apart from the contact electrode (700A). The sixth heat dissipation pattern (730) may be placed in the first heat dissipation dummy area (DMA1). The sixth heat dissipation pattern (730) may be placed on the fourth heat dissipation pattern (230) and the fifth heat dissipation pattern (521). The sixth heat dissipation pattern (730) may be in direct contact with one side of the fourth heat dissipation pattern (230) exposed by the third contact portion (OP3) penetrating the second insulating layer (510).

[0217] The sixth heat dissipation pattern (730) may be one of a plurality of layers constituting the first dummy pattern section (DP1). The sixth heat dissipation pattern (730) may be the second layer (730) of the first dummy pattern section (DP1) described above with reference to FIGS. 10 and FIGS. 11. Hereinafter, the same reference numeral '730' may be referred to as the 'sixth heat dissipation pattern (730)' or the 'second layer (730) of the first dummy pattern section (DP1)'.

[0218] The first contact electrode (710), the second contact electrode (720), and the sixth heat dissipation pattern (730) may be made of the same material. The first contact electrode (710), the second contact electrode (720), and the sixth heat dissipation pattern (730) may be formed on the same layer. That is, the first contact electrode (710), the second contact electrode (720), and the sixth heat dissipation pattern (730) may be formed simultaneously through a single mask process. As described above, the sixth heat dissipation pattern (730) may be formed with the same pattern as one of the first contact electrode (710) and the second contact electrode (720).

[0219] The fourth conductive layer (700) may include a conductive material. For example, the fourth conductive layer (700) may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the fourth conductive layer (700) may include a transparent conductive material, but is not limited thereto.

[0220] The wavelength control layer (800) may be located in the display area (DA). The wavelength control layer (800) may be placed in the light emission area (LA). As illustrated in the drawing, the light transmission pattern (TPL) may be placed to cover the electrode layer (200A), light-emitting element (ED), fixed pattern (521), and contact electrode (700A) placed in the third light emission area (LA3).

[0221] The first light-blocking member (BM1) may be located in the display area (DA). The first light-blocking member (BM1) may be placed in the light-blocking area (BA). The first light-blocking member (BM1) may be placed to cover the fourth heat dissipation pattern (230), the fifth heat dissipation pattern (522), and the sixth heat dissipation pattern (730) placed in the first heat dissipation dummy area (DMA1).

[0222] The first flattening layer (OC1) may be disposed on the wavelength control layer (800) and the first light-blocking member (BM1). The first flattening layer (OC1) may be disposed in the display area (DA) and the non-display area (NDA).

[0223] A color filter layer (CF) can be placed on the first planarization layer (OC1). A color filter layer (CF) can be placed in the display area (DA).

[0224] The protective layer (OC2) can be placed on the color filter layer (CF). The protective layer (OC2) can be placed in the display area (DA) and the non-display area (NDA).

[0225] In this embodiment, the electrode layer (200A), the fixed pattern (521), and the contact electrode (700A) may be placed in the light-emitting area (LA) to form a pixel pattern. The first dummy pattern section (DP1) may include the first layer (230), the second layer (730), and the sixth layer (522) of the first dummy pattern section (DP1), which are placed in the first heat dissipation dummy area (DMA1) and formed with a pattern shape similar to the pixel pattern. Meanwhile, even though additional patterns are formed in the first heat dissipation dummy area (DMA1), additional masking processes may be unnecessary because the additional patterns have a pattern similar to the pixel pattern and are formed on the same layer as the plurality of layers that constitute the pixel pattern. Therefore, since the first dummy pattern section (DP1) capable of dissipating heat generated during the manufacturing process of the display device (10) described later can be formed without an additional masking process, a decrease in the efficiency of the manufacturing process of the display device (10) can be prevented.

[0226] A first dummy pattern portion (DP1) disposed in a first heat dissipation dummy region (DMA1) may have a stacked structure composed of at least some of the layers (conductive layers) constituting a light-emitting element layer or a circuit element layer. Specifically, the first dummy pattern portion (DP1) may include a plurality of layers composed of at least some of the lower metal layer (110), the first conductive layer (130), the second conductive layer (140) included in the circuit element layer (CCL), and the third conductive layer (200) and the fourth conductive layer (700) included in the light-emitting element layer. For example, the first dummy pattern portion (DP1) may include a first layer (230), a second layer (730), a third layer (DP11), a fourth layer (DP12), and a fifth layer (DP13). At least one layer among the first to fifth layers (230, 730, DP11, DP12, DP13) of the first dummy pattern portion (DP1) may include a metal material. Additionally, the first to fifth layers (230, 730, DP11, DP12, DP13) can be in direct contact with each other through at least one hole. Accordingly, the first dummy pattern portion (DP1) has a laminated structure in which a layer made of a metal material with excellent thermal conductivity is in direct contact through at least one hole, thereby having a heat dissipation path through which heat transferred from the non-display area (NDA) to the light-emitting area (LA) is conducted. Accordingly, the heat transferred to the light-emitting area (LA) is minimized, thereby preventing damage to a plurality of members, such as the wavelength control layer (800), placed in the light-emitting area (LA) by heat.

[0227] The first dummy pattern section (DP1) placed in the first heat dissipation dummy area (DMA1) may further include a sixth layer (522) composed of an insulating layer constituting a light-emitting element layer. The sixth layer (522) of the first dummy pattern section (DP1) may include an insulating material different from the first to fifth layers (230, 730, DP11, DP12, DP13) of the first dummy pattern section (DP1). The sixth layer (522) of the first dummy pattern section (DP1) may be formed with a predetermined thickness between the wavelength control layer (800) located in the light-emitting area (LA) placed at the outermost edge and the non-display area (NDA). The sixth layer (522) of the first dummy pattern section (DP1) may serve as a heat dissipation barrier. Therefore, the diffusion of heat from the non-display area (NDA) to the light-emitting area (LA) can be efficiently blocked by the heat dissipation barrier.

[0228] FIG. 14 is a cross-sectional view showing an example cut along the line III-III' of FIG. 6.

[0229] The display device (10) illustrated in FIG. 14 illustrates a non-display area (NDA) and a display area (DA) adjacent to the non-display area (NDA). Specifically, the display area (DA) in FIG. 14 illustrates a light-emitting area (LA) and a third heat-dissipating dummy area (DMA3) together.

[0230] Referring to FIGS. 10 to 12 and FIG. 14, the third dummy pattern section (DP3) may have a structure in which a plurality of layers are stacked. Specifically, the third dummy pattern section (DP3) may include a third layer (DP31), a fourth layer (DP32), a fifth layer (DP33), a first layer (211, 221), and a second layer (740).

[0231] The lower metal layer (110) may further include a seventh heat dissipation pattern (DP31) disposed in a third heat dissipation dummy area (DMA3). The seventh heat dissipation pattern (DP31) may be one of a plurality of layers constituting the third dummy pattern section (DP3). The seventh heat dissipation pattern (DP31) may be the third layer (DP31) of the third dummy pattern section (DP3).

[0232] The first conductive layer (130) may further include an eighth heat dissipation pattern (DP32) disposed in the third heat dissipation dummy region (DMA3). The eighth heat dissipation pattern (DP32) may be one of a plurality of layers constituting the third dummy pattern section (DP3). The eighth heat dissipation pattern (DP32) may be the fourth layer (DP32) of the third dummy pattern section (DP3).

[0233] The eighth heat dissipation pattern (DP32) may be placed overlappingly with the seventh heat dissipation pattern (DP31). The eighth heat dissipation pattern (DP32) may directly contact one side of the seventh heat dissipation pattern (DP31) through a contact hole (CNT16) penetrating the buffer layer (161) and the gate insulating film (162).

[0234] The second conductive layer (140) may further include a ninth heat dissipation pattern (DP33) disposed in the third heat dissipation dummy region (DMA3). The ninth heat dissipation pattern (DP33) may be one of a plurality of layers constituting the third dummy pattern portion (DP3). The ninth heat dissipation pattern (DP33) may be the fifth layer (DP33) of the third dummy pattern portion (DP3).

[0235] The ninth heat dissipation pattern (DP33) can be placed overlappingly with the eighth heat dissipation pattern (DP32). The ninth heat dissipation pattern (DP33) can directly contact one side of the eighth heat dissipation pattern (DP32) through a contact hole (CNT17) penetrating the interlayer insulating film (163).

[0236] The third conductive layer (200) may further include a tenth heat dissipation pattern (221) disposed in the third heat dissipation dummy region (DMA3). Although not shown in the drawings, the third conductive layer (200) may further include another heat dissipation pattern (211) disposed in the third heat dissipation dummy region (DMA3). The tenth heat dissipation pattern (221) may be one of a plurality of layers constituting the third dummy pattern section (DP3). The tenth heat dissipation pattern (221) may be the second pattern (221) of the first layer (211, 221) of the third dummy pattern section (DP3) described above with reference to FIGS. 10 and FIGS. 11.

[0237] The 10th heat dissipation pattern (221) may be placed overlappingly with the 9th heat dissipation pattern (DP33). The 10th heat dissipation pattern (221) may be in direct contact with one side of the 9th heat dissipation pattern (DP33) through a third dummy electrode contact hole (CTH3) that penetrates the via layer (165) and the passivation layer (164).

[0238] The fourth conductive layer (700) may further include an eleventh heat dissipation pattern (740) disposed in the third heat dissipation dummy region (DMA3). The eleventh heat dissipation pattern (740) may be one of a plurality of layers constituting the third dummy pattern section (DP3). The eleventh heat dissipation pattern (740) may be the second layer (740) of the third dummy pattern section (DP3) described above with reference to FIGS. 10 and FIGS. 11.

[0239] The 11th heat dissipation pattern (740) may be placed overlappingly with the 10th heat dissipation pattern (221). The 11th heat dissipation pattern (740) may be in direct contact with one side of the 10th heat dissipation pattern (221) exposed by the 4th contact portion (OP4) penetrating the 2nd insulation layer (510).

[0240] The third dummy pattern section (DP3) placed in the third heat dissipation dummy area (DMA3) may have a stacked structure composed of at least some of the multiple layers (conductive layers) constituting the light-emitting element layer or circuit element layer, similar to the first dummy pattern section (DP1). Meanwhile, the third dummy pattern section (DP3) may not include a heat dissipation pattern composed of the first insulating layer (520). Even though the third dummy pattern section (DP3) does not include a pattern that acts as a heat dissipation barrier composed of an insulating material, the third dummy pattern section (DP3) may include at least one layer made of a metallic material and have a heat dissipation path conducted through the multiple layers. Accordingly, heat transferred to the light-emitting area (LA) is minimized, thereby preventing damage to multiple members placed in the light-emitting area (LA), such as the wavelength control layer (800), by heat.

[0241] Hereinafter, other embodiments regarding the structure of the display device (10) will be described. In the following embodiments, descriptions of components identical to those in the previously described embodiments will be omitted or simplified, and the differences will be explained in detail.

[0242] Fig. 15 is a cross-sectional view showing another example cut along the line II-II' of Fig. 6.

[0243] Referring to FIG. 15, the display device (10) according to the present embodiment differs from the embodiment of FIG. 13 in that the first insulating layer (520_1) includes a fifth heat dissipation pattern (522_1) and a fixed pattern (521) having different heights from each other.

[0244] Specifically, the first insulating layer (520_1) may include a fixed pattern (521) and a fifth heat dissipation pattern (522_1) placed in a display area (DA). The fixed pattern (521) may be placed in a light-emitting area (LA), and the fifth heat dissipation pattern (522_1) may be placed in a first heat dissipation dummy area (DMA1).

[0245] A fixed pattern (521) may be placed on a light-emitting element (ED) in a light-emitting region (LA). The fixed pattern (521) may be formed on the light-emitting element (ED) with a first thickness (h1). The first thickness (h1) of the fixed pattern (521) may be larger than the diameter of the light-emitting element (ED).

[0246] The fifth heat dissipation pattern (522_1) may be placed between the outermost light-emitting area (LA) and the non-display area (NDA). For example, the fifth heat dissipation pattern (522_1) may be placed in the first heat dissipation dummy area (DMA1).

[0247] The fifth heat dissipation pattern (522_1) may be placed on the first layer (230). The fifth heat dissipation pattern (522_1) may be formed on the first layer (230) with a second thickness (h2). The second thickness (h2) may be greater than the first thickness (h1).

[0248] By forming the thickness (h2) of the fifth heat dissipation pattern (522_1) constituting the first dummy pattern section (DP1) to be greater than the thickness (h1) of the fixed pattern (521), heat generated outside the display area (DA) during the cutting process in the manufacturing process of the display device (10) as described below can be efficiently prevented from spreading to the light-emitting area (LA).

[0249] Specifically, during the cutting process in the manufacturing process of the display device (10), a laser beam can be irradiated onto a cutting area (CTA, see FIG. 24) located around the display area (DA) to be described later to cut. In this case, heat may be generated outside the display area (DA) by the laser beam, and the heat may spread from the cutting area (CTA) to the light-emitting area (LA) of the display area (DA). The fifth heat dissipation pattern (522_1) may be formed with a predetermined thickness (h2) and placed in a first heat dissipation dummy area (DMA1) located between the cutting area (CTA) and the light-emitting area (LA) to form a first dummy pattern section (DP1). That is, the fifth heat dissipation pattern (522_1) can serve as a heat dissipation barrier that prevents the spread of heat from the cutting area (CTA) to the light-emitting area (LA). Therefore, as the thickness (h2) of the fifth heat dissipation pattern (522_1) increases, the heat dissipation barrier becomes higher, so the diffusion of heat from the cutting area (CTA) to the light-emitting area (LA) can be efficiently blocked.

[0250] Accordingly, the display device (10) according to the present embodiment forms the fifth heat dissipation pattern (522_1) thicker than the fixed pattern (521) formed through the same process, so that the fifth heat dissipation pattern (522_1) can more efficiently serve as a barrier (heat dissipation barrier) that blocks heat that can spread from outside the display area (DA) to the light-emitting area (LA). Accordingly, damage to the wavelength control layer (800, light-transmitting pattern (TPL) in the drawing) placed in the light-emitting area by the heat generated during the cutting process can be minimized.

[0251] Figure 16 is a cross-sectional view showing another example cut along the line II-II' of Figure 6.

[0252] Referring to FIG. 16, the display device (10) according to the present embodiment differs from the embodiment of FIG. 13 in that the light-emitting element layer further includes a third insulating layer (400) and the first dummy pattern part (DP1) further includes a seventh layer (430).

[0253] Specifically, the light-emitting element layer may further include a third insulating layer (400) disposed on the via layer (165). The third insulating layer (400) is disposed directly on the upper surface of the via layer (165), and the third conductive layer (200) may be disposed on the third insulating layer (400).

[0254] The third insulating layer (400) may be placed in the display area (DA). The third insulating layer (400) may include the seventh layer (430) of the first bank (BK1) and the first dummy pattern portion (DP1). In an exemplary embodiment, the third insulating layer (400) may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0255] The first bank (BK1) may be placed in the light-emitting area (LA). The first bank (BK1) may be placed in the light-emitting area (LA) to provide a space for the light-emitting element (ED) to be placed, or may serve as a reflective barrier that reflects light emitted from the light-emitting element (ED) in the direction of display.

[0256] The first bank (BK1) may include a plurality of spaced-apart sub-banks. For example, the first bank (BK1) may include a first sub-bank (410) and a second sub-bank (420) spaced apart from each other. The spaced-apart space between the first sub-bank (410) and the second sub-bank (420) may provide a space in which a plurality of light-emitting elements (ED) are arranged.

[0257] Each of the first and second sub-banks (410, 420) may have a structure in which at least a portion protrudes upward (e.g., one side of the third direction (DR3)) relative to the upper surface of the via layer (165). Each of the first and second sub-banks (410, 420) may include an inclined side. By including an inclined side, the first and second sub-banks (410, 420) may serve to change the direction of propagation of light emitted from the light-emitting element (ED) and traveling toward the side of the first bank (BK1) to an upward direction (e.g., display direction). In the drawings, the sides of the first and second sub-banks (410, 420) are shown as being inclined in a linear shape, but are not limited thereto. For example, the sides (or outer surfaces) of the first and second sub-banks (410, 420) may have the shape of a curved semicircle or semi-ellipse.

[0258] The first sub-bank (410) can be overlapped with the first electrode (210) in the light-emitting area (LA) and in the third direction (DR3). The first sub-bank (410) can be overlapped with the first contact electrode (710) and in the third direction (DR3).

[0259] The second sub-bank (420) may be overlapped with the second electrode (220) in the light-emitting area (LA) and in the third direction (DR3). The second sub-bank (420) may be overlapped with the second contact electrode (720) and in the third direction (DR3).

[0260] The seventh layer (430) of the first dummy pattern section (DP1) may be spaced apart from the first bank (BK1). The seventh layer (430) of the first dummy pattern section (DP1) may be placed in the first heat dissipation dummy area (DMA1). The seventh layer (430) of the first dummy pattern section (DP1) may constitute a part of the first dummy pattern section (DP1) in the first heat dissipation dummy area (DMA1).

[0261] The seventh layer (430) of the first dummy pattern section (DP1) may be formed of the same material as the first and second sub-banks (410, 420) of the first bank (BK1). The seventh layer (430) of the first dummy pattern section (DP1) may be formed in the same layer as the first and second sub-banks (410, 420) of the first bank (BK1). Additionally, the shape of the seventh layer (430) of the first dummy pattern section (DP1) may be substantially identical to the respective shapes of the first and second sub-banks (410, 420) of the first bank (BK1). The seventh layer (430) of the first dummy pattern section (DP1) and the first and second sub-banks (410, 420) of the first bank (BK1) may be formed simultaneously through a single process. Since the shape of the 7th layer (430) of the 1st dummy pattern section (DP1) and the 1st and 2nd sub-banks (410, 420) are identical and the 7th layer (430) of the 1st dummy pattern section (DP1) and the 1st and 2nd sub-banks (410, 420) are formed simultaneously through a single process, the 7th layer (430) constituting the 1st dummy pattern section (DP1) can be formed without an additional mask process or design, thereby improving the manufacturing process efficiency of the display device (10).

[0262] The third conductive layer (200) may be placed on the third insulating layer (400). Specifically, the first electrode (210) and the second electrode (220) may be placed on the first bank (BK1), and the first layer (230) of the first dummy pattern portion (DP1) may be placed on the seventh layer (430) of the first dummy pattern portion (DP1).

[0263] The first electrode (210) may be placed on the first sub-bank (410). The first electrode (210) may be placed to cover the upper surface and inclined side of the first sub-bank (410). The second electrode (220) may be placed on the second sub-bank (420). The second electrode (220) may be placed to cover the upper surface and inclined side of the second sub-bank (420). The first layer (230) of the first dummy pattern section (DP1) may be placed on the seventh layer (430) of the first dummy pattern section (DP1). The first layer (230) of the first dummy pattern section (DP1) may be placed to cover the upper surface and inclined side of the seventh layer (430) of the first dummy pattern section (DP1).

[0264] The light-emitting element (ED) can be placed between the first sub-bank (410) and the second sub-bank (420).

[0265] As described above, the first insulating layer (520) may include a fixed pattern (521) disposed in the light-emitting area (LA) and a sixth layer (522) of a first dummy pattern portion (DP1) disposed in the first heat dissipation dummy area (DMA1).

[0266] A fixed pattern (521) can be placed on a light-emitting element (ED). The fixed pattern (521) can be placed between the first sub-bank (410) and the second sub-bank (420) in cross-section. The fixed pattern (521) can be non-overlapping with the first bank (BK1) in the light-emitting region (LA).

[0267] The sixth layer (522) of the first dummy pattern section (DP1) may be placed on the first layer (230) of the first dummy pattern section (DP1) and the seventh layer (430) of the first dummy pattern section (DP1). The sixth layer (522) of the first dummy pattern section (DP1) may overlap with the seventh layer (430) of the first dummy pattern section (DP1) in the first heat dissipation dummy area (DMA1).

[0268] That is, a portion of the third insulating layer (400) placed in the light-emitting area (LA) (e.g., the first bank (BK1)) is not superimposed with the first insulating layer (520) (specifically, the fixed pattern (521)) placed in the light-emitting area (LA), but a portion of the third insulating layer (400) placed in the first heat dissipation dummy area (DMA1) (e.g., the seventh pattern (430)) can be superimposed with the first insulating layer (520) placed in the first heat dissipation dummy area (DMA1) (specifically, the sixth layer (522) of the first dummy pattern portion (DP1)).

[0269] The first and second sub-banks (410, 420) of the first bank (BK1) may overlap with the wavelength control layer (800). The wavelength control layer (800) may be positioned to cover the first and second sub-banks (410, 420) of the first bank (BK1) from above. As illustrated in the drawing, the first and second sub-banks (410, 420) positioned in the third light-emitting region (LA3) may be covered by a light-transmitting pattern (TPL). The first and second sub-banks (410, 420) of the first bank (BK1) may not overlap with the first light-blocking member (BM1) positioned in the light-blocking region (BA).

[0270] The seventh layer (430) of the first dummy pattern section (DP1) may overlap with the first light-blocking member (BM1) placed in the light-blocking area (BA). The first light-blocking member (BM1) may be placed to cover the seventh layer (430) of the first dummy pattern section (DP1) from above.

[0271] In this embodiment, the first dummy pattern section (DP1) may include a third layer (DP11), a fourth layer (DP12), a fifth layer (DP13), a first layer (230), a sixth layer (522), a second layer (730), and a seventh layer (430). That is, the first dummy pattern section (DP1) may further include a seventh layer (430) of the first dummy pattern section (DP1) which has the same shape as the first bank (BK1) placed in the light-emitting area (LA) and is made of the same material. The first dummy pattern section (DP1) further includes a seventh layer (430) of the first dummy pattern section (DP1) protruding upward from the via layer (165), and the first and second layers (230, 730) of the first dummy pattern section (DP1) and the sixth layer (522) of the first dummy pattern section (DP1) are placed on the seventh layer (430) of the first dummy pattern section (DP1), so that the height of the first dummy pattern section (DP1) can be increased by the thickness of the seventh layer (430) of the first dummy pattern section (DP1). Accordingly, the height of the first dummy pattern section (DP1) is increased by the seventh layer (430) of the first dummy pattern section (DP1), so that the first dummy pattern section (DP1) can more efficiently serve as a barrier (heat dissipation barrier) that blocks heat that can spread from outside the display area (DA) to the light-emitting area (LA). Therefore, damage to the wavelength control layer (800, light transmission pattern (TPL) in the drawing) placed in the light-emitting area by the heat generated during the cutting process can be minimized.

[0272] Figure 17 is a cross-sectional view showing another example cut along the line II-II' of Figure 6.

[0273] Referring to FIG. 17, the display device (10) according to the present embodiment differs from the embodiment of FIG. 13 in that the light-emitting element layer further includes a second bank (BK2).

[0274] Specifically, the light-emitting element layer may further include a second bank (BK2) disposed on the second insulating layer (510). The second bank (BK2) may be disposed in a display area (DA). The second bank (BK2) may be disposed between a plurality of subpixels (SPXn) to serve to distinguish them. The second bank (BK2) may perform the function of preventing ink containing the light-emitting element (ED) from overflowing into adjacent pixels or subpixels during an inkjet printing process for aligning the light-emitting element (ED) during the manufacturing process of the display device (10).

[0275] The second bank (BK2) may not be placed in the first heat dissipation dummy area (DMA1) in the light-blocking area (BA). That is, the second bank (BK2) may include an opening that exposes the second insulating layer (510) placed in the light-emitting area (LA) and the first heat dissipation dummy area (DMA1). A plurality of patterns constituting pixels and / or a plurality of patterns constituting the first dummy pattern portion (DP1) may be formed on the second insulating layer (510) exposed by the second bank (BK2).

[0276] FIG. 18 is a cross-sectional view showing another example cut along the line I-I' of FIG. 6.

[0277] Referring to FIG. 18, the display device (10) according to the present embodiment further includes a second light-blocking member (BM2), and the difference from the embodiment of FIG. 9 is that the second light-blocking member (BM2) is placed in a light-blocking area (BA) where a color filter layer (CF) is not placed.

[0278] Specifically, the color filter layer (CF) may be placed in the light-emitting area (LA) and not in the light-blocking area (BA). By placing the color filter layer (CF) in the light-emitting area (LA) and not in the light-blocking area (BA), the color filter layer (CF) may expose the first flattening layer (OC1) placed in the light-blocking area (BA).

[0279] A first color filter (CF1) may be placed in a first light-emitting area (LA1), a second color filter (CF2) may be placed in a second light-emitting area (LA2), and a third color filter (CF3) may be placed in a third light-emitting area (LA3).

[0280] The second light-blocking member (BM2) may be placed on the first flattening layer (OC1) exposed by the color filter layer (CF). The second light-blocking member (BM2) may be placed on the first flattening layer (OC1) along the boundary of the subpixel (SPXn) in the light-blocking area (BA) of the display area (DA). The second light-blocking member (BM2) may be overlapped with the first light-blocking member (BM1) in the thickness direction of the display device (10) (e.g., the third direction (DR3)).

[0281] The second light-blocking member (BM2) can not only block light emission but also suppress external light reflection. The second light-blocking member (BM2) can be formed in a grid shape that surrounds the first to third light emission regions (LA1, LA2, LA3) on a plane.

[0282] The second light-blocking member (BM2) may be formed by including an organic material. In one embodiment, the second light-blocking member (BM2) may include a light-absorbing material that absorbs a visible light wavelength band. As the second light-blocking member (BM2) includes a light-absorbing material and is positioned along the boundary of each subpixel (SPX: SPX1, SPX2, SPX3), the second light-blocking member (BM2) may define the light-emitting region (LA: LA1, LA2, LA3) of each subpixel (SPXn). That is, the second light-blocking member (BM2) may be a subpixel defining film that defines the light-emitting region (LA) and the light-blocking region (BA) of each subpixel (SPXn).

[0283] The second capping layer (CAP2) may be disposed on the color filter layer (CF) and the second light-blocking member (BM2). The second capping layer (CAP2) may be disposed on the color filter layer (CF) and the second light-blocking member (BM2) to cover them. The second capping layer (CAP2) may serve to protect the color filter layer (CF).

[0284] A protective layer (OC2) may be disposed on a second capping layer (CAP2). For example, the protective layer (OC2) may include at least one inorganic film to prevent oxygen or moisture from penetrating. Additionally, the protective layer (OC2) may include at least one organic film to protect the display device (10) from foreign substances such as dust.

[0285] FIG. 19 is a planar layout showing another example of an enlarged region C of FIG. 6. FIG. 20 is a planar view showing a wavelength control layer and a first light-blocking member disposed in a pixel shown in FIG. 19.

[0286] Referring to FIGS. 19 and 20, the display device (10) according to the present embodiment differs from the embodiment of FIGS. 10 and 11 in that the pixel pattern placed in the light-emitting area (LA) of each subpixel (SPXn) and the pattern of the first dummy pattern portion (DP1_1) placed in the first heat dissipation dummy area (DMA) are substantially the same.

[0287] Specifically, the first layer (230_1) of the first dummy pattern portion (DP1_1) disposed in the first heat dissipation dummy area (DMA1_1) may have a pattern substantially identical to the first electrode (210) and the second electrode (220) that are disposed in the light-emitting area (LA) and form a pixel pattern. The first layer (230_1) may contact at least one of a plurality of conductive layers or metal layers of the circuit element layer (CCL) described above through the first dummy electrode contact hole (CTH1_1).

[0288] The first layer (230_1) of the first dummy pattern section (DP1_1) may include a first pattern (231) and a second pattern (232) spaced apart from each other. The first pattern (231) and the second pattern (232) may have a shape extending in a second direction (DR2) from the first heat dissipation dummy area (DMA1_1). The first pattern (231) and the second pattern (232) may be spaced apart from each other in a first direction (DR1).

[0289] The first pattern (231) and the second pattern (232) may each substantially have a pattern with the first electrode (210) and the second electrode (220) placed in the light-emitting region (LA). The first pattern (231) may correspond to the first electrode (210), and the second pattern (232) may correspond to the second electrode (220).

[0290] The first pattern (231) can be in contact with at least one of a plurality of conductive layers or metal layers of the circuit element layer (CCL) through the first sub-dummy electrode contact hole (CTH11). The second pattern (232) can be in contact with at least one of a plurality of conductive layers of the circuit element layer (CCL) through the second sub-dummy electrode contact hole (CTH12).

[0291] The second layer (730_1) of the first dummy pattern section (DP1_1) may have a pattern substantially identical to the first contact electrode (710) and the second contact electrode (720) that are placed in the light-emitting area (LA) and form a pixel pattern. The second layer (730_1) of the first dummy pattern section (DP1_1) may contact the first layer (230_1) through the third contact section (OP3_1).

[0292] The second layer (730_1) of the first dummy pattern section (DP1_1) may include a third pattern (731) and a fourth pattern (732) spaced apart from each other. The third pattern (731) and the fourth pattern (732) may have a shape extending in the second direction (DR2) from the first heat dissipation dummy area (DMA1_1). The third pattern (731) and the fourth pattern (732) may be spaced apart from each other in the first direction (DR1).

[0293] The third pattern (731) and the fourth pattern (732) may each substantially have a pattern with the first contact electrode (710) and the second contact electrode (720) placed in the light-emitting area (LA). The third pattern (731) may correspond to the first contact electrode (710), and the fourth pattern (732) may correspond to the second contact electrode (720).

[0294] The third pattern (731) can contact the first pattern (231) through the first sub-contact part (OP31), and the fourth pattern (732) can contact the second pattern (232) through the second sub-contact part (OP32).

[0295] Since multiple light-emitting elements (ED) are not placed in the light-blocking area (BA), multiple light-emitting elements (ED) may not be placed between the first pattern (231) and the second pattern (232).

[0296] Meanwhile, the first electrode (210), the second electrode (220), the first layer (230_1) of the first dummy pattern section (DP1_1), and the first layer (211, 221) of the third dummy pattern section (DP3_1) can be formed simultaneously through a single mask process. Additionally, the first contact electrode (710), the second contact electrode (720), the second layer (730_1) of the first dummy pattern section (DP1_1), and the second layer (740) of the third dummy pattern section (DP3_1) can be formed simultaneously through a single mask process.

[0297] In the case of the present embodiment, the first electrode (210) and the second electrode (220), which form the pixel pattern of each subpixel, and the first layer (230_1) of the first dummy pattern section (DP1_1) have the same pattern, so additional design for forming the first dummy pattern section (DP1_1) can be omitted. Additionally, the first contact electrode (710) and the second contact electrode (720), which form the pixel pattern of each subpixel, and the second layer (730_1) of the first dummy pattern section (DP1_1) have the same pattern, so additional design for forming the first dummy pattern section (DP1_1) can be omitted.

[0298] In addition, since the pattern constituting the first dummy pattern section (DP1_1) placed in the first heat dissipation dummy area (DMA1) is more numerous than that of the display device (10) shown in FIGS. 10 and 11, the area that can serve as a heat dissipation path can be increased. Accordingly, the heat dissipation area is increased, and the heat dissipation efficiency due to heat generated during the cutting process in the manufacturing process of the display device (10) can be improved.

[0299] The first light-blocking member (BM1) can cover the first pattern (231) and the second pattern (232) constituting the first layer (230_1) of the first dummy pattern part (DP1_1), and the third pattern (731) and the fourth pattern (732) constituting the second layer (730_1) of the first dummy pattern part (DP1_1).

[0300] Below, the cutting process during the manufacturing process of the display device (10) is described.

[0301] FIGS. 21 to 25 are process plan views and cross-sectional views for explaining the cutting process during the manufacturing process of a display device.

[0302] Hereinafter, in the drawings for explaining the manufacturing process of the display device, a fourth direction (DR4), a fifth direction (DR5), and a sixth direction (DR6) are defined. The fourth direction (DR4) and the fifth direction (DR5) may be directions perpendicular to each other within a single plane. The sixth direction (DR6) may be a direction perpendicular to the plane where the fourth direction (DR4) and the fifth direction (DR5) are located. The sixth direction (DR6) is perpendicular to each of the fourth direction (DR4) and the fifth direction (DR5). Hereinafter, the sixth direction (DR6) represents the thickness direction (or display direction) of the display substrate (10').

[0303] FIG. 21 is a plan view showing an example of a display base plate (10'), and FIG. 22 is a cross-sectional view showing an example cut along the line P1-P1' of FIG. 21.

[0304] First, referring to FIGS. 21 and FIGS. 22, a display board (10') is prepared.

[0305] The display board (10') may include a display area (DA) and a cutting area (CTA).

[0306] The display area (DA) of the display base plate (10') may have the same structure as the display area (DA) of the display device (10) described above. Accordingly, the display area (DA) of the display base plate (10') may include a plurality of light-emitting areas (LA) and a light-blocking area (BA) surrounding the light-emitting areas (LA). The display base plate (10') may include a plurality of dummy pattern parts (DP1, DP2, DP3, DP4) disposed between the light-emitting area (LA) and the non-display area (NDA) that are placed at the outermost edge of the display area (DA).

[0307] The cutting area (CTA) may be arranged to surround the display area (DA). The cutting area (CTA) may be an area where a cutting process is performed to cut the outermost edge of the display base plate (10') as described below. The cutting area (CTA) may have a structure generally similar to the non-display area (NDA) of the display device (10) described above, but may be larger than the width of the non-display area (NDA). Multiple conductive layers (130, 140) or metal layers (110) of the circuit element layer (CCL) may not be disposed in the cutting area (CTA). Additionally, multiple conductive layers (200, 700) of the light-emitting element layer may not be disposed in the cutting area (CTA).

[0308] FIG. 23 is a plan view showing cutting lines (CL1, CL2, CL3, CL4) on the display base plate (10') of FIG. 21, and FIG. 24 and FIG. 25 are cross-sectional views showing the cutting process of the display base plate (10').

[0309] Next, referring to FIGS. 23 to 25, a portion of the display base plate (10') is cut using a laser (LAS).

[0310] Specifically, a display device (10) can be manufactured by cutting along a first planned cutting line (CL1) and a second planned cutting line (CL2) extended along the fifth direction (DR5) of the display base plate (10'), and a third planned cutting line (CL3) and a fourth planned cutting line (CL4) extended along the fourth direction (DR4). The first to fourth planned cutting lines (CL1, CL2, CL3, CL4) may be located in a cutting area (CTA).

[0311] A laser (LAS) can be used to irradiate a laser beam (La) onto a cutting area (CTA) of a display base plate (10') to cut a portion of the display base plate (10'). Meanwhile, the substrate (SUB) of the display base plate (10') may include a glass substrate. If the substrate (SUB) includes a glass substrate, the glass substrate can be cut by irradiating it with a high-energy laser beam (La). Accordingly, heat (H) may be generated by the laser beam (La) irradiated to cut the substrate (SUB). The heat (H) may diffuse from the cutting area (CTA) toward the light-emitting area (LA) of the display base plate (10').

[0312] As described above, in order to prevent the boundary area (SA) of the tile-type display device (TD) from being perceived by the user or to minimize the bezel of the display device (10), it is necessary to minimize the width of the non-display area (NDA) of the display device (10). Meanwhile, in the cutting process of cutting the display base plate (10'), when a laser beam (La) is irradiated in the area adjacent to the display area (DA) in the cutting area (CTA) of the display base plate (10') to minimize the width of the non-display area (NDA), the heat (H) generated by the laser beam (La) may be easily transferred (or diffused) toward the light-emitting area (LA). In this embodiment, a heat dissipation path for the heat (H) can be formed by placing a plurality of dummy pattern parts (DP1, DP2, DP3, DP4) in the heat dissipation dummy area (DMA) located between the cutting area (CTA) and the light-emitting area (LA) of the display area (DA).

[0313] Specifically, heat (H) generated by a laser beam (La) irradiated on a cutting area (CTA) can spread from the cutting area (CTA) to a display area (DA). The heat (H) can be transferred to the second layer (730) of the first dummy pattern part (DP1). The heat (H) transferred to the second layer (730) of the first dummy pattern part (DP1) can be conducted from the second layer (730) of the first dummy pattern part (DP1) to the first layer (230) of the first dummy pattern part (DP1) contacted through the third contact part (OP3). The heat (H) transferred to the first layer (230) of the first dummy pattern part (DP1) can be conducted from the first layer (230) of the first dummy pattern part (DP1) to the fifth layer (DP13) of the first dummy pattern part (DP1) contacted through the first dummy electrode contact hole (CTH1). Additionally, heat (H) transferred to the fifth layer (DP13) of the first dummy pattern part (DP1) can be conducted from the fifth layer (DP13) of the first dummy pattern part (DP1) to the fourth layer (DP12) of the first dummy pattern part (DP1) which is contacted through the contact hole (CNT15). Additionally, heat (H) transferred to the fourth layer (DP12) of the first dummy pattern part (DP1) can be conducted from the fourth layer (DP12) of the first dummy pattern part (DP1) to the third layer (DP11) of the first dummy pattern part (DP1) which is contacted through the contact hole (CNT14).

[0314] That is, by having a structure in which a plurality of layers including a metal material that is in direct contact through at least one contact hole are stacked, the heat (H) generated by the laser (LAS) can have a heat dissipation path that is conducted through the plurality of layers of the first dummy pattern part (DP1). For example, the heat (H) transferred to the first dummy pattern part (DP1) can have a path that is conducted from the second layer (730) of the first dummy pattern part (DP1) placed at the top to the third layer (DP11) of the first dummy pattern part (DP1) placed at the bottom. Accordingly, it is possible to prevent damage to a plurality of components placed in the light-emitting area (LA), such as a light-emitting element (ED) and a wavelength control layer (800), by the heat (H).

[0315] The cutting area (CTA) may be divided into a first cutting area (CTA1) and a second cutting area (CTA2) positioned inside the first to fourth cutting lines (CL1, CL2, CL3, CL4). The first cutting area (CTA1) positioned inside the first to fourth cutting lines (CL1, CL2, CL3, CL4) may be an area corresponding to the non-display area (NDA) of the display device (10).

[0316] Meanwhile, the drawing shows that the display base plate (10') includes one display area (DA) and the cutting lines (CL1, CL2, CL3, CL4) are located along the edge of the display base plate (10'), but is not limited thereto. For example, the display base plate includes a plurality of unit substrates corresponding to each display device (10), and in the cutting process of the display base plate, a plurality of display devices (10) may be manufactured by cutting the cutting area between the unit substrates.

[0317] FIGS. 26 and FIGS. 27 are cross-sectional views showing other examples of display boards.

[0318] FIG. 26 is a plan view showing another example of a display base plate (10'_1), and FIG. 27 is a plan view showing cutting lines (CL1, CL2, CL3, CL4) on the display base plate (10'_1) of FIG. 26.

[0319] Referring to FIGS. 26 and 27, the display base plate (10'_1) according to the present embodiment differs from the display base plate (10') of FIGS. 21 and 23 in that it further includes a dummy pixel area (DDM) at the edge.

[0320] Specifically, the display base plate (10'_1) may further include a dummy pixel area (DDM) at the edge. The dummy pixel area (DDM) may be an area where a plurality of dummy pixels (DMP) are placed. The structure of each of the plurality of dummy pixels (DMP) may be substantially the same as the structure of the pixel (PX) placed in the display area (DA). By forming a plurality of dummy pixels (DMP) at the edge of the display base plate (10'_1), the variation in the placement density of a plurality of light-emitting elements (ED) included in the pixel (PX) located in the display area (DA) can be minimized. Specifically, in an inkjet printing process in which a dummy pixel (DMP) is further formed on the outer side of the display area (DA) of the display base plate (10') and a plurality of light-emitting elements (ED) are aligned, ink is first ejected into the dummy pixel (DMP) to align the plurality of light-emitting elements (ED), thereby maintaining a uniform number of light-emitting elements (ED) placed in the display area (DA).

[0321] If the display base plate (10') further includes a dummy pixel region (DDM) in which a dummy pixel (DMP) is formed at the edge, the display device (10) can be manufactured by cutting a cutting region (CTA_1) located between the dummy pixel region (DDM) and the display region (DA) to separate the dummy pixel region (DDM).

[0322] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0323] TD: Tile display 10: Display device 210: First electrode 220: Second electrode 230: The first layer (or fourth heat dissipation pattern) of the first dummy pattern section DA: Display area NDA: Non-displayable English LA: Emission area BA: Shading area DMA: Thermal dummy area DP1: 1st dummy pattern section DP2: 2nd Dummy Pattern Section DP3: Third dummy pattern section DP4: 4th Dummy Pattern Section 710: First contact electrode 720: Second contact electrode 730: The second layer (or sixth heat dissipation pattern) of the first dummy pattern section ED: Light-emitting element

Claims

Claim 1 A display device comprising: a substrate having a defined display area and a non-display area; a circuit element layer disposed on the substrate and including a conductive layer; an electrode layer disposed on the circuit element layer and including a first electrode and a second electrode spaced apart from each other; a light-emitting element disposed between the first electrode and the second electrode; and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer, wherein the display area includes a light-emitting area and a light-shielding area surrounding the light-emitting area, wherein the light-emitting area is located inside the heat dissipation dummy area in the display area, and the dummy pattern portion is disposed in a light-shielding area located between the light-emitting area and the non-display area, and the light-emitting element is disposed between the first electrode and the second electrode in the light-emitting area. Claim 2 In claim 1, the display device wherein the second layer is made of the same material as the electrode layer. Claim 3 A display device according to claim 2, wherein the first layer is disposed on the same layer as the conductive layer, and the second layer is disposed on the same layer as the electrode layer. Claim 4 A display device according to claim 1, wherein at least one of the first layer and the second layer comprises a metal material. Claim 5 In claim 1, the first electrode and the second electrode are each extended along a first direction and spaced apart from each other in a second direction intersecting the first direction, and the second layer is a display device spaced apart from the electrode layer in the second direction. Claim 6 In claim 5, the second layer is a display device having the same planar shape as the first electrode. Claim 7 A display device according to claim 5, wherein the second layer comprises a first pattern and a second pattern spaced apart from each other on the first layer, wherein the first pattern has the same planar shape as the first electrode and the second pattern has the same planar shape as the second electrode. Claim 8 In claim 1, the first electrode and the second electrode are spaced apart from each other in a second direction that extends along a first direction and intersects the first direction, and the second layer is a display device spaced apart from the electrode layer in the first direction. Claim 9 A display device according to claim 8, wherein the second layer comprises a first pattern and a second pattern spaced apart from each other on the first layer, wherein the first pattern is disposed on the extension line of the first electrode in a planar plane and the second pattern is disposed on the extension line of the second electrode in a planar plane. Claim 10 A display device according to claim 1, further comprising: a first contact electrode in contact with one end of the first electrode and the light-emitting element, respectively; and a second contact electrode in contact with the other end of the second electrode and the light-emitting element, respectively, wherein the second layer is made of the same material as any one of the electrode layer, the first contact electrode and the second contact electrode. Claim 11 A display device comprising: a substrate having a defined display area and a non-display area; a circuit element layer disposed on the substrate and including a conductive layer; an electrode layer disposed on the circuit element layer and including a first electrode and a second electrode spaced apart from each other; a light-emitting element disposed between the first electrode and the second electrode; and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer, and further comprises a first contact electrode in contact with one end of the first electrode and the light-emitting element, respectively; and a second contact electrode in contact with the other end of the second electrode and the light-emitting element, respectively, and the dummy pattern portion further comprises a third layer disposed on the second layer, wherein the second layer is made of the same material as the electrode layer, and the third layer is made of the same material as either the first contact electrode or the second contact electrode. Claim 12 A display device according to claim 1, wherein the circuit element layer further comprises a via layer disposed on the conductive layer and the first layer, the electrode layer and the second layer disposed on the via layer, the first electrode contacts the conductive layer through a first contact hole penetrating the via layer, and the second layer contacts the first layer through a second contact hole penetrating the via layer. Claim 13 delete Claim 14 In claim 12, the display device further comprises a wavelength control layer disposed on the light-emitting element in the light-emitting region; and a light-shielding member disposed on the via layer in the light-shielding region, wherein the light-shielding member covers the dummy pattern portion. Claim 15 A display device according to claim 12, further comprising a bank disposed between the via layer and the electrode layer in the light-emitting region, wherein the dummy pattern portion further comprises a third layer disposed between the via layer and the second layer in the heat-dissipating dummy region, and wherein the third layer is made of the same material as the bank. Claim 16 A display device comprising: a substrate having a defined display area and a non-display area; a circuit element layer disposed on the substrate and including a conductive layer; an electrode layer disposed on the circuit element layer and including a first electrode and a second electrode spaced apart from each other; a light-emitting element disposed between the first electrode and the second electrode; and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer, and further comprises a fixed pattern disposed on the light-emitting element to expose both ends of the light-emitting element, and the dummy pattern portion further comprises a third layer disposed on the second layer, wherein the fixed pattern and the third layer are made of the same material. Claim 17 A substrate having a display area including a light-emitting region and a heat dissipation dummy region, and a non-display area defined therein; a semiconductor layer disposed on the substrate and located in the display area; a gate insulating film disposed on the semiconductor layer; a first conductive layer disposed on the gate insulating film, comprising a gate electrode located in the display area; an interlayer insulating film disposed on the first conductive layer; a second conductive layer disposed on the interlayer insulating film, comprising a source electrode and a drain electrode located in the display area, and a first heat dissipation pattern located in the heat dissipation dummy region; a via layer disposed on the second conductive layer and located in the display area; a third conductive layer disposed on the via layer, comprising a first electrode and a second electrode, at least a portion of which are located in the light-emitting region, and a second heat dissipation pattern located in the heat dissipation dummy region; A display device comprising a plurality of light-emitting elements disposed in the light-emitting region, wherein the heat dissipation dummy region is located between the light-emitting region and the non-display region, the first electrode and the second electrode are spaced apart from each other, the plurality of light-emitting elements are disposed between the first electrode and the second electrode, the first electrode is electrically connected to the source electrode through a first contact hole penetrating the via layer, and the second heat dissipation pattern is in direct contact with the first heat dissipation pattern through a second contact hole penetrating the via layer, and the display region includes a light-emitting region and a light-shielding region surrounding the light-emitting region, wherein the light-emitting region is located inside the heat dissipation dummy region in the display region, the first heat dissipation pattern and the second heat dissipation pattern are disposed in the light-shielding region located between the light-emitting region and the non-display region, and the light-emitting element is disposed between the first electrode and the second electrode in the light-emitting region. Claim 18 A tile-type display device comprising a plurality of display devices, wherein each of the plurality of display devices comprises: a substrate in which a display area and a non-display area are defined; a circuit element layer disposed on the substrate and comprising a conductive layer; an electrode layer disposed on the circuit element layer and comprising a first electrode and a second electrode spaced apart from each other; a light-emitting element disposed between the first electrode and the second electrode; and a dummy pattern portion disposed in a heat dissipation dummy area located at the edge of the display area, wherein the dummy pattern portion comprises a first layer made of the same material as the conductive layer of the circuit element layer, and a second layer disposed on the first layer and in contact with at least a portion of the first layer, wherein the display area comprises a light-emitting area and a light-shielding area surrounding the light-emitting area, wherein the light-emitting area is located inside the heat dissipation dummy area in the display area, and the dummy pattern portion is disposed in the light-shielding area located between the light-emitting area and the non-display area, and the light-emitting element is disposed between the first electrode and the second electrode in the light-emitting area. Claim 19 In claim 18, the second layer is a tile-type display device made of the same material as the electrode layer. Claim 20 A tile-type display device according to claim 19, wherein the first layer is disposed on the same layer as the conductive layer, and the second layer is disposed on the same layer as the electrode layer.

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