Method and apparatus for manufacturing a semiconductor device

Abstract

A process of preparing a semiconductor substrate (11) having a first semiconductor part (S1) formed on the upper side of a main board, a process of dividing the first semiconductor part (S1) into a plurality of base semiconductor parts (8) by forming a plurality of trenches (TR) in the first semiconductor part (S1), and a process of forming a compound semiconductor part (9) on the upper side of at least one of the plurality of base semiconductor parts (8) are performed.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] Patent Document 1 discloses a method of performing PEC etching on a device forming layer to separate a semiconductor device. Prior art literature

[0003] Japanese Patent Publication No. 2020-136476

[0004] A method for manufacturing a semiconductor device according to the present disclosure includes a process of preparing a semiconductor substrate having a first semiconductor portion formed on top of a main substrate, a process of dividing the first semiconductor portion into a plurality of base semiconductor portions, and a process of forming a compound semiconductor portion on top of at least one of the plurality of base semiconductor portions. Brief explanation of the drawing

[0005] FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to the present embodiment. FIG. 2 is a plan view showing a method for manufacturing a semiconductor device according to the present embodiment. FIG. 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 1. FIG. 4 is a plan view showing a method for manufacturing a semiconductor device according to Example 1. FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. FIG. 6 is a block diagram showing a manufacturing apparatus for a semiconductor device according to Example 1. Figure 7 is a partial cross-sectional view of the element portion of Example 1. FIG. 8 is a partial plan view of the device part of Example 1. FIG. 9 is a partial cross-sectional view of the element portion of Example 1. FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device of Example 1. FIG. 11 is a cross-sectional view showing an example of the configuration of a template substrate. FIG. 12 is a cross-sectional view showing an example of horizontal growth of the first semiconductor part. FIG. 13 is a plan view showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 14 is a flowchart showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 15 is a plan view showing a method for manufacturing a semiconductor device according to FIG. 14. FIG. 16 is a cross-sectional view showing a method for manufacturing a semiconductor device according to FIG. 14. FIG. 17 is a flowchart showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 18 is a flowchart showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 19 is a flowchart showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 20 is a plan view showing a method for manufacturing a semiconductor device according to FIG. 19. FIG. 21 is a flowchart showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 22 is a plan view showing a method for manufacturing a semiconductor device according to FIG. 21. FIG. 23 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. FIG. 24 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. FIG. 25 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. FIG. 26 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. FIG. 27 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. FIG. 28 is a schematic diagram showing the configuration of an electronic device including the semiconductor device obtained in Example 1. FIG. 29 is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 2. FIG. 30 is a plan view showing a method for manufacturing a semiconductor device according to Example 2. FIG. 31 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 2. FIG. 32 is a block diagram showing a manufacturing apparatus for a semiconductor device of Example 2. FIG. 33a is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 3. FIG. 33b is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 3. FIG. 34 is a plan view showing a method for manufacturing a semiconductor device according to Example 3. FIG. 35 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 3. FIG. 36 is a block diagram showing a manufacturing apparatus for a semiconductor device of Example 3. Specific details for implementing the invention

[0006] FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to the present embodiment. FIG. 2 is a plan view illustrating a method for manufacturing a semiconductor device according to the present embodiment. As shown in FIG. 1 and FIG. 2, the method for manufacturing a semiconductor device according to the present embodiment includes a process of preparing a semiconductor substrate (11) on which a first semiconductor part (S1) is formed on a template substrate (7) including a main board, a process of dividing the first semiconductor part (S1) into a plurality of base semiconductor parts (8), and a process of forming a compound semiconductor part (9) on top of at least one of the plurality of base semiconductor parts (8).

[0007] In conventional methods of etching the device formation layer, there was a risk that the device formation layer would be damaged by the etching. In this embodiment, the first semiconductor part (S1) is divided into a plurality of base semiconductor parts (8) before forming the compound semiconductor part (9). Thus, before forming the active layer of the compound semiconductor part (9), the first semiconductor part (S1) is divided, for example, by forming a trench (TR), and by not performing etching of the device division after the active layer is formed, damage to the active layer can be avoided. By doing so, the quality of the semiconductor device including the compound semiconductor part (9) can be improved.

[0008] A template substrate (7) may have a mask pattern (6) including a main substrate, a mask portion (5), and an opening (K), and a first semiconductor portion (S1) may be formed extending from the opening (K) (a seed portion (3) exposed to the opening (K)) onto the mask portion (5). The first semiconductor portion (S1), the base semiconductor portion (8), and the compound semiconductor portion (9) may include a nitride semiconductor (e.g., a GaN-based semiconductor).

[0009] Specific examples of semiconductor devices include a light emitter (LED chip, semiconductor laser chip, etc.), a light-emitting element in which the light emitter is submounted, and a light-emitting module in which the light-emitting element is packaged, but are not limited to these light-emitting semiconductor devices. For example, a photodetector may be used, and in this case, the same effect as in the case of a light-emitting semiconductor device can be obtained.

[0010] Nitride semiconductors can be represented, for example, as AlxGayInzN (0≤x≤1; 0≤y≤1; 0≤z≤1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor part (8) may be a doped type (e.g., n-type including a donor) or a non-doped type (i-type).

[0011] A first semiconductor part (S1) including a nitride semiconductor can be formed using the ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, the first semiconductor part (S1) is grown in the transverse direction on a template substrate (7) having a mask pattern (6) (selective growth mask pattern). By doing so, even if the main substrate included in the template substrate (7) is a heterogeneous substrate (a substrate with a lattice constant different from that of the first semiconductor part (S1)), a low-defect portion with a low penetration dislocation density can be formed on the mask portion (5). Since the penetration dislocation (dislocation extending in the thickness direction) transferred to the compound semiconductor part (9) on the low-defect portion is reduced, the luminescence efficiency is increased in the case of a light-emitting semiconductor device.

[0012] [Example 1]

[0013] (Method for manufacturing a semiconductor device)

[0014] FIG. 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 1. FIG. 4 is a plan view illustrating a method for manufacturing a semiconductor device according to Example 1. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 1.

[0015] In the method for manufacturing a semiconductor device of Example 1, as shown in FIGS. 3 to 5, the method comprises: a process of preparing a template substrate (7) having a main substrate (1) and a mask pattern (6) including an opening (K) and a mask portion (5); a process of forming a first semiconductor portion (S1) including a nitride semiconductor (e.g., GaN-based semiconductor) over the opening (K) and the mask portion (5); a process of dividing the first semiconductor portion (S1) into a plurality of base semiconductor portions (8) by forming a plurality of trenches (TR) in the first semiconductor portion (S1); a process of forming a compound semiconductor portion (9) including a nitride semiconductor (e.g., GaN-based semiconductor) on each base semiconductor portion (8); a process of forming a first electrode (E1) and a second electrode (E2); and a process of transferring a device portion (device stack) (DS) including the base semiconductor portion (8) and the compound semiconductor portion (9) from the template substrate (7) to a support substrate (SK). The device portion (DS) is transferred to the support substrate (SK) (by holding it on the support substrate (SK)), thereby separating the mask portion (5) of the template substrate (7) and the base semiconductor portion (8). The mask pattern (6) may be a pattern of the mask layer, the first semiconductor portion (S1) may be a first semiconductor layer, the base semiconductor portion (8) may be a base semiconductor layer, and the compound semiconductor portion (9) may be a compound semiconductor layer.

[0016] For example, in conventional methods, if the device formation layer is not completely protected, unintended areas may be etched by the PEC etching etchant, raising concerns about the deterioration of the semiconductor device quality. Additionally, when forming chips with a size of 100 μm or less, such as micro LEDs, device separation was performed by dry etching; however, in small chips as described above, the sides of the dry-etched chips were subjected to physical and chemical damage by the ion atoms of the etchant. When the chip size was about 20 μm or less, the ratio of side damage to the light-emitting area of ​​the chip increased, which sometimes reduced the light-emitting efficiency. There were also cases where side damage to the active layer (e.g., the light-emitting layer of a light-emitting chip, the light-receiving layer of a light-receiving chip) caused a severe decrease in efficiency.

[0017] In Example 1, for example, before forming a compound semiconductor part (9) including an active layer, the first semiconductor part (S1) is divided into a plurality of base semiconductor parts (8), and after forming the active layer, etching damage is avoided by not performing etching of the device division. By doing so, the quality of the semiconductor device including the compound semiconductor part (9) can be improved.

[0018] FIG. 6 is a block diagram showing a semiconductor device manufacturing apparatus according to Example 1. As shown in FIG. 6, the semiconductor device manufacturing method of Example 1 can be realized by a semiconductor device manufacturing apparatus (40) that performs each process. The semiconductor device manufacturing apparatus (40) of Example 1 may include an apparatus (40A) for preparing a template substrate (7), an apparatus (40B) for forming a first semiconductor part (S1), an apparatus (40C) for forming a plurality of trenches (TR) in the first semiconductor part (S1), an apparatus (40D) for forming a compound semiconductor part (9), an apparatus (40E) for forming a first electrode (E1) and a second electrode (E2), an apparatus (40F) for transferring a device part (DS) to a support substrate (SK), and an apparatus (40G) for controlling the apparatus (40A to 40F). For the apparatus (40B) and 40D), an MOCVD apparatus may be used, for example. Device (40B) may be used as device (40D). For example, an etching device may be used for device (40C). For example, a sputtering device may be used for device (40E). Devices (40C and 40E) may include a photolithography device. Device (40G) may include a processor and memory. Device (40G) may be configured to control at least one of devices (40A to 40F) by executing a program stored on, for example, an internal memory, a communicable external device, or an accessible network, and this program, the recording medium in which this program is stored, and the external device, etc. are also included in Example 1.

[0019] In Example 1, the first semiconductor part (S1) is divided into a plurality of base semiconductor parts (8) and then the compound semiconductor part (9) is formed. Accordingly, compared to the form in which the first semiconductor part which is the basis of the base semiconductor part and the second semiconductor part which is the basis of the compound semiconductor part are stacked and then the first and second semiconductor parts are etched (the form in which the side of the second semiconductor part is affected by etching), the condition of the side of the compound semiconductor part (9) can be improved due to the reasons explained above.

[0020] In addition, in Example 1, it is not necessary to perform all trench formations before forming the active layer. Trench formation for chip peeling may be performed after the formation of the compound semiconductor part (9). Meanwhile, trench formation for chip peeling, for example, trench formation for removing the bonding part (neck part) of the base semiconductor part (8), may be performed before forming the active layer.

[0021] As shown in FIGS. 4 and 5, the template substrate (7) has a main substrate (1), a seed portion (3) located on the main substrate (1), and a mask pattern (6) located on the seed portion (3). The mask pattern (6) includes a mask portion (5) and an elongated opening (K). In the template substrate (7), the seed portion (3) is exposed through the opening (K), and a first semiconductor portion (S1) begins crystal growth on the seed portion (3) and combines with the seed portion (3).

[0022] In Example 1, a first semiconductor part (S1) containing a nitride semiconductor is formed in a linear shape extending, for example, in the Y direction using the ELO method. In this case, semiconductor crystals growing in the reverse direction and transverse direction (X direction) on the mask part (5) stop growing before they associate on the mask part (5). Therefore, a gap (GP) is formed between adjacent first semiconductor parts (S1) in the X direction. The X direction is the <11-20> direction (a-axis direction) of the base semiconductor part (8), the Y direction is the <1-100> direction (m-axis direction) of the base semiconductor part (8), and the Z direction is the base semiconductor part (8). <0001> It can be in the direction (c-axis direction).

[0023] In Example 1, a plurality of trenches (TR) may be formed in the first semiconductor part (S1) by etching. At least one of the plurality of trenches (TR) may be extended in the width direction (X direction) of the opening (K). At least one of the plurality of trenches (TR) may be extended in the length direction (Y direction) of the opening (K). The base semiconductor part (8) may be formed into an island shape (not connected to the surroundings) by the plurality of trenches (TR) and gaps (GP) surrounding the base semiconductor part (8).

[0024] The etching of the first semiconductor part (S1) is dry etching, and this dry etching may stop at the mask part (5). In this case, the mask part (5) functions as an etching stopper, and the mask part (5) is exposed at the bottom of the trench (TR). In this case, it is not necessary for the etching to stop at the surface of the mask part (5), but it is acceptable for the etching to stop within the mask part (5). The mask part (5) is formed of a material that is more difficult to etch than the first semiconductor part (S1), and if it can play a role in stopping the etching, a part of the mask part (5) may be etched.

[0025] Each compound semiconductor part (9) may be formed in an island shape corresponding to each base semiconductor part (8). When the base semiconductor part (8) is formed in an island shape by a plurality of trenches (TR) and gaps (GP), the base semiconductor part (8) is surrounded by a mask part (5) when viewed in a planar view (view in the Z direction). Since it is difficult for the nitride semiconductor to be deposited on the mask part (5), which is a selective growth mask, and the compound semiconductor part (9) grows on the upper and side surfaces of the base semiconductor part (8) (which contains the nitride semiconductor), the compound semiconductor part (9) can be formed in an island shape. By doing this, patterning damage can be avoided and the condition of the compound semiconductor part (9) can be improved. In addition, the manufacturing process is simplified.

[0026] In addition, as shown in FIG. 4, if the trench (TR) is formed to extend in the width direction (X direction) of the opening (K), the warping of the wafer can be reduced. This is particularly evident when a heterogeneous substrate having a different coefficient of thermal expansion from that of the base semiconductor part (8) is used on the main substrate (1). Furthermore, the main substrate (1) or the template substrate (7) may be referred to as a wafer, or the template substrate (7) and the semiconductor part above it may be collectively referred to as a wafer. For example, as shown in FIG. 4, adjacent first semiconductor parts (S1) in the X direction are separated by a gap (GP). Therefore, the warping of the wafer in the X direction is small. However, since the first semiconductor part (S1) is formed continuously in the Y direction, longer than the size (width) in the X direction, the warping of the wafer in the Y direction is large. However, by dividing the first semiconductor part (S1) extending in the Y direction by the trench (TR) in the X direction before depositing the active layer, stress is relieved and the warping of the wafer in the Y direction is reduced. Therefore, when depositing the active layer, the wafer warping is reduced, and it is easy to maintain the temperature of the wafer surface uniformly within the plane during deposition. Consequently, the temperature variation of the wafer surface is small, so, for example, when the active layer contains In (indium), the variation in In concentration can be reduced, and the variation in the emission wavelength within the wafer surface can be improved. This effect can be obtained even when the trench (TR) has not reached the lower surface of the base semiconductor part (8) (a state where it stops midway in the depth direction). In this case, while protecting the side of the active layer, the semiconductor chip can be peeled off from the wafer by dry etching the center of the trench (TR) again with a width smaller than the width of the first trench. In this way, the trench (TR) that is formed before the active layer is formed does not need to reach the mask portion (5).

[0027] FIG. 7 is a partial cross-sectional view of the device portion of Example 1. FIG. 8 is a partial plan view of the device portion of Example 1. As shown in FIG. 7, the compound semiconductor portion (9) may include an active portion (active layer) (9K). By dividing the first semiconductor portion (S1) to form the base semiconductor portion (8) before forming the compound semiconductor portion (9), the side condition of the active portion (9K) can be improved. On the base semiconductor portion (8), the n-type portion (9N), the active portion (9K), and the p-type portion (9P) may be formed in this order as the compound semiconductor portion (9). The thickness of the compound semiconductor portion (9) may be less than or equal to half the thickness of the base semiconductor portion (8). The total thickness of the active portion (9K) and the p-type portion (9P) may be less than or equal to half the thickness of the base semiconductor portion (8).

[0028] By making the thickness of the compound semiconductor part (9) less than or equal to half the thickness of the base semiconductor part (8), when the compound semiconductor part (9) is formed on the base semiconductor part (8), it becomes difficult to fill the trench, thereby improving the peeling yield (peeling success rate).

[0029] A ligros layer (e.g., a buffer layer including an n-type GaN-based semiconductor) may be formed on the first semiconductor part (S1), and a plurality of trenches (TR) may be formed on the first semiconductor part (S1) and the ligros layer to form a plurality of base semiconductor parts (8) and a plurality of n-type parts obtained by dividing the ligros layer. In this case, an active part (9K) and a p-type part (9P) may be formed as a compound semiconductor part (9) on the n-type part on the base semiconductor part (8). That is, the trenches (TR) for dividing the first semiconductor part (S1) may be formed before the deposition of the active part (9K), or the n-type part may be deposited on the first semiconductor part (S1) and then the trenches (TR) may be formed.

[0030] The base semiconductor part (8) includes a low-defect part (SD) located above the mask part (5), and the density of the penetrating dislocation (dislocation extending in the Z-axis direction) of the low-defect part (SD) is 5×106 It may be less than / ㎠. The penetration potential density here can be obtained by measuring the Cathode Luminescence (CL) of the wafer surface (e.g., the surface of the base semiconductor part (8) or the compound semiconductor part (9)) (e.g., by counting the number of black spots).

[0031] The penetrating dislocation density of the low-defect portion (SD) may be 1 / 5 or less of the penetrating dislocation density of the dislocation successor portion (HD) located on the opening (K) (on the seed portion (3)). The density of the basal surface dislocation of the low-defect portion (SD) is 5×10 8 / ㎠ It may be as follows. The basal plane dislocation may be a dislocation that extends parallel to the c plane (XY plane) of the base semiconductor part (8). The basal plane dislocation density here is obtained, for example, by dividing the wafer to expose the side of the low defect part (SD) and measuring the dislocation density of this side.

[0032] As shown in FIGS. 7 and 8, the active portion (9K) of the compound semiconductor portion (9) includes a light-emitting portion (LS), and the entire light-emitting portion (LS) may overlap with the low-defect portion (SD) when viewed in a planar view. The size (Ly) of one side of the light-emitting portion (LS) (for example, the side orthogonal to the adjacent trench (TR)) may be 80 μm or less, 40 μm or less, 20 μm or less, 10 μm or less, or 5 μm or less. In Example 1, since etching damage to the compound semiconductor portion (9) (particularly the active portion (9K)) is avoided, the size (Ly) of one side of the light-emitting portion (LS) may be small.

[0033] FIG. 9 is a partial cross-sectional view of the device portion of Example 1. As shown in FIG. 9, in the device portion (DS), the compound semiconductor portion (9) (including the active portion (9K)) may be in contact with at least a portion of the side of the base semiconductor portion (8) (e.g., the side exposed by the trench (TR) and the side facing the gap (GP)).

[0034] The first electrode (E1), which is the anode, may be formed to overlap with the low defect portion (SD) when viewed in a planar view and also to be in contact with the compound semiconductor portion (9) (p-type portion (9P)). If the nitride semiconductor of the base semiconductor portion (8) is n-type, the second electrode (E2), which is the cathode, may be formed to be in contact with the base semiconductor portion (8). The second electrode (E2) may also be formed to be in contact with the n-type portion (9N) of the compound semiconductor portion (9).

[0035] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device of Example 1. A light-emitting body (21) (e.g., an LED chip) can be obtained by peeling off a device part (DS) transferred to a support substrate (SK) from the support substrate (SK). Additionally, a light-emitting device (22) including the light-emitting body (21) and the support (ST) can be obtained by dividing the support substrate (SK). Each of the light-emitting body (21) and the light-emitting device (22) can be referred to as a semiconductor device (20).

[0036] In Example 1, the device portion (DS) is bonded to the template substrate (7) through the opening (K). Therefore, in order to increase the peeling yield, the width of the opening (K) may be reduced to weaken the bonding force. Specifically, the width of the opening (K) may be 8 μm or less, or 4 μm or less.

[0037] (Template board)

[0038] A heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor may be used as the main substrate (1). Examples of heterogeneous substrates include a single-crystal silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate. The plane orientation of the main substrate (1) is, for example, the (111) plane of the silicon substrate, the (0001) plane of the sapphire substrate, and the 6H-SiC (0001) plane of the SiC substrate. These are examples, and any main substrate and plane orientation capable of growing the first semiconductor part (S1) by the ELO method is acceptable. A SiC (bulk crystal) substrate, a GaN (bulk crystal) substrate, or an AlN (bulk crystal) substrate may also be used as the main substrate (1).

[0039] FIG. 11 is a cross-sectional view showing an example of the configuration of a template substrate. The template substrate (7) may be configured such that a seed portion (3) (e.g., AlN) and a mask pattern (6) are formed in this order on a main substrate (1) (e.g., a silicon substrate), or it may be configured such that a multilayer seed portion (3) (e.g., a lower layer including at least one of AlN and SiC and an upper layer including a GaN-based semiconductor) and a mask pattern (6) are formed in this order on a main substrate (1) (e.g., a silicon substrate). The seed portion (3) may be formed locally (e.g., in a stripe shape) so as to overlap with an opening (K) when viewed in a planar view. The seed portion (3) may include a nitride semiconductor formed at a low temperature of 600° or less. By doing so, the bending of the semiconductor substrate (template substrate (7) and device portion (DS)) caused by stress in the seed portion (3) can be reduced. The seed portion (3) may be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). Using a sputtering device enables low-temperature deposition and large-area deposition, and offers advantages such as cost reduction. As shown in FIG. 11, the template substrate (7) may be configured such that a mask pattern (6) is formed on a main substrate (1) (e.g., SiC bulk crystal substrate, GaN bulk crystal substrate).

[0040] The opening (K) of the mask pattern (6) has the function of a growth initiation hole that exposes the seed portion (3) to initiate the growth of the first semiconductor portion (S1), and the mask portion (5) of the mask pattern (6) has the function of a selective growth mask that grows the first semiconductor portion (S1) in the horizontal direction. The area exposed at the opening (K) of the seed portion (3) may be referred to as the seed area, and the mask portion (5) may be referred to as the growth inhibition area or the selective growth area.

[0041] In the mask portion (5), a single layer film comprising, for example, a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (for example, 1000 degrees or higher), or a laminated film comprising at least two of these may be used.

[0042] For example, a silicon oxide film with a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed over the entire surface of the seed portion (3) using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. Then, the resist is patterned using a photolithography method to form a resist having multiple openings in a stripe shape. Then, a portion of the silicon oxide film is removed to form multiple openings (K) using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF), and the resist is removed by organic cleaning to form a mask pattern (6). As another example, a silicon nitride film may be deposited using a sputtering device or a PECVD device. Even if the silicon nitride film is thinner than the silicon oxide film, it can withstand a deposition temperature of about 1000 degrees of the base semiconductor portion (8). The film thickness of the silicon nitride film can be about 5 nm to 4 μm.

[0043] The long shape (slit shape) of the opening (K) can be arranged periodically in the X direction. The width of the opening (K) may be approximately 0.1 μm to 20 μm. The smaller the width of the opening (K), the fewer the number of penetrating potentials propagating from the opening (K) to the first semiconductor part (S1). Additionally, the low defect area (SD) can be made larger.

[0044] Although silicon oxide films may decompose and evaporate in small amounts during the film formation of the first semiconductor part (S1) and be introduced into the first semiconductor part (S1), silicon nitride films and silicon oxynitride films have the advantage of being difficult to decompose and evaporate at high temperatures. Therefore, the mask part (5) may be a single layer of silicon nitride film or silicon oxynitride film, or a stacked film formed by forming a silicon oxide film and a silicon nitride film in this order on the seed part (3), or a stacked film formed by forming a silicon nitride film and a silicon oxide film in this order on the seed part (3), or a stacked film formed by forming a silicon nitride film, a silicon oxide film, and a silicon nitride film in this order on the lower part. In addition, the composition of oxygen and nitrogen of SiON may be controlled to form a desired oxynitride film.

[0045] The abnormal parts, such as pinholes, of the mask portion (5) can be eliminated by performing organic cleaning after film formation and then introducing it back into a film formation device to form a homogeneous film. A high-quality mask portion (5) can also be formed by using a general silicon oxide film (single layer) and utilizing this re-film formation method.

[0046] As an example of a template substrate (7), a silicon substrate having a (111) plane is used on the main substrate (1), an AlN layer (approximately 30 nm to 300 nm, for example 150 nm) is used on the lower part of the seed portion (3), a GaN-based graded layer is used on the upper part of the seed portion (3), and a stacked mask in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) are formed in this order can be used on the mask portion (5). The GaN-based graded layer is the first layer, Al 0.6 Ga 0.4It may include an N layer (e.g., 300 nm) and a second layer, a GaN layer (e.g., 1 to 2 μm). For the mask portion (5), the CVD method (plasma chemical vapor deposition method) may be used for forming the silicon oxide film and the silicon nitride film, respectively, and the thickness of the silicon oxide film may be, for example, 0.3 μm and the thickness of the silicon nitride film may be, for example, 70 nm.

[0047] (1st Semiconductor Division)

[0048] In Example 1, the first semiconductor part (S1) (base semiconductor part (8)) was made of a GaN layer, and an ELO film of gallium nitride (GaN) was formed on the aforementioned template substrate (7) using an MOCVD apparatus. As an example of ELO film formation conditions, substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, and V / III = 6000 (ratio of the supply amount of group V raw material to the supply amount of group III raw material) may be adopted.

[0049] In this case, a first semiconductor part (S1) is selectively grown (longitudinal growth) on a seed part (3) exposed to an opening (K), and then grows transversely on a mask part (5). Then, the transverse growth of the GaN crystal films growing transversely from both sides on the mask part (5) is stopped before they come together.

[0050] The width (size in the X direction) of the mask portion (5) was 50㎛, the width (size in the X direction) of the opening (K) was 5㎛, the horizontal width (size in the X direction) of the first semiconductor portion (S1) was 53㎛, the width (size in the X direction) of the low defect portion (SD) was 24㎛, and the layer thickness (size in the Z direction) of the first semiconductor portion (S1) was 5㎛. The aspect ratio of the first semiconductor portion (S1) was 53㎛ / 5㎛ = 10.6, so a very high aspect ratio was realized. The width of the mask portion (5) can be set according to the specifications of the compound semiconductor portion (9), etc. (for example, about 10㎛ to 200㎛).

[0051] In the formation of the first semiconductor part (S1) in Example 1, a longitudinal growth layer growing in the Z direction (c-axis direction) is formed on the seed part (3) exposed from the opening (K), and then a transverse growth layer growing in the X direction (a-axis direction) is formed. At this time, by making the thickness of the longitudinal growth layer 10 μm or less, 5 μm or less, or 3 μm or less, the thickness of the transverse growth layer can be kept low and the transverse film deposition rate can be increased.

[0052] FIG. 12 is a cross-sectional view illustrating an example of horizontal growth of a first semiconductor part (ELO semiconductor layer). As shown in FIG. 12, it is preferable to form an initial growth layer (SL) on a seed part (3) (GaN layer of the upper part) exposed from an opening (K), and then grow the first semiconductor part (S1) horizontally from the initial growth layer (SL). The initial growth layer (SL) serves as the starting point for horizontal growth of the first semiconductor part (S1). The initial growth layer (SL) can be formed with a thickness of 20 nm to 5000 nm, for example, 50 nm to 400 nm, or 70 nm to 350 nm. By appropriately controlling the ELO film deposition conditions, it is possible to control the growth of the first semiconductor part (S1) in the Z direction (c-axis direction) or in the X direction (a-axis direction).

[0053] Here, the deposition of the initial growth layer (SL) may be stopped at the timing immediately before the edge of the initial growth layer (SL) rises to the upper surface of the mask portion (5) (the stage where it is in contact with the upper side of the mask portion (5)), or immediately after it rises to the upper surface of the mask portion (5) (i.e., at this timing, the ELO deposition condition may be switched from the c-axis direction deposition condition to the a-axis direction deposition condition). By doing so, the initial growth layer (SL) is grown in the transverse direction while slightly protruding from the mask portion (5), thereby suppressing the growth of the first semiconductor portion (S1) in the c-axis direction (thickness direction), allowing the first semiconductor portion (S1) to be grown in the transverse direction at high speed and with high crystallinity, and reducing raw material consumption. By doing this, a low-defect first semiconductor portion (S1) (a crystal of a nitride semiconductor such as GaN) can be formed thinly and widely at low cost. The aspect ratio (ratio of size in the X direction to thickness) of the first semiconductor part (S1) can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more.

[0054] (Compound semiconductor part and electrode)

[0055] The compound semiconductor part (9) can be formed, for example, by the MOCVD method. In the compound semiconductor part (9) of FIG. 7, for example, the n-type part (9N) can be made of an n-GaN layer, the active part (9K) including the light-emitting part (LS) can be made of an MQW (Multi-Quantum Well) including an InGaN layer and a GaN layer, and the p-type part (9P) can be made of a stacked structure of a p-AlGaN layer and a p-GaN layer, so that the device part (DS) can be made of an LED (light-emitting diode). As described above, the n-type part (9N) may be formed from a ligros layer on the first semiconductor part (S1).

[0056] The first electrode (E1) (anode) and the second electrode (E2) (cathode) may have a single-layer or multi-layer structure including at least one of Al, Ag, Cr, Pd, Pt, Au, Ni, Ti, V, W, Cu, Zn, Sn, and In, or may include an alloy layer. At least one of the first and second electrodes (E1·E2) may have a stacked structure of a transparent conductive film (ITO (Indium Tin Oxide), etc.) and a light-reflective metal film (Ag, Al, Ti, etc.).

[0057] (Variation Example)

[0058] FIG. 13 is a plan view showing another example of a method for manufacturing a semiconductor device according to Example 1. As shown in FIG. 13, a first semiconductor part (S1) including a nitride semiconductor may be formed in a planar shape using the ELO method. In this case, during film formation by the ELO method, semiconductor crystals growing in the reverse direction (X direction) on the mask part (5) may be assembled on the mask part (5). Assembly occurs approximately at the center of adjacent openings (K) (the center of the mask part (5)), and a void may be formed immediately below the assembly part. This void is formed inside the first semiconductor part (S1) created by assembly and serves to open up deformation after assembly. Additionally, by forming a plurality of trenches (TR) extending in the X direction and a plurality of trenches (TR) extending in the Y direction with respect to the first semiconductor part (S1), a plurality of island-shaped base semiconductor parts (8) are formed.

[0059] FIG. 14 is a flowchart illustrating another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 15 is a plan view illustrating a method for manufacturing a semiconductor device according to FIG. 14. FIG. 16 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to FIG. 14. As shown in FIG. 14 to FIG. 16, the connection between the first semiconductor part (S1) and the seed part (3) (the part exposed from the opening (K)) may be removed by at least one of the plurality of trenches (TR) formed in the first semiconductor part (S1). In this case, so that the plurality of base semiconductor parts (8) in the shape of islands do not scatter on the template substrate (7), an anchor film (AF) may be formed after forming the plurality of trenches (TR), and then a compound semiconductor part (9) may be formed.

[0060] The anchor film (AF) is in contact with the side of the base semiconductor part (8) and the mask part (5), and holds the base semiconductor part (8) to the template substrate (7). As the anchor film (AF), dielectric films such as silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, aluminum oxide-silicon, aluminum oxynitride, zirconium oxide, titanium oxide, and tantalum oxide can be used. By using silicon oxide, silicon nitride, aluminum oxide-silicon, silicon oxynitride, or titanium nitride as the anchor film (AF), the nitride semiconductor of the compound semiconductor part (9) does not grow on the anchor film (AF), so the compound semiconductor part (9) can be formed in an island shape. When transferring the device part (DS), at least a portion of the anchor film (AF) may remain on the template substrate (7) or may be attached to the device part (DS).

[0061] For example, a resist mask is used to form trenches (TR) by dry etching, and an anchor film (AF) is deposited over the entire surface by sputtering or Electron Beem Deposition (EB). Afterward, the unnecessary portion of the anchor film (AF) can be lifted off by removing the resist mask. By using the anchor film (AF) to secure the chip, it also functions to protect the chip sides (it is known that etching damage occurs on the sides of trenches formed by dry etching) and to recover damage. Since the anchor film (AF) is non-conductive, there is no risk of electrical leakage even if it remains on the chip.

[0062] FIG. 17 is a flowchart illustrating another example of a method for manufacturing a semiconductor device according to Example 1. In FIG. 14, an anchor film (AF) is formed before the formation of the compound semiconductor part (9), but this is not limited thereto. As in FIG. 17, an anchor film (AF) may be formed after the formation of the compound semiconductor part (9).

[0063] FIG. 18 is a flowchart illustrating another example of a method for manufacturing a semiconductor device according to Example 1. In FIG. 14 and FIG. 16, a second electrode is formed on the upper surface of the base semiconductor part (8), but this is not limited thereto. As in FIG. 18, a first electrode (E1) may be formed after the compound semiconductor part (9) is formed, and a second electrode (E2) (cathode) may be formed on the lower surface (back surface) of the base semiconductor part (8) after the device part (DS) is transferred to the support substrate (SK).

[0064] FIG. 19 is a flowchart showing another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 20 is a plan view showing a method for manufacturing a semiconductor device according to FIG. 19. As shown in FIG. 19 to FIG. 20, the mask portion (5) may be removed after the base semiconductor portion (8) is formed. For example, the mask portion (5) may be removed by etching by injecting an etchant into a plurality of trenches (TR). By doing so, the transfer of the device portion (DS) to the support substrate (SK) becomes easier. To increase the peeling (transfer) yield, the width of the opening (K) may be reduced to weaken the bonding force between the base semiconductor portion (8) and the template substrate (7). Specifically, the width of the opening (K) may be 8 μm or less, or 4 μm or less.

[0065] FIG. 21 is a flowchart illustrating another example of a method for manufacturing a semiconductor device according to Example 1. FIG. 22 is a plan view illustrating a method for manufacturing a semiconductor device according to FIG. 21. As shown in FIG. 21 and FIG. 22, after the formation of the compound semiconductor part (9), the base semiconductor part (8), which is a nitride semiconductor crystal, and the compound semiconductor part (9) may be cleaved, for example, on an m-plane ((1-100) plane) (HF) having a normal parallel to the Y direction. When the device part (DS) is a semiconductor laser, two cleavage planes facing each other in the Y direction (m-axis direction) may be formed on the compound semiconductor part (9), and these cleavage planes may be used as resonator end planes. In FIG. 21, cleavage is performed on the m-plane (HF) before transfer to the support substrate (SK) and after cleavage, but this is not limited thereto. Cleaving may also be performed on the support substrate (SK) after transfer.

[0066] In this case, the n-type portion (9N) and the p-type portion (9P) of the compound semiconductor portion (9) may each include a light guide layer and a clad layer with a refractive index greater than that of the active portion (9K), and the p-type portion (9P) may have a ridge (current narrowing portion). Specifically, as the n-type portion (9N), a first contact layer (e.g., an n-type GaN layer), a first clad layer (e.g., an n-type AlGaN layer), and a first light guide layer (e.g., an n-type GaN layer) may be formed. As the active layer (9K), a Multi-Quantum Well (MQW) structure including an InGaN layer may be used. As the p-type portion (9P), an electron blocking layer (e.g., a p-type AlGaN layer), a second light guide layer (e.g., a p-type GaN layer), a second clad layer (e.g., a p-type AlGaN layer), and a second contact layer (e.g., a p-type GaN layer) may be formed. As described above, the n-type portion (9N) may be formed from the ligros layer on the first semiconductor portion (S1).

[0067] (Semiconductor device)

[0068] FIGS. 23 to 27 are perspective views showing the configuration of a semiconductor device obtained in Example 1. By the manufacturing method of FIG. 3, a light-emitting body (LED chip) (21) shown in FIG. 23 or FIG. 24 can be obtained. In FIG. 23, the second electrode (E2) is in contact with the base semiconductor part (8), and in FIG. 24, the second electrode (E2) is in contact with the n-type part (9N) of the compound semiconductor part (9). By the manufacturing method of FIG. 14, a light-emitting body (21) shown in FIG. 25 can be obtained. By the manufacturing method of FIG. 18, a light-emitting body (21) shown in FIG. 26 can be obtained. By the manufacturing method of FIG. 21, a light-emitting body (21) (semiconductor laser chip) shown in FIG. 27 can be obtained. The ridge (RJ) is a current-constricting portion, and laser light is emitted from the cleavage plane (m plane) of the active portion (9K) of the compound semiconductor portion (9). The ridge (RJ) can be formed by dry etching the p-type portion (9P), and there is little risk that this etching will have an adverse effect on the active portion (9K). A light-reflecting film may be formed on the cleavage plane (m plane) of the active portion (9K) of FIG. 27. The light-reflecting film may be formed, for example, from a plurality of dielectric films. Examples of materials for the dielectric films include SiO2, Al2O3, AlN, AlON, SiON, Nb2O5, Ta2O5, ZrO2, etc. In addition, a stacked film containing multiple types of these may be used as a light-reflecting film.

[0069] FIG. 28 is a schematic diagram showing the configuration of an electronic device including a semiconductor device obtained in Example 1. The electronic device (70) of FIG. 28 includes a semiconductor device (20) obtained in Example 1 (e.g., a light emitter (21), a light-emitting element (22)), a driving circuit (50) for driving the semiconductor device (20), and a control circuit (60) for controlling the driving circuit (50). The control circuit (60) includes, for example, a processor and a memory. Examples of the electronic device (70) include a display device, a lighting device, a light receiving device, a communication device, a measuring device, an information processing device, a medical device, an electric vehicle (EV), etc.

[0070] [Example 2]

[0071] FIG. 29 is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 2. FIG. 30 is a plan view illustrating a method for manufacturing a semiconductor device according to Example 2. FIG. 31 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 2.

[0072] In Example 2, as shown in FIGS. 29 to 31, the process comprises: preparing a template substrate (7) including a main substrate (1) and a mask pattern (6) including an opening (K) and a mask portion (5); forming a first semiconductor portion (S1) including a nitride semiconductor (e.g., GaN-based semiconductor) over the opening (K) and the mask portion (5); dividing the first semiconductor portion (S1) into a plurality of base semiconductor portions (8) by cleaving the first semiconductor portion (S1) on the m-plane (8F) of the nitride semiconductor; forming a compound semiconductor portion (9) including a nitride semiconductor (e.g., GaN-based semiconductor) above at least one of the plurality of base semiconductor portions (8); forming a first electrode (E1) and a second electrode (E2); and supporting a device portion (device stack) (DS) including the base semiconductor portion (8) and the compound semiconductor portion (9) from the template substrate (7). A process of transferring to a substrate (SK) is performed. The compound semiconductor part (9) may include an active part (active layer) (9K).

[0073] By performing device division by cleavage, the volume of the first semiconductor part (S1) that is lost is reduced compared to the case where device division is performed by, for example, dry etching, so that the wafer can be effectively utilized (as a device).

[0074] For example, when a heterogeneous substrate (such as a Si substrate) is used on the main substrate (1), warping of the substrate (template substrate (7) and the first semiconductor part (S1)) may occur due to stress resulting from the difference in the coefficient of thermal expansion between the main substrate (1) and the first semiconductor part (S1). If this warping occurs when forming the compound semiconductor part (9), the temperature of the growth surface becomes uneven, and the composition of the compound semiconductor part (9) (for example, the indium concentration of the active part (9K)) becomes uneven within the plane, which may lead to a deterioration in light emission characteristics. By cleaving the first semiconductor part (S1) before forming the compound semiconductor part (9), the stress of the first semiconductor part (S1) is relieved and the warping of the substrate is reduced, thereby improving light emission characteristics (for example, the uniformity of the light emission wavelength within the plane). By scribing the first semiconductor part (S1), the cleaving of the first semiconductor part (S1) may proceed naturally. It may be in the form where the m-plane cleavage of the nitride semiconductor crystal proceeds naturally as internal stress is released. As a compound semiconductor part (9), the n-type part (9N), the active part (9K), and the p-type part (9P) may be formed in this order.

[0075] Since an island-shaped base semiconductor part (8) separated from the surroundings is formed by the cleavage of the first semiconductor part (S1), an island-shaped compound semiconductor part (9) can be formed on the base semiconductor part (8). If the compound semiconductor part (9) does not become an island shape (separated from the surroundings), it is possible to obtain an island-shaped compound semiconductor part (9) by cleaving or patterning the nitride semiconductor crystal that forms the basis of the compound semiconductor part (9) again.

[0076] A ligross layer (e.g., an n-type GaN-based semiconductor) may be formed on the first semiconductor part (S1), and by cleaving the first semiconductor part (S1) and the ligross layer, a plurality of base semiconductor parts (8) and a plurality of n-type parts obtained by dividing the ligross layer may be formed. In this case, an active part (9K) and a p-type part (9P) may be formed as a compound semiconductor part (9) on the n-type part on the base semiconductor part (8).

[0077] FIG. 32 is a block diagram showing a semiconductor device manufacturing apparatus of Example 2. The semiconductor device manufacturing apparatus (40) may include an apparatus (40A) for preparing a template substrate (7), an apparatus (40B) for forming a first semiconductor part (S1), an apparatus (40H) for cleaving the first semiconductor part (S1), an apparatus (40D) for forming a compound semiconductor part (9), an apparatus (40E) for forming a first electrode (E1) and a second electrode (E2), an apparatus (40F) for transferring a device part (DS) to a support substrate (SK), and an apparatus (40G). The apparatus (40G) controls the apparatus (40A, 40B, 40H) and the apparatus (40D to 40F).

[0078] When transferring the device portion (DS) divided on the wafer by cleavage to the support substrate (SK), it may be selectively peeled over multiple device portions, such as two or three intervals. This is possible because the base semiconductor portion (8) on the wafer is divided into small pieces. In addition, when device separation is performed by cleavage, the spacing between adjacent device portions is narrow, but since each device portion is bonded to the template substrate (7) through an opening, it is possible to selectively peel off only the desired device portion.

[0079] In addition, by performing selective transfer of multiple spaced element parts on the support substrate (SK), when the support substrate (SK) is divided into multiple parts (e.g., light-emitting element, light-receiving element) with one chip mounted thereon after transfer to the support substrate (SK), the size of the parts can be increased, and it becomes easy to handle the parts and mount them to a desired package.

[0080] [Example 3]

[0081] FIGS. 33a and FIG. 33b are flowcharts illustrating a method for manufacturing a semiconductor device according to Example 3. FIG. 34 is a plan view illustrating a method for manufacturing a semiconductor device according to Example 3. FIG. 35 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 3.

[0082] In Example 3, as shown in FIG. 33a, a process of preparing a semiconductor substrate (11) having a first semiconductor part (S1) including a nitride semiconductor formed on a template substrate (7), a process of forming a second semiconductor part (S2) on the first semiconductor part (S1), and a process of separating the first and second semiconductor parts (S1 and S2) into a plurality of device parts (DS) by cleaving the first and second semiconductor parts (S1 and S2) may be performed.

[0083] As shown in FIG. 33b, the process comprises preparing a template substrate (7) including a main substrate (1) and a mask pattern (6) including an opening (K) and a mask portion (5); forming a first semiconductor portion (S1) including a nitride semiconductor (e.g., a GaN-based semiconductor) over the opening (K) and the mask portion (5); forming a second semiconductor portion (second semiconductor layer) (S2) including a nitride semiconductor on the first semiconductor portion (S1); forming a first electrode (E1) and a second electrode (E2); separating the first and second semiconductor portions (S1 and S2) into a plurality of device portions (DS) by cleaving the first and second semiconductor portions (S1 and S2) on the m-plane (HF) of the nitride semiconductor; and supporting a device portion (device stack) (DS) including a base semiconductor portion (8) and a compound semiconductor portion (9) from the template substrate (7). A process of transferring to a substrate (SK) is performed. The compound semiconductor part (9) may include an active part (9K).

[0084] The device part (DS) may be an LED or a semiconductor laser. When the device part (DS) is a semiconductor laser, two cleavage planes (HF) facing each other in the Y direction (m-axis direction) are formed in the compound semiconductor part (9), and these cleavage planes (HF) can be used as end planes of the resonator.

[0085] A second semiconductor part (S2) may be formed by interposing a ligross layer (e.g., an n-type GaN-based semiconductor) on a first semiconductor part (S1), and a plurality of device parts (DS) may be formed by cleaving the first semiconductor part (S1), the ligross layer, and the second semiconductor part (S2).

[0086] FIG. 36 is a block diagram showing a semiconductor device manufacturing apparatus of Example 3. The semiconductor device manufacturing apparatus (40) may include an apparatus (40A) for preparing a template substrate (7), an apparatus (40B) for forming a first semiconductor part (S1), an apparatus (40S) for forming a second semiconductor part (S2), an apparatus (40E) for forming a first electrode (E1) and a second electrode (E2), an apparatus (40J) for splitting the first and second semiconductor parts (S1·S2), an apparatus (40F) for transferring a device part (DS) to a support substrate (SK), and an apparatus (40G). The apparatus (40G) controls the apparatus (40A·40B·40S·40E·40J·40F).

[0087] When transferring the device portion (DS) divided on the wafer by cleavage to the support substrate (SK), it may be selectively peeled over multiple device portions, such as two or three intervals. This is possible because the base semiconductor portion (8) on the wafer is divided into small pieces. In addition, when device separation is performed by cleavage, the spacing between adjacent device portions is narrow, but since each device portion is bonded to the template substrate (7) through an opening, it is possible to selectively peel off only the desired device portion.

[0088] In addition, by performing selective transfer of multiple spaced device portions on the support substrate (SK), the size of the portion can be increased when the support substrate (SK) is divided into multiple portions with one chip mounted thereon after transfer to the support substrate (SK), and it becomes easy to handle the portions and mount them to a desired package.

[0089] [Example 4]

[0090] In Examples 1 to 3, the first semiconductor part (S1) may be a GaN layer, but is not limited thereto. The first semiconductor part (S1) in Examples 1 to 3 may be an InGaN layer, which is a GaN-based semiconductor layer. The transverse deposition of the InGaN layer is performed at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases, and it is not effectively introduced into the film. By making the deposition temperature low, the mutual reaction between the mask part (5) and the InGaN layer is reduced. Additionally, the InGaN layer has the effect of having lower reactivity with the mask part (5) than the GaN layer. It is desirable that indium be introduced into the InGaN layer at an In composition level of 1% or more, as this further reduces reactivity with the mask part (5). It is preferable to use triethylgallium (TEG) as the gallium source gas.

[0091] The technical forms described above are for illustrative and illustrative purposes only and are not intended to be limiting. It is clear to those skilled in the art that many variations are possible based on these examples and descriptions. Explanation of the symbols

[0092] 1: Main board 3: Seed section 5: Mask section 6: Mask pattern 7: Template substrate 8: Base semiconductor section 9: Compound semiconductor section 9K: Active section 11: Semiconductor substrate 20: Semiconductor device 21: Light emitter 22: Light-emitting element 40: Manufacturing apparatus for a semiconductor device K: Aperture S1: First semiconductor section S2: Second semiconductor section TR: Trench DS: Device section RJ: Ridge section SD: Low defect section HD: Potential succession section E1: First electrode E2: Second electrode ST: Support SK: Support substrate

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a process of preparing a semiconductor substrate having a template substrate including a main board and a plurality of bar-shaped semiconductor portions including a first semiconductor portion having an elongated shape above the template substrate; a process of dividing the first semiconductor portion into a plurality of base semiconductor portions such that each cross-section follows the width direction; and a process of forming a compound semiconductor portion above at least one of the plurality of base semiconductor portions, wherein the process of dividing the first semiconductor portion is performed before the formation of the compound semiconductor portion. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the first semiconductor part is divided into a plurality of base semiconductor parts by forming one or a plurality of trenches in the first semiconductor part. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the first semiconductor part comprises a GaN-based semiconductor, and the first semiconductor part is separated into a plurality of base semiconductor parts by cleaving at the m-plane of the first semiconductor part. Claim 4 A method for manufacturing a semiconductor device according to claim 2, wherein the plurality of trenches are formed by etching. Claim 5 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the compound semiconductor part comprises an active part. Claim 6 In claim 5, the method for manufacturing a semiconductor device wherein the compound semiconductor part comprises a p-type part above the active part. Claim 7 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the template substrate is disposed above the main substrate and has a mask pattern including a mask portion and an opening, and the first semiconductor portion is formed extending from the opening to the mask portion. Claim 8 A method for manufacturing a semiconductor device according to claim 7, wherein the template substrate includes a seed portion exposed from the opening, and the first semiconductor portion is coupled to the seed portion. Claim 9 A method for manufacturing a semiconductor device according to claim 7, wherein the first semiconductor part is divided into a plurality of base semiconductor parts by forming a plurality of trenches in the first semiconductor part, the opening has an elongated shape, and at least one of the plurality of trenches extends in the width direction of the opening. Claim 10 A method for manufacturing a semiconductor device according to claim 7, wherein the first semiconductor part is divided into a plurality of base semiconductor parts by forming a plurality of trenches in the first semiconductor part, the opening has an elongated shape, and at least one of the plurality of trenches extends in the longitudinal direction of the opening. Claim 11 A method for manufacturing a semiconductor device according to claim 8, wherein the first semiconductor part is divided into a plurality of base semiconductor parts by forming a plurality of trenches in the first semiconductor part, and the coupling part of at least a portion of the first semiconductor part and the seed part is removed by at least one of the plurality of trenches. Claim 12 A method for manufacturing a semiconductor device according to claim 7, wherein, after forming the compound semiconductor portion, a process of separating the plurality of base semiconductor portions and the mask pattern is performed. Claim 13 In claim 7, at least one of the plurality of base semiconductor parts includes a low-defect portion located above the mask portion, and the penetration dislocation density of the low-defect portion is 5×10 6 Method for manufacturing a semiconductor device with a diameter of / ㎠ or less. Claim 14 In claim 7, at least one of the plurality of base semiconductor parts includes a low-defect portion located above the mask portion, and the basal plane dislocation density of the low-defect portion is 5×10 8 Method for manufacturing a semiconductor device with a diameter of / ㎠ or less. Claim 15 A method for manufacturing a semiconductor device according to claim 13, wherein the compound semiconductor part comprises an active part, and the active part comprises a light-emitting part located above the low-defect part. Claim 16 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the thickness of the compound semiconductor part is 1 / 2 or less of the thickness of at least one of the plurality of base semiconductor parts. Claim 17 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor part comprises a nitride semiconductor. Claim 18 A method for manufacturing a semiconductor device according to claim 17, wherein the first semiconductor part is divided into a plurality of base semiconductor parts by forming a plurality of trenches in the first semiconductor part, and at least one of the plurality of trenches extends in the <1-100> direction or the <11-20> direction of the nitride semiconductor. Claim 19 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the compound semiconductor part comprises a GaN-based semiconductor, and the compound semiconductor part is subjected to a process of cleaving the compound semiconductor part at the m-plane of the GaN-based semiconductor. Claim 20 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor part is formed in a linear shape. Claim 21 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor part is formed in a planar shape. Claim 22 A method for manufacturing a semiconductor device according to claim 7, wherein the first semiconductor part is divided into a plurality of base semiconductor parts by forming a plurality of trenches by dry etching in the first semiconductor part, and the dry etching is stopped at the mask part. Claim 23 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the compound semiconductor portion is formed in an island shape corresponding to each base semiconductor portion. Claim 24 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein at least one of the plurality of base semiconductor parts and the compound semiconductor part constitute the device part. Claim 25 A method for manufacturing a semiconductor device according to claim 24, comprising a process of maintaining the above-mentioned device portion on a support substrate. Claim 26 A method for manufacturing a semiconductor device according to claim 13, comprising a process of forming a first electrode that overlaps the low-defect portion when viewed in a plane and also contacts the compound semiconductor portion. Claim 27 A method for manufacturing a semiconductor device according to claim 26, wherein a second electrode is formed to be in contact with one of the plurality of base semiconductor parts. Claim 28 A method for manufacturing a semiconductor device according to claim 27, wherein the first electrode is an anode and the second electrode is a cathode. Claim 29 A method for manufacturing a semiconductor device according to claim 15, wherein the opening has an elongated shape and the light-emitting part has a size of 20 μm or less in the width direction of the opening. Claim 30 A method for manufacturing a semiconductor device according to claim 8, wherein the opening is in the shape of a slit and the seed portion is formed in an elongated shape so as to overlap with the opening. Claim 31 A method for manufacturing a semiconductor device according to claim 12, wherein the mask portion located below at least one of the plurality of base semiconductor portions is removed before forming the compound semiconductor portion. Claim 32 A method for manufacturing a semiconductor device according to claim 7, comprising a process of forming an anchor film in contact with at least one of the plurality of base semiconductor parts and the mask part. Claim 33 A method for manufacturing a semiconductor device in which the anchor film contacts the compound semiconductor portion in accordance with claim 32. Claim 34 A method for manufacturing a semiconductor device according to claim 3, wherein the cleavage of the first semiconductor part proceeds naturally by scribing the first semiconductor part. Claim 35 A method for manufacturing a semiconductor device according to claim 3, wherein the compound semiconductor part comprises a GaN semiconductor, and the compound semiconductor part is subjected to a process of cleaving the m-plane of the GaN-based semiconductor. Claim 36 delete Claim 37 delete Claim 38 A manufacturing apparatus for a semiconductor device that performs each process described in claim 1.

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