Method, device, and program for synchronizing lockstep cores under asynchronous reset conditions

Abstract

An asynchronous reset-based lockstep core synchronization method according to various embodiments of the present invention is disclosed. The method may include the steps of detecting the activation time of each of the primary core and the checker core, obtaining delay time information related to the difference in execution time between the two cores based on the activation time, applying a delay to the output signal of the primary core based on the delay time information, and determining whether there is a malfunction by comparing the output signal of the primary core to which the delay is applied with the output signal of the checker core.

Description

Technology Field

[0001] The present invention relates to a synchronization method for aligning execution between cores in a multi-core system with a lockstep structure to which an asynchronous reset is applied. More specifically, it relates to a lockstep core synchronization method that enables stable output comparison by correcting the difference in execution timing between a primary core and a checker core caused by an asynchronous reset, an apparatus for performing the same, and a program. Background Technology

[0002] Recently, lockstep structures are being widely adopted as a technical means to ensure computational stability and error recovery capabilities in various high-reliability systems.

[0003] The lockstep structure is a structure in which multiple processor cores execute the same instruction simultaneously and determine whether there is an anomaly by comparing the output of each core in real time. It has established itself as an essential error detection mechanism in fields requiring high reliability, such as aerospace, autonomous driving, and industrial control devices.

[0004] In particular, it is designed so that one primary core and one or more checker cores run the same software and compare the output results, enabling immediate error detection and subsequent actions such as system reset in the event of an error. This lockstep method has the advantage of being able to quickly identify errors occurring in a single core.

[0005] However, for this lockstep structure to operate effectively, the execution timing of each core must be fully synchronized, and in particular, the initialization timing after the reset operation must match exactly.

[0006] However, in actual systems, the asynchronous reset method is widely used, and in this case, there may be differences in the timing of when the reset signal is delivered to each core.

[0007] Since asynchronous resets are generally designed to respond immediately to external events or interrupts, there is a problem where the reset release timing of each core varies depending on the hardware structure or path delay differences.

[0008] Such minute differences in reset timing can lead to inconsistencies in execution timing rather than simple initialization time differences in a lockstep environment, and as a result, false detection may occur where the output results of two cores running identically do not match, or the entire system may be unnecessarily reset due to being considered an error in the comparison circuit.

[0009] In particular, in structures where precise comparisons are performed at the clock level, an error can be determined by a difference of only a few clocks, requiring a very sophisticated time-point correction mechanism.

[0010] In addition, with the recent increase in multi-lockstep structures that include multiple checker cores in addition to the primary core, ensuring uniformity in reset and execution timing between each checker core has emerged as an important challenge. In this situation, it is necessary to optimize comparison alignment between various cores rather than a simple comparison with a single reference core, and the need for advanced timing coordination technology to achieve this is growing. Prior art literature

[0011] Republic of Korea Registered Patent Publication No. 10-1610220 The problem to be solved

[0012] The problem that the present invention aims to solve is to provide a core synchronization method, an apparatus for performing the same, and a program that can improve the reliability of malfunction detection within a lockstep structure by effectively correcting execution timing errors caused by a mismatch in initialization timing between a primary core and a checker core in an asynchronous reset environment and precisely aligning the output comparison timing of the two cores in clock units.

[0013] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0014] An asynchronous reset-based lockstep core synchronization method according to an embodiment of the present invention for solving the above-described problem is disclosed. The method may include the steps of detecting the activation time of each of the primary core and the checker core, obtaining delay time information related to the difference in execution time between the two cores based on the activation time, applying a delay to the output signal of the primary core based on the delay time information, and determining whether there is a malfunction by comparing the output signal of the primary core to which the delay is applied with the output signal of the checker core.

[0015] In an alternative embodiment, the step of detecting the activation time of each of the primary core and the checker core may include the step of applying one or more delay circuits to the reset signal path of the checker core so that the reset signal of the checker core is valid after a certain time delay compared to the reset signal of the primary core.

[0016] In an alternative embodiment, the step of acquiring the delay time information includes generating delay time information by measuring the number of clock cycles from the activation time of the primary core until the activation of the checker core through a delay estimation unit comprising a state controller and a counter that detect whether the primary core and the checker core are activated, wherein the state controller is configured to start measuring the counter when the activation of the primary core is detected and stop measuring the counter when the activation of the checker core is detected, and the counter can be controlled by the state controller to store the number of clock cycles corresponding to the difference in execution time.

[0017] In an alternative embodiment, the step of applying a delay to the output signal of the primary core based on the delay time information may be characterized by delaying the output signal of the primary core based on the delay time information to correct it so that the comparison time with the output signal of the checker core matches.

[0018] In an alternative embodiment, the step of applying a delay to the output signal of the primary core based on the delay time information may be characterized by controlling the operation of an output comparison circuit such that a comparison between the output signal of the primary core and the output signal of the checker core is not performed before the delay is applied to the output signal of the primary core.

[0019] In an alternative embodiment, the method may further include the step of determining that there is a synchronization error in the system when the delay time information exceeds a preset threshold, and controlling to block the output comparison operation or re-execute the reset sequence.

[0020] In an alternative embodiment, the method further comprises the steps of calculating reliability information corresponding to the primary core and the checker core based on the delay time information, and switching the roles between the primary core and the checker core when the reliability information is less than a preset threshold value, wherein the reliability information may be information that serves as a criterion for determining whether to switch roles.

[0021] In an alternative embodiment, the checker core is characterized by being provided in a plurality of units, and the method may further include the steps of calculating a core evaluation score suitable for performing a comparison based on at least one of a difference in execution time, a history of past comparison results, or internal state information for each of the plurality of checker cores, and dynamically selecting a reference checker core to be used for performing a comparison with the output of the primary core by comparing the core evaluation scores corresponding to each checker core.

[0022] According to another embodiment of the present invention, an apparatus for performing an asynchronous reset-based lockstep core synchronization method is disclosed. The apparatus includes a memory for storing one or more instructions and a processor for executing one or more instructions stored in the memory, and the processor can perform the asynchronous reset-based lockstep core synchronization method described above by executing one or more instructions.

[0023] According to another embodiment of the present invention, a computer program stored on a computer-readable recording medium is disclosed. The computer program is combined with a computer, which is hardware, to perform an asynchronous reset-based lockstep core synchronization method.

[0024] Other specific details of the present invention are included in the detailed description and drawings. Effects of the invention

[0025] According to one embodiment of the present invention, the inconsistency in the initialization timing between the primary core and the checker core that may occur in an asynchronous reset environment is precisely detected in clock units, and the output comparison timing is corrected by reflecting the difference, thereby effectively improving the output comparison accuracy and the reliability of malfunction detection in a lockstep structure.

[0026] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0027] FIG. 1 is an exemplary diagram schematically illustrating a system for implementing an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention. FIG. 2 is a hardware configuration diagram of a computing device performing an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention. FIG. 3 illustrates a flowchart exemplarily showing an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention. FIG. 4 is an exemplary diagram illustrating a general Lockstep Mode structure related to one embodiment of the present invention. FIG. 5 is a diagram showing the structure of a reset signal path corresponding to each of the primary core and checker core related to one embodiment of the present invention. FIG. 6 is a timing diagram illustrating the difference in reset timing in an asynchronous reset scenario related to one embodiment of the present invention. FIG. 7 shows an exemplary block diagram of the overall system structure related to one embodiment of the present invention. FIG. 8 illustrates a Finite State Machine (FSM) state transition flowchart related to one embodiment of the present invention. FIG. 9 illustrates a flowchart of a delay time estimation operation related to an embodiment of the present invention. Specific details for implementing the invention

[0028] Various embodiments are now described with reference to the drawings. In this specification, various descriptions are provided to facilitate an understanding of the invention. However, it is evident that these embodiments can be practiced without such specific descriptions.

[0029] As used herein, terms such as “component,” “module,” “system,” etc. refer to computer-related entities, hardware, firmware, software, combinations of software and hardware, or executions of software. For example, a component may be a process, processor, object, execution thread, program, and / or computer running on a processor, but is not limited thereto. For example, both an application running on a computing device and the computing device itself may be a component. One or more components may reside within a processor and / or execution thread. A component may be localized within a single computer. A component may be distributed among two or more computers. Additionally, these components may be executed from various computer-readable media having various data structures stored therein. Components may communicate through local and / or remote processes, for example, according to signals having one or more data packets (e.g., data from a component interacting with another component in a local system or distributed system, and / or data transmitted through signals to other systems and networks such as the Internet).

[0030] Furthermore, the term "or" is intended to mean an implicit "or" rather than an exclusive "or." That is, unless otherwise specified or evident from the context, "X uses A or B" is intended to mean one of the natural implicit substitutions. In other words, if X uses A; if X uses B; or if X uses both A and B, "X uses A or B" may apply to any of these cases. Additionally, the term "and / or" as used herein should be understood to refer to and include all possible combinations of one or more of the enumerated related items.

[0031] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that such features and / or components are present. However, the terms “comprising” and / or “comprising” should be understood not to exclude the presence or addition of one or more other features, components and / or groups thereof. Furthermore, unless otherwise specified or clearly evident from the context to indicate a singular form, the singular in this specification and claims should generally be interpreted to mean “one or more.”

[0032] Those skilled in the art should recognize that the various exemplary logical blocks, configurations, modules, circuits, means, logics, and algorithmic steps described in connection with the embodiments disclosed herein may be implemented in electronic hardware, computer software, or a combination of both. To clearly exemplify the interchangeability of hardware and software, various exemplary components, blocks, configurations, means, logics, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the specific application and design constraints imposed on the overall system. Skilled technicians may implement the described functionality in various ways for each specific application. However, such decisions regarding implementation should not be construed as moving out of the scope of the invention.

[0033] The description of the presented embodiments is provided to enable those skilled in the art to use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments without departing from the scope of the present invention. Thus, the present invention is not limited to the embodiments presented herein. The present invention should be interpreted in the broadest possible scope consistent with the principles and novel features presented herein.

[0034] In this specification, the term "computer" refers to any type of hardware device comprising at least one processor, and may be understood to include software configurations operating on said hardware device according to the embodiments. For example, the term "computer" may be understood to include smartphones, tablet PCs, desktops, laptops, and user clients and applications running on each of these devices, but is not limited thereto.

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0036] Each step described in this specification is described as being performed by a computer, but the subject of each step is not limited thereto, and depending on the embodiment, at least some of each step may be performed on different devices.

[0038] FIG. 1 is an exemplary diagram schematically illustrating a system for implementing an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention.

[0039] As illustrated in FIG. 1, a system according to embodiments of the present invention may include a computing device (100), a user terminal (200), an external server (300), and a network (400). The components illustrated in FIG. 1 are exemplary, and additional components may exist or some of the components illustrated in FIG. 1 may be omitted. The computing device (100), the external server (300), and the user terminal (200) according to embodiments of the present invention may mutually transmit and receive data for a system according to embodiments of the present invention through a network (400).

[0040] A network (400) according to embodiments of the present invention can use various wired communication systems such as a Public Switched Telephone Network (PSTN), xDSL (x Digital Subscriber Line), RADSL (Rate Adaptive DSL), MDSL (Multi Rate DSL), VDSL (Very High Speed ​​DSL), UADSL (Universal Asymmetric DSL), HDSL (High Bit Rate DSL), and a Local Area Network (LAN).

[0041] In addition, the network (400) presented here may use various wireless communication systems such as CDMA (Code Division Multi Access), TDMA (Time Division Multi Access), FDMA (Frequency Division Multi Access), OFDMA (Orthogonal Frequency Division Multi Access), SC-FDMA (Single Carrier-FDMA), and other systems.

[0042] A network (400) according to embodiments of the present invention may be configured regardless of the mode of communication, such as wired or wireless, and may be configured as various communication networks, such as a Personal Area Network (PAN) or a Wide Area Network (WAN). Additionally, the network (400) may be a known World Wide Web (WWW) and may utilize wireless transmission technologies used for short-range communication, such as Infrared Data Association (IrDA) or Bluetooth. The technologies described in this specification may be used in other networks as well as the networks mentioned above.

[0043] A computing device (100) (hereinafter referred to as 'computing device (100)') that performs an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention can be applied to a lockstep structure for performing an error detection function in a high-reliability computing environment.

[0044] The lockstep structure utilizes two cores (primary core and checker core) that execute the same instruction simultaneously, and can detect internal errors in real time by comparing the execution results of the two cores. For example, in embedded environments where ensuring safety is critical, such as autonomous driving systems, aviation control systems, or industrial control systems, if one core malfunctions, the error can be detected immediately and protection actions, such as system recovery or shutdown, can be performed.

[0045] The computing device (100) of the present invention can provide a solution to the problem that a lockstep-based comparison operation produces an incorrect result due to a mismatch in execution timing caused by an asynchronous reset.

[0046] According to one embodiment, the computing device (100) can synchronize the execution timing between one or more primary cores and checker cores equipped with a lockstep structure.

[0047] Specifically, the computing device (100) can control the activation time of the checker core to be later than that of the primary core by setting a differential delay in the reset paths of the primary core and the checker core, respectively. This is intended to prevent in advance the problem of the execution start points of the two cores not matching due to a minute difference in the timing of when the reset signal is transmitted, and to block the detection of unnecessary errors that may occur in the subsequent comparison step.

[0048] For example, by connecting multiple delay circuits or flip-flops in series to the reset signal path of a checker core to generate a clock-unit time delay, initial conditions can be set so that the primary core is always activated first. This structure can contribute to improving the synchronization stability of the entire system by consistently securing a reference point when performing lockstep comparisons.

[0049] Subsequently, the computing device (100) can detect when each core is actually activated and calculate delay time information corresponding to the difference in execution time based on the difference in activation time between the two cores. This enables effective response to situations requiring dynamic correction based on actual measurements, as simply designing a reset path cannot accurately reflect the effects of physical clock delay, temperature, power characteristics, etc., in the actual environment.

[0050] For example, the computing device (100) can quantify the execution delay between the two cores in clock units by utilizing a delay estimation unit including a state controller and a counter, starting counter measurement based on the point in time when the primary core is first activated, and stopping counting the moment the checker core is activated. The calculated delay time information can be applied to the primary core output in a subsequent comparison step and used to precisely match the comparison point of the two cores.

[0051] Subsequently, the computing device (100) applies a corresponding delay to the output signal of the primary core based on the estimated delay time information, and by comparing the output signal with the delay reflected and the output signal of the checker core, it can perform more accurate error determination. That is, by correcting the difference in actual execution time, which is difficult to correct with only a simple reset delay setting, in clock units at the output comparison stage, it provides a structure that can increase the accuracy of comparison between the two cores and substantially reduce the false positive rate even in an asynchronous reset environment.

[0052] A detailed description of the asynchronous reset-based lockstep core synchronization method provided by the computing device (100) and the effects caused by it will be described in detail later with reference to FIG. 3.

[0053] In the embodiment, only one computing device (100) in FIG. 1 is illustrated, but it will be obvious to those skilled in the art that more computing devices may also be included within the scope of the invention and that the computing device (100) may include additional components. That is, the computing device (100) may be composed of multiple computing devices. In other words, a set of multiple nodes may constitute the computing device (100).

[0054] According to one embodiment of the present invention, the computing device (100) may be a server that provides cloud computing services. More specifically, the computing device (100) may be a server that provides cloud computing services, which are a type of internet-based computing, where information is processed by another computer connected to the internet rather than the user's computer. Cloud computing services may be services that store data on the internet and allow users to access necessary data or programs anytime and anywhere via internet access without installing them on their own computers, and allow data stored on the internet to be easily shared and transmitted through simple operations and clicks. Furthermore, cloud computing services may not only simply store data on a server on the internet but also allow users to perform desired tasks using the functions of applications provided on the web without installing separate programs, and may be services that allow multiple people to work while sharing documents simultaneously. Additionally, cloud computing services may be implemented in at least one form among IaaS (Infrastructure as a Service), PaaS (Platform as a Service), SaaS (Software as a Service), a virtual machine-based cloud server, and a container-based cloud server. That is, the computing device (100) of the present invention may be implemented in at least one form among the aforementioned cloud computing services. The specific description of the aforementioned cloud computing service is merely an example and may include any platform for establishing the cloud computing environment of the present invention.

[0055] A user terminal (200) according to an embodiment of the present invention may mean any node in a system having a structure capable of communicating with a computing device (100), and may mean a terminal for checking the lockstep-based system operation status or transmitting and receiving setting information.

[0057] The user terminal (200) may be a terminal used by a system manager or operator in, for example, an embedded system, an industrial control system, a vehicle ECU (electronic control unit), or a board test environment. Through this terminal, the user can check the core synchronization status, latency information, comparison results, etc., performed on the computing device (100), or remotely control settings such as a reset reference value and a comparison allowance threshold.

[0058] Additionally, the user terminal (200) can be used to visually check and analyze the activation time, synchronization error, and comparison result history of each core in a test environment, and may include a function to collect diagnostic logs when an error occurs or to manually or automatically adjust delay correction parameters.

[0059] As another example, the user terminal (200) can perform the function of dynamically changing the core to be the reference comparison target in a system including multiple checker cores, or collecting and analyzing the evaluation scores of each core to adjust the comparison priority. Through this, high-reliability comparison coordination and malfunction detection are possible even in a system in real-time operation.

[0060] The configuration of such a user terminal (200) can contribute to improving the stability and reliability of the entire system by providing a flexible system environment that assists and monitors the operation of the computing device (100) and can directly intervene in the synchronization control flow when necessary.

[0061] In an embodiment, the user terminal (200) is equipped with a display to receive input from the user and provide output of any form to the user.

[0062] A user terminal (200) may refer to any form of entity(s) in a system having a mechanism for communicating with a computing device (100). For example, such a user terminal (200) may include a PC (personal computer), a notebook, a mobile terminal, a smartphone, a tablet PC, and a wearable device, and may include any type of terminal capable of connecting to a wired or wireless network. Additionally, the user terminal (200) may include any server implemented by at least one of an agent, an API (Application Programming Interface), and a plug-in. Additionally, the user terminal (200) may include an application source and / or a client application.

[0063] In one embodiment, an external server (300) may be connected to a computing device (100) through a network (400) and may provide various configuration information, system operation logs, and analysis data required for the computing device (100) to perform an asynchronous reset-based lockstep core synchronization method, or receive, store, and manage delay information, comparison results, error history, etc. generated according to the operation of the computing device (100).

[0064] For example, the external server (300) may be a control server or a storage server installed independently outside the computing device (100), and may perform the role of providing initialization parameters when the system boots, or periodically updating reference information such as synchronization thresholds and comparison timing correction values.

[0065] In various embodiments, the external server (300) may operate as a central control node that calculates a comparison policy or correction parameter optimized for each system based on comparison history and delay pattern data collected from multiple lockstep systems, and provides this to the computing device (100). Through this configuration, the comparison reliability of individual systems can be increased, while error diagnosis and maintenance at the overall system level can be performed more effectively.

[0066] Additionally, the external server (300) may include benchmark reference data for verifying the delay estimation operation and comparison accuracy of the computing device (100) during the system development or verification phase, and may also include a function to collect analysis results regarding delay occurrence conditions, comparison failure conditions, etc. during system testing and provide them in the form of a visualized report.

[0067] The external server (300) is a device including computing resources to perform these functions, and may be implemented as, for example, a laptop, desktop, server computer, test board, or cloud-based virtual server, but is not limited to the aforementioned forms.

[0069] FIG. 2 is a hardware configuration diagram of a computing device performing an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention.

[0070] Referring to FIG. 2, a computing device (100) performing an asynchronous reset-based lockstep core synchronization method according to one embodiment of the present invention may include one or more processors (110), a memory (120) for loading a computer program (151) executed by the processor (110), a bus (130), a communication interface (140), and a storage (150) for storing the computer program (151). Here, FIG. 2 only illustrates components related to the embodiment of the present invention. Therefore, a person skilled in the art to which the present invention pertains will understand that other general-purpose components may be included in addition to the components illustrated in FIG. 2.

[0071] According to one embodiment of the present invention, the processor (110) can typically handle the overall operation of the computing device (100). The processor (110) can provide or process appropriate information or functions to a user or user terminal by processing signals, data, information, etc. that are input or output through the components described above, or by running an application program stored in memory (120).

[0072] Additionally, the processor (110) can perform operations for at least one application or program for executing the method according to embodiments of the present invention, and the computing device (100) may have one or more processors.

[0073] According to one embodiment of the present invention, the processor (110) may be composed of one or more cores and may include a processor for data analysis and deep learning, such as a central processing unit (CPU), a general purpose graphics processing unit (GPGPU), and a tensor processing unit (TPU) of a computing device.

[0074] In particular, in this embodiment, the processor (110) may be configured to be integrated inside a Microcontroller Unit (MCU), and the MCU may include a plurality of cores having a lockstep structure, such as a primary core and one or more checker cores. The processor (110) manages the execution time and output information of each core to detect execution timing errors that may occur in an asynchronous reset environment and performs the role of correcting them according to the method of the present invention.

[0075] This processor (110) can, for example, provide a reset signal to each core, detect the actual activation time of the primary and checker cores, calculate delay time information through a delay estimation unit or delay control circuit included therein, and control output comparison operations. By doing so, it can contribute to reducing comparison errors caused by differences in execution timing and increasing the stability and reliability of the lockstep structure.

[0076] Additionally, the processor (110) can perform each step of the asynchronous reset-based core synchronization method of the present invention through a computer program (151) stored in memory (120), and can integrally process a series of processes such as detecting the execution time, calculating the delay time, correcting the output delay, and comparison control. Comparison results between multiple cores and diagnostic logs, etc., can be transmitted to an external server (300) or a user terminal (200) through a communication interface (140).

[0077] In various embodiments, the processor (110) may further include RAM (Random Access Memory) and ROM (Read-Only Memory) for temporarily and / or permanently storing signals (or data) processed within the processor (110). Additionally, the processor (110) may be implemented in the form of a system-on-chip (SoC) comprising at least one of a graphics processing unit, RAM, and ROM.

[0078] Memory (120) stores various data, instructions and / or information. Memory (120) may load a computer program (151) from storage (150) to execute a method / operation according to various embodiments of the present invention. When the computer program (151) is loaded into memory (120), the processor (110) may perform the method / operation by executing one or more instructions constituting the computer program (151). Memory (120) may be implemented as a volatile memory such as RAM, but the technical scope of the present disclosure is not limited thereto.

[0079] The bus (130) provides communication functions between components of the computing device (100). The bus (130) can be implemented as various types of buses, such as an address bus, a data bus, and a control bus.

[0080] The communication interface (140) supports wired and wireless internet communication of the computing device (100). Additionally, the communication interface (140) may support various communication methods other than internet communication. To this end, the communication interface (140) may be configured to include a communication module well known in the art of the present invention. In some embodiments, the communication interface (140) may be omitted.

[0081] Storage (150) can store a computer program (151) non-temporarily. When performing an asynchronous reset-based lockstep core synchronization process through a computing device (100), storage (150) can store various information necessary to provide the asynchronous reset-based lockstep core synchronization process.

[0082] The storage (150) may be configured to include non-volatile memory such as ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, a hard disk, a removable disk, or any form of computer-readable recording medium well known in the art to which the present invention belongs.

[0083] A computer program (151) may include one or more instructions that cause a processor (110) to perform a method / operation according to various embodiments of the present invention when loaded into memory (120). That is, the processor (110) may perform the method / operation according to various embodiments of the present invention by executing the one or more instructions.

[0084] In one embodiment, the computer program (151) may include one or more instructions for performing an asynchronous reset-based lockstep core synchronization method, the steps of detecting the activation time of each primary core and checker core, obtaining delay time information related to the difference in execution time between the two cores based on the activation time, applying a delay to the output signal of the primary core based on the delay time information, and determining whether there is a malfunction by comparing the output signal of the primary core with the delay applied and the output signal of the checker core.

[0085] The steps of the method or algorithm described in connection with embodiments of the present invention may be implemented directly in hardware, implemented as a software module executed by hardware, or implemented by a combination thereof. The software module may reside in RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash Memory, a hard disk, a removable disk, a CD-ROM, or any form of computer-readable recording medium well known in the art to which the present invention belongs.

[0086] The components of the present invention may be implemented as a program (or application) and stored on a medium to be executed in combination with a computer, which is hardware. The components of the present invention may be implemented as software programming or software elements, and similarly, embodiments may be implemented in programming or scripting languages ​​such as C, C++, Java, assembler, etc., including various algorithms implemented as combinations of data structures, processes, routines, or other programming configurations. Functional aspects may be implemented as algorithms executed on one or more processors.

[0088] FIG. 3 illustrates a flowchart exemplarily showing an asynchronous reset-based lockstep core synchronization method related to one embodiment of the present invention.

[0089] The steps illustrated in FIG. 3 may be changed in order as needed, and at least one step may be omitted or added. The steps of FIG. 3 are merely one embodiment of the present invention, and the scope of the present invention is not limited thereto.

[0090] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may include a step (S100) of detecting the activation time of each of the primary core and the checker core.

[0091] In an embodiment, the primary core is a core that performs a standard operation of the system, performs computation or control functions based on instructions input from the outside, and may be a core that serves as a reference when compared with a checker core. The primary core is utilized as a standard for the timing of system operation and provides a reference time for comparison timing correction.

[0092] Additionally, the checker core is an auxiliary core configured to execute the same instructions as the primary core, and generates a reference output to determine whether there is a malfunction by comparing it with the execution result of the primary core. According to an embodiment, the checker core may include a delay element to activate after a certain period of time compared to the primary core, thereby intentionally causing a difference in the initialization time.

[0093] Meanwhile, Figure 4 is an example illustrating the execution timing discrepancy that may occur when an asynchronous reset is applied in a typical Dual-core Lockstep structure. In a typical Dual-core Lockstep structure, the Primary Core and the Checker Core must execute in a fully synchronized state based on the same instructions and input data. At this time, the two cores share the same clock, and execution is considered normal operation only when they start in the same initialization state.

[0094] Meanwhile, in environments where asynchronous reset is applied, there may be slight differences in the timing at which the reset signal is delivered to each core. More specifically, even if the reset signal is applied simultaneously from the outside, there may be differences in how the reset synchronization circuits within each core receive and process the reset signal. For example, in one core, the reset signal is synchronized immediately at the rising edge of the clock, whereas in another core, the same signal may become effective only after one or two clock cycles. These differences may be caused by flip-flop delays, wiring delays, or differences in the reset signal propagation path within each core.

[0095] The characteristics of such asynchronous resets consequently make the reset release timing of each core non-uniform, which may result in the initialization timings of the primary core and the checker core being set differently.

[0096] Timing mismatches cause subtle differences in the execution timing of each core, and if the Lockstep comparison timings do not align precisely, it may be perceived as a malfunction even when there are no actual issues. In particular, when output comparisons are performed on a clock basis, unsynchronized execution timings can lead to different comparison results, which can result in unnecessary system resets or error handling.

[0097] For example, if an error is incorrectly detected due to such a discrepancy in a vehicle MCU or avionics system that requires real-time control, a situation may occur where a system that is actually operating normally is forcibly restarted or shut down urgently. This can cause unexpected response delays or output interruptions in safety-critical systems such as braking systems or flight control logic, and consequently, seriously impair the safety and reliability of the system.

[0098] As such, since even comparison errors caused by simple timing mismatches can lead to catastrophic subsequent failures in high-reliability systems, accurate synchronization of execution time is a critical technical challenge in Lockstep architectures.

[0099] In an embodiment, the computing device (100) of the present invention may include a configuration for detecting the actual activation time of each of the primary core and the checker core to perform synchronization of the execution time between the cores. According to an embodiment, the computing device (100) includes a state controller (Finite State Machine, FSM) capable of monitoring the operating state of each core after the reset release and a counter circuit (i.e., a counter), thereby enabling the moment when each core is actually activated to be measured in clock units.

[0100] According to one embodiment of the present invention, a computing device (100) may be configured to artificially separate the activation times of two cores in order to clearly identify the difference in execution time between a primary core and a checker core. Specifically, the primary core is set to be activated immediately after normal reset release, whereas the checker core may be configured to be activated after a certain time later than the primary core by inserting one or more delay circuits on the same reset signal path. Such a structure can more clearly induce a difference in activation timing according to the reset release time, thereby enabling more precise measurement and correction of delay time performed in subsequent steps.

[0101] In a specific embodiment, the step of detecting the activation time of each of the primary core and the checker core may include the step of applying one or more delay circuits to the reset signal path of the checker core so that the reset signal of the checker core is valid after a certain time delay compared to the reset signal of the primary core.

[0102] FIG. 5 is a diagram illustrating an example of a reset synchronization circuit corresponding to each of the primary core and the checker core according to one embodiment of the present invention.

[0103] FIG. 5(a) shows a typical reset synchronization circuit applied to a primary core. As illustrated, an asynchronous reset signal applied from the outside is synchronized through two D flip-flops to generate an output reset signal. At this time, the two flip-flops are connected in series to convert the reset signal into a stable signal synchronized with the clock, and the signal is then input to the primary core, thereby configuring the circuit so that the primary core can be quickly activated.

[0104] On the other hand, FIG. 5(b) illustrates a modified example of a reset synchronization circuit applied to a checker core, characterized by the inclusion of an additional delay circuit in addition to the basic structure identical to that of the primary core. More specifically, multiple additional D flip-flops are inserted in series after two synchronization flip-flops, and this part is indicated by a red dotted box in the drawing. The added flip-flop series exists on the transmission path of an external reset signal and performs the role of delaying the validation of the reset signal in clock units.

[0105] According to this delay circuit configuration, even if the same reset input is applied to the primary core and the checker core simultaneously, the checker core is activated after a certain time later than the primary core, and the completion time of initialization between the two cores is intentionally separated.

[0106] FIG. 6 is a timing diagram showing the reset timing applied to each of the primary core and the checker core in an asynchronous reset environment according to one embodiment of the present invention.

[0107] Referring to FIG. 6, the same external reset input (Reset(Input)) is applied to both the primary core and the checker core, but the reset release timing differs depending on the internal reset synchronization circuit (Synchronizer) of each core. In particular, logic to add a delay time is inserted into the reset synchronization circuit of the checker core, so that the reset can be implemented in a structure where it is released at a relatively delayed time compared to the primary core.

[0108] In other words, the checker core is designed to delay reset release by a certain number of clock cycles after the reset input, ensuring that the primary core's reset release always occurs first. This structure guarantees a consistent initialization order between the two cores, which is advantageous for clearly establishing reference timing for subsequent delay time measurement and correction processes.

[0109] Since this structural delay generates a clearly defined delay in the unit of clock cycles rather than arbitrary disturbances or random electrical noise, it is suitable for use as a reference point in the subsequent delay time measurement step. Therefore, in this invention, it serves as a prerequisite for clearly inducing a difference in execution time between the primary core and the checker core, and for precisely correcting synchronization based on said difference.

[0110] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may include a step (S200) of obtaining delay time information related to the difference in execution time between two cores based on the activation time.

[0111] In an embodiment, the step of acquiring delay time information may include generating delay time information by measuring the number of clock cycles from the activation time of the primary core until the activation of the checker core through a delay estimation unit comprising a state controller and a counter that detect whether the primary core and the checker core are activated.

[0112] Here, the delay estimator is a component that detects the point at which computation actually begins after each core is released from reset, and by quantifying the difference in clock units, converts minute discrepancies in execution timing between two cores into measurable information. The delay estimator may consist, for example, of a state controller (FSM) and a measurement counter, and these components may be implemented by hardware logic circuits within the computing device or by control routines at the firmware level.

[0113] Additionally, the state controller can be configured to start measuring the counter when the activation status of the primary core is detected, and to stop measuring the counter when the activation status of the checker core is detected. The state controller can be designed in an FSM manner and configured to sequentially detect the state transitions of each core immediately after the reset is released.

[0114] The counter operates under the control of the state controller and can store the number of clocks corresponding to the difference in execution times by accumulating and recording the number of clock pulses from the time the primary core is activated until the checker core is activated. The clocks measured in this way can be utilized as delay time information for subsequent alignment of output comparison times and synchronization correction.

[0115] Latency information is data that quantifies the actual difference in execution timing between the primary core and the checker core, and can be used as a quantitative standard to align the timing of subsequent output signal comparisons.

[0116] For example, if the delay time measured by the delay estimation unit is calculated as 4 clocks, the computing device can correct the timing of comparison with the output signal of the checker core by applying a delay of 4 clocks corresponding to the delay value to the output delay circuit located on the output path of the primary core.

[0117] As a specific example, the primary core starts operations at the 10th clock after the reset is released, and the checker core starts operations at the 14th clock depending on the delay circuit and internal structural characteristics on the reset path. In this case, the delay estimation unit detects a 4-clock difference between the two cores, stores the information as delay time information, and then transmits it to the output comparison circuit to apply the delay only to the output signal of the primary core.

[0118] As a result, since the output comparison of the two cores can be performed at the same reference point, errors in detecting malfunction caused by simple reset timing differences can be effectively prevented, and the false positive rate in a high-reliability lockstep system can be significantly reduced.

[0119] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may include a step (S300) of applying a delay to an output signal of a primary core based on delay time information.

[0120] In one embodiment, the step of applying a delay to the output signal of the primary core based on delay time information may be characterized by delaying the output signal of the primary core based on the delay time information to correct it so that the comparison time with the output signal of the checker core matches.

[0121] More specifically, the delay applied to the output signal can be implemented through one or more delay circuits having a clock delay period set according to the delay time information calculated in the previous step (S200). For example, the output signal can be delayed in clock units through a flip-flop, shift register, or clock delay line (buffer delay line), etc., connected in series to the output line of the primary core.

[0122] This delay circuit acts as a structure to prevent false error detection that may occur when comparison timing is mismatched, and has the effect of synchronizing the output of the primary core with the execution timing of the checker core.

[0123] In addition, according to one embodiment, the step of applying a delay to the output signal of the primary core based on delay time information may be characterized by controlling the operation of an output comparison circuit so that a comparison between the output signal of the primary core and the output signal of the checker core is not performed before the delay is applied to the output signal of the primary core.

[0124] This configuration may be intended to prevent subsequent error handling, such as the detection of unnecessary malfunctions or system resets, that may occur when the comparison circuit compares outputs while the execution timing between the two cores is not synchronized.

[0125] Specifically, the operation capability of the comparison circuit is determined based on internal control signals or FSM control states, and the comparison operation may be kept inactive until the application of a delay is confirmed. As a result, the comparison circuit performs a valid comparison operation only after all output signals are aligned to a normal state.

[0126] For example, if the delay time information is calculated as 5 clocks, a 5-clock delay is applied to the output path of the primary core, and the comparison circuit may block the comparison signal input or remain in an output-ignoring state until the delay is completed. As a result, the comparison circuit determines the output only when the checker core and the primary core are fully synchronized in time, and the comparison accuracy can be maximized.

[0127] In other words, the comparison control structure of the present invention is not a passive method that simply applies delays, but can be an active method that simultaneously secures the precision and stability of system synchronization by linking the application of delays with the execution of comparisons.

[0129] FIG. 7 shows an exemplary block diagram of the overall system structure related to one embodiment of the present invention. FIG. 8 shows a Finite State Machine (FSM) state transition flowchart related to one embodiment of the present invention. FIG. 9 shows a flowchart of a delay time estimation operation related to one embodiment of the present invention.

[0130] Summarizing the present invention with reference to FIG. 7, the structure is configured such that a common input signal is simultaneously transmitted to both the Primary Core and the Checker Core. However, the input signal passes through a separate delay block before being transmitted to the Checker Core, thereby causing the Checker Core to start operation at a relatively later point than the Primary Core. Here, the delay block may include, for example, one or more registers or delay circuits, and may be implemented as a logic circuit for delaying the transmission time of the input signal by a predetermined clock cycle. This configuration provides a foundation for more precise timing analysis and correction in the subsequent delay estimation and output comparison steps by artificially and clearly inducing a minute difference in the start time of operation after reset release between each core in an asynchronous reset environment. This configuration is intended to clearly induce a minute difference in initialization timing in an asynchronous reset environment, thereby providing a foundation for performing the subsequent delay estimation and output comparison steps more accurately.

[0131] The output of each core is generated independently, and the output of the primary core is delayed through an additional delay block before being transmitted to the Output Comparator. The Output Comparator determines whether the two outputs are synchronized and can generate an error signal if they do not match. The Delay Estimator measures the difference in execution timing between the primary core and the checker core in clock units, and the measured information can be utilized to control the output delay and comparison operation of the primary core.

[0132] In addition, FIG. 8 shows the state transition flow of a state controller (or FSM) of a delay estimation unit related to one embodiment of the present invention, and shows the sequence of control operations for measuring delay time information based on the activation time of each of the primary core and the checker core.

[0133] The FSM consists of a total of three states (S0, S1, S2), and state S0 is the initialization state immediately after the system reset, at which point the counter used for delay measurement is initialized to 0. Subsequently, when the activation status of the primary core is detected, the FSM transitions to state S1, and the counter increases by 1 every clock cycle from this point onward.

[0134] State S1 is a waiting period for the activation of the checker core and is a key state for measuring the delay period until the checker core is activated. When the activation of the checker core is detected, the FSM transitions to state S2, and the counter's measurement operation stops. At this time, the stored counter value is determined as delay time information representing the difference in execution timing between the primary core and the checker core in clock units, and this is passed to the subsequent delay block.

[0135] The delay block applies a predetermined clock delay to the primary core's output signal based on the corresponding counter value transmitted from the FSM, thereby correcting the timing of the comparison with the checker core's output to ensure they exactly coincide. This FSM-based control flow enhances the reliability of delay estimation and correction operations and provides a foundation for effectively preventing comparison errors that may occur in an asynchronous reset environment.

[0136] Referring to FIG. 9, the operation procedure of the delay estimation unit consists of a series of flows that detect the activation time of each of the primary core and the checker core after the reset is released, measure the delay between them, and calculate delay time information.

[0137] First, when the reset signal is released, an initialization step is performed to start the delay estimation operation, and the measurement counter is initialized to 0. Subsequently, the system detects whether the primary core is active, and if the primary core is active, it starts measuring the counter. On the other hand, if the primary core is not yet active, it maintains that state and waits for an activation event.

[0138] Once the activation of the primary core is confirmed, the activation status of the checker core is detected next, and the value of the delay time counter is incremented every clock cycle until the checker core is activated. When the checker core is activated, the measurement is terminated, and the accumulated counter value is confirmed and stored as delay time information. This completes the delay estimation procedure, and the confirmed delay time information can subsequently be utilized for adjusting the primary core output delay and for synchronization correction of the comparison circuit.

[0139] In summary, the delay estimation unit of the present invention according to FIGS. 8 and 9 measures the difference in execution timing between the primary core and the checker core in clock units, and is implemented as a synchronization-based control structure to precisely align the timing of output comparison using the result.

[0140] The FSM-based state control flow (Fig. 8) clearly distinguishes the start and end times of the measurement through a state transition process (S0 → S1 → S2) based on the activation event of each core, thereby preventing excessive accumulation or omission of delay information. This can be an important control mechanism that significantly improves the accuracy and reliability of delay measurements.

[0141] Meanwhile, the flowchart-based procedural flow (Fig. 9) shows the logical flow of the state transitions of the FSM in a procedural manner, facilitating application in firmware or hardware state control blocks during actual implementation. In particular, by controlling the flow from reset release to core activation sequentially or conditionally, it is possible to prevent comparisons from being performed while the system is in an unstable state and to completely block false positives or error triggers caused by comparisons between unaligned outputs.

[0142] That is, the delay estimation unit of the present invention is a structure that can be implemented concisely and precisely at the hardware or firmware level, and can be configured to ensure comparison consistency between lockstep cores even in an asynchronous reset environment, which can prevent malfunctions in high-reliability systems and improve error detection accuracy.

[0143] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may further include a step of determining that there is a synchronization error in the system when delay time information exceeds a preset threshold, and controlling to block an output comparison operation or to re-execute a reset sequence.

[0144] To explain in more detail, as described above, the reset release times of the primary core and the checker core may not be the same, and the difference in activation times resulting therefrom is measured as delay time information in clock units through a delay estimation unit. In one embodiment of the present invention, a delay circuit is intentionally configured so that the checker core is activated after a certain number of clocks (e.g., 3 clocks) after the primary core, and a value obtained by adding a system tolerance to the reference delay value designed in this way may be set as a threshold value.

[0145] In other words, if the delay time information exceeds the corresponding threshold, it is determined that the delay is outside the normal range, and the system can be controlled by temporarily blocking output comparison or automatically re-executing the entire reset sequence.

[0146] For example, if the checker core is configured to be delayed by 3 clocks by design and the system tolerance is considered to be ±1 clock, the threshold is set to a total of 4 clocks. In this case, if the primary core is activated at the 5th clock after the reset is released and the checker core is activated at the 13th clock, the difference in execution time between the two cores corresponds to 8 clocks, so this can be considered to exceed the threshold. Accordingly, the computing device (100) can recognize the situation as a synchronization error, stop the operation of the output comparison block, and control the entire reset sequence to be re-executed if necessary.

[0147] Unlike existing lockstep structures that simply compare execution results, this configuration is designed to distinguish between intentional delays allowed by design and exceptional abnormal delays, providing a defensive structure that can simultaneously ensure reliable comparison and system stability. In particular, by preventing false positives and meaningless reset repetitions, it serves as a technical foundation suitable for lockstep synchronization structures in high-reliability environments.

[0148] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may include a step (S400) of determining whether there is a malfunction by comparing the output signal of a primary core with a delay applied and the output signal of a checker core.

[0149] In this case, the output signal of the primary core, whose output timing has been corrected based on the previously mentioned delay information, is compared while synchronized with the actual execution time of the checker core; thus, the possibility of false positives caused by errors in the comparison timing can be substantially reduced. Output comparison can be performed, for example, by an XOR gate-based comparator, a hardware comparison block, or an internal comparison algorithm, and if an output mismatch between the two cores is detected, it is considered a system error, and subsequent processing (e.g., setting an error flag, requesting a reset, etc.) can be performed.

[0150] This comparison step is responsible for the result consistency check, which is the core of the lockstep structure. In particular, since the output of the primary core is dynamically corrected before the comparison is performed in this invention, there is an advantage of preventing system performance degradation or malfunction reset caused by unnecessary error detection.

[0151] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may further include the step of calculating reliability information corresponding to a primary core and a checker core based on delay time information, and the step of switching the roles between the primary core and the checker core when the reliability information is less than a preset threshold value.

[0152] Here, reliability information may serve as a criterion for determining whether to switch roles. Reliability information can be used as an indicator to determine whether each core is operating stably in a lockstep environment, and can be used as a criterion value to determine whether to switch roles subsequently.

[0153] Specifically, reliability information does not rely on one-time delay measurement results, but can be calculated cumulatively based on delay time information repeatedly collected from a certain number of operation sessions. For example, the system obtains delay time information by measuring the difference in execution time between the primary core and the checker core during each operation, and if the delay time measured for each session exceeds a preset reference time value (e.g., 4 clocks), that session can be considered 'abnormal'. Then, by cumulatively counting the number of sessions determined to be abnormal, if a certain threshold (e.g., exceeding it 5 or more times out of a total of 10 times) is exceeded, the reliability of the corresponding core can be determined to be low.

[0154] This accumulation-based judgment method prevents misidentifying transient delay anomalies caused by temporary power noise, clock jitter, or transient errors as a decrease in reliability, and can provide more stable statistical-based judgment criteria. For example, if a pattern is observed where a checker core exceeds a reference delay time in 6 out of the last 10 lockstep operations, it can be determined that the checker core is likely to have a problem with its internal synchronization circuit or reset processing path, or is in an unstable state.

[0155] Based on the results of this judgment, the computing device (100) can improve the lockstep comparison stability of the entire system by switching the roles between the current primary core and the checker core. That is, the configuration can be changed by designating the existing checker core as a new primary core and switching the primary core to an auxiliary role, thereby using a more reliable core as the comparison standard, which can improve the accuracy of the comparison result and the overall error response performance of the system.

[0156] This configuration is distinct from existing lockstep systems that simply perform comparisons between cores. Its technical significance lies in the fact that it allows the system to evolve into an active and autonomous manner that diagnoses operational stability in real time based on repeated comparison results and delay patterns, and automatically realigns the core structure when necessary. In particular, in systems containing multiple cores, if the reliability of some cores decreases, this can serve as a highly effective countermeasure for maintaining the overall comparison quality and malfunction detection accuracy of the system.

[0157] According to one embodiment of the present invention, checker cores configured to execute the same instruction set as the primary core may be provided in multiple numbers, not limited to one.

[0158] For example, two or more checker cores may be configured in parallel for a single primary core, and each of these checker cores may be configured in a structure that performs operations independently based on the same input and then compares the result with the output of the primary core.

[0159] In this case, the computing device (100) can perform more precise error detection and diagnosis by comparing the output generated from each of the multiple checker cores with the output of the primary core. In addition, since mutual comparison between checker cores is also possible, it is possible to perform malfunction analysis and pattern determination based on multiple comparisons, going beyond a simple comparison based on the primary core.

[0160] Furthermore, additional configurations may be considered to automatically select a core with high execution stability among multiple checker cores, or to prioritize diagnosing or disabling a specific checker core if it repeatedly experiences delays or abnormal outputs. Through this, the system can enhance the reliability of lockstep comparison while flexibly performing error detection and recovery functions within an extended multi-core structure.

[0161] According to one embodiment of the present invention, an asynchronous reset-based lockstep core synchronization method may further include, for each of a plurality of checker cores, a core evaluation score suitable for performing a comparison based on at least one of a difference in execution time, a history of past comparison results, or internal state information, and a step of dynamically selecting a reference checker core to be used for performing a comparison with the output of a primary core by comparing the core evaluation scores corresponding to each checker core.

[0162] To explain in more detail, if the system has a structure containing multiple checker cores, each checker core executes the same instructions as the primary core based on the same input; however, the actual execution stability or precision of time alignment may differ from core to core. For example, some checker cores may have excessively long reset delay times or poor output consistency, while others may consistently demonstrate stable delay times and output consistency.

[0163] In the embodiment, a core evaluation score can be calculated based on information regarding the difference in execution timing between the primary core and the checker core. For example, if the activation time of a specific checker core is maintained consistently at an average of 2 clocks or less compared to the primary core, the core is judged to have excellent time alignment precision and may be assigned a high evaluation score. On the other hand, if the difference in execution timing shows a large deviation each time or frequently exceeds a preset allowable threshold (e.g., 5 clocks), the reliability in terms of time alignment is judged to be low and may be assigned a relatively low score.

[0164] In addition, in the embodiment, a core evaluation score can be calculated based on the history of past output comparison results of the checker core. For example, if 9 or more of the last 10 comparison sessions are determined to have a normal output match, the computational reliability of the checker core is considered high, and it may be prioritized for evaluation as a core suitable for performing comparisons. Conversely, a checker core that has experienced 3 or more discrepancies under the same conditions may have a low score because instability in the computational process is suspected.

[0165] In another embodiment, a core evaluation score can be calculated based on the internal state information of the checker core. For example, if a clock boundary anomaly, a metastability warning, or a decrease in thermal stability based on a temperature sensor is detected within the checker core during recent operation, the evaluation score may be lowered because there is a risk in terms of long-term stability, even if the output is normal in the short term. On the other hand, a core whose internal state consistently maintains a normal range is judged to have high comparative stability and may be assigned a relatively high score.

[0166] The core evaluation score calculated in this way can be used as an indicator that numerically represents the suitability of each checker core for comparison performance, and the computing device (100) can dynamically select the most reliable checker core at that time as the reference checker core by comparing the evaluation scores corresponding to each of the multiple checker cores.

[0167] The selected reference checker core is subsequently designated as the primary comparison target for comparison with the output of the primary core, and the comparison results are directly utilized for malfunction detection and system error determination, which are the core of the lockstep structure. In addition, the reference checker core can be re-evaluated at regular intervals, and the system can be configured so that the comparison target can be dynamically changed according to changes in the evaluation score even during real-time operation.

[0168] For example, initially, Checker Core B is designated as the reference Checker Core because it is the best in terms of time alignment and comparison history; however, if comparison errors continuously occur or internal status anomalies are detected thereafter, the system can maintain overall comparison reliability by switching the reference to Checker Core C, which has a higher evaluation score.

[0169] Unlike static fixed structures, this dynamic reference core selection method can flexibly respond to real-time state changes in the system. It improves the accuracy of error detection while reducing dependency on specific checker cores, thereby contributing to increased fault tolerance of the entire system. This can be particularly usefully applied in embedded systems, automotive MCUs, and aerospace systems where availability and high reliability are critical.

[0170] According to another embodiment of the present invention, when the system includes a plurality of checker cores, a function to configure delayed alignment information based on the difference in execution time between each core and to optimize comparison timing using the delayed alignment information may be additionally performed.

[0171] Specifically, the computing device (100) can measure the difference in execution time in clock units for each of the primary core and the plurality of checker cores, and use this measurement value to generate a Delay Matrix or a Delay Map. The Delay Matrix is ​​a data structure that quantitatively arranges delay time information corresponding to each checker core, and can substantially serve as a numerical standard for expressing the relative time difference with respect to the primary core.

[0172] For example, if the system includes a total of three checker cores, checker core A, checker core B, and checker core C, the computing device can independently measure the difference in execution time between the primary core and each checker core. More specifically, by measuring the number of clock cycles from the activation time of the primary core to the time when each checker core is actually activated, it can be measured that checker core A is activated with a delay of 3 clocks compared to the primary core, checker core B has a delay of 5 clocks, and checker core C has a delay of 2 clocks.

[0173] The latency information for each checker core measured in this manner can be stored and managed within the system in the form of an alignment matrix, and is subsequently utilized in the process of correcting the comparison point or selecting reference checker cores. Going beyond simple time records, the alignment matrix can function as key reference data for the system to optimize alignment at the time of comparison and ensure output consistency.

[0174] This configuration can solve the problem of optimizing delay alignment between multiple checker cores, which was not considered in conventional single-checker core-based lockstep systems, thereby maximizing the accuracy of output comparison and error detection performance across the system. In particular, it can improve the precision of delay correction and structural flexibility in a multi-lockstep environment where parallel comparisons are performed with multiple checker cores based on a single primary core.

[0176] The components of the present invention may be implemented as a program (or application) and stored on a medium to be executed in combination with a computer, which is hardware. The components of the present invention may be implemented as software programming or software elements, and similarly, embodiments may be implemented in programming or scripting languages ​​such as C, C++, Java, assembler, etc., including various algorithms implemented as combinations of data structures, processes, routines, or other programming configurations. Functional aspects may be implemented as algorithms executed on one or more processors.

[0177] Those skilled in the art will understand that the various exemplary logic blocks, modules, processors, means, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented by electronic hardware, various forms of programs or design code (referred to herein as “software”), or a combination of all such. To clearly illustrate this interoperability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been generally described above in relation to their functions. Whether such functions are implemented as hardware or software depends on the design constraints imposed on the specific application and the overall system. Those skilled in the art may implement the functions described in various ways for each specific application, but such implementation decisions should not be interpreted as being outside the scope of the invention.

[0178] The various embodiments presented herein may be implemented as methods, devices, or articles of manufacture using standard programming and / or engineering techniques. The term “article of manufacture” includes a computer program, carrier, or medium accessible from any computer-readable device. For example, computer-readable media include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, etc.), optical discs (e.g., CDs, DVDs, etc.), smart cards, and flash memory devices (e.g., EEPROMs, cards, sticks, key drives, etc.). Additionally, the various storage media presented herein include one or more devices and / or other machine-readable media for storing information. The term “machine-readable media” includes, but is not limited to, wireless channels and various other media capable of storing, holding, and / or transmitting command(s) and / or data.

[0179] It should be understood that the specific order or hierarchy of steps in the presented processes is merely an example of exemplary approaches. It should be understood that, based on design priorities, the specific order or hierarchy of steps in the processes may be rearranged within the scope of the invention. The appended method claims provide various step elements in a sample order, but do not imply limitation to the specific order or hierarchy presented.

[0180] The description of the presented embodiments is provided so that any person skilled in the art may use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of the present invention. Thus, the present invention is not limited to the embodiments presented herein, but should be interpreted in the broadest possible scope consistent with the principles and novel features presented herein. Explanation of the symbols

[0181] 100: Computing device 200 : User terminal 300 : External server 400 : Network

Claims

Claim 1 A method for asynchronous reset-based lockstep core synchronization performed on one or more processors of a computing device, comprising: detecting the activation time of each of a primary core and a checker core; acquiring delay time information related to the difference in execution time between the two cores based on the activation time; applying a delay to an output signal of the primary core based on the delay time information; and determining whether there is a malfunction by comparing the output signal of the primary core to which the delay is applied with the output signal of the checker core; wherein the step of acquiring the delay time information comprises the step of generating delay time information by measuring the number of clock cycles from the activation time of the primary core until the checker core is activated. Claim 2 Asynchronous reset-based lockstep core synchronization method according to claim 1, wherein the step of detecting the activation time of each of the primary core and the checker core comprises the step of applying one or more delay circuits to the reset signal path of the checker core so that the reset signal of the checker core is valid after a certain time delay compared to the reset signal of the primary core. Claim 3 In claim 1, the step of acquiring delay time information comprises generating delay time information by measuring the number of clock cycles from the activation time of the primary core until the activation of the checker core through a delay estimation unit including a state controller and a counter that detect whether the primary core and the checker core are activated, wherein the state controller is configured to start measuring the counter when the activation of the primary core is detected and stop measuring the counter when the activation of the checker core is detected, and wherein the counter is controlled by the state controller to store the number of clocks corresponding to the difference in execution time, an asynchronous reset-based lockstep core synchronization method. Claim 4 Asynchronous reset-based lockstep core synchronization method according to claim 1, wherein the step of applying a delay to the output signal of the primary core based on the delay time information is characterized by delaying the output signal of the primary core based on the delay time information to correct it so that the comparison time with the output signal of the checker core matches. Claim 5 In claim 4, the step of applying a delay to the output signal of the primary core based on the delay time information is characterized by controlling the operation of an output comparison circuit so that a comparison between the output signal of the primary core and the output signal of the checker core is not performed before the delay is applied to the output signal of the primary core. Claim 6 The asynchronous reset-based lockstep core synchronization method according to claim 1, further comprising the step of determining that there is a synchronization error in the system when the delay time information exceeds a preset threshold, and controlling to block an output comparison operation or re-execute a reset sequence. Claim 7 The asynchronous reset-based lockstep core synchronization method according to claim 1, further comprising: a step of calculating reliability information corresponding to the primary core and the checker core based on the delay time information; and a step of switching the roles between the primary core and the checker core when the reliability information is less than a preset reference value, wherein the reliability information is information that serves as a reference for determining whether to switch roles. Claim 8 The asynchronous reset-based lockstep core synchronization method according to claim 1, wherein the checker core is provided in a plurality of units, and the method further comprises: a step of calculating a core evaluation score suitable for performing a comparison based on at least one of a difference in execution time, a history of past comparison results, or internal state information for each of the plurality of checker cores; and a step of dynamically selecting a reference checker core to be used for performing a comparison with the output of the primary core by comparing the core evaluation scores corresponding to each checker core. Claim 9 A device comprising: a memory for storing one or more instructions; and a processor for executing the one or more instructions stored in the memory, wherein the processor performs the method of claim 1 by executing the one or more instructions. Claim 10 A computer program stored on a recording medium readable by a computer, combined with a computer which is hardware, to perform the method of claim 1.

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