Semiconductor device and manufacturing method of the same

Abstract

A semiconductor device according to some embodiments of the concept of the present invention comprises: a base structure comprising a first bonding pad and a first test pad; and a semiconductor chip comprising a second bonding pad in contact with the first bonding pad of the base structure and a second test pad in contact with the first test pad of the base structure. The width of the second bonding pad of the semiconductor chip is smaller than the width of the second test pad of the semiconductor chip. An air gap is provided between the first test pad of the base structure and the second test pad of the semiconductor chip.

Description

Technology Field

[0001] Embodiments of the concept of the present invention relate to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a test pad and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and / or low operating voltages. To meet these requirements, more highly integrated semiconductor devices are necessary. However, as the integration of semiconductor devices intensifies, their electrical characteristics and production yield may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. The problem to be solved

[0004] Embodiments of the concept of the present invention aim to provide a semiconductor device with improved electrical characteristics and reliability and a method for manufacturing the same. means of solving the problem

[0005] A semiconductor device according to some embodiments comprises a base structure including a first bonding pad and a first test pad; and a semiconductor chip including a second bonding pad in contact with the first bonding pad of the base structure and a second test pad in contact with the first test pad of the base structure, wherein the width of the second bonding pad of the semiconductor chip is smaller than the width of the second test pad of the semiconductor chip, and an air gap may be provided between the first test pad of the base structure and the second test pad of the semiconductor chip.

[0006] A semiconductor device according to some embodiments comprises: a first insulating structure; a first bonding pad within the first insulating structure; a first test pad within the first insulating structure; a second insulating structure on the first insulating structure; a second bonding pad provided within the second insulating structure and in contact with the first bonding pad; and a second test pad provided within the second insulating structure and in contact with the first test pad, wherein the width of the second bonding pad is smaller than the width of the second test pad, and the second test pad of the semiconductor chip comprises a contact surface in contact with the first test pad of the base structure and an exposed surface spaced apart from the first test pad of the base structure, wherein the exposed surface may be closer to the side wall of the second test pad of the semiconductor chip than to the contact surface.

[0007] A semiconductor device according to some embodiments comprises a base structure including a first bonding pad and a first test pad; and a semiconductor chip including a second bonding pad in contact with the first bonding pad of the base structure and a second test pad in contact with the first test pad of the base structure, wherein the width of the second bonding pad of the semiconductor chip is smaller than the width of the second test pad of the semiconductor chip, and the width of the first bonding pad of the base structure is smaller than the width of the first test pad of the base structure, and an air gap is provided between the first test pad of the base structure and the second test pad of the semiconductor chip, and the air gap may surround a portion of the first test pad and a portion of the second test pad. Effects of the invention

[0008] A semiconductor device according to embodiments of the concept of the present invention includes test pads with a relatively large width, so that the bonding quality of the bonding pads can be improved. Brief explanation of the drawing

[0009] FIG. 1a is a plan view of a semiconductor device according to some embodiments. Figure 1b is a cross-sectional view along the line A-A' of Figure 1a. Figure 1c is an enlarged view of area B of Figure 1b. FIG. 2a is a flowchart for explaining a method for manufacturing a semiconductor device according to some embodiments. FIG. 2b is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. Figure 2c is an enlarged view of area C of Figure 2b. FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 4 is a plan view of a semiconductor device according to some embodiments. FIG. 5 is a plan view of a semiconductor device according to some embodiments. FIG. 6 is a plan view of a semiconductor device according to some embodiments. FIG. 7 is a plan view of a semiconductor device according to some embodiments. FIG. 8 is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 9 is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 10 is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 11 is a cross-sectional view of a semiconductor device according to some embodiments. Specific details for implementing the invention

[0010] Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the concept of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1a is a plan view of a semiconductor device according to some embodiments. FIG. 1b is a cross-sectional view along the line A-A' of FIG. 1a. FIG. 1c is an enlarged view of region B of FIG. 1b.

[0013] Referring to FIGS. 1a and 1b, the semiconductor device may include a base structure (BS) and a first semiconductor chip (SC1), a second semiconductor chip (SC2), a third semiconductor chip (SC3), and a fourth semiconductor chip (SC4) sequentially disposed on the base structure (BS). Although the number of semiconductor chips (SC1, SC2, SC3, SC4) is depicted as four, the present disclosure is not limited thereto. In some embodiments, the number of semiconductor chips (SC) may be eight or twelve. A molding film (MD) may be provided that is disposed on the base structure (BS) and surrounds the semiconductor chips (SC1, SC2, SC3, SC4). The molding film (MD) may comprise a polymer material. Terminals (TE) connected to the base structure (BS) may be provided. The semiconductor device may be electrically connected to an external device through the terminals (TE). The terminals (TE) may comprise a conductive material.

[0014] The base structure (BS) may include a first insulating structure (111), first bonding pads (112), a first test pad (113), a first wiring structure (114), a first substrate (115), first through-vias (116), a second insulating structure (117) and second bonding pads (118).

[0015] A first wiring structure (114) and a first substrate (115) may be provided between the first insulating structure (111) and the second insulating structure (117). The first and second insulating structures (111, 117) may include an insulating material. In some embodiments, each of the first and second insulating structures (111, 117) may include a plurality of insulating films.

[0016] First bonding pads (112) may be provided within a first insulating structure (111). Second bonding pads (118) and a first test pad (113) may be provided within a second insulating structure (117). Each of the first bonding pads (112) may be connected to each terminal (TE). The first bonding pads (112), the second bonding pads (118), and the first test pad (113) may include a conductive material.

[0017] A first wiring structure (114) may be provided on a first insulating structure (111). The first wiring structure (114) may be connected to first bonding pads (112). The first wiring structure (114) may include a conductive structure and an insulating film surrounding the conductive structure. The conductive structure of the first wiring structure (114) may include at least one of a conductive contact, a conductive line, or a conductive pad. The conductive structure of the first wiring structure (114) may be electrically connected to the first bonding pad (112). In some embodiments, the first wiring structure (114) may include a plurality of insulating films.

[0018] The base structure (BS) may include a semiconductor device. For example, the base structure (BS) may include a logic device. The semiconductor device of the base structure (BS) may be provided between the first substrate (115) and the first wiring structure (114). The semiconductor device may be electrically connected to a conductive structure of the first wiring structure (114). In some embodiments, the base structure (BS) may be a rewiring board or a printed circuit board that does not include a semiconductor device.

[0019] A first substrate (115) may be provided on a first wiring structure (114). The first substrate (115) may have the form of a plate extending along a plane extending in a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be horizontal directions orthogonal to each other. In some embodiments, the first substrate (115) may be a semiconductor substrate. For example, the first substrate (115) may include silicon, germanium, silicon-germanium, GaP, or GaAs. In some embodiments, the first substrate (115) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0020] The first through vias (116) can penetrate the first substrate (115). The first through vias (116) can extend in a third direction (D3). The third direction (D3) can intersect the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be a vertical direction orthogonal to the first direction (D1) and the second direction (D2).

[0021] The first through-via (116) may be electrically connected to a conductive structure of the first wiring structure (114). The first through-via (116) may be connected to a second bonding pad (118) or a first test pad (113). The first through-vias (116) may include a conductive material.

[0022] The components of the first to fourth semiconductor chips (SC1, SC2, SC3, SC4) may be similar to the components of the base structure (BS).

[0023] The first semiconductor chip (SC1) may include a third insulating structure (121), third bonding pads (122), a second test pad (123), a second wiring structure (124), a second substrate (125), second through-vias (126), a fourth insulating structure (127), fourth bonding pads (128), and a third test pad (129).

[0024] The third bonding pads (122) and the second test pad (123) may be provided within the third insulation structure (121). The fourth bonding pads (128) and the third test pad (129) may be provided within the fourth insulation structure (127).

[0025] The third insulating structure (121) of the first semiconductor chip (SC1) can be in contact with the second insulating structure (117) of the base structure (BS). The third bonding pad (122) of the first semiconductor chip (SC1) can be in contact with the second bonding pad (118) of the base structure (BS). The second test pad (123) of the first semiconductor chip (SC1) can be in contact with the first test pad (113) of the base structure (BS).

[0026] The second semiconductor chip (SC2) may include a fifth insulating structure (131), fifth bonding pads (132), a fourth test pad (133), a third wiring structure (134), a third substrate (135), third through-vias (136), a sixth insulating structure (137), sixth bonding pads (138), and a fifth test pad (139).

[0027] The fifth insulating structure (131) of the second semiconductor chip (SC2) can be in contact with the fourth insulating structure (127) of the first semiconductor chip (SC1). The fifth bonding pad (132) of the second semiconductor chip (SC2) can be in contact with the fourth bonding pad (128) of the first semiconductor chip (SC1). The fourth test pad (133) of the second semiconductor chip (SC2) can be in contact with the third test pad (129) of the first semiconductor chip (SC1).

[0028] The third semiconductor chip (SC3) may include a seventh insulating structure (141), seventh bonding pads (142), a sixth test pad (143), a fourth wiring structure (144), a fourth substrate (145), fourth through-vias (146), an eighth insulating structure (147), eighth bonding pads (148), and a seventh test pad (149).

[0029] The fourth semiconductor chip (SC4) may include a ninth insulating structure (151), ninth bonding pads (152), eighth test pad (153), fifth wiring structure (154), fifth substrate (155), tenth insulating structure (157), and tenth bonding pads (158). The fourth semiconductor chip (SC4) positioned at the top of the first to fourth semiconductor chips (SC1, SC2, SC3, SC4) may not include through-vias. The fourth semiconductor chip (SC4) may not include test pads within the tenth insulating structure (10).

[0030] The first semiconductor chip (SC1) may include a center region (CR) and a surround region (SR) surrounding the center region (CR). The center region (CR) and the surround region (SR) may be planarly separated regions defined by a first direction (D1) and a second direction (D2). The surround region (SR) may be closer to the side wall of the first semiconductor chip (SC1) than the center region (CR).

[0031] The surround region (SR) may include corner regions (OR) and edge regions (ER). The corner region (CR) may be an area adjacent to the part where the side walls of the first semiconductor chip (SC1) are connected. The edge region (ER) may be an area positioned between two corner regions (OR).

[0032] The second test pad (123) and the third test pad (129) of the first semiconductor chip (SC1) may be placed in the corner region (OR) of the first semiconductor chip (SC1). Each of the third bonding pads (122) and the fourth bonding pads (128) of the first semiconductor chip (SC1) may be placed in one of the center region (CR), the corner region (OR), or the edge region (ER) of the first semiconductor chip (SC1).

[0033] The second test pad (123) and the third test pad (129) of the first semiconductor chip (SC1) may be positioned closer to the side wall of the first semiconductor chip (SC1) than some of the third bonding pads (122) and the fourth bonding pads (128) of the first semiconductor chip (SC1).

[0034] Similar to the first semiconductor chip (SC1), the first test pad (113) of the base structure (BS) may be placed in the corner area of ​​the base structure (BS), and each of the test pads (133, 139, 143, 149, 153) of the second to fourth semiconductor chips (SC2, SC3, SC4) may be placed in the corner area of ​​each of the second to fourth semiconductor chips (SC2, SC3, SC4).

[0035] Referring to FIG. 1c, the second insulating structure (117) of the base structure (BS) may include a plurality of insulating films. As an example, the second insulating structure (117) may include a silicon nitride film and a silicon oxide film.

[0036] The third insulating structure (121) of the first semiconductor chip (SC1) may include a first insulating film (121a1) in contact with the second insulating structure (117) and a second insulating film (121a2) on the first insulating film (121a1). The first insulating film (121a1) may be, for example, a silicon carbonitride film. The second insulating film (121a2) may include a plurality of insulating films. As an example, the second insulating film (121a2) may include a silicon nitride film and a silicon oxide film.

[0037] The width of the second bonding pad (118) may be smaller than the width of the first test pad (113) and the width of the second test pad (123). For example, the maximum width (W1) of the second bonding pad (118) in the first direction (D1) may be smaller than the maximum width (W2) of the first test pad (113) in the first direction (D1) and the maximum width (W3) of the second test pad (123) in the first direction (D1). For example, the width of the first test pad (113) may be greater than 1.1 times the width of the second bonding pad (118).

[0038] The width of the third bonding pad (122) may be smaller than the width of the first test pad (113) and the width of the second test pad (123). For example, the maximum width (W4) of the third bonding pad (122) in the first direction (D1) may be smaller than the maximum width (W2) of the first test pad (113) in the first direction (D1) and the maximum width (W3) of the second test pad (123) in the first direction (D1). For example, the width of the second test pad (123) may be larger than 1.1 times the width of the third bonding pad (122).

[0039] As shown above, the width of each bonding pad (122, 128, 132, 138, 142, 148, 152) of the semiconductor chips (SC1, SC2, SC3, SC4) may be smaller than the width of the test pads (113, 123, 129, 133, 139, 143, 149, 153).

[0040] Each of the first to tenth bonding pads (112, 118, 122, 128, 132, 138, 142, 148, 152, 158) and the first to eighth test pads (113, 123, 129, 133, 139, 143, 149, 153) may include a conductive film (CL) and a barrier film (BL). The barrier film (BL) may surround the conductive film (CL). The conductive film (CL) may include, for example, copper, and the barrier film (BL) may include, for example, titanium, tantalum, titanium oxide, tantalum oxide, titanium nitride, or tantalum nitride.

[0041] The width of the second bonding pad (118) may be greater than the width of the third bonding pad (122), and the entire lower surface of the third bonding pad (132) may be in contact with the upper surface of the second bonding pad (118). The entire lower surface of the conductive film (CL) of the third bonding pad (122) and the entire lower surface of the barrier film (BL) of the third bonding pad (122) may be in contact with the upper surface of the conductive film (CL) of the second bonding pad (128). The upper surface of the second bonding pad (118) may be flat, and the lower surface of the third bonding pad (122) may be flat. In some embodiments, the width of the third bonding pad (122) may be greater than the width of the second bonding pad (118), and the entire upper surface of the second bonding pad (118) may be in contact with the lower surface of the third bonding pad (122). In some embodiments, a portion of the lower surface of the third bonding pad (122) and a portion of the upper surface of the second bonding pad (118) may come into contact.

[0042] An air gap (AG) may be provided between the first test pad (113) and the second test pad (123) that are in contact with each other. The width of the first test pad (113) may be greater than the width of the second test pad (123), and the air gap (AG) may expose the upper surface of the first test pad (113), the lower surface of the second test pad (123), and the lower surface of the third insulating structure (121). In some embodiments, the width of the second test pad (123) may be greater than the width of the first test pad (113), and the air gap (AG) may expose the upper surface of the first test pad (113), the lower surface of the second test pad (123), and the upper surface of the second insulating structure (117). In some embodiments, the air gap (AG) may expose the upper surface of the first test pad (113), the lower surface of the second test pad (123), the upper surface of the second insulating structure (117), and the lower surface of the third insulating structure (121).

[0043] The conductive film (CL) of the first test pad (113) may include a first contact surface (CS1) that contacts the conductive film (CL) of the second test pad (123). The conductive film (CL) of the second test pad (123) may include a second contact surface (CS2) that contacts the first contact surface (CS1) of the conductive film (CL) of the first test pad (113). The first contact surface (CS1) and the second contact surface (CS2) may be flat. The first contact surface (CS1) may be the center of the upper surface of the conductive film (CL) of the first test pad (113). The second contact surface (CS2) may be the center of the lower surface of the conductive film (CL) of the second test pad (123).

[0044] The air gap (AG) may surround a portion of the first test pad (113) and a portion of the second test pad (123). The air gap (AG) may surround the first contact surface (CS1) and the second contact surface (CS2). The air gap (AG) may have the shape of a ring. At least a portion of the air gap (AG) may be provided between the first contact surface (CS1) and the side wall (113s) of the first test pad (113). At least a portion of the air gap (AG) may be provided between the second contact surface (CS2) and the side wall (123s) of the second test pad (123).

[0045] The level of the uppermost part of the air gap (AG) may be higher than the level of the first and second contact surfaces (CS1, CS2). The level of the lowermost part of the air gap (AG) may be lower than the level of the first and second contact surfaces (CS1, CS2).

[0046] The conductive film (CL) of the first test pad (113) may include a first exposed surface (ES1) exposed by an air gap (AG). The conductive film (CL) of the second test pad (123) may include a second exposed surface (ES2) exposed by an air gap (AG). The first exposed surface (ES1) and the second exposed surface (ES2) may be curved. The first exposed surface (ES1) may be provided between the first contact surface (CS1) and the side wall (113s) of the first test pad (113). The second exposed surface (ES2) may be provided between the second contact surface (CS2) and the side wall (123s) of the second test pad (123). The first exposed surface (ES1) and the second exposed surface (ES2) may define an air gap (AG).

[0047] The upper surface (BL1) of the barrier film (BL) of the first test pad (113) may be flat. The upper surface (BL1) of the barrier film (BL) of the first test pad (113) may be in contact with the third insulating structure (121). The lower surface (BL2) of the barrier film (BL) of the second test pad (123) may be flat. The lower surface (BL2) of the barrier film (BL) of the second test pad (123) may be exposed by an air gap (AG). The lower surface (BL2) of the barrier film (BL) of the second test pad (123) may be spaced apart from the first test pad (113).

[0048] The structure of the third and fourth test pads (129, 133) in contact with each other, the structure of the fifth and sixth test pads (139, 143) in contact with each other, and the structure of the seventh and eighth test pads (149, 153) in contact with each other may be similar to the structure of the first and second test pads (113, 123) according to FIG. 1C.

[0049] Bonding pads (112, 118, 122, 128, 132, 138, 142, 148, 152, 158) may be pads that provide electrical connections for driving a semiconductor device. Test pads (113, 123, 129, 133, 139, 143, 149, 153) may be pads for testing the bonding process of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152).

[0050] According to some embodiments, the semiconductor device includes relatively wide test pads (113, 123, 129, 133, 139, 143, 149, 153), so that the bonding quality of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152) can be improved.

[0051] In a semiconductor device according to some embodiments, as test pads (113, 123, 129, 133, 139, 143, 149, 153) are placed in a corner region (OR), the bonding quality of bonding pads (118, 122, 128, 132, 138, 142, 148, 152) can be improved.

[0053] FIG. 2a is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments. FIG. 2b is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. FIG. 2c is an enlarged view of region C of FIG. 2b.

[0054] Referring to FIG. 2a, a method for manufacturing a semiconductor device may include forming a base structure and a semiconductor chip (S10), bonding the base structure and the semiconductor chip (S20), performing a heat treatment process (S30), obtaining measurement data by measuring the bonding of test pads (S40), evaluating the bonding of bonding pads based on the measurement data (S50), and determining whether to adjust the heat treatment process or the bonding process based on the evaluation result (S60).

[0055] Referring to FIGS. 2a, 2b and 2c, a base structure (BS) and a first semiconductor chip (SC1) can be formed (S10). Forming the base structure (BS) may include forming a first wiring structure (114) on a first substrate (115), forming first through vias (116) penetrating the first substrate (115), forming a first insulating structure (111) on the first wiring structure (114), forming first preliminary bonding pads (p112) within the first insulating structure (111), forming a second insulating structure (117) on the first substrate (115), and forming second preliminary bonding pads (p118) and a first preliminary test pad (p113) within the second insulating structure (117).

[0056] Forming the first pre-bonding pads (p112) may include etching the first insulating structure (111), forming a barrier film (BL) within the first insulating structure (111), forming a first conductive material film on the first insulating structure (111), and performing a first polishing process to polish the first conductive material film.

[0057] Forming the second preliminary bonding pads (p118) and the first preliminary test pad (p113) may include etching the second insulating structure (117), forming a barrier film (BL) within the second insulating structure (117), forming a second conductive material film on the second insulating structure (117), and performing a second polishing process to polish the second conductive material film.

[0058] A conductive film (CL) of each of the first preliminary bonding pads (p112), the second preliminary bonding pads (p118), and the first preliminary test pad (p113) can be formed by the first and second polishing processes. A recess (RS) can be formed in each of the conductive films (CL) of the first preliminary bonding pads (p112), the second preliminary bonding pads (p118), and the first preliminary test pad (p113) formed by the first and second polishing processes.

[0059] As the width of the first preliminary test pad (p113) is greater than the width of each of the first and second preliminary bonding pads (p112, p118), the recess (RS) formed in the conductive film (CL) of the first preliminary test pad (p113) may be larger than the recess (RS) formed in each of the conductive films (CL) of the first and second preliminary bonding pads (p112, p118).

[0060] For example, the recess (RS) of the first preliminary test pad (p113) may be larger than the recess (RS) of the second preliminary bonding pad (p118). The level difference between the top (p118a1) and bottom (p118a2) of the upper surface (p118a) of the second preliminary bonding pad (p118) may be smaller than the level difference between the top (p113a1) and bottom (p113a2) of the upper surface (p113a) of the first preliminary test pad (p113). The height of the recess (RS) of the second preliminary bonding pad (p118) may be smaller than the height of the recess (RS) of the first preliminary test pad (p113). The level of the uppermost part (p118a1) of the upper surface (p118a) of the second preliminary bonding pad (p118) and the level of the uppermost part (p113a1) of the upper surface (p113a) of the first preliminary test pad (p113) may be the same. The level of the lowermost part (p113a2) of the upper surface (p113a) of the first preliminary test pad (p113) may be lower than the level of the lowermost part (p118a2) of the upper surface (p118a) of the second preliminary bonding pad (p118).

[0061] The uppermost portion (p118a1) of the upper surface (p118a) of the second preliminary bonding pad (p118) may be the upper surface of the barrier film (BL) of the second preliminary bonding pad (p118). The lowermost portion (p118a2) of the upper surface (p118a) of the second preliminary bonding pad (p118) may be a part of the upper surface of the conductive film (CL) of the second preliminary bonding pad (p118).

[0062] The uppermost portion (p113a1) of the upper surface (p113a) of the first preliminary test pad (p113) may be the upper surface of the barrier film (BL) of the first preliminary test pad (p113). The lowermost portion (p113a2) of the upper surface (p113a) of the first preliminary test pad (p113) may be a part of the upper surface of the conductive film (CL) of the first preliminary test pad (p113).

[0063] Similar to the process of forming a base structure (BS), a first semiconductor chip (SC1) may be formed. The first semiconductor chip (SC1) may include a second substrate (125), a second wiring structure (124), second through-vias (126), a third insulating structure (121), third preliminary bonding pads (p122), a second preliminary test pad (p123), a fourth insulating structure (127), fourth preliminary bonding pads (p128), and a third preliminary test pad (p129).

[0064] As the width of each of the second and third preliminary test pads (p123, p129) is greater than the width of each of the third and fourth preliminary bonding pads (p122, p128), the recess (RS) formed in each of the second and third preliminary test pads (p123, p129) may be larger than the recess (RS) formed in each of the third and fourth preliminary bonding pads (p122, p128).

[0065] For example, the recess (RS) of the second preliminary test pad (p123) may be larger than the recess (RS) of the third preliminary bonding pad (p122). The level difference between the lowest part (p122a1) and the highest part (p122a2) of the lower surface (p122a) of the third preliminary bonding pad (p122) may be smaller than the level difference between the lowest part (p123a1) and the highest part (p123a2) of the lower surface (p123a) of the second preliminary test pad (p123). The height of the recess (RS) of the third preliminary bonding pad (p122) may be smaller than the height of the recess (RS) of the second preliminary test pad (p123). The level of the lowest part (p122a1) of the lower surface (p122a) of the third preliminary bonding pad (p122) and the level of the lowest part (p123a1) of the lower surface (p123a) of the second preliminary test pad (p123) may be the same. The level of the upper part (p123a2) of the lower surface (p123a) of the second preliminary test pad (p123) may be higher than the level of the upper part (p122a2) of the lower surface (p122a) of the third preliminary bonding pad (p122).

[0066] The lowest portion (p122a1) of the lower surface (p122a) of the third preliminary bonding pad (p122) may be the lower surface of the barrier film (BL) of the third preliminary bonding pad (p122). The upper portion (p122a2) of the lower surface (p122a) of the third preliminary bonding pad (p122) may be part of the lower surface of the conductive film (CL) of the third preliminary bonding pad (p122).

[0067] The lowest part (p123a1) of the lower surface (p123a) of the second preliminary test pad (p123) may be the lower surface of the barrier film (BL) of the second preliminary test pad (p123). The upper part (p123a2) of the lower surface (p123a) of the second preliminary test pad (p123) may be part of the lower surface of the conductive film (CL) of the second preliminary test pad (p123).

[0068] Referring to FIGS. 2a, 1b and 1c, a base structure (BS) and a first semiconductor chip (SC1) can be bonded (S20). Bonding the base structure (BS) and the first semiconductor chip (SC1) may include applying pressure to the first semiconductor chip (SC1) and the base structure (BS) using a pressure device. In some embodiments, the pressure applied at the center of the base structure (BS) and the first semiconductor chip (SC1) may be relatively high.

[0069] Depending on the bonding of the first semiconductor chip (SC1) of the base structure (BS), the second insulating structure (117) and the third insulating structure (121) may be bonded, the second preliminary bonding pad (p118) and the third preliminary bonding pad (p122) may be bonded, and the first preliminary test pad (p113) and the second preliminary test pad (p123) may be bonded. Recesses (RS) may be provided between the second preliminary bonding pad (p118) and the third preliminary bonding pad (p122), and recesses (RS) may be provided between the first preliminary test pad (p113) and the second preliminary test pad (p123).

[0070] Similar to the first semiconductor chip (SC1), second to fourth semiconductor chips (SC2, SC3, SC4) may be formed, the second semiconductor chip (SC2) may be bonded to the first semiconductor chip (SC1), the third semiconductor chip (SC3) may be bonded to the second semiconductor chip (SC2), and the fourth semiconductor chip (SC4) may be bonded to the third semiconductor chip (SC3).

[0071] A heat treatment process can be performed (S30). Depending on the heat treatment process, the bonded second and third pre-bonding pads (p118, p122) can be enlarged, and the second and third bonding pads (118, 122) can be formed. As the second and third pre-bonding pads (p118, p122) become enlarged, the recesses (RS) between the second and third pre-bonding pads (p118, p122) can be completely filled by the second and third bonding pads (118, 122).

[0072] Depending on the heat treatment process, the bonded first and second preliminary test pads (p113, p123) may be enlarged, and the first and second test pads (113, 123) may be formed. As the first and second preliminary test pads (p113, p123) become enlarged, an air gap (AG) may be formed between the first and second test pads (113, 123). A first contact surface (CS1) in contact with the second test pad (123) may be formed on the first test pad (113), and a second contact surface (CS2) in contact with the first test pad (113) may be formed on the second test pad (123). Only a portion of the recesses (RS) between the first and second preliminary test pads (p113, p123) may be filled by the first and second test pads (113, 123).

[0073] Similar to the second and third bonding pads (118, 122) and the first and second test pads (113, 123), other bonding pads (128, 132, 138, 142, 148, 152) and other test pads (129, 133, 139, 143, 149, 153) may be formed.

[0074] Terminals (TE) connected to the first preliminary bonding pads (p112) may be formed. The first preliminary bonding pads (p112) connected to the terminals (TE) may be defined as the first bonding pads (112). A molding film (MD) surrounding the first to fourth semiconductor chips (SC1, SC2, SC3, SC4) may be formed. According to the above process, a first semiconductor device may be formed.

[0075] Measurement data can be obtained by measuring the bonding of the test pads (113, 123, 129, 133, 139, 143, 149, 153) of the first semiconductor device (S40). Measuring the bonding of the test pads (113, 123, 129, 133, 139, 143, 149, 153) may include measuring the electrical connection of the test pads (113, 123, 129, 133, 139, 143, 149, 153) that are in contact with each other, or measuring the size of the air gap (AG) provided between the test pads (113, 123, 129, 133, 139, 143, 149, 153) that are in contact with each other. Measuring the electrical connection of the test pads (113, 123, 129, 133, 139, 143, 149, 153) in contact with each other may include, for example, measuring the flow of current between the test pads (113, 123, 129, 133, 139, 143, 149, 153) in contact with each other.

[0076] Measurement data resulting from measuring the bonding of test pads (113, 123, 129, 133, 139, 143, 149, 153) can be stored. For example, the magnitude of the current flowing between the first test pad (113) and the second test pad (123) can be stored as measurement data. For example, the magnitude of the air gap (AG) between the first test pad (113) and the second test pad (123) can be stored as measurement data. The measurement data can be stored in a storage device, for example, a server.

[0077] Based on the measurement data, the bonding of bonding pads (118, 122, 128, 132, 138, 142, 148, 152) in contact with each other can be evaluated, and an evaluation result can be obtained (S50). The evaluation result may be pass or fail. If the measurement data meets a predetermined standard, the evaluation result may be pass. If the measurement data does not meet a predetermined standard, the evaluation result may be fail.

[0078] For example, if the magnitude of the current between the first test pad (113) and the second test pad (123) according to a constant voltage is greater than or equal to a predetermined value, the bonding quality of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152) may be evaluated as secured, and the evaluation result may be pass. For example, if the magnitude of the current between the first test pad (113) and the second test pad (123) according to a constant voltage is less than a predetermined value, the bonding quality of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152) may be evaluated as not secured, and the evaluation result may be fail.

[0079] Based on the evaluation result of the bonding of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152), it may be determined whether to adjust the heat treatment process or the bonding process (S60). If the evaluation result of the bonding of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152) is a failure, the heat treatment process or the bonding process may be adjusted. For example, the temperature of the heat treatment process may be increased or the time of the heat treatment process may be increased. For example, the pressure applied during the bonding process may be increased. If the evaluation result of the bonding of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152) is a failure, subsequent semiconductor devices can be manufactured using an adjusted heat treatment process or a bonding process.

[0080] If the evaluation result of the bonding of the bonding pads (118, 122, 128, 132, 138, 142, 148, 152) is a pass, subsequent semiconductor devices can be manufactured without adjusting the heat treatment process or the bonding process.

[0081] A method for manufacturing a semiconductor device according to some embodiments includes evaluating the bonding of bonding pads using data obtained by measuring the bonding of test pads with a relatively large width, thereby enabling process conditions to be obtained in which the bonding pads have improved bonding quality.

[0082] A method for manufacturing a semiconductor device according to some embodiments includes evaluating the bonding of bonding pads using data obtained by measuring the bonding of test pads located in a corner region with relatively weak pressure, thereby enabling the acquisition of process conditions that allow the bonding pads to have improved bonding quality.

[0084] FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments.

[0085] Referring to FIG. 3, the semiconductor device may include a base structure (BSa) and a first semiconductor chip (SC1a) on the base structure (BSa).

[0086] The base structure (BSa) may include a first bonding pad (118a) and a first test pad (113a). The first semiconductor chip (SC1a) may include a second bonding pad (122a) in contact with the first bonding pad (118a) and a second test pad (123a) in contact with the first test pad (113a).

[0087] The width of the first test pad (113a) may be greater than the width of the second test pad (123a), and the entire lower surface of the second test pad (123a) may be in contact with the upper surface of the first test pad (113a). The entire lower surface of the conductive film (CL) of the second test pad (123a) and the entire lower surface of the barrier film (BL) of the second test pad (123a) may be in contact with the upper surface of the conductive film (CL) of the first test pad (113a). An air gap may not be formed between the first test pad (113a) and the second test pad (123a). The upper surface of the first test pad (113a) and the lower surface of the second test pad (123a) may be flat.

[0088] In some embodiments, the width of the second test pad (123a) may be greater than the width of the first test pad (113a), and the entire upper surface of the first test pad (113a) may be in contact with the lower surface of the second test pad (123a). In some embodiments, a portion of the lower surface of the second test pad (123a) may be in contact with a portion of the upper surface of the first test pad (113a).

[0090] FIG. 4 is a plan view of a semiconductor device according to some embodiments.

[0091] Referring to FIG. 4, the semiconductor device may include a base structure (BSb) and a first semiconductor chip (SC1b) on the base structure (BSb).

[0092] The first semiconductor chip (SC1b) may include first to fourth corner regions (OR1, OR2, OR3, OR4), edge regions (ER), and a center region (CR). The first semiconductor chip (SC1b) may include bonding pads (122b) disposed in the center region (CR) and edge regions (ER), and test pads (123b) disposed in the first to fourth corner regions (OR1, OR2, OR3, OR4).

[0093] The widths of the test pad (123b) placed in the first corner area (OR1) and the test pad (123b) placed in the second corner area (OR2) may differ from each other. For example, the maximum width (W5) of the test pad (123b) placed in the first corner area (OR1) in the first direction (D1) may be smaller than the maximum width (W6) of the test pad (123b) placed in the second corner area (OR2) in the first direction (D1). The width of the test pads (123b) may be larger than the width of the bonding pads (122b).

[0094] The base structure (BSb) may include bonding pads and test pads having positions corresponding to the positions of the bonding pads (122b) and test pads (123b) of the first semiconductor chip (SC1b).

[0096] FIG. 5 is a plan view of a semiconductor device according to some embodiments.

[0097] Referring to FIG. 5, the semiconductor device may include a base structure (BSc) and a first semiconductor chip (SC1c) on the base structure (BSc).

[0098] The first semiconductor chip (SC1c) may include bonding pads (122c) and test pads (123c). The shape of the test pad (123c) may differ from the shape of the bonding pads (122c). The planar shape of the test pad (123c) may be polygonal. For example, the planar shape of the test pad (123c) may be square, and the planar shape of the bonding pads (122c) may be circular.

[0099] In some embodiments, the planar shape of the test pad (123c) and the bonding pads (122c) may be rectangular.

[0100] The base structure (BSc) may include bonding pads and test pads having shapes corresponding to the bonding pads (122c) and test pads (123c) of the first semiconductor chip (SC1c).

[0102] FIG. 6 is a plan view of a semiconductor device according to some embodiments.

[0103] Referring to FIG. 6, the semiconductor device may include a base structure (BSd) and a first semiconductor chip (SC1d) on the base structure (BSd).

[0104] The first semiconductor chip (SC1d) may include bonding pads (122d) and test pads (123d). The shape of the test pad (123d) may differ from the shape of the bonding pads (122d). For example, the planar shape of the test pad (123d) may be octagonal, and the planar shape of the bonding pads (122d) may be circular.

[0105] In some embodiments, the planar shape of the test pad (123d) and the bonding pads (122d) may be octagonal.

[0106] The base structure (BSd) may include bonding pads and test pads having shapes corresponding to the bonding pads (122d) and test pads (123d) of the first semiconductor chip (SC1d).

[0108] FIG. 7 is a plan view of a semiconductor device according to some embodiments.

[0109] Referring to FIG. 7, the semiconductor device may include a base structure (BSe) and a first semiconductor chip (SC1e) on the base structure (BSe).

[0110] The first semiconductor chip (SC1e) may include bonding pads (122e) and test pads (123e). The bonding pads (122e) may be placed in corner regions (OR), edge regions (ER), and center region (CR). The test pad (123e) may be placed in the edge region (ER).

[0111] The base structure (BSd) may include bonding pads and test pads having positions corresponding to the positions of the bonding pads (122e) and test pads (123e) of the first semiconductor chip (SC1d).

[0112] In some embodiments, the test pads (123e) may be multiple, and the test pads (123e) may be placed in the edge region (ER) and the corner region (OR).

[0114] FIG. 8 is a cross-sectional view of a semiconductor device according to some embodiments.

[0115] Referring to FIG. 8, the semiconductor device may include a package substrate (600). For example, the package substrate (600) may be a printed circuit board (PCB). First terminals (610) electrically connected to the package substrate (600) may be provided. Through the first terminals (610), the semiconductor device may be mounted on an external device (e.g., a main board).

[0116] An interposer (700) may be provided on a package substrate (600). Second terminals (710) that electrically connect the package substrate (600) and the interposer (700) may be provided. The second terminals (710) may be provided between the package substrate (600) and the interposer (700).

[0117] A processor chip (800) may be provided on the interposer (700). For example, the processor chip (800) may be a graphics processing unit (GPU) or a central processing unit (CPU). Third terminals (810) that electrically connect the processor chip (800) and the interposer (700) may be provided. The third terminals (810) may be provided between the processor chip (800) and the interposer (700).

[0118] A base structure (BSf) and semiconductor chips (SCf) may be provided on an interposer (700). The base structure (BSf) and semiconductor chips (SCf) may be spaced apart from a processor chip (800) in a first direction (D1). Fourth terminals (TEf) that electrically connect the base structure (BSf) and the interposer (700) may be provided. Fourth terminals (TEd) may be provided between the base structure (BSf) and the interposer (700). A first molding film (MD1) surrounding the base structure (BSf) and semiconductor chips (SCf) may be provided.

[0119] A second molding film (MD2) surrounding an interposer (700), a processor chip (800), a base structure (BSf), and semiconductor chips (SCf) may be provided on a package substrate (600).

[0121] FIG. 9 is a cross-sectional view of a semiconductor device according to some embodiments.

[0122] Referring to FIG. 9, the semiconductor device may include a rewiring substrate (100), terminals (210), a semiconductor chip (SCg), and a molding film (MDg).

[0123] The redistribution substrate (100) may include under-bump patterns (161), insulating films (162), redistribution patterns (163), first bonding pads (164), and first test pads (165). The insulating films (162) may include an organic material, for example, a photo-imageable dielectric (PID) material. The photo-imageable dielectric material may include at least one of, for example, a photosensitive polyimide, polybenzoxazole, a phenolic polymer, and a benzocyclobutene polymer.

[0124] Under bump patterns (161) may be disposed within the insulating film (162) that is placed at the bottom of the insulating films (162). A terminal (210) may be connected to the under bump pattern (161). The terminal (210) and the under bump pattern (161) may include a conductive material.

[0125] Rewiring patterns (163) may be provided within insulating films (162). The rewiring patterns (163) may be electrically connected to the under-bump pattern (161). Each of the rewiring patterns (163) positioned at the bottom of the rewiring patterns (163) may be connected to the under-bump pattern (161). The rewiring patterns (163) may include a conductive material. The rewiring patterns (163) may include vias for vertical connection and wiring sections for horizontal connection.

[0126] The first bonding pads (164) may be provided within the insulating film (162) positioned at the top of the insulating films (162). The first bonding pad (164) may be connected to the redistribution pattern (163) positioned at the top of the redistribution patterns (163). The first test pad (165) may be provided within the insulating film (162) positioned at the top of the insulating films (162). The first test pad (165) may be connected to the redistribution pattern (163) positioned at the top of the redistribution patterns (163). The width of the first test pad (165) may be greater than the width of the first bonding pad (164).

[0127] A semiconductor chip (SCg) may be provided on a redistribution board (100). An insulating structure of the semiconductor chip (SCg) may be in contact with an upper insulating film (162) of the redistribution board (100). The semiconductor chip (SCg) may include second bonding pads (122g) connected to first bonding pads (164) and a second test pad (123g) connected to a first test pad (165). The width of the second test pad (123g) may be greater than the width of the second bonding pad (122g).

[0128] The molding film (MDg) can be placed on the redistribution substrate (100) to surround the semiconductor chip (SCg).

[0130] FIG. 10 is a cross-sectional view of a semiconductor device according to some embodiments.

[0131] Referring to FIG. 10, the semiconductor device may include a first rewiring substrate (310), terminals (220), a first semiconductor chip (SC1h), a first molding film (MD1h), connecting vias (320), a second rewiring substrate (330), a second semiconductor chip (SC2h), and a second molding film (MD2h).

[0132] The first rewiring substrate (310) may include under-bump patterns (311), first insulating films (312), first rewiring patterns (313), first bonding pads (314), first test pads (315) and connection pads (316).

[0133] The connecting pads (316) may be disposed within the insulating film (312) that is placed at the top of the first insulating films (312). The connecting pads (316) may include a conductive material.

[0134] A first semiconductor chip (SC1h) may be provided on a first redistribution board (310). An insulating structure of the first semiconductor chip (SC1h) may be in contact with an uppermost insulating film (312) of the first redistribution board (310). The first semiconductor chip (SC1h) may include second bonding pads (122h) connected to first bonding pads (314) and a second test pad (123h) connected to a first test pad (315).

[0135] A first molding film (MD1h) may be provided on a first redistribution substrate (310) to surround a first semiconductor chip (SC1h). Connection vias (320) may penetrate the first molding film (MD1h). Connection vias (320) may be connected to connection pads (316). Connection vias (320) may include a conductive material.

[0136] A second redistribution substrate (330) may be provided on a first molding film (MD1h). The second redistribution substrate (330) may include second insulating films (332), second redistribution patterns (333), a third bonding pad (334), and a third test pad (335). Each of the second redistribution patterns (333) of the second redistribution substrate (330) that is placed at the bottom may be connected to a connecting via (320).

[0137] A second semiconductor chip (SC2g) may be provided on a second rewiring substrate (330). An insulating structure of the second semiconductor chip (SC2h) may be in contact with the uppermost insulating film (332) of the second rewiring substrate (330). The second semiconductor chip (SC2h) may include fourth bonding pads (132h) connected to a third bonding pad (334) and a fourth test pad (133h) connected to a third test pad (335). A second molding film (MD2h) may be provided on the second rewiring substrate (330) to surround the second semiconductor chip (SC2h).

[0139] FIG. 11 is a cross-sectional view of a semiconductor device according to some embodiments.

[0140] Referring to FIG. 11, the semiconductor device may include a substrate (410), a first insulating structure (420) on the substrate (410), a second insulating structure (430) on the first insulating structure (420), first bonding pads (440) within the first insulating structure (420), a first test pad (450) within the first insulating structure (420), second bonding pads (460) within the second insulating structure (430), and a second test pad (470) within the second insulating structure (430).

[0141] The substrate (410) may be a semiconductor substrate. A first insulating structure (420) may be provided on the substrate (410). A semiconductor device may be provided between the substrate (410) and the first insulating structure (420). For example, the semiconductor device may be a logic device, a memory device, or an image sensor device.

[0142] First bonding pads (440) and a first test pad (450) may be provided within the first insulating structure (420). The width of the first test pad (450) may be greater than the width of the first bonding pad (440). The first bonding pad (440) may be electrically connected to a semiconductor device through a first conductive structure within the first insulating structure (420). The first conductive structure may include, for example, at least one of a conductive contact, a conductive line, or a conductive pad.

[0143] Second bonding pads (460) and a second test pad (470) may be provided within the second insulating structure (430). The width of the second test pad (470) may be greater than the width of the second bonding pad (460).

[0144] In some embodiments, the second bonding pad (460) may be electrically connected to the second conductive structure within the second insulating structure (430).

[0145] The second bonding pad (460) can be bonded to the first bonding pad (440). The second test pad (470) can be bonded to the first test pad (450). An air gap can be provided between the second test pad (470) and the first test pad (450).

[0146] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising: a base structure including a first bonding pad and a first test pad; and a semiconductor chip including a second bonding pad in contact with the first bonding pad of the base structure and a second test pad in contact with the first test pad of the base structure, wherein the width of the second bonding pad of the semiconductor chip is smaller than the width of the second test pad of the semiconductor chip, and an air gap is provided between the first test pad of the base structure and the second test pad of the semiconductor chip. Claim 2 A semiconductor device according to claim 1, wherein the width of the first bonding pad of the base structure is smaller than the width of the first test pad of the base structure. Claim 3 A semiconductor device according to claim 1, wherein the semiconductor chip comprises a center region and a surround region surrounding the center region, the second bonding pad of the semiconductor chip is disposed in the center region of the semiconductor chip, and the second test pad of the semiconductor chip is disposed in the surround region of the semiconductor chip. Claim 4 A semiconductor device according to claim 1, wherein the second test pad of the semiconductor chip is positioned closer to the sidewall of the semiconductor chip than the second bonding pad of the semiconductor chip. Claim 5 A semiconductor device according to claim 1, wherein the second test pad of the semiconductor chip includes a contact surface that contacts the first test pad of the base structure, and the air gap is provided between the contact surface and the side wall of the second test pad of the semiconductor chip. Claim 6 In claim 5, the air gap is a semiconductor device surrounding the contact surface. Claim 7 A semiconductor device according to claim 5, wherein the level of the uppermost part of the air gap is higher than the level of the contact surface and the level of the lowermost part of the air gap is lower than the level of the contact surface. Claim 8 A semiconductor device according to claim 1, wherein the second test pad of the semiconductor chip comprises a conductive film and a barrier film surrounding the conductive film, and the air gap exposes the lower surface of the barrier film of the second test pad of the semiconductor chip. Claim 9 A semiconductor device comprising: a first insulating structure; a first bonding pad within the first insulating structure; a first test pad within the first insulating structure; a second insulating structure on the first insulating structure; a second bonding pad provided within the second insulating structure and in contact with the first bonding pad; a second test pad provided within the second insulating structure and in contact with the first test pad, wherein the width of the second bonding pad is smaller than the width of the second test pad, and the second test pad includes a contact surface in contact with the first test pad and an exposed surface spaced apart from the first test pad, wherein the exposed surface is closer to the sidewall of the second test pad than the contact surface. Claim 10 In claim 9, the insulating structure comprises a center region and a surround region surrounding the center region, the surround region comprises corner regions and an edge region between the corner regions, and the second test pad is disposed in the corner regions. Claim 11 In claim 10, the second test pad comprises a plurality of second test pads, and the plurality of second test pads are disposed in the corner regions and the edge regions of the semiconductor device. Claim 12 In claim 9, the semiconductor device comprises a plurality of second test pads having different widths. Claim 13 In claim 9, the shape of the second test pad is different from the shape of the second bonding pad in the semiconductor device. Claim 14 In claim 13, the second test pad is a semiconductor device having a planar polygonal shape. Claim 15 A semiconductor device according to claim 9, wherein the second test pad comprises a barrier film and a conductive film within the barrier film, and the contact surface is the center of the lower surface of the conductive film. Claim 16 In claim 15, the lower surface of the barrier film of the second test pad is spaced apart from the first test pad in a semiconductor device. Claim 17 In claim 9, the semiconductor device having a flat contact surface and a curved exposure surface. Claim 18 In claim 9, the exposed surface is a semiconductor device defining an air gap. Claim 19 A semiconductor device comprising: a base structure including a first bonding pad and a first test pad; and a semiconductor chip including a second bonding pad in contact with the first bonding pad of the base structure and a second test pad in contact with the first test pad of the base structure, wherein the width of the second bonding pad of the semiconductor chip is smaller than the width of the second test pad of the semiconductor chip, the width of the first bonding pad of the base structure is smaller than the width of the first test pad of the base structure, and an air gap is provided between the first test pad of the base structure and the second test pad of the semiconductor chip, and the air gap surrounds a portion of the first test pad and a portion of the second test pad. Claim 20 In claim 19, the second test pad includes a contact surface that contacts the first test pad, and the air gap surrounds the contact surface in a semiconductor device.

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