Semiconductor element, electronic system including the semiconductor element, and method for fabricating the semiconductor element

Abstract

An embodiment according to the present disclosure provides a semiconductor device comprising: a substrate; a source region and a drain region formed spaced apart from each other by a trench formed in the substrate; a gate insulating layer covering the bottom surface and side wall of the trench; a gate electrode comprising a lower embedded portion provided inside the trench and surrounded by the gate insulating layer and filling the lower region of the trench, and an upper embedded portion provided on the lower embedded portion and surrounded by the gate insulating layer and filling the upper region of the trench; and a capping layer provided on the gate electrode. The upper buried portion comprises a two-dimensional material layer covering the upper surface of the first conductive layer and the upper region of the sidewall of the gate insulating layer within the trench, and a second conductive layer provided to fill the upper region of the trench and be surrounded by the two-dimensional material layer, and may be provided to overlap with the source region and the drain region.

Description

Technology Field

[0001] The technical concept of the present disclosure generally relates to a semiconductor device, an electronic system including a semiconductor device, and a method for manufacturing a semiconductor device, and relates to a semiconductor device that exhibits a minimized GIDL effect by including a two-dimensional material layer, an electronic system including a semiconductor device, and a method for manufacturing a semiconductor device. Background Technology

[0002] Transistors are semiconductor devices that perform the role of electrical switching and are employed in various integrated circuits, including memory, driver ICs, and logic devices. As the integration density of integrated circuits increases, the space occupied by transistors is rapidly shrinking; therefore, research is underway to maintain performance while reducing the size of transistors.

[0003] Recently, research has been conducted on buried channel array transistor (BCAT) structures that can secure a sufficient effective channel distance even with a small occupied area. A BCAT structure includes a structure in which a gate electrode fills a trench formed between the source and drain regions of a substrate. A channel is formed beneath the gate electrode buried in the trench by the potential formed between the source and drain regions. As such, since the gate electrode is buried in the trench formed between the source and drain regions, a portion of the gate electrode overlaps with the source and drain regions.

[0004] In this case, as the integration density of the integrated circuit device increases, the thickness of the gate insulating layer provided between the gate electrode and the source and drain regions decreases, and consequently, a gate-induced drain leakage (GIDL) effect occurs in which the charge stored in the capacitor connected to the drain region is discharged, thereby degrading the performance of the semiconductor device.

[0005] Patent document KR 10-2250583 B1 forms an n-type polysilicon layer having a low work function in the upper region of the gate electrode adjacent to the source and drain regions to reduce the GIDL effect of a semiconductor device. However, although n-type polysilicon has a small work function, it has low electrical conductivity compared to metal, so it can degrade the performance of the gate electrode. The problem to be solved

[0006] According to various embodiments of the present disclosure, the present invention aims to provide a semiconductor device having a structure in which a two-dimensional material layer is provided in an upper region of a gate electrode adjacent to source and drain regions, an electronic system including the semiconductor device, and a method for manufacturing a semiconductor device. means of solving the problem

[0007] One embodiment is,

[0008] A semiconductor device is provided comprising: a substrate including a trench; a source region and a drain region formed on the substrate and spaced apart from each other by the trench; a gate insulating layer covering the bottom surface and side wall of the trench; a gate electrode including a lower filling portion that fills the lower region of the trench and is surrounded by the gate insulating layer within the trench, and an upper filling portion that fills the upper region of the trench and is surrounded by the gate insulating layer on the lower filling portion, and a capping layer provided on the gate electrode.

[0009] The lower buried portion may include a barrier layer covering the lower region of the bottom surface and side wall of the gate insulating layer inside the trench, and a first conductive layer filled in the lower region of the trench and surrounded by the barrier layer, and may be provided so as not to overlap with the source region and the drain region.

[0010] The upper buried portion may include a two-dimensional material layer covering the upper surface of the first conductive layer and the upper region of the sidewall of the gate insulating layer within the trench, and a second conductive layer provided to fill the upper region of the trench and be surrounded by the two-dimensional material layer, and may be provided to overlap with the source region and the drain region.

[0011] The work function of the second conductive layer may be smaller than the work function of the first conductive layer.

[0012] The work function of the second conductive layer may be 2 eV to 5 eV.

[0013] The second conductive layer may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).

[0014] The above two-dimensional material layer may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide.

[0015] The above transition metal dichalcogenide may include one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

[0016] The first thickness of the lower region of the gate insulating layer surrounding the barrier layer may be thinner than the second thickness of the upper region of the gate insulating layer surrounding the two-dimensional material layer.

[0017] The first dielectric constant of the lower region of the gate insulating layer surrounding the barrier layer may be greater than the second dielectric constant of the upper region of the gate insulating layer surrounding the two-dimensional material layer.

[0018] The material included in the first conductive layer and the material included in the second conductive layer may be different from each other.

[0019] The first conductive layer above may include tungsten (W).

[0020] The above barrier layer may include titanium nitride.

[0021] Another example is,

[0022] A semiconductor device is provided comprising a substrate including a trench, a source region and a drain region formed on the substrate spaced apart from each other by the trench, a gate insulating layer covering the bottom surface and sidewall of the trench, a barrier layer arranged to be surrounded by the gate insulating layer inside the trench and covering the lower region of the bottom surface and sidewall of the gate insulating layer inside the trench, a two-dimensional material layer covering the upper region of the sidewall of the gate insulating layer inside the trench, and a gate electrode including a conductive layer that fills the trench and is arranged to be surrounded by the barrier layer and the two-dimensional material layer, and a capping layer arranged on the gate electrode.

[0023] The barrier layer is provided so as not to overlap with the source region and the drain region, and the two-dimensional material layer can be provided so as to overlap with the source region and the drain region.

[0024] The conductive layer may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).

[0025] The above two-dimensional material layer

[0026] It may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide.

[0027] The above transition metal dichalcogenide may include one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

[0028] One embodiment is,

[0029] A method for manufacturing a semiconductor device is provided, comprising the steps of: forming a trench in a substrate; forming a gate insulating layer covering the bottom surface and sidewalls of the trench; forming a gate electrode that fills the trench on the gate insulating layer; forming a capping layer on the gate electrode; and forming a source region and a drain region in the substrate on both sides of the gate electrode.

[0030] The step of forming the gate electrode may include the step of forming a barrier layer covering the lower region of the bottom surface and sidewall of the gate insulating layer inside the trench, the step of forming a two-dimensional material layer covering the upper region of the sidewall of the gate insulating layer inside the trench, and the step of forming a conductive layer arranged to be surrounded by the barrier layer and the two-dimensional material layer inside the trench.

[0031] The work function of the upper region of the conductive layer surrounded by the above two-dimensional material layer can be formed to be smaller than the work function of the lower region of the conductive layer surrounded by the above barrier layer.

[0032] In the step of forming the above two-dimensional material layer, the two-dimensional material layer can be formed using chemical vapor deposition (CVD).

[0033] In the step of forming the above two-dimensional material layer, hydrogen radicals can be supplied to form the two-dimensional material layer.

[0034] In the step of forming the above two-dimensional material layer, oxygen radicals can be supplied to form the two-dimensional material layer.

[0035] The step of forming a conductive layer within the trench that is surrounded by the barrier layer and the two-dimensional material layer may include, after the step of forming the barrier layer and before the step of forming the two-dimensional material layer, a step of forming a first conductive layer that fills the lower region of the trench and is surrounded by the barrier layer, and after the step of forming the two-dimensional material layer, a step of forming a second conductive layer that fills the upper region of the trench and is surrounded by the two-dimensional material layer.

[0036] In the step of forming the above two-dimensional material layer, the two-dimensional material layer can be formed such that the two-dimensional material layer simultaneously covers the upper surface of the first conductive layer and the upper region of the sidewall of the gate insulating layer inside the trench.

[0037] The second conductive layer may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).

[0038] The above two-dimensional material layer may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide.

[0039] One embodiment is,

[0040] An electronic system is provided comprising a controller, a memory that stores commands executed by the controller and includes a semiconductor device according to any one of claims 1 to 15, and an input / output device capable of inputting user commands to the controller. Effects of the invention

[0041] According to various embodiments of the present disclosure, a semiconductor device having a structure in which a two-dimensional material layer is provided in an upper region of a gate electrode adjacent to source and drain regions, an electronic system including the semiconductor device, and a method for manufacturing a semiconductor device may be provided.

[0042] According to various embodiments of the present disclosure, a method for manufacturing a semiconductor device that can minimize the GIDL effect can be provided by supplying hydrogen radicals to lower the dielectric constant of an adjacent gate insulating layer or supplying oxygen radicals to increase the thickness of an adjacent gate insulating layer during the process of forming a two-dimensional material layer. Brief explanation of the drawing

[0043] FIG. 1 is a plan view illustrating an exemplary configuration of a semiconductor device according to one embodiment. Figure 2 is a cross-sectional view along the line A-A' of Figure 1. Figure 3 is a graph showing the change in work function before and after contact with a two-dimensional material of various types of metallic materials. FIG. 4 is a side cross-sectional view illustrating an exemplary configuration of a semiconductor device according to another embodiment. FIG. 5 is a side cross-sectional view illustrating an exemplary configuration of a semiconductor device according to another embodiment. FIG. 6 briefly illustrates an exemplary configuration of a semiconductor device array according to one embodiment. FIG. 7 briefly illustrates an exemplary configuration of a memory device according to one embodiment. FIGS. 8 to 16 are intended to explain a method for manufacturing a semiconductor device according to one embodiment. FIGS. 17 to 22 are intended to explain a method for manufacturing a semiconductor device according to another embodiment. FIG. 23 is a circuit diagram of a CMOS inverter according to one embodiment. FIG. 24 is a circuit diagram of a CMOS SRAM device according to one embodiment. FIG. 25 is a circuit diagram of a CMOS NAND circuit according to one embodiment. FIG. 26 is a block diagram illustrating an electronic system according to one embodiment. FIG. 27 is a block diagram of an electronic system according to one embodiment. Specific details for implementing the invention

[0044] Below, with reference to the attached drawings, semiconductor devices, electronic systems including semiconductor devices, and methods for manufacturing semiconductor devices according to various embodiments are described in detail to enable those skilled in the art to easily implement them. In the drawings, the same reference numerals refer to the same components, and the size or thickness of each component may be exaggerated for clarity of explanation.

[0045] Meanwhile, the semiconductor device, the electronic system including the semiconductor device, and the method for manufacturing the semiconductor device described below may be implemented in various different forms and are not limited to the embodiments described herein. Terms such as "first," "second," etc., may be used to describe various components, but the components should not be limited by these terms. The terms are used solely for the purpose of distinguishing one component from another.

[0046] In the following, terms written as "upper" or "upper" may include not only those directly above in contact but also those above without contact. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0047] Throughout the specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0048] The use of the term “for the above” and similar descriptive terms may be in both singular and plural. All examples or the use of exemplary terms are merely intended to describe the technical concept in detail and, unless limited by the claims, the scope is not limited by such examples or exemplary terms.

[0049] Unless there is an explicit statement that the steps constituting the method must be performed in the described order, they may be performed in a suitable order. Furthermore, the use of all exemplary terms (e.g., etc.) is merely intended to describe the technical concept in detail and, unless limited by the claims, such terms do not limit the scope of the rights.

[0050] FIG. 1 is a plan view illustrating an exemplary configuration of a semiconductor device (100) according to one embodiment. FIG. 2 is a cross-sectional view along the line A-A' of FIG. 1. FIG. 3 is a graph showing the change in work function before and after contact with a two-dimensional material of various types of metal materials.

[0051] Referring to FIGS. 1 and 2, the semiconductor device (100) may include a substrate (10) including a trench (T1), a source region (71) and a drain region (72) formed on the substrate (10) spaced apart from each other by the trench (T1), a gate insulating layer (60) covering the bottom surface and side wall of the trench (T1), a gate electrode (40) including a lower embedded portion (41) that fills the lower region of the trench (T1) and is surrounded by the gate insulating layer (60) inside the trench (T1), and an upper embedded portion (42) that fills the upper region of the trench (T1) and is surrounded by the gate insulating layer (60) on the lower embedded portion (41), and a capping layer (50) provided on the gate electrode (40).

[0052] The substrate (10) may include a semiconductor substrate. The substrate (10) may include a material containing silicon. The substrate (10) may include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate (10) may include other semiconductor materials such as germanium. The substrate (10) may include a compound semiconductor substrate such as a group V semiconductor substrate, e.g., GaAs. The substrate (10) may include a Silicon On Insulator (SOI) substrate. A trench (T1) may be formed in the substrate (10) by etching a portion of the substrate (10) in the vertical direction (z).

[0053] A source region (71) and a drain region (72) may be formed on the substrate (10) and spaced apart from each other in the horizontal direction (y) by a trench (T1). The source region (71) and the drain region (72) may be arranged parallel to the upper region of the trench (T1). For example, the upper surface of the source region (71) and the drain region (72) and the upper surface of the substrate (10) may be provided on the same plane. Additionally, the lower surface of the source region (71) and the drain region (72) may be located higher than the bottom surface of the trench (T1). Furthermore, the source region (71) and the drain region (72) may be in contact with the side wall of the trench (T1).

[0054] The source region (71) and drain region (72) can be formed by doping impurities into a portion of the substrate (10). For example, the source region (71) and drain region (72) can be formed by doping any one of phosphorus (P), arsenic (As), antimony (Sb), and boron (B) into a portion of the substrate (10).

[0055] A gate structure (100G) may be provided within a trench (T1). The gate structure (100G) may include a gate electrode (40), a capping layer (50), and a gate insulating layer (60). The gate electrode (40) may partially fill the interior of the trench (T1). Thus, the gate electrode (40) may be referred to as a buried gate electrode. The capping layer (50) may be provided on the gate electrode (40). The gate insulating layer (60) may be provided to cover the bottom surface and side walls of the trench (T1). For example, the gate electrode (40) may partially fill the interior of the trench (T1), and the gate insulating layer (60) may be formed to surround the gate electrode (40) by being provided between the substrate (10) and the gate electrode (40). Accordingly, the gate electrode (40) may not be in direct contact with the bottom surface and side walls of the trench (T1).

[0056] The gate insulating layer (60) may comprise silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may comprise a material having a dielectric constant greater than the dielectric constant of silicon oxide. For example, the high-k material may comprise a material having a dielectric constant greater than 3.9. In another example, the high-k material may comprise a material having a dielectric constant greater than 10. In yet another example, the high-k material may comprise a material having a dielectric constant of 10 to 30. The high-k material may comprise at least one metallic element. The high-k material may comprise a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In another embodiment, the high dielectric material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and combinations thereof. Other known high dielectric materials may optionally be used as the high dielectric material.

[0057] The gate electrode (40) may include a lower embedded portion (41) and an upper embedded portion (42). The lower embedded portion (41) may include a barrier layer (31) and a first conductive layer (32). The barrier layer (31) may be formed to cover the lower region of the bottom surface and side wall of the gate insulating layer (60) inside the trench (T1). The first conductive layer (32) may be provided to fill the lower region of the trench (T1) and be surrounded by the barrier layer (31). For example, the first conductive layer (32) may partially fill the lower region inside the trench (T1), and the barrier layer (31) may be formed to surround the first conductive layer (32) by being provided between the gate insulating layer (60) and the first conductive layer (32). Accordingly, the first conductive layer (32) may not be in direct contact with the bottom surface and side wall of the gate insulating layer (60). The barrier layer (31) prevents the metal material contained in the first conductive layer (32) from diffusing into the gate insulating layer (60). Additionally, since the lower buried portion (41) is provided in the lower region inside the trench (T1), it may not overlap with the source region (71) and drain region (72) which are arranged parallel to the upper region of the trench (T1).

[0058] When a potential is formed between the source region (71) and the drain region (72), a channel (CH) is formed around the lower buried portion (41) buried in the trench (T1).

[0059] The barrier layer (31) may include titanium nitride. For example, the barrier layer (31) may include TiN. The first conductive layer (32) may include a conductive metallic material. For example, the first conductive layer (32) may include tungsten (W). However, it is not limited thereto, and the first conductive layer (32) may include other metallic materials other than tungsten (W).

[0060] The upper embedded portion (42) may include a two-dimensional material layer (33) and a second conductive layer (34). The two-dimensional material layer (33) may be formed to cover the upper surface of the first conductive layer (32) and the upper region of the sidewall of the gate insulating layer (60) inside the trench (T1). The second conductive layer (34) may be provided to fill the upper region of the trench (T1) and be surrounded by the two-dimensional material layer (33). For example, the second conductive layer (34) may partially fill the upper region inside the trench (T1), and the two-dimensional material layer (33) may be provided between the gate insulating layer (60) and the second conductive layer (34) to surround the second conductive layer (34). Accordingly, the second conductive layer (34) may not be in direct contact with the bottom surface and sidewall of the gate insulating layer (60). The two-dimensional material layer (33) surrounds the second conductive layer (34), but may not cover the upper surface of the second conductive layer (34). Accordingly, the upper surface of the second conductive layer (34) and the two-dimensional material layer (33) may not come into contact with each other.

[0061] A capping layer (50) may be provided on the upper surface of the second conductive layer (34). In this case, the second conductive layer (34) may be formed to extend to the side of the capping layer (50). Accordingly, the side of the capping layer (50) may be surrounded by the second conductive layer (34). For example, the capping layer (50) may be filled into a capping layer trench (T2) formed by the upper surface of the second conductive layer (34) and the upper region of the inner side wall of the two-dimensional material layer (33).

[0062] The capping layer (50) may include an insulating material. For example, the capping layer (50) may include silicon nitride, silicon oxide nitride, or a combination thereof. Additionally, the capping layer (50) may include a combination of silicon nitride and silicon oxide. For example, to form the capping layer (50), it may be lined with silicon nitride and then filled with a spin-on dielectric (SOD).

[0063] Since the two-dimensional material layer (33) is formed to cover the upper surface of the first conductive layer (32), the lower surface of the second conductive layer (34) surrounded by the two-dimensional material layer (33) may not come into direct contact with the upper surface of the first conductive layer (32). In this way, the two-dimensional material layer (33) can act as a barrier between the first conductive layer (32) and the second conductive layer (34). Furthermore, since the upper buried portion (42) is provided in the upper region inside the trench (T1), it may overlap with the source region (71) and the drain region (72) which are arranged parallel to the upper region of the trench (T1).

[0064] The two-dimensional material layer (33) may include various types of two-dimensional materials. For example, the two-dimensional material layer (33) may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide. Transition metal dichalcogenides may include one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

[0065] The second conductive layer (34) may include a conductive metallic material. The second conductive layer (34) may include a metallic material different from that of the first conductive layer (32). When the metallic material included in the second conductive layer (34) comes into contact with the two-dimensional material included in the two-dimensional material layer (33), a dipole is formed at the interface between the metallic material and the two-dimensional material, and accordingly, the work function of the second conductive layer (34) may be reduced.

[0066] For example, the second conductive layer (34) may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt). Referring to FIG. 3, when a metal material such as aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt) comes into contact with a two-dimensional material such as graphene, two-dimensional hexagonal boron nitride (h-BN), the work functions of each metal material decrease. However, it is not limited thereto, and the second conductive layer (32) may include various other metal materials whose work functions decrease when in contact with a two-dimensional material other than aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).

[0067] Meanwhile, the work function of the second conductive layer (34) may be smaller than the work function of the first conductive layer (32). For example, the work function of the second conductive layer (34) may be 2 eV to 5 eV. The work function of the second conductive layer (34) that overlaps the source region (71) and the drain region (72) is formed to be sufficiently small so that the GIDL phenomenon can be effectively minimized. In addition, since the second conductive layer (34) includes a metal material, the conductivity of the gate electrode (40), which is sufficiently necessary for operating as a switching element, can be secured.

[0068] Additionally, if the gate insulating layer (60) includes silicon oxide, the gate insulating layer (60) may have different dielectric constants depending on the region. For example, the first dielectric constant (ε1) of the lower region of the gate insulating layer (60) surrounding the barrier layer (31) may be greater than the second dielectric constant (ε2) of the upper region of the gate insulating layer (60) surrounding the two-dimensional material layer (33). The upper region of the gate insulating layer (60) may include silicon oxycarbide, and accordingly, may have a smaller dielectric constant compared to the lower region of the gate insulating layer (60) which includes only silicon oxide. In this way, compared to the case where the upper region of the gate insulating layer (61) has the same first dielectric constant (ε1) as the lower region, when it has the second dielectric constant (ε2), the capacitance between the upper buried portion (42) and the drain region (72) is reduced, so that the GIDL phenomenon can be effectively minimized.

[0069] FIG. 4 is a side cross-sectional view illustrating an exemplary configuration of a semiconductor device (110) according to another embodiment. The semiconductor device (110) of FIG. 4 may be substantially identical to the semiconductor device (100) of FIG. 2, except that the thickness of the upper region and the thickness of the lower region of the gate insulating layer (61) are different. In describing FIG. 4, content that overlaps with FIG. 1 to FIG. 3 is omitted.

[0070] Referring to FIG. 4, the semiconductor device (110) may include a substrate (10) including a trench (T1), a source region (71) and a drain region (72) formed on the substrate (10) spaced apart from each other by the trench (T1), a gate insulating layer (61) covering the bottom surface and side wall of the trench (T1), a gate electrode (44) including a lower embedded portion (41) that fills the lower region of the trench (T1) and is surrounded by the gate insulating layer (61) inside the trench (T1), and an upper embedded portion (43) that fills the upper region of the trench (T1) and is surrounded by the gate insulating layer (61) on the lower embedded portion (41), and a capping layer (51) provided on the upper embedded portion (43).

[0071] The gate insulating layer (61) may be provided to cover the bottom surface and side walls of the trench (T1). For example, the gate electrode (44) may partially fill the interior of the trench (T1), and the gate insulating layer (61) may be formed to surround the gate electrode (44) by being provided between the substrate (10) and the gate electrode (44). Accordingly, the gate electrode (44) may not come into direct contact with the bottom surface and side walls of the trench (T1).

[0072] Additionally, the gate insulating layer (61) may have different thicknesses depending on the region. For example, the first thickness (t1) of the lower region of the gate insulating layer (61) surrounding the barrier layer (31) may be thinner than the second thickness (t2) of the upper region of the gate insulating layer (61) surrounding the two-dimensional material layer (35). Thus, compared to the case where the upper region of the gate insulating layer (61) has the same first thickness (t1) as the lower region, when it has the second thickness (t2), the capacitance between the upper buried portion (43) and the drain region (72) is reduced, so that the GIDL phenomenon can be effectively minimized.

[0073] The upper embedded portion (43) may include a two-dimensional material layer (35) and a second conductive layer (36). The upper embedded portion (43) may be substantially the same as the upper embedded portion (42) of FIG. 2, except that it has a narrower width as the thickness of the upper region of the gate insulating layer (61) becomes thicker.

[0074] The capping layer (51) may be substantially the same as the capping layer (50) of FIG. 2, except that it has a narrower width as the width of the two-dimensional material layer (35) narrows. For example, the capping layer (51) may be filled into a capping layer trench (T3) formed by the upper surface of the second conductive layer (36) and the upper region of the inner sidewall of the two-dimensional material layer (35).

[0075] FIG. 5 is a side cross-sectional view illustrating an exemplary configuration of a semiconductor device (120) according to another embodiment. The semiconductor device (120) of FIG. 5 may be substantially identical to the semiconductor device (110) of FIG. 4, except that the gate electrode (45) includes a single conductive layer (38), unlike the gate electrode (44) of FIG. 4 which includes a first conductive layer (32) and a second conductive layer (36). In describing FIG. 5, content that overlaps with FIG. 1 to FIG. 4 is omitted.

[0076] Referring to FIG. 5, the semiconductor device (120) may include a substrate (10) including a trench (T1), a source region (71) and a drain region (72) formed on the substrate (10) separated from each other by the trench (T1), a gate insulating layer (61) covering the bottom surface and side wall of the trench (T1), a gate electrode (45) arranged to be surrounded by the gate insulating layer (61) inside the trench (T1), and a capping layer (51) arranged on the gate electrode (45).

[0077] The gate electrode (45) is provided to be surrounded by a gate insulating layer (61) inside the trench (T1), and may include a barrier layer (37) covering the lower region of the bottom surface and sidewall of the gate insulating layer (61) inside the trench (T1), a two-dimensional material layer (39) covering the upper region of the sidewall of the gate insulating layer (61) inside the trench (T1), and a conductive layer (38) that fills the trench (T1) and is provided to be surrounded by the barrier layer (37) and the two-dimensional material layer (39). The lower region of the conductive layer (38) may be surrounded by the barrier layer (37), and the upper region may be surrounded by the two-dimensional material layer (39).

[0078] The conductive layer (38) may include a conductive metallic material. The conductive layer (38) may include the same metallic material as the second conductive layer (36) of FIG. 4. The work function of the upper region of the conductive layer (38) in contact with the two-dimensional material layer (39) may be smaller than the work function of the lower region of the conductive layer (38) in contact with the barrier layer (37). For example, the conductive layer (38) may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).

[0079] FIG. 6 briefly illustrates an exemplary configuration of a semiconductor device array (200) according to one embodiment.

[0080] Referring to FIG. 6, the semiconductor device array (200) may include a substrate (11) having a plurality of trenches (T4, T5), a plurality of gate structures (201G, 202G) provided in the plurality of trenches (T4, T5), and a plurality of source regions (S1~S12) and a plurality of drain regions (D1~D12) formed spaced apart from each other with each of the plurality of trenches (T4, T5) in between.

[0081] A plurality of trenches (T4, T5) may be formed on a substrate (11) by extending in a first direction (x) and arranged in parallel in a second direction (y) that intersects the first direction (x). Here, the first direction (x) and the second direction (y) may be perpendicular to each other. A first gate structure (201G) included in a plurality of gate structures (201G, 202G) may be provided in the first trench (T4) included in the plurality of trenches (T4, T5). Additionally, a second gate structure (202G) included in a plurality of gate structures (201G, 202G) may be provided in the second trench (T5) included in the plurality of trenches (T4, T5). A plurality of gate structures (201G, 202G) are formed by extending in a first direction (x) similar to a plurality of trenches (T4, T5) and can be arranged side by side in a second direction (y).

[0082] A plurality of source regions (S1~S12) and a plurality of drain regions (D1~D12) may share any one of a plurality of gate structures (201G, 202G). For example, a plurality of source regions (S1~S6) and a plurality of drain regions (D1~D6) may face each other with the first gate structure (201G) in between. Additionally, a plurality of source regions (S7~S12) and a plurality of drain regions (D7~D12) may face each other with the second gate structure (202G) in between. A first source region (S1) among the plurality of source regions (S1~S12) facing each other with the first gate structure (201G) in between and a first drain region (D1) among the plurality of drain regions (D1~D12) may form a first semiconductor device. The first semiconductor device may include any one of the various types of semiconductor devices (100, 110, 120) described with reference to FIGS. 1 to 5. In this way, a plurality of semiconductor devices may be formed along each of the plurality of gate structures (201G, 202G).

[0083] FIG. 7 briefly illustrates an exemplary configuration of a memory element (1000) according to one embodiment.

[0084] Referring to FIG. 7, the memory element (1000) may include a semiconductor element (100) and a capacitor (300). The semiconductor element (100) is identical to the semiconductor element (100) described with reference to FIG. 1 and FIG. 2. However, it is not limited thereto, and the memory element (1000) may include any one of the various types of semiconductor elements (110, 120) described with reference to FIG. 4 and FIG. 5. In describing FIG. 7, reference is made to the contents of FIG. 2.

[0085] A semiconductor device (100) can operate as a switching device. A capacitor (300) may be provided on the semiconductor device (100). For example, an interlayer insulating film (90) covering a source region (71), a drain region (72), and a gate structure (100G) may be provided on a substrate (10). The interlayer insulating film (90) may include an insulating material. For example, the interlayer insulating film (90) may include silicon oxide (e.g., SiO2) or aluminum oxide (e.g., Al2O3). A capacitor (300) may be provided on the interlayer insulating film (90). The capacitor (300) may include a lower electrode (91) provided on the interlayer insulating film (90), a dielectric film (92) provided on the lower electrode (91), and an upper electrode (93) provided on the dielectric film (92). The lower electrode (91) and the upper electrode (93) may include various types of conductive materials. The dielectric film (92) may contain various types of insulating materials.

[0086] A via hole may be formed in a portion of the interlayer insulating film (90), and a contact (94) may be filled into the via hole. The contact (94) may include various types of conductive materials. For example, the via hole may be formed to expose a drain region (72), and the contact (94) may be arranged to be in contact with the drain region (72). A capacitor (300) may be arranged on the interlayer insulating film (90) to be in contact with the contact (94). Accordingly, the capacitor (300) may be electrically connected to the drain region (72) through the contact (94).

[0087] FIGS. 8 to 16 are intended to explain a method for manufacturing a semiconductor device according to one embodiment.

[0088] Referring to FIG. 8, a method for manufacturing a semiconductor device according to one embodiment may include the steps of forming a trench in a substrate (S101), forming a gate insulating layer covering the bottom surface and sidewalls of the trench (S102), forming a gate electrode that fills the trench on the gate insulating layer (S103), forming a capping layer on the gate electrode (S104), and forming a source region and a drain region in the substrate on both sides of the gate electrode (S105).

[0089] Additionally, in the step of forming a gate electrode (S103), a gate electrode including a barrier layer, a first conductive layer, a two-dimensional material layer, and a second conductive layer may be formed. For example, the step of forming a gate electrode (S103) may include, as illustrated in FIG. 9, a step of forming a barrier layer that covers the bottom surface of the gate insulating layer and the lower region of the sidewall inside the trench (S201); a step of forming a first conductive layer that fills the lower region of the trench and is surrounded by the barrier layer (S202); a step of forming a two-dimensional material layer that simultaneously covers the upper surface of the first conductive layer and the upper region of the sidewall of the gate insulating layer inside the trench (S203); and a step of forming a second conductive layer that fills the upper region of the trench and is surrounded by the two-dimensional material layer (S204).

[0090] For example, referring to FIG. 10, a trench (T6) can be formed by patterning a part of the substrate (10).

[0091] Referring to FIG. 11, a gate insulating layer (16) can be formed on a substrate (10) to cover the bottom surface and sidewalls of a trench (T6). A preliminary barrier layer (17A) can be formed on the gate insulating layer (16). A preliminary first conductive layer (19A) can be formed on the preliminary barrier layer (17A) to fill the preliminary barrier layer trench (T6).

[0092] Referring to FIG. 12, a lower embedded portion (20) can be formed by patterning a preliminary barrier layer (17A) and a preliminary first conductive layer (19A) to contact the lower region of the sidewall of the gate insulating layer (16) within the trench (T6). The lower embedded portion (20) may include a barrier layer (17) covering the bottom surface of the gate insulating layer (16) and the lower region of the sidewall, and a first conductive layer (19) that fills the lower region of the trench (T6) and is surrounded by the barrier layer (17).

[0093] Referring to FIG. 13, a preliminary two-dimensional material layer (21A) covering the upper surface of the first conductive layer (19) and the gate insulating layer (16) can be formed. The preliminary two-dimensional material layer (21A) can be formed using chemical vapor deposition (CVD).

[0094] In the process of forming a preliminary two-dimensional material layer (21A) by the CVD method, hydrogen radicals can be supplied. In this case, if the gate insulating layer (16) adjacent to the preliminary two-dimensional material layer (21A) contains silicon oxide, the composition of a portion of the upper region of the gate insulating layer (16) can be changed to silicon oxycarbide, and accordingly, the upper region of the gate insulating layer (16) can have a smaller dielectric constant compared to the lower region of the gate insulating layer (16) which contains only silicon oxide.

[0095] Additionally, oxygen radicals can be supplied during the process of forming a preliminary two-dimensional material layer (21A) using the CVD method. In this case, the thickness of the gate insulating layer (16) adjacent to the preliminary two-dimensional material layer (21A) can be increased. Accordingly, the thickness of the upper region of the gate insulating layer (16) can be greater than the thickness of the lower region of the gate insulating layer (16).

[0096] Referring to FIG. 14, a preliminary two-dimensional material layer (21A) can be patterned to form a two-dimensional material layer (21) that covers the upper surface of the first conductive layer (19) and the upper region of the sidewall of the gate insulating layer (16). Additionally, a preliminary second conductive layer (23A) can be formed to fill the upper region of the trench (T6) on the gate insulating layer (16).

[0097] Referring to FIG. 15, a preliminary second conductive layer (23A) can be patterned to partially fill the upper region of the trench (T6) and form a second conductive layer (23) surrounded by a two-dimensional material layer (21). For example, the upper surface of the second conductive layer (23) may be lower than the upper surface of the substrate (10). Accordingly, a capping layer trench (T7) that exposes a portion of the gate insulating layer (16) may be formed. Additionally, during the process of patterning the preliminary second conductive layer (23A), a portion of the gate insulating layer (16) provided on the upper surface of the substrate (10) may also be patterned together.

[0098] Referring to FIG. 16, a capping layer (52) that fills the capping layer trench (T7) can be formed.

[0099] The semiconductor device (130) of FIG. 16 can be manufactured by the semiconductor device manufacturing method described with reference to FIG. 8 to FIG. 16. The semiconductor device (130) may include a structure in which a gate structure (130G) is embedded in a trench (T6). The semiconductor device (130) may be substantially the same as the semiconductor device (110) of FIG. 4.

[0100] FIGS. 17 to 22 are intended to explain a method for manufacturing a semiconductor device according to another embodiment.

[0101] In the step (S103) of forming the gate electrode of FIG. 8, a gate electrode including a barrier layer, a two-dimensional material layer, and a conductive layer can be formed. For example, the step (S103) of forming the gate electrode may include, as shown in FIG. 17, a step (S301) of forming a barrier layer covering the bottom surface of the gate insulating layer and the lower region of the sidewall inside the trench, a step (S302) of forming a two-dimensional material layer covering the upper region of the sidewall of the gate insulating layer inside the trench, and a step (S303) of forming a conductive layer arranged to be surrounded by the barrier layer and the two-dimensional material layer inside the trench.

[0102] For example, referring to FIG. 18, a portion of the substrate (10) may be patterned to form a trench (T6), and a gate insulating layer (16) may be formed on the substrate (10) to cover the bottom surface and sidewalls of the trench (T6). A barrier layer (17) may be formed on the gate insulating layer (16) to cover the lower region of the bottom surface and sidewalls of the gate insulating layer (16).

[0103] Referring to FIG. 19, a two-dimensional material layer (22) can be formed to cover the upper region of the sidewall of the gate insulating layer (16). In this case, the upper end of the barrier layer (17) and the lower end of the two-dimensional material layer (22) can come into contact. For example, a preliminary two-dimensional material layer (22) can be formed using chemical vapor deposition (CVD).

[0104] In the process of forming a two-dimensional material layer (22) using the CVD method, hydrogen radicals can be supplied. In this case, if the gate insulating layer (16) adjacent to the two-dimensional material layer (22) contains silicon oxide, the composition of a portion of the upper region of the gate insulating layer (16) can be changed to silicon oxycarbide, and accordingly, the upper region of the gate insulating layer (16) can have a smaller dielectric constant compared to the lower region of the gate insulating layer (16) which contains only silicon oxide.

[0105] Additionally, oxygen radicals can be supplied during the process of forming the two-dimensional material layer (22) using the CVD method. In this case, the thickness of the gate insulating layer (16) adjacent to the two-dimensional material layer (22) can be increased. Accordingly, the thickness of the upper region of the gate insulating layer (16) can be greater than the thickness of the lower region of the gate insulating layer (16).

[0106] Referring to FIG. 20, a preliminary conductive layer (29A) can be formed to fill a trench (T6) on the gate insulating layer (16).

[0107] Referring to FIG. 21, a preliminary second conductive layer (29A) can be patterned to partially fill a trench (T6) and form a conductive layer (29) surrounded by a barrier layer (17) and a two-dimensional material layer (22). In this case, the lower region of the conductive layer (29) can be surrounded by the barrier layer (17), and the upper region can be surrounded by the two-dimensional material layer (22). Additionally, the upper surface of the conductive layer (29) can be lower than the upper surface of the substrate (10). Accordingly, a capping layer trench (T8) that exposes a portion of the gate insulating layer (16) can be formed. Furthermore, during the process of patterning the preliminary second conductive layer (29A), a portion of the gate insulating layer (16) provided on the upper surface of the substrate (10) can also be patterned together.

[0108] Referring to FIG. 22, a capping layer (52) that fills the capping layer trench (T8) can be formed.

[0109] The semiconductor device (140) of FIG. 22 can be manufactured by the semiconductor device manufacturing method described with reference to FIG. 8 and FIG. 17 to FIG. 22. The semiconductor device (140) may include a structure in which a gate structure (140G) is embedded in a trench (T6). The semiconductor device (140) may be substantially the same as the semiconductor device (120) of FIG. 5.

[0110] FIG. 23 is a circuit diagram of a CMOS inverter (600) according to one embodiment.

[0111] The CMOS inverter (600) includes a CMOS transistor (610). The CMOS transistor (610) is composed of a PMOS transistor (620) and an NMOS transistor (630) connected between a power terminal (Vdd) and a ground terminal. The CMOS transistor (610) may include at least one of the semiconductor devices (100, 110, 120) according to the various embodiments described above with reference to FIGS. 1 to 5.

[0112] FIG. 24 is a circuit diagram of a CMOS SRAM device (700) according to one embodiment.

[0113] The CMOS SRAM device (700) includes a pair of driving transistors (710). The pair of driving transistors (710) each consists of a PMOS transistor (720) and an NMOS transistor (730) connected between a power terminal (Vdd) and a ground terminal. The CMOS SRAM device (700) may further include a pair of transfer transistors (740). The source of the transfer transistor (740) is cross-connected to the common node of the PMOS transistor (720) and the NMOS transistor (730) constituting the driving transistor (710). The power terminal (Vdd) is connected to the source of the PMOS transistor (720), and the ground terminal is connected to the source of the NMOS transistor (730). A word line (WL) is connected to the gate of the pair of transfer transistors (740), and a bit line (BL) and an inverted bit line may be connected to the drain of each of the pair of transfer transistors (740), respectively.

[0114] At least one of the driving transistor (710) and the transfer transistor (740) of the CMOS SRAM device (700) may include at least one of the semiconductor devices (100, 110, 120) according to the various embodiments described above with reference to FIGS. 1 to 5.

[0115] FIG. 25 is a circuit diagram of a CMOS NAND circuit (800) according to one embodiment.

[0116] The CMOS NAND circuit (800) includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit (800) may include at least one of the semiconductor devices (100, 110, 120) according to the various embodiments described above with reference to FIGS. 1 to 5.

[0117] FIG. 26 is a block diagram illustrating an electronic system (900) according to one embodiment.

[0118] The electronic system (900) includes a memory (910) and a memory controller (920). The memory controller (920) can control the memory (910) to read data from the memory (910) and / or write data to the memory (910) in response to a request from the host (930). At least one of the memory (910) and the memory controller (920) may include at least one of the semiconductor devices (100, 110, 120) according to the various embodiments described above with reference to FIGS. 1 to 5.

[0119] FIG. 27 is a block diagram of an electronic system (1000) according to one embodiment.

[0120] The electronic system (1000) may be configured as a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic system (1000) includes a controller (1010), an input / output device (I / O) (1020), a memory (1030), and a wireless interface (1040), each of which is interconnected via a bus (1050).

[0121] The controller (1010) may include at least one of a microprocessor, a digital signal processor, or a similar processing device. The input / output device (1020) is a device capable of inputting user commands to the controller (1010) and may include at least one of a keypad, a keyboard, or a display. The memory (1030) may be used to store commands executed by the controller (1010). For example, the memory (1030) may be used to store user data. The electronic system (1000) may use the wireless interface (1040) to transmit / receive data through a wireless communication network. The wireless interface (1040) may include an antenna and / or a wireless transceiver. In some embodiments, the electronic system (1000) may be used in a communication interface protocol of a third-generation communication system, such as CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (extended-time division multiple access), and / or WCDMA (wide band code division multiple access). The electronic system (1000) may include at least one of the semiconductor devices (100, 110, 120) according to the various embodiments described above with reference to FIGS. 1 through 5. For example, the memory (1030) may include at least one of the semiconductor devices (100, 110, 120) according to the various embodiments described above with reference to FIGS. 1 through 5.

[0122] The various embodiments described above are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true scope of technical protection according to the various exemplary embodiments must be determined by the technical concept of the invention as described in the following claims. Explanation of the symbols

[0123] 10, 11: Substrate 16, 60, 61: Gate insulation layer 17, 31, 37: Barrier layer 19, 23, 29, 32, 34, 36, 38: Challenge Layer 21, 22, 33, 35, 39: Two-dimensional material layers 20, 41: Lower buried section 24, 42, 43: Upper buried section 25, 30, 40, 44, 45: Gate electrodes 50, 51, 52: Capping layer 71, 73: Source area 72, 74: Drain area 100, 110, 120, 130, 140: Semiconductor devices 200: Semiconductor device array 300: Capacitor 100G, 110G, 120G, 130G, 140G, 201G, 202G: Gate structure T1, T2, T3, T4, T5, T6, T7, T8: Trench

Claims

Claim 1 A substrate including a trench; a source region and a drain region formed on the substrate and spaced apart from each other by the trench; a gate insulating layer covering the bottom surface and sidewall of the trench; a gate electrode comprising a lower embedded portion that fills the lower region of the trench and is surrounded by the gate insulating layer within the trench, and an upper embedded portion that fills the upper region of the trench and is surrounded by the gate insulating layer on the lower embedded portion; and a capping layer provided on the gate electrode. A semiconductor device comprising: a lower embedded portion, wherein the lower embedded portion comprises a barrier layer covering the lower region of the bottom surface and sidewall of the gate insulating layer inside the trench and a first conductive layer filling the lower region of the trench and surrounded by the barrier layer, and is arranged so as not to overlap with the source region and the drain region; and the upper embedded portion comprises a two-dimensional material layer covering the upper surface of the first conductive layer and the upper region of the sidewall of the gate insulating layer inside the trench and a second conductive layer filling the upper region of the trench and surrounded by the two-dimensional material layer, and is arranged so as to overlap with the source region and the drain region, wherein the first dielectric constant of the lower region of the gate insulating layer is greater than the second dielectric constant of the upper region of the gate insulating layer. Claim 2 A semiconductor device according to claim 1, wherein the work function of the second conductive layer is smaller than the work function of the first conductive layer. Claim 3 A semiconductor device according to claim 1, wherein the work function of the second conductive layer is 2 eV to 5 eV. Claim 4 A semiconductor device according to claim 1, wherein the second conductive layer comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni) and platinum (Pt). Claim 5 A semiconductor device according to claim 1, wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide. Claim 6 A semiconductor device according to claim 5, wherein the transition metal dichalcogenide comprises one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te). Claim 7 A semiconductor device according to claim 1, wherein the first thickness of the lower region of the gate insulating layer surrounding the barrier layer is thinner than the second thickness of the upper region of the gate insulating layer surrounding the two-dimensional material layer. Claim 8 A semiconductor device according to claim 1, wherein the lower region of the gate insulating layer surrounds the barrier layer, and the upper region of the gate insulating layer surrounds the two-dimensional material layer. Claim 9 A semiconductor device according to claim 1, wherein the material comprising the first conductive layer and the material comprising the second conductive layer are different. Claim 10 A semiconductor device according to claim 1, wherein the first conductive layer comprises tungsten (W). Claim 11 A semiconductor device according to claim 1, wherein the barrier layer comprises titanium nitride. Claim 12 A semiconductor device comprising: a substrate including a trench; a source region and a drain region formed on the substrate and spaced apart from each other by the trench; a gate insulating layer covering the bottom surface and sidewall of the trench; a gate electrode provided to be surrounded by the gate insulating layer inside the trench, comprising a barrier layer covering the lower region of the bottom surface and sidewall of the gate insulating layer inside the trench, a two-dimensional material layer covering the upper region of the sidewall of the gate insulating layer inside the trench, and a conductive layer filling the trench and provided to be surrounded by the barrier layer and the two-dimensional material layer; and a capping layer provided on the gate electrode; wherein the barrier layer is provided so as not to overlap with the source region and the drain region, and the two-dimensional material layer is provided to overlap with the source region and the drain region, and the first dielectric constant of the lower region of the gate insulating layer is greater than the second dielectric constant of the upper region of the gate insulating layer. Claim 13 A semiconductor device according to claim 12, wherein the conductive layer comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni) and platinum (Pt). Claim 14 A semiconductor device according to claim 12, wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide. Claim 15 A semiconductor device according to claim 14, wherein the transition metal dichalcogenide comprises one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te). Claim 16 A method for manufacturing a semiconductor device comprising: a step of forming a trench in a substrate; a step of forming a gate insulating layer covering the bottom surface and sidewall of the trench; a step of forming a gate electrode filling the trench on the gate insulating layer; a step of forming a capping layer on the gate electrode; and a step of forming a source region and a drain region in the substrate on both sides of the gate electrode; wherein the step of forming the gate electrode comprises: a step of forming a barrier layer covering the bottom surface and lower region of the sidewall of the gate insulating layer inside the trench; a step of forming a two-dimensional material layer covering the upper region of the sidewall of the gate insulating layer inside the trench; and a step of forming a conductive layer arranged to be surrounded by the barrier layer and the two-dimensional material layer inside the trench, wherein the first dielectric constant of the lower region of the gate insulating layer is greater than the second dielectric constant of the upper region of the gate insulating layer, and the work function of the upper region of the conductive layer surrounded by the two-dimensional material layer is formed to be smaller than the work function of the lower region of the conductive layer surrounded by the barrier layer. Claim 17 A semiconductor device manufacturing method according to claim 16, wherein in the step of forming the two-dimensional material layer, the two-dimensional material layer is formed using chemical vapor deposition (CVD). Claim 18 A semiconductor device manufacturing method according to claim 17, wherein in the step of forming the two-dimensional material layer, hydrogen radicals are supplied to form the two-dimensional material layer. Claim 19 A semiconductor device manufacturing method according to claim 17, wherein in the step of forming the two-dimensional material layer, oxygen radicals are supplied to form the two-dimensional material layer. Claim 20 A method for manufacturing a semiconductor device according to claim 17, wherein the step of forming a conductive layer arranged to be surrounded by the barrier layer and the two-dimensional material layer inside the trench comprises: a step of forming a first conductive layer arranged to be surrounded by the barrier layer and filling the lower region of the trench after the step of forming the barrier layer and before the step of forming the two-dimensional material layer; and a step of forming a second conductive layer arranged to be surrounded by the two-dimensional material layer and filling the upper region of the trench after the step of forming the two-dimensional material layer; wherein, in the step of forming the two-dimensional material layer, the two-dimensional material layer is formed such that the two-dimensional material layer simultaneously covers the upper surface of the first conductive layer and the upper region of the sidewall of the gate insulating layer inside the trench. Claim 21 A method for manufacturing a semiconductor device according to claim 20, wherein the second conductive layer comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni) and platinum (Pt). Claim 22 A method for manufacturing a semiconductor device according to claim 16, wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, or transition metal dichalcogenide. Claim 23 An electronic system comprising: a controller; a memory that stores commands executed by the controller and includes a semiconductor element according to any one of claims 1 to 15; and an input / output device capable of inputting user commands to the controller.

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