Semiconductor device

Abstract

A semiconductor device may be provided comprising a substrate including a first surface and a second surface facing each other, an active pattern protruding from the first surface, a source / drain pattern on the active pattern, an active contact on the source / drain pattern, an upper contact connected to the active contact and extending toward the first surface, a first etching stop film on the second surface, a second etching stop film spaced apart from the substrate with the first etching stop film in between, and a power wiring connected to the upper contact by penetrating the first etching stop film and the substrate, wherein the first etching stop film comprises SiGeC and the second etching stop film comprises SiGeB.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability.

[0006] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device with improved electrical characteristics and reliability. means of solving the problem

[0008] A semiconductor device according to an embodiment of the present invention comprises a substrate including a first surface and a second surface facing each other, an active pattern protruding from the first surface, a source / drain pattern on the active pattern, an active contact on the source / drain pattern, an upper contact connected to the active contact and extending toward the first surface, a first etching stop film on the second surface, and a second etching stop film spaced apart from the substrate with the first etching stop film in between; and a power wiring connected to the upper contact by penetrating the second etching stop film, the first etching stop film, and the substrate, wherein the first etching stop film may comprise SiGeC and the second etching stop film may comprise SiGeB.

[0009] A semiconductor device according to another embodiment of the present invention comprises a substrate including facing first surfaces and second surfaces, an active pattern protruding from the first surface, a source / drain pattern on the active pattern, an active contact on the source / drain pattern, an upper contact connected to the active contact and extending toward the first surface, and a power wiring penetrating the substrate and connected to the upper contact, wherein the substrate includes a doping region, the doping region is formed within a range of 10 nm from the second surface toward the first surface, the doping region includes boron, and the concentration of boron is 1.00E+19 / cm³ 3 Up to 6.00E+20 / cm 3 It can be formed within the range of.

[0010] A semiconductor device according to another embodiment of the present invention comprises a substrate including a first surface and a second surface facing each other, an active pattern protruding from the first surface, a source / drain pattern on the active pattern, an active contact on the source / drain pattern, an upper contact connected to the active contact and extending toward the first surface, an etching stop film on the second surface, and a power wiring connected to the upper contact by penetrating the etching stop film and the substrate, wherein the etching stop film may include SiGeCB. Effects of the invention

[0012] A semiconductor device according to the present invention includes an etching stop layer required for etching a semiconductor substrate. Specifically, the present invention stacks a first etching stop layer containing SiGeC and a second etching stop layer containing SiGeB in sequence on a semiconductor substrate, or forms a third etching stop layer containing SiGeCB alone. According to the present invention, since SiGeB containing boron is etched first compared to a conventional etching stop layer structure, the selectivity ratio for the etchant is higher compared to a conventional etching stop layer structure. In addition, as a higher concentration of boron is found in the semiconductor substrate due to diffusion caused by heat generated during the device fabrication process compared to a conventional etching stop layer structure, it can function as an additional etching stop layer even after the etching stop layer is removed. Brief explanation of the drawing

[0014] FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention. FIG. 4 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 5a to 5d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. FIG. 6 is a drawing of a semiconductor device according to another embodiment of the present invention, and is a cross-sectional view along the line C-C' of FIG. 4. FIGS. 7a and 7b are graphs showing the effects of a semiconductor device according to an embodiment of the present invention. FIGS. 8 to 19 are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 20 is a drawing for illustrating a method of manufacturing a semiconductor device according to some embodiments. FIG. 21 is a drawing of a semiconductor device according to some embodiments, and is a cross-sectional view along the line C-C' of FIG. 4. Specific details for implementing the invention

[0015] The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings.

[0017] FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention.

[0018] Referring to FIG. 1, a Single Height Cell (SHC) may be provided. Specifically, a first lower power line (VPR1) and a second lower power line (VPR2) may be provided on the lower part of the substrate (100). The first lower power line (VPR1) may be a channel for providing a source voltage (VSS), for example, a ground voltage. The second lower power line (VPR2) may be a channel for providing a drain voltage (VDD), for example, a power voltage.

[0019] A single height cell (SHC) may be defined between the first lower power line (VPR1) and the second lower power line (VPR2). The single height cell (SHC) may include one PMOSFET region (PR) and one NMOSFET region (NR). In other words, the single height cell (SHC) may have a CMOS structure provided between the first lower power line (VPR1) and the second lower power line (VPR2).

[0020] Each of the PMOSFET region (PR) and the NMOSFET region (NR) may have a first width in a first direction (D1). The length of the single height cell (SHC) in the first direction (D1) may be defined as a first height (HE1). The first height (HE1) may be substantially equal to the distance (e.g., pitch) between the first lower power line (VPR1) and the second lower power line (VPR2).

[0021] A single height cell (SHC) can constitute a single logic cell. In this specification, a logic cell may refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic cell may include transistors for constituting a logic element and wirings connecting said transistors to each other.

[0022] Referring to FIG. 2, a Double Height Cell (DHC) may be provided. Specifically, a first lower power line (VPR1), a second lower power line (VPR2), and a third lower power line (VPR3) may be provided on a substrate (100). The second lower power line (VPR2) may be positioned between the first lower power line (VPR1) and the third lower power line (VPR3). The third lower power line (VPR3) may be a passage through which a source voltage (VSS) is provided.

[0023] A double height cell (DHC) may be defined between the first lower power line (VPR1) and the third lower power line (VPR3). The double height cell (DHC) may include a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2).

[0024] The first NMOSFET region (NR1) may be adjacent to the first lower power line (VPR1). The second NMOSFET region (NR2) may be adjacent to the third lower power line (VPR3). The first and second PMOSFET regions (PR1, PR2) may be adjacent to the second lower power line (VPR2). In a planar view, the second lower power line (VPR2) may be positioned between the first and second PMOSFET regions (PR1, PR2).

[0025] The length of the double height cell (DHC) in the first direction (D1) can be defined as the second height (HE2). The second height (HE2) may be approximately twice the first height (HE1) of FIG. 1. The first and second PMOSFET regions (PR1, PR2) of the double height cell (DHC) can be combined to operate as a single PMOSFET region. Thus, the channel size of the PMOS transistor of the double height cell (DHC) may be larger than the channel size of the PMOS transistor of the single height cell (SHC) of FIG. 1.

[0026] For example, the channel size of the PMOS transistor in a double-height cell (DHC) may be approximately twice the channel size of the PMOS transistor in a single-height cell (SHC). Consequently, the double-height cell (DHC) can operate at a higher speed than the single-height cell (SHC). In the present invention, the double-height cell (DHC) shown in FIG. 2 may be defined as a multi-height cell. Although not illustrated, the multi-height cell may include a triple-height cell in which the cell height is approximately three times that of the single-height cell (SHC).

[0027] Referring to FIG. 3, a first single height cell (SHC1), a second single height cell (SHC2), and a double height cell (DHC) may be arranged two-dimensionally on a substrate (100). The first single height cell (SHC1) may be placed between the first and second lower power lines (VPR1, VPR2). The second single height cell (SHC2) may be placed between the second and third lower power lines (VPR2, VPR3). The second single height cell (SHC2) may be adjacent to the first single height cell (SHC1) in a first direction (D1).

[0028] A double height cell (DHC) may be placed between the first and third lower power lines (VPR1, VPR3). The double height cell (DHC) may be adjacent to the first and second single height cells (SHC1, SHC2) in the second direction (D2).

[0029] A separation structure (DB) may be provided between the first single-height cell (SHC1) and the double-height cell (DHC), and between the second single-height cell (SHC2) and the double-height cell (DHC). By the separation structure (DB), the active region of the double-height cell (DHC) may be electrically separated from the active region of each of the first and second single-height cells (SHC1, SHC2).

[0030] FIG. 4 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIG. 5a to 5d are cross-sectional views along lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. The semiconductor device illustrated in FIG. 4 and FIG. 5a to 5d is an example showing the first and second single-height cells (SHC1, SHC2) of FIG. 3 in more detail.

[0031] Referring to FIGS. 4 and FIGS. 5a through 5d, first and second single-height cells (SHC1, SHC2) may be provided on a substrate (100). Logic transistors constituting a logic circuit may be disposed on each of the first and second single-height cells (SHC1, SHC2). The substrate (100) may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. As an example, the substrate (100) may be a silicon substrate.

[0032] The substrate (100) may have a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2). Each of the first PMOSFET region (PR1), the second PMOSFET region (PR2), the first NMOSFET region (NR1), and the second NMOSFET region (NR2) may extend in a second direction (D2). A first single height cell (SHC1) may include a first NMOSFET region (NR1) and a first PMOSFET region (PR1), and a second single height cell (SHC2) may include a second PMOSFET region (PR2) and a second NMOSFET region (NR2). The substrate (100) may include an facing first surface (100a) and a second surface (100b). The second surface (100b) can come into contact with the first etching stop film (ES1) to be described later.

[0033] A first active pattern (AP1) and a second active pattern (AP2) may be defined by a trench (TR) formed on the upper surface of the substrate (100). The first active pattern (AP1) may be provided on each of the first and second PMOSFET regions (PR1, PR2). The second active pattern (AP2) may be provided on each of the first and second NMOSFET regions (NR1, NR2). The first and second active patterns (AP1, AP2) may extend in a second direction (D2). The first and second active patterns (AP1, AP2) may be parts of the substrate (100) that protrude vertically from the first surface (100a).

[0034] The device isolation layer (ST) may fill the trench (TR). The device isolation layer (ST) may include a silicon oxide film. The device isolation layer (ST) may not cover the first and second channel patterns (CH1, CH2) to be described later.

[0035] A first channel pattern (CH1) may be provided on a first active pattern (AP1). A second channel pattern (CH2) may be provided on a second active pattern (AP2). Each of the first channel pattern (CH1) and the second channel pattern (CH2) may include a first semiconductor pattern (SP1), a second semiconductor pattern (SP2), and a third semiconductor pattern (SP3) that are sequentially stacked. The first to third semiconductor patterns (SP1, SP2, SP3) may be spaced apart from each other in a vertical direction (i.e., a third direction (D3)).

[0036] Each of the first to third semiconductor patterns (SP1, SP2, SP3) may comprise silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns (SP1, SP2, SP3) may comprise crystalline silicon. Each of the first to third semiconductor patterns (SP1, SP2, SP3) may be a nanosheet.

[0037] A plurality of first source / drain patterns (SD1) may be provided on a first active pattern (AP1). A plurality of first recesses (RS1) may be formed on the upper portion of the first active pattern (AP1). Each of the first source / drain patterns (SD1) may be provided within the first recesses (RS1). The first source / drain patterns (SD1) may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern (CH1) may be interposed between a pair of first source / drain patterns (SD1). In other words, stacked first to third semiconductor patterns (SP1, SP2, SP3) may connect a pair of first source / drain patterns (SD1) to each other.

[0038] A plurality of second source / drain patterns (SD2) may be provided on a second active pattern (AP2). A plurality of second recesses (RS2) may be formed on the upper portion of the second active pattern (AP2). The second source / drain patterns (SD2) may each be provided within the second recesses (RS2). The second source / drain patterns (SD2) may be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern (CH2) may be interposed between a pair of second source / drain patterns (SD2). In other words, stacked first to third semiconductor patterns (SP1, SP2, SP3) may connect a pair of second source / drain patterns (SD2) to each other.

[0039] The first and second source / drain patterns (SD1, SD2) may be epitaxial patterns formed by an optional epitaxial growth (SEG) process. For example, the upper surface of each of the first and second source / drain patterns (SD1, SD2) may be located at substantially the same level as the upper surface of the third semiconductor pattern (SP3). For another example, the upper surface of each of the first and second source / drain patterns (SD1, SD2) may be higher than the upper surface of the third semiconductor pattern (SP3).

[0040] The first source / drain patterns (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate (100). Thus, a pair of first source / drain patterns (SD1) can provide compressive stress to the first channel pattern (CH1) between them. The second source / drain patterns (SD2) may include the same semiconductor element (e.g., Si) as the substrate (100).

[0041] Each of the first source / drain patterns (SD1) may include a buffer layer (BFL) and a main layer (MAL) on the buffer layer (BFL). Referring again to FIG. 5a, the buffer layer (BFL) may cover the inner wall of the first recess (RS1). In one embodiment, the buffer layer (BFL) may have a substantially conformal thickness. For example, the thickness of the buffer layer (BFL) in the third direction (D3) on the bottom of the first recess (RS1) may be substantially the same as the thickness of the buffer layer (BFL) in the second direction (D2) on the top of the first recess (RS1).

[0042] In another embodiment, the thickness of the buffer layer (BFL) may become thinner from its lower part to its upper part. For example, the thickness of the buffer layer (BFL) in the third direction (D3) on the bottom of the first recess (RS1) may be greater than the thickness of the buffer layer (BFL) in the second direction (D2) on the upper part of the first recess (RS1). The buffer layer (BFL) may have a U-shape along the profile of the first recess (RS1).

[0043] The main layer (MAL) can fill most of the remaining area of ​​the first recess (RS1), excluding the buffer layer (BFL). The volume of the main layer (MAL) may be larger than the volume of the buffer layer (BFL). Each of the buffer layer (BFL) and the main layer (MAL) may contain silicon-germanium (SiGe). Specifically, the buffer layer (BFL) may contain a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer (BFL) may contain only silicon (Si) excluding germanium (Ge). The concentration of germanium (Ge) in the buffer layer (BFL) may be 0 at% to 10 at%.

[0044] The main layer (MAL) may contain a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the main layer (MAL) may be 30 at% to 70 at%. The concentration of germanium (Ge) in the main layer (MAL) may increase toward the third direction (D3). For example, the main layer (MAL) adjacent to the buffer layer (BFL) may have a germanium (Ge) concentration of about 40 at%, but the upper part of the main layer (MAL) may have a germanium (Ge) concentration of about 60 at%.

[0045] Each of the buffer layer (BFL) and the main layer (MAL) may contain an impurity (e.g., boron, gallium, or indium) that causes the first source / drain pattern (SD1) to have a p-type. The impurity concentration of each of the buffer layer (BFL) and the main layer (MAL) may be 1E18 atomic / cm3 to 5E22 atomic / cm3. The impurity concentration of the main layer (MAL) may be greater than the impurity concentration of the buffer layer (BFL).

[0046] The buffer layer (BFL) can prevent stacking faults between the substrate (100) (i.e., the first active pattern (AP1)) and the main layer (MAL), and between the first to third semiconductor patterns (SP1, SP2, SP3) and the main layer (MAL). If a stacking fault occurs, the channel resistance may increase. The buffer layer (BFL) can protect the main layer (MAL) during the process of replacing the second semiconductor layers (SAL), which will be described later, with the first to third portions (PO1, PO2, PO3) of the gate electrode (GE). In other words, the buffer layer (BFL) can prevent the etching material that removes the second semiconductor layers (SAL) from penetrating into the main layer (MAL) and etching it.

[0047] Each of the second source / drain patterns (SD2) may include silicon (Si). The second source / drain pattern (SD2) may further include impurities (e.g., phosphorus, arsenic, or antimony) that cause it to be n-type. The impurity concentration of the second source / drain pattern (SD2) may be 1E18 atomic / cm3 to 5E22 atomic / cm3.

[0048] Gate electrodes (GE) extending in a first direction (D1) across the first and second channel patterns (CH1, CH2) may be provided. The gate electrodes (GE) may be arranged in a second direction (D2) according to a first pitch. Each gate electrode (GE) may be perpendicularly overlapped with the first and second channel patterns (CH1, CH2).

[0049] The gate electrode (GE) may include a first portion (PO1) interposed between an active pattern (AP1 or AP2) and a first semiconductor pattern (SP1), a second portion (PO2) interposed between a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2), a third portion (PO3) interposed between a second semiconductor pattern (SP2) and a third semiconductor pattern (SP3), and a fourth portion (PO4) on the third semiconductor pattern (SP3).

[0050] A first etching stop film (ES1) may be disposed on a second surface (100b) of the substrate (100). A second etching stop film (ES2) may be disposed spaced apart from the substrate (100) with the first etching stop film (ES1) in between. The first etching stop film (ES1) and the second etching stop film (ES2) may overlap in a third direction (D3). The second surface (100b) of the substrate (100) and the upper surface of the first etching stop film (ES1) may be in contact. The lower surface of the first etching stop film (ES1) and the upper surface of the second etching stop film (ES2) may be in contact. The sum of the thicknesses of the first etching stop film (ES1) and the second etching stop film (ES2) may be between 5 nm and 50 nm. The first etching stop layer (ES1) above may include SiGeC. The SiGeC is Si (1-x-y) Ge x C y It has a chemical formula of the form, and the x and y can have values ​​of 0.001 to 0.01.

[0051] The second etching stop layer (ES2) above may include SiGeB. The SiGeB is Si (1-x-y) Ge x B y It has a chemical formula of the form, and the x and y can have values ​​of 0.001 to 0.01.

[0052] In the case of carbon (C) included in the first etching stop film (ES1), it may be a substitutional solid solution. Therefore, the occurrence of lattice dismatch at the interface between the first etching stop film (ES1) and the substrate (100) can be reduced. Due to these characteristics, the first etching stop film (ES1) can be stably formed on the substrate (100), and the thickness of the first etching stop film (ES1) can be increased to a desired range.

[0053] In the case of the second etching stop film (ES2), by including boron (B), the selectivity ratio for the etchant can be more than twice as high as that of the first etching stop film (ES1) which includes carbon (C).

[0055] Referring again to FIG. 5c, the substrate (100) may include a second region (RG2) including a first surface (100a) and a first region (RG1) including a second surface (100b). The first region (RG1) is 1.00E+19 / cm 3 or 6.00E+19 / cm 3 It may include boron (B) having a concentration of . The first region (RG1) may include a SiB compound. The length in the third direction (D3) of the first region (RG1) may be approximately 10 nm. On the other hand, for the second region (RG2), 2.00E+19 / cm 3 It may contain boron with a concentration below the following level.

[0057] Referring again to FIG. 5d, the gate electrode (GE) may be provided on the top surface (TS), bottom surface (BS), and both sidewalls (SW) of each of the first to third semiconductor patterns (SP1, SP2, SP3). In other words, the transistor according to the present embodiment may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode (GE) surrounds the channel three-dimensionally.

[0058] Typically, the first single height cell (SHC1) may have a first boundary (BD1) and a second boundary (BD2) facing each other in the second direction (D2). The first and second boundaries (BD1, BD2) may extend in the first direction (D1). The first single height cell (SHC1) may have a third boundary (BD3) and a fourth boundary (BD4) facing each other in the first direction (D1). The third and fourth boundaries (BD3, BD4) may extend in the second direction (D2).

[0059] Gate cutting patterns (CT) may be placed on the boundary toward the second direction (D2) of each of the first and second single-height cells (SHC1, SHC2). For example, gate cutting patterns (CT) may be placed on the third and fourth boundaries (BD3, BD4) of the first single-height cell (SHC1). The gate cutting patterns (CT) may be arranged along the third boundary (BD3) at the first pitch. The gate cutting patterns (CT) may be arranged along the fourth boundary (BD4) at the first pitch. In a planar view, the gate cutting patterns (CT) on the third and fourth boundaries (BD3, BD4) may be placed so as to overlap each other on the gate electrodes (GE). The gate cutting patterns (CT) may include an insulating material such as a silicon oxide film, a silicon nitride film, or a combination thereof.

[0060] The gate electrode (GE) on the first single height cell (SHC1) can be separated from the gate electrode (GE) on the second single height cell (SHC2) by a gate cutting pattern (CT). A gate cutting pattern (CT) may be interposed between the gate electrode (GE) on the first single height cell (SHC1) and the gate electrode (GE) on the second single height cell (SHC2) aligned with it in the first direction (D1). In other words, the gate electrode (GE) extending in the first direction (D1) can be separated into a plurality of gate electrodes (GE) by the gate cutting patterns (CT).

[0061] Referring again to FIGS. 4 and FIGS. 5a through 5d, a pair of gate spacers (GS) may be disposed on both sidewalls of the fourth portion (PO4) of the gate electrode (GE). The gate spacers (GS) may extend along the gate electrode (GE) in a first direction (D1). The upper surfaces of the gate spacers (GS) may be higher than the upper surface of the gate electrode (GE). The upper surfaces of the gate spacers (GS) may co-plane with the upper surface of the first interlayer insulating film (110) to be described later. The gate spacers (GS) may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers (GS) may include a multi-layer composed of at least two of SiCN, SiCON, and SiN.

[0062] A gate capping pattern (GP) may be provided on a gate electrode (GE). The gate capping pattern (GP) may extend along the gate electrode (GE) in a first direction (D1). The gate capping pattern (GP) may include a material that is etch selective with respect to the first and second interlayer insulating films (110, 120) described later. Specifically, the gate capping pattern (GP) may include at least one of SiON, SiCN, SiCON, and SiN.

[0063] A gate insulating film (GI) may be interposed between the gate electrode (GE) and the first channel pattern (CH1), and between the gate electrode (GE) and the second channel pattern (CH2). The gate insulating film (GI) may cover the top surface (TS), bottom surface (BS), and both side walls (SW1, SW2) of each of the first to third semiconductor patterns (SP1, SP2, SP3). The gate insulating film (GI) may cover the top surface of the device isolation film (ST) below the gate electrode (GE).

[0064] In one embodiment of the present invention, the gate insulating film (GI) may include a silicon oxide film, a silicon oxynitride film and / or a high dielectric film. The high dielectric film may include a high dielectric constant material having a higher dielectric constant than that of the silicon oxide film. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0065] The gate electrode (GE) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on a gate insulating film (GI) and may be adjacent to first to third semiconductor patterns (SP1, SP2, SP3). The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. By controlling the thickness and composition of the first metal pattern, a desired threshold voltage of the transistor can be achieved. For example, the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) may be composed of the first metal pattern, which is a work function metal.

[0066] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). Furthermore, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0067] The second metal pattern may include a metal having lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion (PO4) of the gate electrode (GE) may include the first metal pattern and the second metal pattern on the first metal pattern.

[0068] Referring again to FIG. 5b, inner spacers (IP) may be provided on the first and second NMOSFET regions (NR1, NR2). In other words, inner spacers (IP) may be provided on the second active pattern (AP2). The inner spacers (IP) may be interposed between the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) and the second source / drain pattern (SD2), respectively. The inner spacers (IP) may be in direct contact with the second source / drain pattern (SD2). Each of the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) may be spaced apart from the second source / drain pattern (SD2) by the inner spacers (IP).

[0069] A first interlayer insulating film (110) may be provided on a substrate (100). The first interlayer insulating film (110) may cover gate spacers (GS) and first and second source / drain patterns (SD1, SD2). The upper surface of the first interlayer insulating film (110) may substantially co-plane with the upper surface of the gate capping pattern (GP) and the upper surface of the gate spacer (GS). A second interlayer insulating film (120) covering the gate capping pattern (GP) may be disposed on the first interlayer insulating film (110). A third interlayer insulating film (130) may be provided on the second interlayer insulating film (120). A fourth interlayer insulating film (140) may be provided on the third interlayer insulating film (130). In one example, the first to fourth interlayer insulating films (110-140) may comprise a silicon oxide film.

[0070] A pair of separation structures (DB) facing each other in a second direction (D2) may be provided on both sides of each of the first and second single-height cells (SHC1, SHC2). For example, a pair of separation structures (DB) may be provided on the first and second boundaries (BD1, BD2) of the first single-height cell (SHC1), respectively. The separation structure (DB) may extend parallel to the gate electrodes (GE) in a first direction (D1). The pitch between the separation structure (DB) and the adjacent gate electrode (GE) may be the same as the first pitch.

[0071] The isolation structure (DB) can penetrate the first and second interlayer insulating films (110, 120) and extend into the first and second active patterns (AP1, AP2). The isolation structure (DB) can penetrate the top of each of the first and second active patterns (AP1, AP2). The isolation structure (DB) can electrically isolate the active region of each of the first and second single-height cells (SHC1, SHC2) from the active region of an adjacent cell.

[0072] Active contacts (AC) may be provided that penetrate the first and second interlayer insulating films (110, 120) and are electrically connected to the first and second source / drain patterns (SD1, SD2), respectively. A pair of active contacts (AC) may be provided on each side of the gate electrode (GE). In a planar view, the active contacts (AC) may have a bar shape extending in the first direction (D1).

[0073] A metal-semiconductor compound layer (SC), for example, a silicide layer, may be interposed between the active contact (AC) and the first source / drain pattern (SD1), and between the active contact (AC) and the second source / drain pattern (SD2), respectively. The active contact (AC) may be electrically connected to the source / drain patterns (SD1, SD2) through the metal-semiconductor compound layer (SC). For example, the metal-semiconductor compound layer (SC) may include at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

[0074] Gate contacts (GC) that are electrically connected to gate electrodes (GE), respectively, by penetrating the second interlayer insulating film (120) and the gate capping pattern (GP) may be provided. In a planar view, two gate contacts (GC) on the first single height cell (SHC1) may be placed overlappingly on the first PMOSFET region (PR1). In other words, two gate contacts (GC) on the first single height cell (SHC1) may be provided on the first active pattern (AP1) (see FIG. 5a). In a planar view, one gate contact (GC) on the first single height cell (SHC1) may be placed overlappingly on the first NMOSFET region (NR1). In other words, one gate contact (GC) on the first single height cell (SHC1) may be provided on the second active pattern (AP2) (see FIG. 5b).

[0075] The gate contact (GC) can be freely positioned on the gate electrode (GE) without positional restrictions. For example, the gate contacts (GC) on the second single-height cell (SHC2) can be positioned on the second PMOSFET region (PR2), the second NMOSFET region (NR2), and the device isolation film (ST) filling the trench (TR), respectively (see FIG. 4).

[0076] In one embodiment of the present invention, referring to FIGS. 5a and 5d, the upper portion of an active contact (AC) adjacent to a gate contact (GC) may be filled with an upper insulating pattern (UIP). The bottom surface of the upper insulating pattern (UIP) may be lower than the bottom surface of the gate contact (GC). In other words, the upper surface of the active contact (AC) adjacent to the gate contact (GC) may be lower than the bottom surface of the gate contact (GC) by the upper insulating pattern (UIP). This prevents the problem of a short circuit occurring when the gate contact (GC) comes into contact with the active contact (AC) adjacent to it.

[0077] Each of the active contact (AC) and the gate contact (GC) may include a conductive pattern (FM) and a barrier pattern (BM) surrounding the conductive pattern (FM). For example, the conductive pattern (FM) may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern (BM) may cover the sidewalls and bottom surface of the conductive pattern (FM). The barrier pattern (BM) may include a metal film / metal nitride film. The metal film may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0079] Referring again to FIGS. 4, 5c, and 5d, first to third lower power lines (VPR1, VPR2, VPR3) may be disposed through the first etching stop layer (ES1), the second etching stop layer (ES2), and the substrate (100). The first to third lower power lines (VPR1, VPR2, VPR3) may extend parallel to each other in the second direction (D2). The first lower power line (VPR1) may be disposed on the fourth boundary (BD4) of the first single height cell (SHC1). The second lower power line (VPR2) may be disposed on the third boundary (BD3) of the first single height cell (SHC1). In other words, the first single height cell (SHC1) may be defined between the first lower power line (VPR1) and the second lower power line (VPR2). A second single height cell (SHC2) can be defined between the second lower power wiring (VPR2) and the third lower power wiring (VPR3).

[0080] Referring again to FIGS. 5c and 5d, typically, the second lower power wiring (VPR2) may be electrically connected to at least one active contact (AC). The second lower power wiring (VPR2) may include a line-shaped buried wiring section (BPR) extending in a second direction (D2) and a lower contact section (LCP) protruding from the buried wiring section (BPR) in a third direction (D3). In one embodiment of the present invention, the second lower power wiring (VPR2) may further include a connection section (CNP) between the buried wiring section (BPR) and the lower contact section (LCP). However, the connection section (CNP) may be omitted.

[0081] An upper contact (UCT) may be provided on a lower contact portion (LCP). The upper contact (UCT) may electrically connect the lower contact portion (LCP) of the second lower power wiring (VPR2) to an active contact (AC). Consequently, in the semiconductor device according to the present embodiment, the lower power wiring (VPR1-VPR3) may be electrically connected to source / drain patterns (SD1, SD2) through the lower contact portion (LCP), the upper contact (UCT), and the active contact (AC).

[0082] The buried wiring section (BPR), the connection section (CNP), and the lower contact section (LCP) can be integrally connected to form a single second lower power wiring (VPR2). For example, the second lower power wiring (VPR2) may include a conductive pattern (FM) and a barrier pattern (BM). In this case, the barrier pattern (BM) may be omitted between the buried wiring section (BPR) and the connection section (CNP), and between the connection section (CNP) and the lower contact section (LCP).

[0083] The upper contact (UCT) may include a conductive pattern (FM) and a barrier pattern (BM). The barrier pattern (BM) of the upper contact (UCT) and the barrier pattern (BM) of the lower contact portion (LCP) may be in direct contact with each other. The conductive pattern (FM) of the upper contact (UCT) and the conductive pattern (FM) of the lower power wiring (VPR1-VPR3) may include the same or different metals. For example, the conductive pattern (FM) of the lower power wiring (VPR1-VPR3) may include copper, and the conductive pattern (FM) of the upper contact (UCT) may include molybdenum or ruthenium.

[0084] A lower spacer (LSP) may be interposed between the lower power wiring (VPR1, VPR2, VPR3) and the substrate (100). The lower spacer (LSP) may include a silicon-based insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The lower power wiring (VPR1, VPR2, VPR3) may be insulated from the substrate (100) by the lower spacer (LSP).

[0085] A power transmission network layer (PDN) may be provided on the lower surface of the second etching stop layer (ES2). The power transmission network layer (PDN) may include a plurality of lower wires electrically connected to the first to third lower power wires (VPR1, VPR2, VPR3). For example, the power transmission network layer (PDN) may include a wiring network for applying a source voltage (VSS) to the first and third lower power wires (VPR1, VPR3). The power transmission network layer (PDN) may include a wiring network for applying a drain voltage (VDD) to the second lower power wire (VPR2).

[0086] A first metal layer (M1) may be provided within the third interlayer insulating film (130). The first metal layer (M1) may include first wirings (M1_I). The first wirings (M1_I) of the first metal layer (M1) may extend parallel to each other in a second direction (D2).

[0087] The first metal layer (M1) may further include first vias (VI1). The first vias (VI1) may each be provided below the first wirings (M1_I) of the first metal layer (M1). Through the first vias (VI1), the active contact (AC) and the first wiring (M1_I) of the first metal layer (M1) may be electrically connected to each other. Through the first vias (VI1), the gate contact (GC) and the first wiring (M1_I) of the first metal layer (M1) may be electrically connected to each other.

[0088] The first wiring (M1_I) of the first metal layer (M1) and the first via (VI1) below it can each be formed by a separate process. In other words, the first wiring (M1_I) and the first via (VI1) of the first metal layer (M1) can each be formed by a single damascene process. The semiconductor device according to the present embodiment may be formed using a process of less than 20 nm.

[0089] A second metal layer (M2) may be provided within the fourth interlayer insulating film (140). The second metal layer (M2) may include a plurality of second wires (M2_I). Each of the second wires (M2_I) of the second metal layer (M2) may have a line shape or a bar shape extending in a first direction (D1). In other words, the second wires (M2_I) may extend parallel to each other in the first direction (D1).

[0090] The second metal layer (M2) may further include second vias (VI2) provided below each of the second wires (M2_I). Through the second vias (VI2), the first wire (M1_I) of the first metal layer (M1) and the second wire (M2_I) of the second metal layer (M2) can be electrically connected to each other. For example, the second wire (M2_I) of the second metal layer (M2) and the second via (VI2) below it can be formed together by a dual damascene process.

[0091] The first wiring (M1_I) of the first metal layer (M1) and the second wiring (M2_I) of the second metal layer (M2) may comprise the same or different conductive materials. For example, the first wiring (M1_I) of the first metal layer (M1) and the second wiring (M2_I) of the second metal layer (M2) may comprise at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not illustrated, metal layers (e.g., M3, M4, M5...) stacked on the fourth interlayer insulating film (140) may be additionally disposed. Each of the stacked metal layers may comprise wiring for routing between cells.

[0092] FIG. 6 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Descriptions that overlap with FIG. 5c are omitted. A substrate (100) may include a third region (RG3) including a second surface (100b) and a fourth region (RG4) including a first surface (100a). The third region (RG3) is 1.00E+19 / cm 3 or 6.00E+19 / cm 3 It may include boron having a concentration of . Additionally, the third region (RG3) may include a SiB compound. The length in the third direction (D3) of the third region (RG3) may be approximately 10 nm. On the other hand, for the fourth region (RG2), 2.00E+19 / cm 3 It may contain boron with a concentration below the following level.

[0093] A third etching stop film (ES3) may be disposed on a second surface (100b) of a substrate (100). The second surface (100b) of the substrate (100) and the upper surface of the third etching stop film (ES3) may be in contact. The thickness of the third etching stop film (ES3) may be between 5 and 50 nm. The third etching stop film may include SiGeCB. The SiGeCB is Si (1-x-y-z) Ge x C y B zIt has a chemical formula of the form, and the x, y, and z may have values ​​of 0.001 to 0.01. The first and second lower power lines (VPR1, VPR2) may be disposed through the third etching stop film (ES3) and the substrate (100). A power transmission network layer (PDN) may be provided on the lower surface of the third etching stop film (ES3).

[0095] FIG. 7a is a graph showing the concentration of boron (B) according to regions of semiconductor devices according to Example (EX) and Comparative Example 1 (PE1). Example (EX) is a graph showing the concentration of boron (B) within a semiconductor device after sequentially stacking a first etching stop film (ES1) containing SiGeC, which is the structure of the present invention, and a second etching stop film (ES2) containing SiGeB on the second surface (100b) of a substrate (100). Unlike Example, Comparative Example 1 (PE1) used an etching stop film containing SiGe.

[0096] Referring to FIG. 7a, in the case of Example (EX), the boron (B) concentration in the portion adjacent to the second surface (100b) within the substrate (100) is 1.00E+19 / cm 3 or 6.00E+19 / cm 3 The region (BRE) can be formed with a length of approximately 10 nm in a direction perpendicular to the second surface (100b). In contrast, in the case of Comparative Example 1 (PE1), the boron (B) concentration with a length of approximately 10 nm in a direction perpendicular to the second surface (100b) within the substrate (100) is 1.00E+19 / cm 3 or 2.00E+19 / cm 3That is, the boron (B) concentration in the region of 10 nm in a direction perpendicular to the second surface (100b) within the substrate (100) can be formed higher in Example (EX) than in Comparative Example 1 (PE1). This is because the boron concentration in the substrate formed in Example (EX) includes boron (B) diffused from the second etching stop film (ES2) along with boron (B) doped as an impurity in the part adjacent to the second surface (100b) for NFET formation, whereas the boron (B) concentration in the substrate formed in Comparative Example 1 (PE1) includes only boron (B) doped as an impurity for NFET formation.

[0098] FIG. 7b is a graph showing the concentration of carbon (C) according to a region of a semiconductor device according to Comparative Example 2 (PE2). Comparative Example 2 (PE2) used a single-layer etching stop film containing SiGeC. Referring to FIG. 7b, the carbon (C) concentration in the region adjacent to the second surface (100b) within the substrate (100) is 1.00E+19 / cm² 3 The abnormal region (CRE) is formed within approximately 4 nm in a direction perpendicular to the second plane (100b). That is, in the embodiment (EX) illustrated in FIG. 7a, the boron (B) concentration is 1.00E+19 / cm² 3 or 6.00E+19 / cm 3 The phosphorus region (BRE) is formed with a length of approximately 10 nm in a direction perpendicular to the second plane (100b), but in the case of Comparative Example 2 (PE2), the carbon (C) concentration is 1.00E+19 / cm² 3 The area of ​​excess (CRE) is formed within approximately 4 nm in a direction perpendicular to the second surface (100b). This is because the amount of boron (B) included in the second etching stop film (ES2) of Example (EX) that diffuses into the substrate (100) is greater than the amount of carbon (C) included in the etching stop film of Comparative Example 2 (PE2) that diffuses into the substrate (100).

[0100] FIGS. 8 to 19 are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, FIGS. 8, 9a, 10a, 11a, 12a, 13a, 14a, and 15a are cross-sectional views corresponding to line A-A' of FIG. 4. FIGS. 11b, 12b, 13b, 14b, and 15b are cross-sectional views corresponding to line B-B' of FIG. 4. FIGS. 9b, 11c, 12c, 13c, 14c, 15c, 16, 17, 18, and 19 are cross-sectional views corresponding to line C-C' of FIG. 4. FIGS. 10b and 15d are cross-sectional views corresponding to line D-D' of FIG. 4.

[0102] Referring to FIG. 8, a sacrificial substrate (200) may be provided. The sacrificial substrate (200) may include silicon. A second etching stop layer (ES2) may be formed on the carrier substrate. A first etching stop layer (ES1) may be formed on the second etching stop layer (ES2). The first etching stop layer (ES1) and the second etching stop layer (ES2) may be formed through a chemical vapor deposition process. The second etching stop layer (ES2) may be formed to have epitaxial crystallinity in relation to the sacrificial substrate (200). The first etching stop layer (ES1) may be formed to have epitaxial crystallinity in relation to the second etching stop layer (ES2).

[0104] Referring to FIGS. 9a and 9b, a substrate (100) comprising first and second PMOSFET regions (PR1, PR2) and first and second NMOSFET regions (NR1, NR2) may be provided on the first etching stop layer (ES1). First semiconductor layers (ACL) and second semiconductor layers (SAL) may be formed alternately stacked on the substrate (100). The first semiconductor layers (ACL) may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the second semiconductor layers (SAL) may include the other of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0105] The second semiconductor layer (SAL) may include a material capable of having an etch selectivity with respect to the first semiconductor layer (ACL). For example, the first semiconductor layers (ACL) may include silicon (Si), and the second semiconductor layers (SAL) may include silicon-germanium (SiGe). The concentration of germanium (Ge) in each of the second semiconductor layers (SAL) may be 10 at% to 30 at%.

[0106] Mask patterns may be formed on the first and second PMOSFET regions (PR1, PR2) and the first and second NMOSFET regions (NR1, NR2) of the substrate (100), respectively. The mask pattern may have a line shape or a bar shape extending in the second direction (D2).

[0107] A patterning process can be performed on the above mask patterns using an etching mask to form a trench (TR) defining a first active pattern (AP1) and a second active pattern (AP2). The first active pattern (AP1) can be formed on each of the first and second PMOSFET regions (PR1, PR2). The second active pattern (AP2) can be formed on each of the first and second NMOSFET regions (NR1, NR2). In a planar view, the first and second active patterns (AP1, AP2) can have a line shape extending parallel to each other in a second direction (D2).

[0108] According to one embodiment of the present invention, the patterning process may further include forming at least one dummy pattern (DAP). For example, the dummy pattern (DAP) may be formed between the first and second PMOSFET regions (PR1, PR2). Unlike the first and second active patterns (AP1, AP2) described above, the dummy pattern (DAP) may be formed in a pillar shape (or contact shape). That is, from a planar perspective, the dummy pattern (DAP) may have an island shape rather than a line shape.

[0109] A stacking pattern (STP) may be formed on each of the first and second active patterns (AP1, AP2). The stacking pattern (STP) may include first semiconductor layers (ACL) and second semiconductor layers (SAL) that are alternately stacked. The stacking pattern (STP) may be formed together with the first and second active patterns (AP1, AP2) during the patterning process. The stacking pattern (STP) may also be formed on a dummy pattern (DAP).

[0110] A device isolation layer (ST) that fills the trench (TR) can be formed. Specifically, an insulating layer covering the first and second active patterns (AP1, AP2) and stacked patterns (STP) can be formed on the front surface of the substrate (100). The device isolation layer (ST) can be formed by recessing the insulating layer until the stacked patterns (STP) are exposed.

[0111] The device isolation layer (ST) may include an insulating material such as a silicon oxide film. Stacked patterns (STP) may be exposed over the device isolation layer (ST). In other words, the stacked patterns (STP) may protrude vertically over the device isolation layer (ST).

[0113] Referring to FIGS. 10a and 10b, sacrifice patterns (PP) can be formed across stacked patterns (STP) on a substrate (100). Each sacrifice pattern (PP) can be formed in a line shape or a bar shape extending in a first direction (D1). The sacrifice patterns (PP) can be arranged along a second direction (D2) with a first pitch.

[0114] Specifically, forming the sacrificial patterns (PP) may include forming a sacrificial film on the front surface of a substrate (100), forming hard mask patterns (MP) on the sacrificial film, and patterning the sacrificial film using the hard mask patterns (MP) as an etching mask. The sacrificial film may include polysilicon.

[0115] A pair of gate spacers (GS) may be formed on both sidewalls of each of the sacrifice patterns (PP). Forming the gate spacers (GS) may include conformally forming a gate spacer film on the front surface of the substrate (100) and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer film may be a multi-layer film including at least two of SiCN, SiCON, and SiN.

[0117] Referring to FIGS. 11a through 11c, first recesses (RS1) may be formed within a stacked pattern (STP) on a first active pattern (AP1). Second recesses (RS2) may be formed within a stacked pattern (STP) on a second active pattern (AP2). While forming the first and second recesses (RS1, RS2), the device isolation film (ST) on each side of the first and second active patterns (AP1, AP2) may be further recessed. While forming the first and second recesses (RS1, RS2), the stacked pattern (STP) on a dummy pattern (DAP) may be removed.

[0118] Specifically, first recesses (RS1) can be formed by etching a stacked pattern (STP) on a first active pattern (AP1) using hard mask patterns (MA) and gate spacers (GS) as an etching mask. The first recess (RS1) can be formed between a pair of sacrifice patterns (PP). Second recesses (RS2) within the stacked pattern (STP) on the second active pattern (AP2) can be formed in the same way as the first recesses (RS1).

[0119] First to third semiconductor patterns (SP1, SP2, SP3) can be formed sequentially between adjacent first recesses (RS1) from the first semiconductor layers (ACL). First to third semiconductor patterns (SP1, SP2, SP3) can be formed sequentially between adjacent second recesses (RS2) from the first semiconductor layers (ACL). The first to third semiconductor patterns (SP1, SP2, SP3) between adjacent first recesses (RS1) can form a first channel pattern (CH1). The first to third semiconductor patterns (SP1, SP2, SP3) between adjacent second recesses (RS2) can form a second channel pattern (CH2).

[0121] Referring to FIGS. 12a through 12c, first source / drain patterns (SD1) may each be formed within the first recesses (RS1). Specifically, a buffer layer (BFL) may be formed by performing a first SEG process in which the inner wall of the first recess (RS1) serves as a seed layer. The buffer layer (BFL) may be grown using the first to third semiconductor patterns (SP1, SP2, SP3) exposed by the first recess (RS1) and the substrate (100) as seeds. As an example, the first SEG process may include a Chemical Vapor Deposition (CVD) process or a Molecular Beam Epitaxy (MBE) process.

[0122] The buffer layer (BFL) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate (100). The buffer layer (BFL) may contain a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer (BFL) may contain only silicon (Si) excluding germanium (Ge). The concentration of germanium (Ge) in the buffer layer (BFL) may be 0 at% to 10 at%.

[0123] A second SEG process can be performed on the buffer layer (BFL) to form a main layer (MAL). The main layer (MAL) can be formed to completely or nearly completely fill the first recess (RS1). The main layer (MAL) may contain a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the main layer (MAL) may be 30 at% to 70 at%.

[0124] In one embodiment of the present invention, a capping layer may be formed by performing a third SEG process on a main layer (MAL). The capping layer may include silicon (Si). The concentration of silicon (Si) in the capping layer may be 98 at% to 100 at%.

[0125] While forming the buffer layer (BFL) and the main layer (MAL), impurities (e.g., boron, gallium, or indium) that cause the first source / drain pattern (SD1) to have a p-type can be injected in-situ. As another example, impurities can be injected into the first source / drain pattern (SD1) after the first source / drain pattern (SD1) is formed.

[0126] Second source / drain patterns (SD2) may each be formed within the second recesses (RS2). Specifically, the second source / drain pattern (SD2) may be formed by performing an optional epitaxial growth (SEG) process in which the inner wall of the second recess (RS2) is used as a seed layer. As an example, the second source / drain pattern (SD2) may include the same semiconductor element (e.g., Si) as the substrate (100).

[0127] While forming the second source / drain pattern (SD2), impurities (e.g., phosphorus, arsenic, or antimony) that cause the second source / drain pattern (SD2) to have an n-type can be injected in-situ. As another example, impurities can be injected into the second source / drain pattern (SD2) after the second source / drain pattern (SD2) has been formed.

[0128] In one embodiment of the present invention, before forming the second source / drain pattern (SD2), an inner spacer (IP) can be formed by replacing a portion of the second semiconductor layer (SAL) exposed through the second recess (RS2) with an insulating material. Consequently, inner spacers (IPs) can be formed between the second source / drain pattern (SD2) and the second semiconductor layers (SAL), respectively.

[0129] In one embodiment of the present invention, a source / drain pattern (i.e., an epitaxial pattern) may not be formed on the dummy pattern (DAP). While the first and second source / drain patterns (SD1, SD2) are being formed, a mask pattern may be formed on the dummy pattern (DAP). In another embodiment of the present invention, an epitaxial pattern may be formed on the dummy pattern (DAP).

[0131] Referring to FIGS. 13a through 13c, a first interlayer insulating film (110) covering first and second source / drain patterns (SD1, SD2), hard mask patterns (MP), and gate spacers (GS) may be formed. As an example, the first interlayer insulating film (110) may include a silicon oxide film.

[0132] The first interlayer insulating film (110) can be flattened until the upper surfaces of the sacrificial patterns (PP) are exposed. The flattening of the first interlayer insulating film (110) can be performed using an etch back or chemical mechanical polishing (CMP) process. During the flattening process, all hard mask patterns (MP) can be removed. Consequently, the upper surface of the first interlayer insulating film (110) can be co-planar with the upper surfaces of the sacrificial patterns (PP) and the upper surfaces of the gate spacers (GS).

[0133] Although not shown, an upper contact (UCT) may be formed in a hole formed by penetrating the first interlayer insulating film (110) and the dummy pattern (DAP). Subsequently, the upper contact (UCT) may be formed by filling the upper contact hole with a conductive material. Forming the upper contact (UCT) may include forming a barrier pattern (BM) within the upper contact hole (UCH) and forming a conductive pattern (FM) on the barrier pattern (BM).

[0135] Referring to FIGS. 14a through 14c, a region of the sacrificial pattern (PP) can be selectively opened using photolithography. For example, a region of the sacrificial pattern (PP) on the third and fourth boundaries (BD3, BD4) of the first single height cell (SHC1) can be selectively opened. The opened region of the sacrificial pattern (PP) can be selectively etched and removed. An insulating material can be filled into the space where the sacrificial pattern (PP) has been removed to form a gate cutting pattern (CT) (see FIG. 14c).

[0136] The exposed sacrifice patterns (PP) can be selectively removed. By removing the sacrifice patterns (PP), an outer region (ORG) exposing the first and second channel patterns (CH1, CH2) can be formed (see FIG. 14c). Removing the sacrifice patterns (PP) may include wet etching using an etchant that selectively etches polysilicon.

[0137] The second semiconductor layers (SAL) exposed through the outer region (ORG) can be selectively removed to form inner regions (IRG) (see FIG. 14c). Specifically, an etching process can be performed to selectively etch the second semiconductor layers (SAL) so that only the second semiconductor layers (SAL) are removed while the first to third semiconductor patterns (SP1, SP2, SP3) remain intact. The etching process can have a high etching rate for silicon-germanium having a relatively high germanium concentration. For example, the etching process can have a high etching rate for silicon-germanium having a germanium concentration greater than 10 at%.

[0138] During the etching process, the second semiconductor layers (SAL) on the first and second PMOSFET regions (PR1, PR2) and the first and second NMOSFET regions (NR1, NR2) can be completely removed. The etching process may be a wet etch. The etching material used in the etching process can rapidly remove the second semiconductor layer (SAL) having a relatively high germanium concentration. Meanwhile, the first source / drain pattern (SD1) on the first and second PMOSFET regions (PR1, PR2) can be protected during the etching process by a buffer layer (BFL) having a relatively low germanium concentration.

[0139] Referring again to FIG. 14c, the second semiconductor layers (SAL) are selectively removed so that only the stacked first to third semiconductor patterns (SP1, SP2, SP3) remain on each of the first and second active patterns (AP1, AP2). The first to third inner regions (IRG1, IRG2, IRG3) can each be formed through the regions where the second semiconductor layers (SAL) have been removed.

[0140] Specifically, a first inner region (IRG1) may be formed between an active pattern (AP1 or AP2) and a first semiconductor pattern (SP1), a second inner region (IRG2) may be formed between the first semiconductor pattern (SP1) and a second semiconductor pattern (SP2), and a third inner region (IRG3) may be formed between the second semiconductor pattern (SP2) and a third semiconductor pattern (SP3).

[0142] Referring to FIGS. 15a through 15d, a gate insulating film (GI) may be conformally formed on exposed first to third semiconductor patterns (SP1, SP2, SP3). A gate electrode (GE) may be formed on the gate insulating film (GI). The gate electrode (GE) may include first to third portions (PO1, PO2, PO3) formed respectively within first to third inner regions (IRG1, IRG2, IRG3) and a fourth portion (PO4) formed within an outer region (ORG).

[0143] The gate electrode (GE) can be recessed so that its height can be reduced. While the gate electrode (GE) is recessed, the upper portions of the first and second gate cutting patterns (CT1, CT2) can also be slightly recessed. A gate capping pattern (GP) can be formed on the recessed gate electrode (GE).

[0144] A second interlayer insulating film (120) may be formed on the first interlayer insulating film (110). The second interlayer insulating film (120) may include a silicon oxide film. Active contacts (AC) electrically connected to the first and second source / drain patterns (SD1, SD2) may be formed by penetrating the second interlayer insulating film (120) and the first interlayer insulating film (110). A gate contact (GC) electrically connected to the gate electrode (GE) may be formed by penetrating the second interlayer insulating film (120) and the gate capping pattern (GP).

[0145] Forming the active contact (AC) and the gate contact (GC), respectively, may include forming a barrier pattern (BM) and forming a conductive pattern (FM) on the barrier pattern (BM). The barrier pattern (BM) may be formed conformally and may include a metal film / metal nitride film. The conductive pattern (FM) may include a low-resistance metal.

[0146] At least one active contact (AC) may be formed on the upper contact (UCT) (see FIG. 7t). The active contact (AC) may be directly connected to the upper contact (UCT). The active contact (AC) may wrap around the upper part of the upper contact (UCT).

[0147] A pair of isolation structures (DB) may be formed on both sides of each of the first and second single-height cells (SHC1, SHC2). The isolation structure (DB) may extend from the second interlayer insulating film (120) through the gate electrode (GE) into the active pattern (AP1 or AP2). The isolation structure (DB) may include an insulating material such as a silicon oxide film or a silicon nitride film.

[0149] Referring to FIG. 16, a third interlayer insulating film (130) may be formed on active contacts (AC) and gate contacts (GC). A first metal layer (M1) may be formed within the third interlayer insulating film (130). A fourth interlayer insulating film (140) may be formed on the third interlayer insulating film (130). A second metal layer (M2) may be formed within the fourth interlayer insulating film (140).

[0151] Referring to FIG. 17, the sacrificial substrate (200) of FIG. 16 and the element on the sacrificial substrate (200) can be flipped so that the bottom surface of the sacrificial substrate (200) is exposed. After that, back grinding and chemical and mechanical polishing processes can be performed on the sacrificial substrate (200).

[0153] Referring to FIG. 18, a wet etching process can be performed to etch the remaining sacrificial substrate (200). The etching process can be performed until the upper surface of the second etching stop film (ES2) is exposed.

[0155] Referring to FIG. 19, a hole can be formed by penetrating the first etching stop layer (ES1), the second etching stop layer (ES2), and the substrate (100). Subsequently, a lower power wiring (VPR1-VPR3) can be formed within the hole. The lower power wiring (VPR1-VPR3) can be electrically connected to an active contact (AC) through an upper contact (UCT).

[0156] Subsequently, a power transmission network layer (PDN) may be formed on the second etching stop layer (ES2). The power transmission network layer (PDN) may be formed to apply a source voltage or a drain voltage to the lower power wiring (VPR1-VPR3). FIG. 5c is a flipped form of the semiconductor device of FIG. 19.

[0158] FIG. 20 illustrates a manufacturing process of a semiconductor device according to another embodiment of the present invention. Referring to FIG. 20, a third etching stop layer (ES3) may be formed on a sacrificial substrate (200). The third etching stop layer (ES3) may be formed through a chemical vapor deposition process. The third etching stop layer (ES3) may be formed to have epitaxial crystallinity in relation to the sacrificial substrate (200). The third etching stop layer (ES3) may be formed to have epitaxial crystallinity in relation to the sacrificial substrate (200). Subsequently, the manufacturing process of FIG. 9a to FIG. 19 may be carried out in the same manner on the third etching stop layer (ES3).

[0160] FIG. 21 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Excluding parts that overlap with FIG. 5c, the differences will be described in detail. First to third lower power lines (VPR1, VPR2, VPR3) may be arranged through the substrate (100). An upper contact (UCT) may be provided on the lower power lines (VPR1, VPR2, VPR3). A power transmission network layer (PDN) may be provided on the second surface (100b) of the substrate (100).

[0161] Referring again to FIG. 7a, the boron (B) concentration shown in Example (EX) can be formed in the same way on the substrate (100) shown in FIG. 21. The substrate (100) may include a SiB compound. The SiB compound can function as an etching stop layer and has excellent heat resistance and corrosion resistance. The SiB compound may be formed mainly within a range of 10 nm from the second surface (100b) in a direction perpendicular to the second surface (100b) of the substrate (100). In addition, in the case of the substrate (100) shown in FIG. 21, carbon (C) diffused from the first etching stop layer (ES1) shown in FIG. 5c may also be included along with boron (B).

[0162] The following describes a process for manufacturing a semiconductor device illustrated in FIG. 21. First, referring to FIG. 18, after the sacrificial substrate (200) is etched, the first etching stop layer (ES1) and the second etching stop layer (ES2) can be removed. Subsequently, although not illustrated, a hole can be formed by penetrating the substrate (100). Subsequently, a lower power wiring (VPR1-VPR3) can be formed within the hole. The lower power wiring (VPR1-VPR3) can be electrically connected to an active contact (AC) through an upper contact (UCT).

[0163] Subsequently, a power transmission network layer (PDN) may be formed on the substrate (100). The power transmission network layer (PDN) may be formed to apply a source voltage or a drain voltage to the lower power wiring (VPR1-VPR3).

[0165] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art. Explanation of the symbols

[0167] 100: Substrate ES1: First etching stop film ES2: 2nd etching stop layer ES3: 3rd etching stop layer PDN: Power Transmission Network Layer UCT: Upper Contact AC: Active contact

Claims

Claim 1 A semiconductor device comprising: a substrate including a first surface and a second surface facing each other; an active pattern protruding from the first surface; a source / drain pattern on the active pattern; an active contact on the source / drain pattern; an upper contact connected to the active contact and extending toward the first surface; a first etching stop film on the second surface; a second etching stop film spaced apart from the substrate with the first etching stop film in between; and power wiring connected to the upper contact by penetrating the second etching stop film, the first etching stop film, and the substrate, wherein the first etching stop film comprises SiGeC and the second etching stop film comprises SiGeB. Claim 2 In claim 1, the substrate has an impurity-doped region in a portion adjacent to the second surface, and the impurity-doped region comprises boron doped within the semiconductor, wherein the concentration of the boron is 1.00E+19 / cm² 3 Up to 6.00E+20 / cm 3 Semiconductor device. Claim 3 In claim 2, the impurity doping region is formed within a range of 10 nm from the second surface in a direction perpendicular to the second surface of the substrate. Claim 4 A semiconductor device according to claim 1, wherein the sum of the thickness of the first etching stop film and the thickness of the second etching stop film is between 5 nm and 50 nm. Claim 5 In claim 1, the above SiGeB is Si (1-x-y) Ge x B y Having a chemical formula of the form, the above SiGeC is Si (1-x-y) Ge x C y A semiconductor device having a chemical formula of the form, wherein x and y are 0.001 to 0.

01. Claim 6 A substrate comprising facing first and second surfaces; an active pattern protruding from the first surface; a source / drain pattern on the active pattern; an active contact on the source / drain pattern; an upper contact connected to the active contact and extending toward the first surface; and a power wiring penetrating the substrate and connected to the upper contact, wherein the substrate comprises a doping region, the doping region is formed within a range of 10 nm from the second surface toward the first surface, the doping region comprises boron, and the concentration of boron is 1.00E+19 / cm³ 3 Up to 6.00E+20 / cm 3 semiconductor device. Claim 7 A semiconductor device comprising: a substrate including a first surface and a second surface facing each other; an active pattern protruding from the first surface; a source / drain pattern on the active pattern; an active contact on the source / drain pattern; an upper contact connected to the active contact and extending toward the first surface; an etching stop film on the second surface; and a power wiring connected to the upper contact by penetrating the etching stop film and the substrate, wherein the etching stop film comprises SiGeCB. Claim 8 A semiconductor device according to claim 7, wherein the thickness of the etching stop film is 5 nm to 50 nm. Claim 9 In claim 7, the substrate includes a doping region adjacent to the second plane, and the doping region has a boron concentration of 1.00E+19 / cm² 3 Up to 6.00E+20 / cm 3 A semiconductor device in the region. Claim 10 In claim 9, the semiconductor device wherein the doping region is formed within a range of 10 nm from the second surface in a direction perpendicular to the second surface of the substrate.

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