Offset compensation front-end module and offset compensation method

Abstract

The present specification relates to an offset compensation front-end module. An offset compensation front-end module according to one embodiment is a front-end module that transmits power produced from a photovoltaic (PV) panel to the DC input of an inverter, and may include a voltage generation unit that receives a target bias current and generates a reference voltage, a comparator that compares the reference voltage with a voltage generated by a current that is offset, and a control unit that monitors the output of the comparator and the magnitude of the offset, compensates for the bias current, and receives a mode signal to change the operating mode.

Description

Technology Field

[0001] The embodiment relates to an offset compensation front-end module and an offset compensation method. Background Technology

[0003] In CMOS processes, differential amplifiers typically exhibit an offset of approximately ~10mV. This offset arises from variations in the semiconductor fabrication process. For instance, unlike BJTs, MOSFETs generally exhibit a larger offset due to variations in the threshold voltage (VTH) during the process, and this difference in VTH varies by device depending on the wafer location. Additionally, the device area also varies. Variations in the equivalent size of MOSFETs affect mismatch between devices. This can be mitigated by using larger device sizes.

[0004] Figure 1 is a graph showing the noise spectrum of a CMOS amplifier.

[0005] 1 / f noise is known to originate primarily from interface defects between the gate oxide and the silicon substrate. The corner frequency for determining whether 1 / f noise or thermal noise has a dominant influence in the frequency domain is approximately ~kHz to ~tens of kHz in CMOS processes.

[0006] 1 / f noise has a power spectral density inversely proportional to frequency. Additionally, since 1 / f noise is inversely proportional to the device area, a large device area must be used for low-frequency applications.

[0007] Drift is caused by variations in characteristics due to changes in temperature or time. For example, offset is treated like DC, but the threshold voltage VTH is a function of carrier doping concentration, and therefore the offset is. For this reason, offset is an error that is affected by temperature and changes at a low frequency over time.

[0008] Referring to Figure 1, since the maximum power point tracking (MPPT) operates at 1 kHz, the input of the current sensing amplifier also changes to a frequency of 1 kHz. Therefore, the main sources of error in the amplifier are expected to be offset, drift, and 1 / f noise. Prior art literature

[0010] Korean Registered Patent Publication No. 10-1266876 (May 16, 2013) “Offset Compensation Filter Circuit for Position Detector for Long Stator LSM” The problem to be solved

[0011] The embodiment aims to provide a simplified circuit that reduces low-frequency errors while reducing the error to a level that the circuit can handle by sensing output terminal errors caused by high-voltage level input terminal errors and compensating them using a mixed-signal method. means of solving the problem

[0013] An offset compensation front-end module according to one embodiment is a front-end module that transmits power produced from a photovoltaic (PV) panel to the DC input of an inverter, and may include a voltage generation unit that receives a target bias current and generates a reference voltage, a comparator that compares the reference voltage with a voltage generated by a current that is offset, and a control unit that monitors the output of the comparator and the magnitude of the offset, compensates for the bias current, and receives a mode signal to change the operating mode.

[0014] In addition, the control unit can monitor the magnitude of the offset using a 6-bit up-down counter and a 6-bit ADC (analog to digital converter).

[0015] In addition, the control unit can transmit a control signal to a variable current current DAC (digital to analog converter) to compensate for a bias current that is misaligned by the magnitude of the offset.

[0016] In addition, the above operating mode may include a compensation mode and an operation mode.

[0017] In addition, the above operating mode can operate with the offset compensated using the stored offset compensation value.

[0018] In addition, the above comparator can correct the offset using auto-zeroing.

[0019] An offset compensation method according to one embodiment may include a method for compensating an offset using a front-end module comprising a voltage generator, a comparator, and a control unit, wherein the voltage generator receives a target bias current and generates a reference voltage; the comparator compares the reference voltage with a voltage generated by a current that is offset; and the control unit monitors the output of the comparator and the magnitude of the offset and compensates the bias current.

[0020] In addition, the control unit can monitor the magnitude of the offset using a 6-bit up-down counter and a 6-bit ADC (analog to digital converter).

[0021] A photovoltaic (PV) panel according to one embodiment may include a plurality of offset compensation front-end modules, each comprising: a voltage generation unit that receives a target bias current and generates a reference voltage; a comparator that compares the reference voltage with a voltage generated by a current that is offset; and a control unit that monitors the output of the comparator and the magnitude of the offset, compensates for the bias current, and receives a mode signal to change the operating mode. Effects of the invention

[0023] According to an embodiment, the error at the input of an amplifier for current sensing at high voltage is compensated at the output using a mixed-signal method, thereby reducing the error to a level that the circuit can handle, while also reducing low-frequency errors and providing a simplified circuit. Brief explanation of the drawing

[0025] Figure 1 is a graph showing the noise spectrum of a CMOS amplifier. Figure 2 is a circuit diagram of a current sensing amplifier reflecting an offset. Figure 3 is a circuit diagram of the input stage of Auto-zeroing. Figure 4 is a circuit diagram of an amplifier with a chopping switch and a chopping technique applied. FIG. 5 is a circuit diagram capable of performing amplifier offset mixed-signal compensation of an embodiment. Figure 6 is a circuit diagram of the comparator used in the embodiment. Figure 7 is a graph showing the simulation results of the offset compensation method of the embodiment. FIG. 8 is a flowchart of the offset compensation method of an embodiment. Specific details for implementing the invention

[0026] In describing the embodiments of this specification, detailed descriptions of known technologies related to this specification are omitted if it is determined that such descriptions would unnecessarily obscure the essence of this specification. Furthermore, the terms described below are defined in consideration of their functions within this specification, and these definitions may vary depending on the intentions or practices of the user or operator. Therefore, such definitions should be based on the content throughout this specification. Terms used in the detailed description are intended merely to describe the embodiments of this specification and should never be interpreted restrictively. Unless explicitly stated otherwise, expressions in the singular form include the meaning of the plural form. In this description, expressions such as "include" or "comprise" are intended to refer to certain characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof, and should not be interpreted as excluding the existence or possibility of one or more other characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof other than those described.

[0027] Terms containing ordinal numbers, such as “first,” “second,” etc., may be used to describe various components, but said components are not limited by said terms. These terms may be used solely in a nominal sense to distinguish one component from another, and their sequential meaning is determined not by such nomenclature but by the context of the description.

[0028] The term “and / or” is used to include all cases of any combination of the multiple items in question. For example, “and / or B” means including all three cases, such as “and B.”

[0029] When it is stated that one component is "connected" or "joined" to another component, it should be understood that while it may be directly connected or joined to that other component, there may also be other components in between.

[0030] Hereinafter, specific embodiments of the examples will be described with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the methods, devices, and / or objects described herein. However, this is merely illustrative and the examples are not limited thereto.

[0031] Figure 2 is a circuit diagram of a current sensing amplifier reflecting an offset.

[0032] Figure 2 is a circuit modeled with the amplifier offset as a virtual voltage source. When calculated using the virtual ground of the amplifier with negative feedback applied, the differential output voltage is given by Equation 1 below. Looking at the differential output of the current sensor, an error term due to the amplifier offset appears.

[0033]

[0034] Figure 3 is a circuit diagram of the input stage of Auto-zeroing.

[0035] Auto-zeroing is an error compensation technique using sampling. Figure 2 shows a circuit implementing the auto-zeroing technique at the input stage to compensate for amplifier errors. When CK is high, the amplifier operates as a buffer with a gain of 1, and negative feedback is applied so that the inputs across the amplifier are virtually grounded. Additionally, because the input is provided at the same potential, the capacitor samples errors in low-frequency components, including offset. When CK is low, the capacitor holds the stored errors in low-frequency components, and the amplifier automatically compensates by subtracting the error from the input.

[0036] Auto-zeroing is a powerful technique for eliminating low-frequency errors, but due to its sampling characteristics, it cannot avoid an increase in noise within the signal bandwidth and has the problem of being unable to process signals in continuous time.

[0037] Figure 4 is a circuit diagram of an amplifier with a chopping switch and a chopping technique applied.

[0038] Chopping is a continuous-time frequency modulation technique that, unlike auto-zeroing, does not undergo noise folding. Figure 3 shows a chopping switch and an amplifier with chopping applied. The chopping switch connects the input in the forward direction or reverses the polarity of the input depending on the chopping clock (fCH). Due to the chopping switch, the input signal takes the form of a pulse wave.

[0039] Chopping can eliminate low-frequency error components at the amplifier input stage, including high-frequency modulated offsets, by passing the output through a final low-pass filter. However, there is a problem with chopping ripple occurring because the circuit continuously switches at the frequency of fch.

[0040] Auto-zeroing and chopping eliminate low-frequency error components, but residual error exists when implementing the switch with an actual MOSFET. Causes of residual error include clock feedthrough and charge injection.

[0041] Auto-zeroing and chopping can be implemented at both the input and output stages of the proposed circuit. However, implementing the technique at the input stage presents the problem of requiring the switch to be driven at a high voltage level. When implementing a switch using a MOSFET, the MOSFET's gate voltage must be higher than the input voltage to function as a switch. Since the circuit's input is the PV panel voltage, which is the highest voltage in the system, there is a circuital burden of having to artificially generate a high voltage. Applying the technique to the output stage avoids the burden of driving the switch at a high voltage level. However, there is a problem where the signal saturates to the power supply or ground and is lost due to low-frequency error components, including amplifier gain and offset. In such cases, since the signal is lost and only the DC component remains, error compensation is impossible through the application of the technique. Currently, CDS, a type of auto-zeroing technique, is applied to the SHA, which is the input stage of the ADC. This exhibits effects similar to the auto-zeroing implementation at the sensor output stage and effectively eliminates offset, drift, and 1 / f noise. Therefore, an additional method is required to appropriately reduce the offset level in the sensor so that the signal is not lost.

[0042] FIG. 5 is a circuit diagram capable of performing amplifier offset mixed-signal compensation of an embodiment.

[0043] Referring to FIG. 5, the offset compensation circuit of the embodiment may include a control unit (110) that receives a clock and a mode signal and changes the operating mode, a comparator (115) that compares a reference voltage with a voltage generated by an offset or distorted current, a voltage generation unit (120), and a current sensing amplifier (130).

[0044] The compensation offset compensation circuit of the embodiment can be controlled in a mixed-signal manner for amplifier offset correction.

[0045] The current sensing amplifier (130) has a symmetrical structure on the left and right sides, so it is explained based on the half circuit.

[0046] The control unit (110) can receive a mode signal and change the operating mode of the offset compensation circuit of the embodiment. The control unit (110) can control the circuit of the embodiment to operate as a circuit for offset compensation in a compensation mode when the mode signal is high, and to operate as a current sensor operating mode when the mode signal is low.

[0047] Before operating the circuit of the embodiment as a current sensor, the circuit is first configured without a load. Since there is no signal from the sensor's perspective when there is no load, an ideally set bias current and an error current due to the offset may flow through the output resistor (R3). Equation 2 below represents the output node voltage when there is no load.

[0048]

[0049] The voltage generation unit (120) can generate a reference voltage by using these characteristics to cause a current of the same magnitude as the target bias current to flow through R5 (=R3). The comparator (115) can compare this reference voltage with the voltage generated by the offset or distorted current. The output (UD) of the comparator (115) can be input to a 6-bit up-down counter included in the control unit (110).

[0050] The control unit (110) can monitor the magnitude of the offset using a 6-bit analog-to-digital converter (ADC) configured with a comparator (115) and a counter. The control unit (110) can compensate for the bias current that is misaligned by the magnitude of the offset through a variable current current DAC (digital-to-analog converter) (e.g., C-DAC of FIG. 5) with 6 bits containing information about the magnitude of the offset. When the operation mode is switched after the compensation is finished, the set 6 bits are stored in the counter, so the compensation for the offset is maintained during operation.

[0051] Figure 6 is a circuit diagram of the comparator used in the embodiment.

[0052] While the compensation circuit is operating, there is also an offset in the comparator (115). The offset of the comparator (115) results in a reduction in the validity of the stored 6 bits when the compensation mode ends and the operation mode is switched. Therefore, the offset in the comparator (115) of the compensation circuit was corrected using an auto-zeroing technique. FIG. 6 is the circuit of the comparator (115) used in the compensation mode. The comparator (115) operates based on the clock, and the charge amount stored in capacitors C1 and C2 is given by Equations 3 and 4 below when the clock is high, and Equations 5 and 6 below when the clock is low. When the differential transfer function is obtained using the law of conservation of charge, it is as shown in Equation 7.

[0053]

[0054]

[0055]

[0056]

[0057]

[0058] VCOMP is input to the latch and maintains its value. Therefore, in the operation mode based on the comparator offset of the compensation mode, the validity of the stored 6 bits does not need to be considered, and compensation can be performed based on the amplifier offset.

[0059] Figure 7 is a graph showing the simulation results of the offset compensation method of the embodiment.

[0060] Figure 7 shows the simulation results of an offset compensation method using the compensation circuit of the embodiment. The simulation was conducted with an offset of 12mV, assuming a worst-case scenario. In the simulation results, when MODE is high, the output node voltage (ISENP) and the reference voltage (REF) are compared, and compensation is performed by monitoring the offset using a 6-bit binary code. When the output node voltage and the reference voltage become similar, the counter output swings by 1 bit, and when MODE becomes low, it latches to store the compensated value. Finally, the offset-compensated circuit can be used in the operating mode. After offset compensation, a parameter called residue offset was defined as shown in Equation 8 below to evaluate the equivalent offset on the input side using the calculation formula for the output node voltage. In the simulation, after compensation, the residue offset was confirmed to be approximately 0.7mV.

[0061]

[0062] FIG. 8 is a flowchart of the offset compensation method of an embodiment.

[0063] The offset compensation method of the embodiment can be performed in a front-end module that transmits power produced from a photovoltaic (PV) panel to the DC input of an inverter.

[0064] The front-end module of the embodiment may include a voltage generation unit (120) that receives a target bias current and generates a reference voltage, a comparator (115) that compares the reference voltage with a voltage generated by a current that is offset, and a control unit (110) that monitors the output of the comparator and the magnitude of the offset, compensates for the bias current, and receives a mode signal to change the operating mode.

[0065] Referring to FIG. 8, the offset compensation method of the embodiment may include the step of a voltage generating unit receiving a target bias current and generating a reference voltage (S810), a comparator comparing the reference voltage with a voltage generated by a current that is offset (S820), and a control unit monitoring the output of the comparator and the magnitude of the offset and compensating the bias current (S830).

[0066] Step S810 is, for example, in the current sensing amplifier (130) of FIG. 5, I BIAS0 cast Receive input, I received by the voltage generating unit (120) BIAS0 This is the step of generating a reference voltage using [it].

[0067] Step S820 is a step in which, for example, a comparator compares a reference voltage with a voltage that is offset or distorted, and transmits the comparison result to the input of a 6-bit up-down counter included in the control unit (110).

[0068] Step S830 is a step in which, for example, a control unit (110) monitors the magnitude of the offset and transmits a control signal to a variable current current DAC (digital to analog converter) (e.g., C-DAC of FIG. 5) to compensate for a bias current that is misaligned by the magnitude of the offset.

[0069] The offset compensation circuit of the high-voltage HS (high-side) current sensing amplifier proposed in the embodiment can operate as a compensation circuit by raising the MODE signal before operating the circuit as a sensing amplifier.

[0070] The circuit of the embodiment generates a reference voltage (REF) by flowing a set current through resistors R3 and R5 of the same size, and compares this with the output (VOUT) using a comparator. An error in the output (VOUT) is detected using a 6-bit code by utilizing the output (UD) of the comparator and a 6-bit up-down counter circuit. The 6-bit code is used as the input to a current DAC (C-DAC) to flow a current that compensates for the error. When the MODE signal is lowered to operate as a sensing amplifier, the equivalent code of the error is stored in the up-down counter, allowing the sensing amplifier to operate with the error compensated.

[0071] The foregoing description of this specification is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical concept or essential features of the embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

[0072] The scope of the embodiments is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and the concept of equivalents thereof should be interpreted as being included within the scope of the embodiments.

Claims

Claim 1 An offset compensation front-end module comprising: a reference voltage generating unit that receives a target bias current and generates a reference voltage; a comparator that compares the reference voltage with an output voltage formed at the output of a current sensing amplifier due to an offset; and a control unit that controls the output voltage to correspond to the reference voltage by compensating the bias current that generates the reference voltage according to the output of the comparator, and changes the operating mode according to the compensation result. Claim 2 In claim 1, the control unit is an offset compensation front-end module that monitors the magnitude of the offset using a 6-bit up-down counter and a 6-bit ADC (analog to digital converter). Claim 3 In claim 1, the control unit transmits a control signal to a variable current current DAC (digital to analog converter) to compensate for a bias current that is misaligned by the magnitude of the offset, in an offset compensation front-end module. Claim 4 In claim 1, the operating mode is an offset compensation front-end module including a compensation mode and an operation mode. Claim 5 In paragraph 4, the operation mode is an offset compensation front-end module that operates in an offset-compensated state using a stored offset compensation value. Claim 6 In claim 1, the comparator is an offset compensation front-end module that corrects the offset using auto-zeroing. Claim 7 A method for compensating an offset using a front-end module comprising a reference voltage generating unit, a comparator, and a control unit, comprising: a step in which the reference voltage generating unit receives a target bias current and generates a reference voltage; a step in which the comparator compares the reference voltage with an output voltage formed at the output of a current sensing amplifier due to the offset; and a step in which the control unit compensates the bias current generating the reference voltage according to the output of the comparator so that the output voltage corresponds to the reference voltage, and changes the operating mode according to the compensation result. Claim 8 In claim 7, the control unit transmits a control signal to a variable current current DAC (digital to analog converter) to compensate for a bias current that is misaligned by the magnitude of the offset. Claim 9 In claim 7, the control unit monitors the magnitude of the offset using a 6-bit up-down counter and a 6-bit ADC (analog to digital converter). Claim 10 A photovoltaic (PV) panel comprising a plurality of offset compensation front-end modules, each comprising: a reference voltage generating unit that receives a target bias current and generates a reference voltage; a comparator that compares the reference voltage with an output voltage formed at the output of a current sensing amplifier due to an offset; and a control unit that compensates the bias current generating the reference voltage according to the output of the comparator so that the output voltage corresponds to the reference voltage, and changes the operating mode according to the compensation result.

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