Display apparatus

Abstract

The present invention provides a display device capable of stably applying an electrical signal to a gate electrode, comprising: a substrate; an oxide semiconductor layer disposed on the substrate and including a first channel region and a second channel region disposed spaced apart from the first channel region; a first conductive layer interposed between the substrate and the oxide semiconductor layer and including a first gate electrode that overlaps with the first channel region; and a second conductive layer disposed on the upper portion of the oxide semiconductor layer and including a shielding layer that overlaps with the first channel region and a second gate electrode that overlaps with the second channel region.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device, and more specifically, to a display device capable of stably applying an electrical signal to a gate electrode. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as display units for small products such as mobile phones, and also for large products such as televisions.

[0003] The display device includes a display element capable of emitting light and a pixel circuit equipped with a transistor and a storage capacitor, and the display element can be driven by the pixel circuit. The problem to be solved

[0004] However, these conventional display devices had a problem in that a voltage different from the preset voltage was applied to the gate electrode due to parasitic capacitance, or the voltage of the gate electrode could not be maintained at a constant level after the voltage was applied.

[0005] The present invention aims to solve various problems, including the problems mentioned above, and provides a display device capable of stably applying an electrical signal to a gate electrode. However, these problems are examples and the scope of the present invention is not limited by them. means of solving the problem

[0006] According to one aspect of the present invention, a display device is provided comprising: a substrate; an oxide semiconductor layer disposed on the substrate and comprising a first channel region and a second channel region disposed spaced apart from the first channel region; a first conductive layer interposed between the substrate and the oxide semiconductor layer and comprising a first gate electrode that overlaps with the first channel region; and a second conductive layer disposed on the oxide semiconductor layer and comprising a shielding layer that overlaps with the first channel region and a second gate electrode that overlaps with the second channel region.

[0007] The shielding layer and the second gate electrode may contain the same material and have the same layer structure.

[0008] The above display device further comprises a first insulating layer covering the first conductive layer so as to be interposed between the first conductive layer and the oxide semiconductor layer, and a second insulating layer covering the oxide semiconductor layer so as to be interposed between the oxide semiconductor layer and the second conductive layer, wherein the oxide semiconductor layer further comprises a first connection region in contact with the first channel region and having at least a portion having electrical characteristics different from the electrical characteristics of the first channel region, and a second connection region in contact with the second channel region and having at least a portion having electrical characteristics different from the electrical characteristics of the second channel region, and the second conductive layer may further comprise a first connection electrode electrically connected to the first connection region through a first contact hole formed in the second insulating layer, and a second connection electrode spaced apart from the first connection electrode and electrically connected to the second connection region through a second contact hole formed in the first insulating layer and the second insulating layer.

[0009] The first insulating layer covers the first conductive layer to correspond to the entire surface of the substrate, and the second insulating layer may be interposed between the first insulating layer and the second conductive layer on the outside of the oxide semiconductor layer.

[0010] The second insulating layer may be disposed only below the second conductive layer.

[0011] The first connecting electrode above may be integral with the shielding layer.

[0012] The first conductive layer may further include a scan line extending along a first direction.

[0013] The second conductive layer may further include a data line extending along a second direction that intersects the first direction.

[0014] The first conductive layer further includes a connecting wire, and the data line can be electrically connected to the second connecting electrode through the connecting wire.

[0015] The first conductive layer comprises a first capacitor electrode, and the oxide semiconductor layer comprises a second capacitor electrode that overlaps with the first capacitor electrode, and the second capacitor electrode may have electrical characteristics different from the electrical characteristics of the first channel region.

[0016] The above display device further comprises a display element including a pixel electrode, a light-emitting layer, and a counter electrode, and the second capacitor electrode may be electrically connected to the display element.

[0017] The second capacitor electrode can be in direct contact with the pixel electrode.

[0018] According to one aspect of the present invention, a display device may be provided comprising: a substrate; an oxide semiconductor layer disposed on the substrate and including a first channel region and a second channel region disposed spaced apart from the first channel region; a first conductive layer interposed between the substrate and the oxide semiconductor layer and including a first gate electrode overlapping the first channel region and a second gate electrode overlapping the second channel region; and a second conductive layer disposed on the upper portion of the oxide semiconductor layer and including a shielding layer overlapping the first channel region.

[0019] The first gate electrode and the second gate electrode may contain the same material and have the same layer structure.

[0020] The above display device further comprises a first insulating layer covering the first conductive layer so as to be interposed between the first conductive layer and the oxide semiconductor layer, and a second insulating layer covering the oxide semiconductor layer so as to be interposed between the oxide semiconductor layer and the second conductive layer, wherein the oxide semiconductor layer further comprises a first connecting region in contact with the first channel region and a second connecting region in contact with the second channel region, and the second conductive layer may further comprise a first connecting electrode electrically connected to the first connecting region through a first contact hole formed in the second insulating layer and a second connecting electrode spaced apart from the first connecting electrode and electrically connected to the second connecting region through a second contact hole formed in the second insulating layer.

[0021] The first connecting electrode above may be integral with the shielding layer.

[0022] The second conductive layer may further include a scan line extending along the first direction.

[0023] The first conductive layer may further include a data line extending along a second direction intersecting the first direction.

[0024] The second conductive layer further includes a connecting wire integrated with the second connecting electrode, and the connecting wire can be electrically connected to the data line.

[0025] The above display device may further comprise a first connecting metal layer disposed on the first connecting area and corresponding to the first connecting area, and a second connecting metal layer disposed on the second connecting area and corresponding to the second connecting area.

[0026] The first conductive layer comprises a first capacitor electrode, and the oxide semiconductor layer comprises a second capacitor electrode that overlaps with the first capacitor electrode, and may further comprise a capacitor metal layer disposed on the second capacitor electrode and corresponding to the second capacitor electrode.

[0027] The above display device further comprises a display element including a pixel electrode, a light-emitting layer, and a counter electrode, and the second capacitor electrode may be electrically connected to the display element.

[0028] The above capacitor metal layer can be in direct contact with the pixel electrode.

[0029] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention. Effects of the invention

[0030] According to one embodiment of the present invention as described above, a display device capable of stably applying an electrical signal to a gate electrode can be implemented. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0031] FIG. 1 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 3 is an equivalent circuit diagram illustrating a display element included in a light-emitting panel according to one embodiment of the present invention and a pixel circuit connected to the display element. FIG. 4 is a schematic layout diagram illustrating the locations of transistors and capacitors, etc., in pixels included in a display device according to one embodiment of the present invention. FIGS. 5 to 8 are layout diagrams schematically illustrating the components, such as transistors and capacitors, of the display device shown in FIG. 4 layer by layer. FIG. 9a is a cross-sectional view schematically illustrating a cross section taken along the line I-I' of the display device shown in FIG. 4. FIGS. 9b to 9d are cross-sectional views schematically illustrating the process of manufacturing a part of the display device shown in FIG. 4. FIG. 10 is a cross-sectional view schematically illustrating a cross section taken along the line II-II' of the display device shown in FIG. 4. FIGS. 11 to 14 are cross-sectional views schematically illustrating the process of manufacturing a part of the display device shown in FIG. 4. FIG. 15 is a schematic layout diagram illustrating the locations of transistors and capacitors, etc., in pixels included in a display device according to another embodiment of the present invention. FIGS. 16 to 19 are layout diagrams schematically illustrating the components, such as transistors and capacitors, of the display device shown in FIG. 15 layer by layer. FIG. 20 is a cross-sectional view schematically illustrating a cross section taken along the line III-III' of the display device shown in FIG. 15. FIG. 21 is a cross-sectional view schematically illustrating a cross section taken along the line IV-IV' of the display device shown in FIG. 15. FIGS. 22 to 24 are cross-sectional views schematically illustrating the process of manufacturing a part of the display device shown in FIG. 15. Specific details for implementing the invention

[0032] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0034] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" another component, this includes not only cases where they are "directly on" another component, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the size of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0035] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0036] In the following examples, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0037] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0038] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0039] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0040] In the following embodiments, when it is stated that a membrane, region, component, etc. is connected, it includes not only cases where the membrane, region, or component is directly connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated in this specification that a membrane, region, component, etc. is electrically connected, it includes not only cases where the membrane, region, or component, etc. are directly electrically connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0041] FIG. 1 is a plan view schematically illustrating a part of a display device (1) according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically illustrating a part of a display device (1) according to one embodiment of the present invention.

[0042] As illustrated in FIG. 1, the display device (1) may include a display area (DA) in which a plurality of pixels (P) are arranged, and a peripheral area (PA) located outside the display area (DA). The peripheral area (PA) may completely surround the display area (DA).

[0043] The display area (DA) may have a polygonal shape including a rectangle, as illustrated in FIG. 1. For example, the display area (DA) may have a rectangular shape where the width is greater than the height, a rectangular shape where the width is smaller than the height, or a square shape. Alternatively, the display area (DA) may have various shapes such as an ellipse or a circle.

[0044] The display device (1) may include a stacked light-emitting panel (10) and a filter panel (20) as shown in FIG. 2. The light-emitting panel (10) may include a plurality of display elements (DPE), and each display element (DPE) is electrically connected to a circuit (PC, hereinafter referred to as a pixel circuit). The display elements (DPE) and the pixel circuits (PC) may be placed in a display area (DA).

[0045] The display area (DA) can provide a predetermined image using light from display elements (DPE). For example, blue light (L) emitted from display elements (DPE) B ) passes through the filter panel (20) and becomes red light (L R ) and green light(L G It can be converted into ) or transmitted as is without conversion. The display device (1) transmits light, such as red light (L), which is converted or transmitted without conversion by the filter panel (20). R ), green light (L G ) and blue light (L B A specified image can be provided using ).

[0046] The peripheral area (PA) is a non-display area that does not provide an image and may completely surround the display area (DA). Drivers or main power lines for providing electrical signals or power to pixel circuits (PCs) may be placed in the peripheral area (PA). The peripheral area (PA) may include pads, which are areas where electronic components or printed circuit boards can be electrically connected.

[0047] FIG. 3 is an equivalent circuit diagram illustrating a display element (DPE) included in a light-emitting panel according to an embodiment of the present invention and a pixel circuit (PC) connected to the display element (DPE). As shown in FIG. 3, the display element (DPE), such as an organic light-emitting diode (OLED), can be electrically connected to the pixel circuit (PC). Specifically, the pixel electrode of the organic light-emitting diode (OLED) can be electrically connected to the pixel circuit (PC), and the counter electrode of the organic light-emitting diode (OLED) can be electrically connected to a common voltage line (VSL) that provides a common power supply voltage (ELVSS). The organic light-emitting diode (OLED) can emit light with a brightness corresponding to the amount of current supplied from the pixel circuit (PC).

[0048] The pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), and a storage capacitor (Cst). Each of the first transistor (T1), the second transistor (T2), and the third transistor (T3) may be an oxide semiconductor thin-film transistor comprising a semiconductor layer composed of an oxide semiconductor, or a silicon semiconductor thin-film transistor comprising a semiconductor layer composed of polysilicon.

[0049] The first transistor (T1) may be a driving transistor. One connecting electrode of the first transistor (T1) may be electrically connected to a pixel electrode of an organic light-emitting diode (OLED), and the other connecting electrode of the first transistor (T1) may be electrically connected to a driving voltage line (VDL) that supplies a driving power supply voltage (ELVDD). The first gate electrode of the first transistor (T1) may be electrically connected to a first node (N1). The first transistor (T1) can control the amount of current flowing through the organic light-emitting diode (OLED) from the driving power supply voltage (ELVDD) in correspondence with the voltage of the first node (N1).

[0050] The second transistor (T2) may be a switching transistor. One connection electrode of the second transistor (T2) may be electrically connected to the data line (DL), and the other connection electrode of the second transistor (T2) may be electrically connected to the first node (N1). The second gate electrode of the second transistor (T2) may be electrically connected to the scan line (SL). The second transistor (T2) may be turned on when a scan signal is supplied to the scan line (SL) to electrically connect the data line (DL) and the first node (N1).

[0051] The third transistor (T3) may be an initialization transistor and / or a sensing transistor. One connection electrode of the third transistor (T3) may be electrically connected to the initialization-sensing line (ISL), and the other connection electrode of the third transistor (T3) may be electrically connected to the second node (N2). The third gate electrode of the third transistor (T3) may be electrically connected to the control line (CL).

[0052] The third transistor (T3) can be turned on when a control signal is supplied to the control line (CL) to electrically connect the initialization-sensing line (ISL) and the second node (N2). In some embodiments, the third transistor (T3) can be turned on according to a signal received through the control line (CL) to initialize the pixel electrode of the organic light-emitting diode (OLED) using the initialization voltage from the initialization-sensing line (ISL). In some embodiments, the third transistor (T3) can be turned on when a control signal is supplied to the control line (CL) to sense characteristic information of the organic light-emitting diode (OLED). The third transistor (T3) may have both the function of an initialization transistor and the function of a sensing transistor as described above, or may have either one of these functions. In some embodiments, if the third transistor (T3) has the function of an initialization transistor, the initialization-sensing line (ISL) may be named the initialization voltage line, and if it has the function of a sensing transistor, the initialization-sensing line (ISL) may be named the sensing line. The initialization operation and the sensing operation of the third transistor (T3) may proceed individually or simultaneously. In other words, the third transistor (T3) may be an initialization transistor and / or a sensing transistor. For convenience of explanation, the following description will focus on the case where the third transistor (T3) has both the functions of an initialization transistor and a sensing transistor.

[0053] A storage capacitor (Cst) can be connected between a first node (N1) and a second node (N2). For example, one capacitor electrode of the storage capacitor (Cst) can be electrically connected to the gate electrode of the first transistor (T1), and the other capacitor electrode of the storage capacitor (Cst) can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED).

[0054] FIG. 3 illustrates a pixel circuit (PC) comprising three transistors and one storage capacitor, but in other embodiments, the number of transistors or the number of storage capacitors may vary depending on the design of the pixel circuit (PC).

[0055] FIG. 3 illustrates that the display element (DPE) includes an organic light-emitting diode (OLED) containing an organic material, but the present invention is not limited thereto. In another embodiment, the display element (DPE) may be an inorganic light-emitting diode containing an inorganic material. The inorganic light-emitting diode may include a PN diode containing inorganic semiconductor-based materials. When a forward voltage is applied to the PN junction diode, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The aforementioned inorganic light-emitting diode may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light-emitting diode may be referred to as a micro LED.

[0056] FIG. 4 is a schematic layout diagram illustrating the locations of a first transistor (T1), a second transistor (T2), a third transistor (T3), and a storage capacitor (Cst) in pixels included in a display device (1) according to an embodiment of the present invention, and FIG. 5 to 8 are layout diagrams illustrating the components of the first transistor (T1), the second transistor (T2), the third transistor (T3), and the storage capacitor (Cst) of the display device (1) shown in FIG. 4 in a layered manner. FIG. 9a is a schematic cross-sectional view taken along the line I-I' of the display device (1) shown in FIG. 4, and FIG. 10 is a schematic cross-sectional view taken along the line II-II' of the display device (1) shown in FIG. 4.

[0057] As illustrated in these drawings, the display device (1) may include a first pixel, a second pixel, and a third pixel adjacent to each other. Accordingly, the first pixel may include a first pixel circuit (PC1), the second pixel may include a second pixel circuit (PC2), and the third pixel may include a third pixel circuit (PC3). And as illustrated in FIG. 4, the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be located adjacent to each other. The light-emitting panel (10) of such a display device (1) may include a pixel circuit (PC) such as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), a scan line (SL), a control line (CL), a data line (DL), an initialization-sensing line (ISL), a driving voltage line (ELVDL), and a common voltage line (VSL), etc.

[0058] As described above, the first pixel may include a first pixel circuit (PC1), the second pixel may include a second pixel circuit (PC2), and the third pixel may include a third pixel circuit (PC3). That is, the first pixel circuit (PC1) may drive the first display element (DPE1) of the first pixel, the second pixel circuit (PC2) may drive the second display element (DPE2) of the second pixel, and the third pixel circuit (PC3) may drive the third display element (DPE3) of the third pixel.

[0059] Each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include three transistors and one storage capacitor. Specifically, the first pixel circuit (PC1) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), and a storage capacitor (Cst). Since the second pixel circuit (PC2) and the third pixel circuit (PC3) are similar to the first pixel circuit (PC1), for the sake of convenience of explanation, the following description will focus on the first pixel circuit (PC1).

[0060] A buffer layer (not shown) comprising silicon oxide, silicon nitride, or silicon oxynitride may be positioned on the substrate (100). The buffer layer may serve to increase the smoothness of the upper surface of the substrate (100), and the buffer layer may prevent metal atoms or impurities from the substrate (100) from diffusing into the oxide semiconductor layer (300, see FIG. 6) located above it. The buffer layer may be a single layer or a multilayer comprising silicon oxide, silicon nitride, or silicon oxynitride.

[0061] A first conductive layer (200), such as that shown in FIG. 5, may be disposed on a substrate (100). The first conductive layer (200) may include a scan line (SL) and a control line (CL) extending in a first direction (e.g., x-axis direction). Since the scan line (SL) may be electrically connected to a second gate electrode (GE2, see FIG. 7), an electrical signal may be applied to the second gate electrode (GE2) through the scan line (SL). Meanwhile, the first conductive layer (200) may include a connecting wire (CNL) extending in a first direction (e.g., x-axis direction), and the connecting wire (CNL) may be electrically connected to a data line (DL, see FIG. 7).

[0062] The first conductive layer (200) may further include a first gate electrode (GE1) and a first capacitor electrode (CE1). The first gate electrode (GE1) and the first capacitor electrode (CE1) may be integral. That is, the first gate electrode (GE1) and the first capacitor electrode (CE1) may be formed integrally through the same process. Therefore, the first gate electrode (GE1) may include the same material as the first capacitor electrode (CE1). In addition, the first gate electrode (GE1) may have the same layer structure as the first capacitor electrode (CE1). For example, if the first gate electrode (GE1) has a two-layer structure, the first capacitor electrode (CE1) may also have a two-layer structure formed of the same material. Although FIG. 5 illustrates the first gate electrode (GE1) and the first capacitor electrode (CE1) as being integral, the present invention is not limited thereto. For example, the first capacitor electrode (CE1) may be spaced apart from the first gate electrode (GE1).

[0063] The first conductive layer (200) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first conductive layer (200) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first conductive layer (200) may have a multilayer structure, for example, the first conductive layer (200) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0064] A first insulating layer (110, see FIG. 9a) covers a first conductive layer (200) and can be disposed on a substrate (100). The first insulating layer (110) may include an insulating material. For example, the first insulating layer (110) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0065] An oxide semiconductor layer (300) such as that shown in FIG. 6 may be disposed on a first insulating layer (110). The oxide semiconductor layer (300) may include a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2). The first semiconductor pattern (SP1) includes a first channel region (CHA1), a third channel region (CHA3), and a second capacitor electrode (CE2), and the second semiconductor pattern (SP2) may include a second channel region (CHA2). The first channel region (CHA1) may overlap with a first gate electrode (GE1).

[0066] Specifically, the first semiconductor pattern (SP1) further includes a first-1 connection region (CNA1-1) and a first-2 connection region (CNA1-2), and the first channel region (CHA1) may be disposed between the first-1 connection region (CNA1-1) and the first-2 connection region (CNA1-2). For example, the first-1 connection region (CNA1-1) may be in contact with one side of the first channel region (CHA1), and the first-2 connection region (CNA1-2) may be in contact with the other side of the first channel region (CHA1), and the first channel region (CHA1) may be integral with the first-1 connection region (CNA1-1) and the first-2 connection region (CNA1-2).

[0067] The first-1 connection region (CNA1-1) and the first-2 connection region (CNA1-2) are regions having electrical characteristics different from the electrical characteristics of the first channel region (CHA1) and may correspond to a source region or a drain region. Specifically, current can flow in the first channel region (CHA1) only when voltage is applied to a conductive layer placed above or below the first channel region (CHA1). However, current can flow in the first-1 connection region (CNA1-1) and the first-2 connection region (CNA1-2) even if voltage is not applied to the conductive layer placed above or below the first-1 connection region (CNA1-1) and the first-2 connection region (CNA1-2). That is, when no voltage is applied to the conductive layer placed above or below the first-1 connection region (CNA1-1) and the first-2 connection region (CNA1-2), the resistance of the first-1 connection region (CNA1-1) and the resistance of the first-2 connection region (CNA1-2) may be lower than the resistance of the first channel region (CHA1) when no voltage is applied to the conductive layer placed above or below the first channel region (CHA1).

[0068] The first semiconductor pattern (SP1) further includes a third connection region (CNA3), and the third channel region (CHA3) may be positioned to be in contact with the third connection region (CNA3). For example, the third channel region (CHA3) may be integral with the third connection region (CNA3). The third connection region (CNA3) may correspond to a source region or a drain region, as it is a region having electrical characteristics different from those of the third channel region (CHA3). Specifically, current may flow in the third channel region (CHA3) only when a voltage is applied to a conductive layer positioned above or below the third channel region (CHA3). However, current may flow in the third connection region (CNA3) even if no voltage is applied to the conductive layer positioned above or below the third connection region (CNA3). That is, the resistance of the third connection region (CNA3) when no voltage is applied to the conductive layer placed above or below the third connection region (CNA3) may be lower than the resistance of the third channel region (CHA3) when no voltage is applied to the conductive layer placed above or below the third channel region (CHA3).

[0069] The second capacitor electrode (CE2) may be positioned between the first-1 connection area (CNA1-1) and the third channel area (CHA3). For example, the first-1 connection area (CNA1-1) may be in contact with one side of the second capacitor electrode (CE2), and the third channel area (CHA3) may be in contact with the other side of the second capacitor electrode (CE2), and the second capacitor electrode (CE2) may be integral with the first-1 connection area (CNA1-1) and the third channel area (CHA3). Meanwhile, the first-1 connection area (CNA1-1) may correspond to a part of the second capacitor electrode (CE2). That is, a portion of the second capacitor electrode (CE2) that does not overlap with the first capacitor electrode (CE1) may correspond to the first-1 connection region (CNA1-1) of the first transistor (T1). The second capacitor electrode (CE2) may have electrical characteristics different from the electrical characteristics of the first channel region (CHA1). Unlike the electrical characteristics of the first channel region (CHA1) described above, current may flow in the second capacitor electrode (CE2) even if no voltage is applied to the conductive layer placed above or below the second capacitor electrode (CE2). That is, the resistance of the second capacitor electrode (CE2) when no voltage is applied to the conductive layer placed above or below the second capacitor electrode (CE2) may be lower than the resistance of the first channel region (CHA1) when no voltage is applied to the conductive layer placed above or below the first channel region (CHA1). Therefore, the second capacitor electrode (CE2) can function as one electrode of the storage capacitor (Cst).

[0070] The second semiconductor pattern (SP2) further includes a second-1 connection region (CNA2-1) and a second-2 connection region (CNA2-2), and the second channel region (CHA2) may be disposed between the second-1 connection region (CNA2-1) and the second-2 connection region (CNA2-2). For example, the second-1 connection region (CNA2-1) may be in contact with one side of the second channel region (CHA2), and the second-2 connection region (CNA2-2) may be in contact with the other side of the second channel region (CHA2), and the second channel region (CHA2) may be integral with the second-1 connection region (CNA2-1) and the second-2 connection region (CNA2-2).

[0071] The 2-1 connection region (CNA2-1) and the 2-2 connection region (CNA2-2) are regions having electrical characteristics different from the electrical characteristics of the 2-channel region (CHA2) and may correspond to a source region or a drain region. Specifically, current may flow in the 2-channel region (CHA2) only when voltage is applied to a conductive layer placed above or below the 2-channel region (CHA2). However, current may flow in the 2-1 connection region (CNA2-1) and the 2-2 connection region (CNA2-2) even if no voltage is applied to the conductive layer placed above or below the 2-1 connection region (CNA2-1) and the 2-2 connection region (CNA2-2). Alternatively, current may flow even if no voltage is applied to the conductive layer placed below. That is, when no voltage is applied to the conductive layer placed above or below the 2-1 connection region (CNA2-1) and the 2-2 connection region (CNA2-2), the resistance of the 2-1 connection region (CNA2-1) and the resistance of the 2-2 connection region (CNA2-2) may be lower than the resistance of the 2-2 channel region (CHA2) when no voltage is applied to the conductive layer placed above or below the 2-2 channel region (CHA2).

[0072] The oxide semiconductor layer (300) may include an oxide semiconductor. For example, the oxide semiconductor may be a Zn oxide-based material and may include Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. Alternatively, the oxide semiconductor may include IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O), in which a metal such as indium (In), gallium (Ga), or tin (Sn) is contained in zinc oxide (ZnO).

[0073] The first-1 connection region (CNA1-1), the first-2 connection region (CNA1-2), the second-1 connection region (CNA2-1), the second-2 connection region (CNA2-2), the third connection region (CNA3), and the second capacitor electrode (CE2) may be regions in which impurities are added to a layer formed of an oxide semiconductor. That is, the first-1 connection region (CNA1-1), the first-2 connection region (CNA1-2), the second-1 connection region (CNA2-1), the second-2 connection region (CNA2-2), the third connection region (CNA3), and the second capacitor electrode (CE2) may be doped regions. Accordingly, the first-1 connection region (CNA1-1), the first-2 connection region (CNA1-2), the second-1 connection region (CNA2-1), the second-2 connection region (CNA2-2), the third connection region (CNA3), and the second capacitor electrode (CE2) may have electrical characteristics different from the electrical characteristics of the undoped oxide semiconductor, such as the first channel region (CHA1), the second channel region (CHA2), and the third channel region (CHA3). That is, when no voltage is applied to the conductive layer disposed above or below the doped region of the oxide semiconductor layer (300), the resistance of the doped region of the oxide semiconductor layer (300) may be lower than the resistance of the undoped region of the oxide semiconductor layer (300) when no voltage is applied to the conductive layer disposed above or below the undoped region of the oxide semiconductor layer (300).

[0074] A second insulating layer (120, see FIG. 9a) covers an oxide semiconductor layer (300) and may be disposed on the first insulating layer (110). The second insulating layer (120) may include an insulating material. The second insulating layer (120) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0075] A second conductive layer (400), such as that illustrated in FIG. 7, may be disposed on the second insulating layer (120). The second conductive layer (400) may include a data line (DL), an initialization-sensing line (ISL), a driving voltage line (VDL), and a common voltage line (VSL). The data line (DL), the initialization-sensing line (ISL), the driving voltage line (VDL), and the common voltage line (VSL) may extend along a second direction (e.g., the y-axis direction) that intersects the first direction. The data line (DL) may include a first data line (DL1), a second data line (DL2), and a third data line (DL3). The first data line (DL1), the second data line (DL2), and the third data line (DL3) may supply data signals to the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3), respectively.

[0076] The second conductive layer (400) may further include a gate wire (GL), a second gate electrode (GE2), and a third gate electrode (GE3). The gate wire (GL) may be electrically connected to a scan line (SL) included in the first conductive layer (200). Specifically, the gate wire (GL) may be electrically connected to the scan line (SL) through a scan line contact hole (H-SL) formed in the first insulating layer (110) and the second insulating layer (120).

[0077] The second gate electrode (GE2) may overlap with the second channel region (CHA2). The second gate electrode (GE2) may correspond to a part of the gate wiring (GL). That is, the parts that overlap with the oxide semiconductor layer (300) of the gate wiring (GL) may correspond to the gate electrode of the second transistor (T2) of each first pixel circuit (PC1), second pixel circuit (PC2), and third pixel circuit (PC3). Meanwhile, the third gate electrode (GE3) may overlap with the third channel region (CHA3). The third gate electrode (GE3) may correspond to a part of the gate wiring (GL). In this way, the portions overlapping with the oxide semiconductor layer (300) of the gate wiring (GL) may correspond to the gate electrodes of the third transistor (T3) of each first pixel circuit (PC1), second pixel circuit (PC2), and third pixel circuit (PC3). The gate wiring (GL) may extend in a second direction (e.g., the y-axis direction) between the driving voltage line (VDL) and the data line (DL).

[0078] The second conductive layer (400) may further include a shielding layer (SDL), a first-1 connection electrode (CNE1-1), a first-2 connection electrode (CNE1-2), a second-1 connection electrode (CNE2-1), a second-2 connection electrode (CNE2-2), and a third connection electrode (CE3). The shielding layer (SDL) has a shape corresponding to the first channel region (CHA1) of the first transistor (T1) and can serve to protect the first channel region (CHA1) that overlaps with the shielding layer (SDL).

[0079] Specifically, the first transistor (T1) may have a bottom gate structure in which the first gate electrode (GE1) is positioned below the first channel region (CHA1). During the metallization process of the display device (1) to be described later, the second gate electrode (GE2) located above the second channel region (CHA2) functions as a mask to prevent the second channel region (CHA2) from being metallized, and the third gate electrode (GE3) located above the third channel region (CHA3) functions as a mask to prevent the third channel region (CHA3) from being metallized. However, since the first gate electrode (GE1) is positioned below the first channel region (CHA1), it cannot function as a mask, and the shielding layer (SDL) positioned above the first channel region (CHA1) can function as a mask to prevent the first channel region (CHA1) from being metallized. That is, the shielding layer (SDL) can serve to protect the first channel region (CHA1). In this specification, "A is metallized" means that A, which includes an oxide semiconductor, undergoes a change in electrical properties through plasma treatment. That is, it means that the resistance of A after plasma treatment is lower than the resistance of A before plasma treatment.

[0080] The first-1 connection electrode (CNE1-1) can be connected to the first-1 connection region (CNA1-1) of the first transistor (T1) through the first-1 contact hole (H1-1) formed in the second insulating layer (120). The first-1 connection electrode (CNE1-1) can be integrated with the shielding layer (SDL). Accordingly, since the shielding layer (SDL) can be connected to the first-1 connection electrode (CNE1-1), the first transistor (T1) can be formed in a source-sink structure. That is, a source voltage can be applied to the shielding layer (SDL) placed below the first channel region (CHA1) of the first transistor (T1).

[0081] In FIG. 7, the first-1 connecting electrode (CNE1-1) is shown as being integral with the shielding layer (SDL), but the present invention is not limited thereto. The first-2 connecting electrode (CNE1-2) can be connected to the first-2 connecting region (CNA1-2) of the first transistor (T1) through the first-2 contact hole (H1-2) formed in the second insulating layer (120). Meanwhile, the first-2 connecting electrode (CNE1-2) may correspond to a part of the driving voltage line (VDL).

[0082] The second-1 connection electrode (CNE2-1) can be connected to the second-1 connection region (CNA2-1) of the second transistor (T2) through a second-1 contact hole (H2-1) formed in the first insulating layer (110) and the second insulating layer (120). The second-2 connection electrode (CNE2-2) can be connected to the second-2 connection region (CNA2-2) of the second transistor (T2) through a second-2 contact hole (H2-2) formed in the first insulating layer (110) and the second insulating layer (120). The third connection electrode (CNE3) can be connected to the third connection region (CNA3) of the third transistor (T3) through a third contact hole (H3) formed in the second insulating layer (120).

[0083] The second conductive layer (400) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second conductive layer (400) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second conductive layer (400) may be formed to have a multilayer structure, for example, the second conductive layer (400) may be formed to have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0084] A third insulating layer (130, see FIG. 9a) covers the second conductive layer (400) and may be disposed on the second insulating layer (120). The third insulating layer (130) may include an insulating material. The third insulating layer (130) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc. A fourth insulating layer (140, see FIG. 9a) may be disposed on the third insulating layer (130) to cover the third insulating layer (130). The fourth insulating layer (140) may include an organic insulating material. For example, the fourth insulating layer (140) may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0085] A first display element (DPE1, see FIG. 9a), such as an organic light-emitting diode (OLED), may be positioned on the fourth insulating layer (140). The first display element (DPE1) may include a pixel electrode (510, see FIG. 9a), an intermediate layer (520, see FIG. 9a) including a light-emitting layer, and a counter electrode (530, see FIG. 9a).

[0086] A pixel electrode (510) as illustrated in FIG. 8 can be placed on a fourth insulating layer (140). The pixel electrode (510) can be electrically connected to a second capacitor electrode (CE2) through a capacitor electrode contact hole (H-CE) formed in the third insulating layer (130) and the fourth insulating layer (140). Since the first display element (DPE1) includes the pixel electrode (510), the first display element (DPE1) can be electrically connected to a second capacitor electrode (CE2) included in the second conductive layer (400).

[0087] The pixel electrode (510) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (510) may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semitransparent electrode layer disposed on the reflective layer. The transparent or semitransparent electrode layer may comprise at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (510) may have a three-layer structure of ITO / Ag / ITO.

[0088] A pixel defining film (not shown) may be disposed on the fourth insulating layer (140). The pixel defining film can prevent arcs from occurring at the edge of the pixel electrode (510) by increasing the distance between the edge of the pixel electrode (510) and the opposing electrode (530) above the pixel electrode (510). The pixel defining film may be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0089] At least a portion of the intermediate layer (520) of the first display element (DPE1) may be located within an opening formed by a pixel defining film. The light-emitting region of the first display element (DPE1) may be defined by the opening.

[0090] The intermediate layer (520) may include a light-emitting layer. The light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally further disposed below and above the light-emitting layer.

[0091] The light-emitting layer may have a patterned shape corresponding to each of the pixel electrodes (510). Various variations are possible, such as the layer other than the light-emitting layer included in the intermediate layer (520) being integral across the plurality of pixel electrodes (510).

[0092] The counter electrode (530) may be a transparent electrode or a reflective electrode. For example, the counter electrode (530) may be a transparent or translucent electrode and may include a metal thin film with a low work function comprising Li, Ca, LiF, Al, Ag, Mg, and compounds thereof. Additionally, the counter electrode (530) may further include a TCO (transparent conductive oxide) film such as ITO, IZO, ZnO, or In2O3 disposed on the metal thin film. The counter electrode (530) may be integrally formed across the entire front surface of the display area (DA) and disposed on top of the intermediate layer (520) and the pixel definition film.

[0093] FIG. 9a is a cross-sectional view schematically illustrating a cross section taken along the line I-I' of the display device (1) shown in FIG. 4. As shown in FIG. 9a, the first gate electrode (GE1) can be placed below the oxide semiconductor layer (300). That is, the first transistor (T1) can be a bottom gate structure. Accordingly, the first insulating layer (110) can cover the first gate electrode (GE1).

[0094] When the driving transistor has a top-gate structure in which its gate electrode is placed on top of the semiconductor layer, the pixel of the display device may contain unintended parasitic capacitance. As shown in the second pixel circuit (PC2) of the second pixel in FIG. 4, a part of the pixel electrode of another pixel may be placed on the pixel circuit of one pixel of the display device. When the driving transistor has a top-gate structure, a part of the pixel electrode of another pixel may be placed on the gate electrode of the driving transistor of one pixel. In this case, parasitic capacitance may be formed between the gate electrode of the driving transistor of one pixel and the pixel electrode of another pixel. This parasitic capacitance may affect the voltage of the gate electrode of one pixel. That is, a voltage different from a preset voltage may be applied to the gate electrode of the driving transistor of one pixel, or even if a preset voltage is applied, the voltage of the gate electrode of the driving transistor may not be maintained at a constant level. Therefore, organic light-emitting diodes (OLEDs) emit light of unintended brightness, which may result in the inability to display high-quality images.

[0095] However, in the case of the display device (1) according to the present embodiment, a driving transistor, such as a first gate electrode (GE1), is placed below the oxide semiconductor layer (300), and a first insulating layer (110) can cover the first gate electrode (GE1). Accordingly, even if a pixel electrode (510) of another pixel is placed on the pixel circuit (PC) of one pixel of the display device (1), parasitic capacitance may not be formed between the first gate electrode (GE1) of the first transistor (T1) of one pixel and the pixel electrode (510) of another pixel. Therefore, the voltage of the first gate electrode (GE1) may not be affected by parasitic capacitance or its effect may be minimized. That is, an electrical signal can be stably applied to the first gate electrode (GE1). Accordingly, the brightness of the organic light-emitting diode (OLED) can be appropriately controlled.

[0096] The reason why a cross-section like that of FIG. 9a appears is explained using FIG. 9b, FIG. 9c, and FIG. 9d. FIG. 9b to FIG. 9d are cross-sectional views schematically illustrating the process of manufacturing a part of the display device (1) shown in FIG. 4.

[0097] First, as illustrated in FIG. 9b, a first conductive layer (200) including a first gate electrode (GE1) and a first capacitor electrode (CE1) can be formed on the upper surface of a substrate (100), and a first insulating layer (110) can be formed to cover the first conductive layer (200). Since the first insulating layer (110) covers the first conductive layer (200) to correspond to the entire surface of the substrate, the first insulating layer (110) can cover the first gate electrode (GE1) and the first capacitor electrode (CE1) included in the first conductive layer (200). A first semiconductor pattern (SP1) including a first channel region (CHA1), a first-1 connection region (CNA1-1), and a first-2 connection region (CNA1-2) can be formed on the upper surface of the first insulating layer (110). A second insulating layer (120) can be formed on the upper portion of the first semiconductor pattern (SP1). Subsequently, as shown in FIG. 9b, a first-1 contact hole (H1-1) and a first-2 contact hole (H1-2) penetrating the second insulating layer (120) can be formed. The first-1 contact hole (H1-1) is formed to overlap with the first-1 connection region (CNA1-1) on a plane, and the first-2 contact hole (H1-2) can be formed to overlap with the first-2 connection region (CNA1-2) on a plane.

[0098] Next, as illustrated in FIG. 9c, a preliminary second conductive layer (not shown) may be formed on the second insulating layer (120) to cover the second insulating layer (120), and then the second conductive layer (400) may be patterned. Accordingly, a second conductive layer (400) including a first-1 connecting electrode (CNE1-1) and a first-2 connecting electrode (CNE1-2) may be formed. In this case, the first-1 contact hole (H1-1) and the first-2 contact hole (H1-2) penetrating the second insulating layer (120) may be filled by a portion of the second conductive layer (400). Accordingly, the first-1 connecting electrode (CNE1-1) can be electrically connected to the first-1 connecting area (CNA1-1) through the first-1 contact hole (H1-1), and the first-2 connecting electrode (CNE1-2) can be electrically connected to the first-2 connecting area (CNA1-2) through the first-2 contact hole (H1-2).

[0099] Next, as illustrated in FIG. 9d, the portion of the second insulating layer (120) where the second conductive layer (400) does not exist can be removed. That is, the second insulating layer (120) may be placed only on the lower part of the second conductive layer (400). Accordingly, the second insulating layer (120) may exist on the lower part of the shielding layer (SDL), the first-1 connecting electrode (CNE1-1), and the first-2 connecting electrode (CNE1-2), but the second insulating layer (120) may not exist on the lower part of the outer side of the first-1 connecting electrode (CNE1-1) and the outer side of the first-2 connecting electrode (CNE1-2).

[0100] Accordingly, in FIGS. 9b and 9c, the first-1 contact hole (H1-1) and the first-2 contact hole (H1-2) appear as holes in a planar shape. However, in FIG. 9d, the second insulating layer (120) on the outer side of the first-1 connecting electrode (CNE1-1) and the outer side of the first-2 connecting electrode (CNE1-2) is removed, so in FIG. 9d, the first-1 contact hole (H1-1) and the first-2 contact hole (H1-2) do not appear as holes in a planar shape. Accordingly, the display device (1) of the present embodiment may have a cross-section as in FIG. 9a.

[0101] FIG. 10 is a cross-sectional view schematically illustrating a cross section taken along line II-II' of the display device (1) illustrated in FIG. 4. As illustrated in FIG. 10, the second-1 connection electrode (CNE2-1) of the second transistor (T2) can be electrically connected to the second-1 connection region (CNA2-1) of the second transistor (T2). Additionally, the second-1 connection electrode (CNE2-1) of the second transistor (T2) can be electrically connected to the connection wire (CNL).

[0102] Specifically, the second-1 connecting electrode (CNE2-1) can be connected to the connecting wire (CNL) through the second-1 contact hole (H2-1) formed in the first insulating layer (110) and the second insulating layer (120). Since the second-1 connecting electrode (CNE2-1) can be connected to the second-1 connecting area (CNA2-1), the second-1 connecting area (CNA2-1) and the connecting wire (CNL) can be connected to each other through the second-1 connecting electrode (CNE2-1). That is, the second-1 connecting electrode (CNE2-1) can serve as a bridge connecting the second-1 connecting area (CNA2-1) and the connecting wire (CNL). Meanwhile, since the connecting wire (CNL) is electrically connected to the first data line (DL1) through the data line contact hole (H-DL), the second-1 connecting electrode (CNE2-1) of the second transistor (T2) can be electrically connected to the first data line (DL1).

[0103] FIGS. 11 to 14 are cross-sectional views schematically illustrating the process of manufacturing a part of the display device (1) shown in FIG. 4. Specifically, FIGS. 11 to 14 are cross-sectional views schematically illustrating the process of manufacturing the connecting wiring (CNL), the second-1 connecting area (CNA2-1), and the second-1 connecting electrode (CNE2-1) of the display device (1) of FIG. 1.

[0104] First, as illustrated in FIG. 11, a connecting wire (CNL) and a first capacitor electrode (CE1) can be formed on the upper surface of a substrate (100), and a first insulating layer (110) can be formed to cover the connecting wire (CNL) and the first capacitor electrode (CE1). Since the first insulating layer (110) covers the first conductive layer (200) to correspond to the entire surface of the substrate, the first insulating layer (110) can cover the connecting wire (CNL) and the first capacitor electrode (CE1) included in the first conductive layer (200). A second semiconductor pattern (SP2) including a second channel region (CHA2), a second-1 connection region (CNA2-1), and a second-2 connection region (CNA2-2) can be formed on the upper surface of the first insulating layer (110). A second insulating layer (120) can be formed on the upper part of the second semiconductor pattern (SP2).

[0105] Next, as illustrated in FIG. 12, a second-1 contact hole (H2-1), a second-2 contact hole (H2-2), and a data line-contact hole (H-DL) can be formed penetrating the first insulating layer (110) and the second insulating layer (120). The second-1 contact hole (H2-1) can be formed to overlap with the second-1 connection area (CNA2-1) and the connection wire (CNL) on a plane. Specifically, a portion of the second-1 contact hole (H2-1) may overlap with the second-1 connection area (CNA2-1) on a plane, and the entirety of the second-1 contact hole (H2-1) may overlap with the connection wire (CNL) on a plane. The second-2 contact hole (H2-2) can be formed to overlap with the second-2 connection area (CNA2-2) and the first capacitor electrode (CE1) on a plane. The data line-contact hole (H-DL) can be formed to overlap with the connection wire (CNL) on a plane.

[0106] The second-1 connection region (CNA2-1) includes a first region (A1) and a second region (A2), wherein the first region (A1) is a portion of the second-1 connection region (CNA2-1) exposed by the second-1 contact hole (H2-1), and the second region (A2) may be a portion of the second-1 connection region (CNA2-1) not exposed by the second-1 contact hole (H2-1). The first region (A1) exposed by the second-1 contact hole (H2-1) may be metallized by plasma treatment, etc. Specifically, the second-1 contact hole (H2-1) is formed using plasma, and the first region (A1) of the second-1 connection region (CNA2-1) may be plasma treated during the process of forming the second-1 contact hole (H2-1).

[0107] For example, plasma treatment may chemically or materially modify the surface of a material by having high-energy particles placed in a plasma state collide with the surface of the material. During plasma treatment, at least one gas selected from the group including hydrogen gas, argon gas, helium gas, xenon gas, nitrogen gas, nitric oxide gas, oxygen gas, and mixtures thereof may be used.

[0108] When an oxide semiconductor is plasma-treated, the oxide semiconductor is reduced, which induces oxygen defects contained within the oxide semiconductor and can increase oxygen vacancies. An oxide semiconductor with increased oxygen vacancies experiences an increase in carrier concentration, which can ultimately shift the concentration of the threshold voltage—the critical voltage at which electricity conducts among semiconductor properties—in a negative direction. This implies that the oxide semiconductor becomes metallized and conducts electricity well. In other words, the electrical characteristics of the oxide semiconductor before plasma treatment and after plasma treatment may differ. For instance, the resistance of the oxide semiconductor after plasma treatment may be lower than that of the oxide semiconductor before plasma treatment. Therefore, since the second-1 contact hole (H2-1) is formed using plasma, the first region (A1) of the second-1 connection region (CNA2-1) exposed by the second-1 contact hole (H2-1) can be plasma-treated. Accordingly, the first region (A1) can be metallized.

[0109] Next, as illustrated in FIG. 13, a second gate electrode (GE2), a second-1 connection electrode (CNE2-1), a second-2 connection electrode (CNE2-2), an initialization-sensing line (ISL), and a data line (DL) can be formed on the second insulating layer (120). Specifically, a portion of the second-1 connection electrode (CNE2-1) may be formed to be in contact with the first region (A1) of the second-1 connection region (CNA2-1), and a portion of the second-1 connection electrode (CNE2-1) may be formed to be in contact with the connection wire (CNL). Accordingly, as described above, the second-1 connection electrode (CNE2-1) can serve as a bridge connecting the second-1 connection region (CNA2-1) and the connection wire (CNL). The 2-1 connection electrode (CNE2-1) may not overlap with the 2-1 connection region (CNA2-1) in a plane.

[0110] Meanwhile, the aforementioned shielding layer (SDL) can be formed through the same process as the second gate electrode (GE2). Therefore, the shielding layer (SDL) may contain the same material as the second gate electrode (GE2). Additionally, the shielding layer (SDL) may have the same layer structure as the second gate electrode (GE2). For example, if the second gate electrode (GE2) has a two-layer structure, the shielding layer (SDL) may also have a two-layer structure formed of the same material.

[0111] Next, as illustrated in FIG. 14, the portion of the second insulating layer (120) where the second conductive layer (400) does not exist on the upper side can be removed. That is, the second insulating layer (120) can be placed only on the lower side of the second conductive layer (400). Accordingly, the second insulating layer (120) may exist on the lower side of the second gate electrode (GE2), the second-1 connecting electrode (CNE2-1), and the second-2 connecting electrode (CNE2-2), but the second insulating layer (120) may not exist on the second region (A2) of the second-1 connecting region (CNA2-1). On the outer side of the second-1 connection region (CNA2-1), the second insulating layer (120) may exist below the second gate electrode (GE2), the second-1 connection electrode (CNE2-1), the second-2 connection electrode (CNE2-2), the initialization-sensing line (ISL), and the data line (DL). That is, on the outer side of the second-1 connection region (CNA2-1), the second insulating layer (120) may be interposed between the first insulating layer (110) and the second conductive layer (400).

[0112] The portion of the second insulating layer (120) where the second conductive layer (400) does not exist on the upper side can be removed using plasma. Accordingly, the portion of the oxide semiconductor layer (300) located below the removed portion of the second insulating layer (120), such as the second region (A2) of the second-1 connection region (CNA2-1), can be metallized by plasma treatment. Thus, the second-1 connection region (CNA2-1) including the first region (A1) and the second region (A2) can be metallized. That is, the electrical characteristics of the second-1 connection region (CNA2-1) may differ from the electrical characteristics of the second channel region (CHA2).

[0113] FIG. 15 is a schematic layout diagram showing the locations of a first transistor (T1), a second transistor (T2), a third transistor (T3), and a storage capacitor (Cst) in pixels included in a display device (2) according to another embodiment of the present invention, and FIG. 16 to 19 are layout diagrams showing the components of the first transistor (T1), the second transistor (T2), the third transistor (T3), and the storage capacitor (Cst) of the display device (2) shown in FIG. 15 in a layered manner. FIG. 20 is a schematic cross-sectional view showing a cross-section taken along the line III-III' of the display device (2) shown in FIG. 15, and FIG. 21 is a schematic cross-sectional view showing a cross-section taken along the line IV-IV' of the display device (2) shown in FIG. 15. Since the display device (2) according to the present embodiment is similar to the display device (1) described above with reference to FIGS. 1 to 14, the following description will focus on the differences from the display device (1) described above with reference to FIGS. 1 to 14.

[0114] A first conductive layer (200), such as that shown in FIG. 16, may be disposed on a substrate (100). The first conductive layer (200) included in the display device (1) according to the above-described embodiment with reference to FIG. 5, etc., includes a control line (CL), a scan line (SL), a connection line (CNL), a first gate electrode (GE1), and a first capacitor electrode (CE1). In the case of the first conductive layer (200) included in the display device (2) according to the present embodiment, it also includes a first gate electrode (GE1) and a first capacitor electrode (CE1). However, in the case of the display device (2) according to the present embodiment, the first conductive layer (200) does not include a control line (CL), a scan line (SL), and a connection line (CNL), whereas the first conductive layer (200) may include a data line (DL), an initialization-sensing line (ISL), a driving voltage line (VDL), a common voltage line (VSL), and a gate line (GL).

[0115] Data line (DL), initialization-sensing line (ISL), driving voltage line (VDL), and common voltage line (VSL) may be extended along a second direction (e.g., the y-axis direction). Data line (DL) may include a first data line (DL1), a second data line (DL2), and a third data line (DL3). The first data line (DL1), the second data line (DL2), and the third data line (DL3) may supply data signals to a first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3), respectively. Gate line (GL) may be electrically connected to a scan line (SL) included in the second conductive layer (400). Specifically, the gate wire (GL) can be electrically connected to the scan line (SL) through a scan line contact hole (H-SL, see FIG. 18) formed in the first insulating layer (110, see FIG. 20) and the second insulating layer (120, see FIG. 20).

[0116] The first conductive layer (200) may further include a first gate electrode (GE1), a first capacitor electrode (CE1), a gate wiring (GL), a second gate electrode (GE2), and a third gate electrode (GE3). The first insulating layer (110) covers the first conductive layer (200) and may be disposed on a substrate (100).

[0117] An oxide semiconductor layer (300) such as that shown in FIG. 17 may be disposed on a first insulating layer (110). The oxide semiconductor layer (300) may include a first channel region (CHA1), a second channel region (CHA2), a third channel region (CHA3), and a second capacitor electrode (CE2). The first channel region (CHA1) may overlap with a first gate electrode (GE1), the second channel region (CHA2) may overlap with a second gate electrode (GE2), and the third channel region (CHA3) may overlap with a third gate electrode (GE3).

[0118] Compared to the display device (1) described above, the first-1 connection region (CNA1-1), the first-2 connection region (CNA1-2), the second-1 connection region (CNA2-1), the second-2 connection region (CNA2-2), the third connection region (CNA3), and the second capacitor electrode (CE2) of the present embodiment are layers formed of a non-metallic oxide semiconductor. Meanwhile, a corresponding connection metal layer may be disposed on the first-1 connection region (CNA1-1), the first-2 connection region (CNA1-2), the second-1 connection region (CNA2-1), the second-2 connection region (CNA2-2), and / or the third connection region (CNA3). A capacitor metal layer may be disposed on the second capacitor electrode (CE2).

[0119] Specifically, a connecting metal layer corresponding to the first-1 connection region (CNA1-1) may be disposed on the first-1 connection region (CNA1-1), and a connecting metal layer corresponding to the first-2 connection region (CNA1-2) may be disposed on the first-2 connection region (CNA1-2). A connecting metal layer corresponding to the second-1 connection region (CNA2-1) may be disposed on the second-1 connection region (CNA2-1), and a connecting metal layer corresponding to the second-2 connection region (CNA2-2) may be disposed on the second-2 connection region (CNA2-2). A connecting metal layer corresponding to the third connection region (CNA3) may be disposed on the third connection region (CNA3). A capacitor metal layer corresponding to the second capacitor electrode (CE2) may be disposed on the second capacitor electrode (CE2).

[0120] The connecting metal layer and / or capacitor metal layer may be a metal layer comprising a metal such as titanium (Ti), molybdenum (Mo), or tungsten (W). The connecting metal layer and / or capacitor metal layer may have a single-layer or multi-layer structure comprising the aforementioned metals. For example, the connecting metal layer and / or capacitor metal layer may have a single-layer structure such as being a titanium layer, a molybdenum layer, or a tungsten layer. Alternatively, the connecting metal layer and / or capacitor metal layer may have a multi-layer structure in which the aforementioned layers are stacked. The second insulating layer (120) covers the oxide semiconductor layer (300) and the connecting metal layer and / or capacitor metal layer and may be disposed on the first insulating layer (110).

[0121] The aforementioned display device (1) can function as a mask during the metallization process, where the second gate electrode (GE2) located above the second channel region (CHA2) covers the second channel region (CHA2) so that it is not metallized, and the third gate electrode (GE3) located above the third channel region (CHA3) covers the third channel region (CHA3) so that it is not metallized. However, in the display device (2) of the present embodiment, the second gate electrode (GE2) cannot function as a mask because it is located below the second channel region (CHA2), and the third gate electrode (GE3) also cannot function as a mask because it is located below the third channel region (CHA3). Accordingly, by placing a corresponding connecting metal layer on each of the non-metallicated first-1 connection region (CNA1-1), first-2 connection region (CNA1-2), second-1 connection region (CNA2-1), second-2 connection region (CNA2-2), and / or third connection region (CNA3), the same effect as the first-1 connection region (CNA1-1), first-2 connection region (CNA1-2), second-1 connection region (CNA2-1), second-2 connection region (CNA2-2), and / or third connection region (CNA3) being metallic can be produced. Of course, even when a capacitor metal layer corresponding to the second capacitor electrode (CE2) is placed on the second capacitor electrode (CE2), the same effect as the second capacitor electrode (CE2) being metallic can be produced.

[0122] A second conductive layer (400), such as that shown in FIG. 18, may be disposed on a second insulating layer (120). The second conductive layer (400) included in the display device (1) according to the above-described embodiment with reference to FIG. 5, etc., includes a data line (DL), an initialization-sensing line (ISL), a driving voltage line (VDL), a common voltage line (VSL), a gate wiring (GL), a shielding layer (SDL), a first-1 connection electrode (CNE1-1), a first-2 connection electrode (CNE1-2), a second-1 connection electrode (CNE2-1), a second-2 connection electrode (CNE2-2), and a third connection electrode (CNE3). In the case of the second conductive layer (400) included in the display device (2) according to the present embodiment, it also includes a shielding layer (SDL), a first-1 connecting electrode (CNE1-1), a first-2 connecting electrode (CNE1-2), a second-1 connecting electrode (CNE2-1), a second-2 connecting electrode (CNE2-2), and a third connecting electrode (CNE3). However, in the case of the display device (2) according to the present embodiment, the second conductive layer (400) does not include a data line (DL), an initialization-sensing line (ISL), a driving voltage line (VDL), a common voltage line (VSL), and a gate line (GL), whereas the second conductive layer (400) may include a control line (CL), a scan line (SL), and a connecting line (CNL).

[0123] The second conductive layer (400) may include a scan line (SL) and a control line (CL) extended in a first direction (e.g., x-axis direction). The second conductive layer (400) may include a connecting wire (CNL) extended in a first direction (e.g., x-axis direction).

[0124] The 2-1 connecting electrode (CNE2-1) and the connecting wire (CNL) may be integral. That is, the 2-1 connecting electrode (CNE2-1) and the connecting wire (CNL) may be formed integrally through the same process. For example, the 2-1 connecting electrode (CNE2-1) may be a part of the connecting wire (CNL). Therefore, the 2-1 connecting electrode (CNE2-1) may contain the same material as the connecting wire (CNL). In addition, the 2-1 connecting electrode (CNE2-1) may have the same layer structure as the connecting wire (CNL). For example, if the 2-1 connecting electrode (CNE2-1) has a two-layer structure, the connecting wire (CNL) may also have a two-layer structure formed of the same material.

[0125] A third insulating layer (130, see FIG. 20) covers the second conductive layer (400) and may be disposed on the second insulating layer (120). A fourth insulating layer (140, see FIG. 20) may be disposed on the third insulating layer (130) to cover the third insulating layer (130). A first display element (DPE1) may be disposed on the fourth insulating layer (140). The first display element (DPE1) may include a pixel electrode (510), an intermediate layer (520) including a light-emitting layer, and a counter electrode (530), and a pixel electrode (510) such as that shown in FIG. 19 may be disposed on the fourth insulating layer (140).

[0126] FIG. 20 is a cross-sectional view schematically illustrating a cross section taken along the line III-III' of the display device (2) illustrated in FIG. 15. Similar to the display device (1) described above, the first gate electrode (GE1) of the display device (2) may be positioned below the oxide semiconductor layer (300). That is, the first transistor (T1) of the display device (2) may have a bottom gate structure. Accordingly, the first insulating layer (110) may cover the first gate electrode (GE1). Since the effect that occurs when the first gate electrode (GE1) is placed below the oxide semiconductor layer (300) and the first insulating layer (110) covers the first gate electrode (GE1) also occurs in the case of the display device (2), the content that overlaps with the previously described content regarding the effect that occurs when the first gate electrode (GE1) of the display device (2) is placed below the oxide semiconductor layer (300) and the first insulating layer (110) covers the first gate electrode (GE1) is omitted. A first-1 connecting metal layer (CNA1-1a) may be placed on the first-1 connecting region (CNA1-1), a first-2 connecting metal layer (CNA1-2a) may be placed on the first-2 connecting region (CNA1-2), and a second capacitor metal layer (CE2a) may be placed on the second capacitor electrode (CE2).

[0127] FIG. 21 is a cross-sectional view schematically illustrating a cross section taken along line IV-IV' of the display device (2) illustrated in FIG. 15. As illustrated in FIG. 21, the second-1 connection electrode (CNE2-1) of the second transistor (T2) can be electrically connected to a connection metal layer on the second-1 connection region (CNA2-1) of the second transistor (T2). Accordingly, the second-1 connection electrode (CNE2-1) of the second transistor (T2) can be electrically connected to the second-1 connection region (CNA2-1) of the second transistor (T2). Additionally, the second-1 connection electrode (CNE2-1) of the second transistor (T2) can be integral with the connection wire (CNL). Since the connecting wire (CNL) is electrically connected to the first data line (DL1), the second-1 connecting electrode (CNE2-1) of the second transistor (T2) can be electrically connected to the first data line (DL1).

[0128] FIGS. 22 to 24 are cross-sectional views schematically illustrating the process of manufacturing a part of the display device (2) shown in FIG. 15. Specifically, FIGS. 22 to 24 are cross-sectional views schematically illustrating the process of manufacturing the connecting wiring (CNL), the second-1 connecting region (CNA2-1), the connecting metal layer on the second-1 connecting region (CNA2-1), and the second-1 connecting electrode (CNE2-1) of the display device (2) shown in FIG. 15.

[0129] First, as shown in FIG. 22, a first capacitor electrode (CE1), a second gate electrode (GE2), an initialization-sensing line (ISL), and a data line (DL) are formed on the upper surface of a substrate (100), and a first insulating layer (110) can be formed to cover the first capacitor electrode (CE1), the second gate electrode (GE2), the initialization-sensing line (ISL), and the data line (DL). Since the first insulating layer (110) covers the first conductive layer (200) to correspond to the entire surface of the substrate, the first insulating layer (110) can cover the first capacitor electrode (CE1), the second gate electrode (GE2), the initialization-sensing line (ISL), and the data line (DL) included in the first conductive layer (200).

[0130] Meanwhile, the aforementioned first gate electrode (GE1) can be formed through the same process as the second gate electrode (GE2). Therefore, the first gate electrode (GE1) may include the same material as the second gate electrode (GE2). Additionally, the first gate electrode (GE1) may have the same layer structure as the second gate electrode (GE2). For example, if the second gate electrode (GE2) has a two-layer structure, the first gate electrode (GE1) may also have a two-layer structure formed of the same material.

[0131] A second semiconductor pattern (SP2) can be formed on the upper portion of the first insulating layer (110). A second-1 connecting metal layer (CNA2-1a) corresponding to the second-1 connecting region (CNA2-1) can be formed on the second-1 connecting region (CNA2-1), and a second-2 connecting metal layer (CNA2-2a) corresponding to the second-2 connecting region (CNA2-2) can be formed on the second-2 connecting region (CNA2-2). To this end, a preliminary oxide semiconductor layer (not shown) is formed on the first insulating layer (110), and a preliminary connecting metal layer (not shown) is formed on the preliminary oxide semiconductor layer, and then the preliminary oxide semiconductor layer and the preliminary connecting metal layer can be patterned simultaneously using a photoresist. Specifically, the preliminary oxide semiconductor layer and the preliminary connecting metal layer can be patterned simultaneously by using a halftone mask during the exposure of the photoresist.

[0132] Next, as illustrated in FIG. 23, a second insulating layer (120) may be formed on the upper portion of the second semiconductor pattern (SP2), and a second-1 contact hole (H2-1) penetrating the second insulating layer (120) may be formed. The second-1 contact hole (H2-1) may be formed to overlap with the second-1 connection region (CNA2-1) on a plane. Additionally, a data line contact hole (H-DL) penetrating the first insulating layer (110) and the second insulating layer (120) may be formed, and the data line contact hole (H-DL) may overlap with the first data line (DL1) on a plane.

[0133] Next, as illustrated in FIG. 24, a second-1 connecting electrode (CNE2-1) and a connecting wire (CNL) can be formed on the second insulating layer (120). Specifically, the second-1 connecting electrode (CNE2-1) and the connecting wire (CNL) can be formed integrally through the same process.

[0134] As such, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0135] 1: Display device 100: Substrate 200: 1st Challenge Layer 300: Oxide semiconductor layer 400: Second Challenge Layer CHA1: 1st channel region CHA2: 2nd channel area GE1: 1st gate electrode GE2: Second gate electrode SDL: Shielding layer

Claims

Claim 1 A substrate; an oxide semiconductor layer disposed on the substrate and comprising a first channel region and a second channel region disposed spaced apart from the first channel region; a first conductive layer interposed between the substrate and the oxide semiconductor layer and comprising a first gate electrode overlapping the first channel region; a second conductive layer disposed on top of the oxide semiconductor layer and comprising a shielding layer overlapping the first channel region and a second gate electrode overlapping the second channel region; and a first insulating layer covering the first conductive layer so as to be interposed between the first conductive layer and the oxide semiconductor layer. and a second insulating layer covering the oxide semiconductor layer so as to be interposed between the oxide semiconductor layer and the second conductive layer; wherein the oxide semiconductor layer further comprises a first connection region in contact with the first channel region and having at least a portion having electrical characteristics different from the electrical characteristics of the first channel region, and a second connection region in contact with the second channel region and having at least a portion having electrical characteristics different from the electrical characteristics of the second channel region; wherein the second conductive layer further comprises a first connection electrode electrically connected to the first connection region through a first contact hole formed in the second insulating layer, and a second connection electrode spaced apart from the first connection electrode and electrically connected to the second connection region through a second contact hole formed in the first insulating layer and the second insulating layer; wherein the first insulating layer covers the first conductive layer so as to correspond to the entire surface of the substrate, and the second insulating layer, on the outer side of the oxide semiconductor layer, the first insulating layer and the second conductive layer A display device interposed between, wherein the second insulating layer is disposed only below the second conductive layer. Claim 2 A display device according to claim 1, wherein the shielding layer and the second gate electrode comprise the same material and have the same layer structure. Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 A display device according to claim 1, wherein the first connecting electrode is integral with the shielding layer. Claim 7 A display device according to claim 1, wherein the first conductive layer further comprises a scan line extending along a first direction. Claim 8 A display device according to claim 7, wherein the second conductive layer further comprises a data line extending along a second direction intersecting the first direction. Claim 9 A display device according to claim 8, wherein the first conductive layer further comprises a connecting wire, and the data line is electrically connected to the second connecting electrode through the connecting wire. Claim 10 A display device according to claim 1, wherein the first conductive layer comprises a first capacitor electrode, the oxide semiconductor layer comprises a second capacitor electrode that overlaps with the first capacitor electrode, and the second capacitor electrode has electrical characteristics different from the electrical characteristics of the first channel region. Claim 11 A display device according to claim 10, further comprising a display element including a pixel electrode, a light-emitting layer, and a counter electrode, wherein the second capacitor electrode is electrically connected to the display element. Claim 12 In claim 11, the display device wherein the second capacitor electrode is in direct contact with the pixel electrode. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete

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