Mobile Data Storage

Abstract

A mobile electronic device may comprise a memory device, an error correction code (ECC) encoder for encoding data, a restricted channel encoder configured to encode the output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming data into the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-word line voltage vector from the memory device and classify each bit of the vector into a log likelihood ration (LLR) value, a restricted channel decoder configured to receive a restricted vector from the EM signal processing component and generate an unrestricted vector, and an ECC decoder configured to decode the unrestricted vector. A machine learning interference cancellation component may operate based on an input from the EM signal processing component or independently.

Description

Technology Field

[0001] The present disclosure relates to data storage, and more specifically to data storage for mobile devices. Background Technology

[0002] A memory device is an electronic component used to store data. Among memory devices, NAND flash memory devices can provide improvements in manufacturing costs and performance by enabling the storage of multiple bits of data per memory cell. A memory cell in which multiple bits of data are stored can be referred to as a multi-level memory cell. A multi-level memory cell divides the threshold voltage range of the memory cell into multiple voltage states, and the data value recorded in the memory cell can be extracted using multiple memory cell voltage levels.

[0003] However, storing multiple bits per memory cell can reduce the dynamic voltage range of each voltage state, and the memory cells may become more sensitive to noise. Compensating for this noise may require increased computational power, which can degrade the performance of mobile devices. Therefore, a reliable low-power multi-level memory system is required for use in mobile electronic devices. The problem to be solved

[0004] The problem that the technical concept of the present invention aims to solve is to provide a reliable low-power multi-level memory system for use in mobile electronic devices. means of solving the problem

[0005] To achieve the above objectives, a mobile electronic device for data storage for a mobile device is described. Embodiments of the mobile electronic device may include a memory device, a processor, and internal memory, and may include a memory controller configured to operate the memory device, wherein the memory controller includes an error correction code (ECC) encoder configured to encode data for programming. Additionally, the memory controller includes a restricted channel encoder configured to encode the output of the ECC encoder based on one or more restrictions for programming to the memory device, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data, a restricted channel decoder configured to receive a restricted vector and generate an unrestricted vector, and an ECC decoder configured to decode the unrestricted vector. In some examples, it includes an expectation maximization (EM) signal processing component configured to receive a noisy multi-word line voltage vector from the memory device and classify each bit of the vector by a log likelihood ration (LLR) value.

[0006] A method for programming data into a memory device is described. Embodiments of the present method receive a data block, encode the data block based on an ECC coding scheme, encode the data block based on a limited coding scheme, and program the encoded data block into a memory device using RLPP.

[0007] A method for reading data from a memory device is described. An embodiment of the method is configured to read a data block from a memory device, process the data block using EM signal processing to classify each bit of the data block into LLR values, decode the data block based on a restricted coding scheme, and decode the data block based on an ECC coding scheme. Effects of the invention

[0008] The mobile data storage of the technical concept of the present invention has the effect of providing a reliable low-power multi-level memory system for use in mobile electronic devices. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing the implementation of a data processing system including a memory system according to an embodiment of the present invention. Figure 2 is a block diagram showing the memory system of Figure 1. Figure 3 is a detailed block diagram of the non-volatile memory device of Figure 1. Figure 4 is a block diagram showing the memory cell array of Figure 2. Figure 5 is a circuit diagram showing an example of a memory block of the memory cell array of Figure 4. FIGS. 6a and 6b show an example of a memory controller according to an embodiment of the present invention. FIG. 7 shows an example of an ECC (Error Correction Code) coding method according to an embodiment of the present invention. FIG. 8 is a diagram illustrating a hierarchical reinforcement learning technique according to an embodiment of the present invention. FIG. 9 is a diagram illustrating the structure of a neural network for noise removal according to one embodiment of the present invention. FIG. 10 shows an example of a neural network decoder according to an embodiment of the present invention. FIG. 11 is a diagram illustrating an example of a process of programming data into a memory device according to embodiments of the present invention. FIG. 12 is a diagram showing an example of a process of reading data from a memory device according to embodiments of the present invention. FIG. 13 shows an example of a process for performing interference removal according to an embodiment of the present invention. FIG. 14 shows an example of a process for performing neural network decoding according to an embodiment of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0011] The disclosure of the present invention relates to a system and method for programming and reading data from a memory device. A specific embodiment of the present disclosure relates to a NAND flash memory device capable of storing 5 bits or 6 bits of data in each memory cell.

[0012] NAND programming is a complex process based on applying voltage to memory cells. However, cell voltage can be affected by variables such as current voltage levels, pulse power, and inter-cell interference. Additionally, cell voltage can be affected by inhibited cell disruption, inter-word-line coupling, and cell retention. Furthermore, the write results to a NAND device can be probabilistic. For example, data may contain noise components, which can cause the aforementioned problems.

[0013] Accordingly, the present invention describes a system and method for reliably programming and reading data from a 5 or 6-bit memory device. Specific embodiments may relate to a memory device designed for use in a mobile architecture.

[0014] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Throughout the attached drawings, the same reference numerals may refer to the same elements.

[0015] Terms such as "first," "second," "third," etc. are used in this specification to distinguish one component from another, and it will be understood that the components are not limited by these terms. Accordingly, in an exemplary embodiment, the "first" component may be described as the "second" component in another exemplary embodiment.

[0016] Additionally, unless the context clearly indicates otherwise, the description of a feature or aspect in each exemplary embodiment may be understood as applicable to other similar features or aspects in other exemplary embodiments.

[0017] Additionally, configurations expressed in the singular in the description of the present disclosure may include a plural meaning unless the context clearly indicates otherwise.

[0018] Herein, when one value is described as being approximately equal to another value, or substantially equal to another value, or equal to another value, the values ​​may be equal within the measurement error, or, if not measurement-wise equal, may be sufficiently close to the value to be functionally equal as understood by a person skilled in the art. For example, the term "approximately" may mean that the mentioned value is within an acceptable range of deviation from a specific value determined by a person skilled in the art, taking into account the measurement and any errors that may be associated therewith (e.g., limitations of the measurement system). For example, the term "approximately" may mean within one or more standard deviations understood by a person skilled in the art. Furthermore, although a parameter may be described herein as being "approximate" with respect to a specific value, according to exemplary embodiments, the parameter may be understood to correspond to an exact specific value, or to be a specific value within a specific possible error to an extent understood by a person skilled in the art.

[0019] Exemplary memory system

[0020] FIG. 1 is a block diagram showing an example of implementation of a data processing system including a memory system according to an exemplary embodiment of the present invention.

[0021] Referring to FIG. 1, the data processing system (10) may include a host (100) and a memory system (200). The memory system (200) illustrated in FIG. 1 may be used in various systems that include data processing functions. Various systems may be various devices, such as mobile devices like smartphones or tablet computers, for example. However, various devices are not limited thereto.

[0022] The memory system (200) may include various types of memory devices. Here, embodiments of the present invention are described as including a memory device that is a non-volatile memory. However, embodiments of the present invention are not limited thereto. For example, the memory system (200) may include a memory device that is a volatile memory.

[0023] According to exemplary embodiments, the memory system (200) may include non-volatile memory devices such as ROM (read-only memory), magnetic disks, optical disks, flash memory, etc. Flash memory may be a memory that stores data according to changes in the threshold voltage of a MOSFET (metal-oxide-semiconductor field-effect transistor) and may include, for example, NAND and NOR flash memory. The memory system (200) may be implemented using a memory card that includes a non-volatile memory device such as, for example, an embedded multimedia card (eMMC), a secure digital (SD) card, a micro SD card, or universal flash storage (UFS). Alternatively, the memory system (200) may be implemented using an SSD that includes a non-volatile memory device as an example. Here, the configuration and operation of the memory system (200) will be described assuming that the memory system (200) is a non-volatile memory system. However, the memory system (200) is not limited thereto. As an example, the host (100) may include a System-on-Chip (SoC) application processor (AP) mounted on a mobile device, or a central processing unit (CPU) included in a computer system.

[0024] As described above, the host (100) may include an AP (110). The AP (110) may include various types of intellectual property (IP) blocks. For example, the AP (110) may include a memory device driver (111) that controls the memory system (200). The host (100) may communicate with the memory system (200) to transmit commands related to memory operations and receive a confirm command in response to the transmitted commands. The host (100) may communicate with the memory system (200) regarding an information table related to memory operations.

[0025] The memory system (200) may include a memory controller (210) and a memory device (220). The memory controller (210) receives a command related to memory operation from the host (100) and can generate an internal command and an internal clock signal using the received command. The memory device (220) can store written data in a memory cell array in response to the internal command, or provide read data to the memory controller (210) in response to the internal command.

[0026] A memory device (220) may include a memory cell array that retains data stored therein even when the power to the memory device (220) is not turned on. The memory cell array may include memory cells such as NAND or NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric access memory (FRAM), phase change memory (PCM), etc. For example, if the memory cell array includes NAND flash memory, the memory cell array may include a plurality of blocks and a plurality of pages. Data may be programmed or read out in page units, and data may also be erased in block units. An example of a memory block included in a memory cell array is illustrated in FIG. 4.

[0027] FIG. 2 is a block diagram illustrating the memory system of FIG. 1 according to an exemplary embodiment of the present invention.

[0028] Referring to FIG. 2, the memory system (200) may include a memory device (220) and a memory controller (210). The memory controller (210) may also be referred to as a controller circuit in this specification. The memory device (220) may perform a write operation, a read operation, or an erase operation under the control of the memory controller (210).

[0029] The memory controller (210) can control the memory device (220) according to a request received from the host (100) or an internally designated schedule. The memory controller (210) may include a controller core (211), internal memory (214), a host interface block (215), and a memory interface block (216). Additionally, the memory controller (210) may include a device information storage unit (217) that provides first device information (DI1) to the host interface block (215) and second device information (DI2) to the controller core (211).

[0030] The controller core (211) may include a memory control core (212) and a machine learning core (213), each of which may be implemented as one or more processors. The memory control core (212) may control and access the memory device (220) according to a request received from the host (100) or an internally specified schedule. Additionally, the memory control core (212) may manage and execute various metadata and codes used to manage or operate the memory system (200).

[0031] The machine learning core (213) can be used to perform training and inference of a neural network designed to perform noise removal for a memory device (220) as described in more detail below.

[0032] The internal memory (214) may be used, for example, as system memory used by the controller core (211), cache memory for storing data of the memory device (220), or buffer memory for temporarily storing data between the host (100) and the memory device (220). The internal memory (214) may store a mapping table (MT) representing the relationship between a logical address assigned to the memory system (200) and a physical address of the memory device (220). The internal memory (214) may include, for example, DRAM or SRAM.

[0033] According to an exemplary embodiment, a neural network such as the example described with reference to FIG. 9 may be included in a computer program stored in the internal memory (214) of the memory controller (210) or in the memory device (220). The computer program including the neural network may be executed by a machine learning core (213) to remove noise from the data stored in the memory device (220). Accordingly, according to exemplary embodiments, the memory system (200) may remove noise from the data stored in the memory device (220) during the normal read operation of the memory device (220). That is, after the manufacturing of the memory system (200) is completed, during the normal operation of the memory system (200), particularly during the normal read operation of the memory system (200) in which data is read from the memory device (220), the noise from the data stored in the memory device (220) being read may be removed using a neural network that is locally stored and executed in the memory system (200), and the noise-removed data may be read from the memory device (220).

[0034] The host interface block (215) may include components for communicating with the host (100), such as a physical block, as an example. The memory interface block (216) may include components for communicating with the memory device (220), such as a physical block, for example.

[0035] Below, an example of the operation of the memory system (200) over time is described. When power is supplied to the memory system (200), the memory system (200) can perform initialization with the host (100).

[0036] The host interface block (215) can provide a first request (REQ1) received from the host (100) to the memory control core (212). The first request (REQ1) may include a command (e.g., a read command or a write command) and a logical address. The memory control core (212) can convert the first request (REQ1) into a second request (REQ2) suitable for the memory device (220).

[0037] For example, the memory control core (212) can convert the format of the command. The memory control core (212) can obtain address information (AI) by referring to the mapping table (MT) stored in the internal memory (214). The memory control core (212) can convert a logical address into a physical address of the memory device (220) using the address information (AI). The memory control core (212) can provide a second request (REQ2) suitable for the memory device (220) to the memory interface block (216).

[0038] The memory interface block (216) can register a second request (REQ2) from the memory control core (212) in the queue. The memory interface block (216) can transmit the request that was first registered in the queue to the memory device (220) as a third request (REQ3).

[0039] If the first request (REQ1) is a write request, the host interface block (215) can write data received from the host (100) to the internal memory (214). If the third request (REQ3) is a write request, the memory interface block (216) can transfer data stored in the internal memory (214) to the memory device (220).

[0040] When data recording is complete, the memory device (220) may transmit a third response (RESP3) to the memory interface block (216). In response to the third response (RESP3), the memory interface block (216) may provide a second response (RESP2) to the memory control core (212) indicating that data recording is complete.

[0041] After the data is stored in the internal memory (214) or after the second response (RESP2) is received, the memory control core (212) can transmit a first response (RESP1) to the host (100) through the host interface block (215) indicating that the request has been completed.

[0042] If the first request (REQ1) is a read request, the read request may be transmitted to the memory device (220) through the second request (REQ2) and the third request (REQ3). The memory interface block (216) may store the data received from the memory device (220) in the internal memory (214). When the transmission of data is completed, the memory device (220) may transmit a third response (RESP3) to the memory interface block (216).

[0043] Upon receiving the third response (RESP3), the memory interface block (216) may provide the second response (RESP2) to the memory control core (212) indicating that the storage of data is complete. Upon receiving the second response (RESP2), the memory control core (212) may transmit the first response (RESP1) to the host (100) through the host interface block (215).

[0044] The host interface block (215) can transmit data stored in the internal memory (214) to the host (100). According to one embodiment, if data corresponding to the first request (REQ1) is stored in the internal memory (214), the transmission of the second request (REQ2) and the third request (REQ3) may be omitted. Additionally, the memory device (220) can transmit the first serial peripheral interface information (SPI1) to the memory interface block (216). The memory interface block (216) can transmit the second serial peripheral interface information (SPI2) to the controller core (211).

[0045] FIG. 3 is a detailed block diagram of a non-volatile memory device of FIG. 1 according to an exemplary embodiment of the present invention. Referring to FIG. 3, as an example, the memory device (220) may include a memory cell array (221), control logic (222), a voltage generation unit (223), a row decoder (224), and a page buffer (225).

[0046] A memory cell array (221) may be connected to one or more string select lines (SSL), multiple word lines (WL), one or more ground select lines (GSL), and multiple bit lines (BL). The memory cell array (221) may include multiple memory cells placed at the intersection of multiple word lines (WL) and multiple bit lines (BL).

[0047] The control logic (222) receives a command (CMD, for example, an internal command) and an address (ADD) from the memory controller (210), and can receive a control signal (CTRL) from the memory controller (210) to control various function blocks within the memory device (220). Based on the command (CMD), address (ADD), and control signal (CTRL), the control logic (222) can output various control signals to write data to the memory cell array (221) or to read data from the memory cell array (221). In this way, the control logic (222) can control the overall operation of the memory device (220).

[0048] Various control signals output by the control logic (222) may be provided to the voltage generator (223), row decoder (224), and page buffer (225). As an example, the control logic (222) may provide a voltage control signal (CTRL_vol) to the voltage generator (223), provide a row address (X-ADD) to the row decoder (224), and provide a column address (Y-ADD) to the page buffer (225).

[0049] The voltage generation unit (223) can generate various voltages for performing program, read, and erase operations on the memory cell array (221) based on the voltage control signal (CTRL_vol). As an example, the voltage generation unit (223) can generate a first driving voltage (VWL) for driving a plurality of word lines (WL), a second driving voltage (VSSL) for driving a plurality of string select lines (SSL), and a third driving voltage (VGSL) for driving a plurality of ground select voltages (GSL). In this case, the first driving voltage (VWL) may be a program voltage (e.g., write voltage), a read voltage, an erase voltage, a pass voltage, or a program verification voltage. Additionally, the second driving voltage (VSSL) may be a string select voltage (e.g., an on voltage or an off voltage). Additionally, the third driving voltage (VGSL) may be a ground select voltage (e.g., an on voltage or an off voltage).

[0050] The row decoder (224) can be connected to the memory cell array (221) through a plurality of word lines (WL) and can activate a portion of the plurality of word lines (WL) in response to a row address (X-ADD) received from the control logic (222). For example, in a read operation, the row decoder (224) can apply a read voltage to a selected word line and a pass voltage to an unselected word line.

[0051] In a program operation, the row decoder (224) may apply a program voltage to a selected word line and a pass voltage to an unselected word line. According to an exemplary embodiment, in at least one of a plurality of program loops, the row decoder (224) may apply a program voltage to a selected word line and additionally to a selected word line.

[0052] The page buffer (225) may be connected to the memory cell array (221) via a plurality of bit lines (BL). As an example, in a read operation, the page buffer (225) may operate as a sensing amplifier that outputs data stored in the memory cell array (221). Alternatively, in a program operation, the page buffer (225) may operate as a write driver that writes desired data to the memory cell array (221).

[0053] FIGS. 4 and 5 illustrate an example in which a memory system (200) is implemented using a three-dimensional flash memory. The three-dimensional flash memory may include three-dimensional (e.g., vertical) NAND (VNAND) memory cells. An implementation of a memory cell array (221) including three-dimensional memory cells is described below. Each of the memory cells described below may be a NAND memory cell.

[0054] FIG. 4 is a block diagram of the memory cell array of FIG. 2 according to an exemplary embodiment of the present invention.

[0055] Referring to FIG. 4, a memory cell array (221) according to an exemplary embodiment of the present invention may include a plurality of memory blocks (BLK1 to BLKz). Each of the memory blocks (BLK1 to BLKz) may have a three-dimensional structure (e.g., a vertical structure). As an example, each of the memory blocks (BLK1 to BLKz) may include structures extending in a first to third direction. For example, each of the memory blocks (BLK1 to BLKz) may include a plurality of NAND strings extending in a second direction. The plurality of NAND strings may be provided, for example, in a first to third direction.

[0056] Each of the NAND strings can be connected to a bit line (BL), a string select line (SSL), a ground select line (GSL), a word line (WL), and a common source line (CSL). That is, each of the memory blocks (BLK1 to BLKz) can be connected to a plurality of bit lines (BL), a plurality of string select lines (SSL), a plurality of ground select lines (GSL), a plurality of word lines (WL), and a common source line (CSL). The memory blocks (BLK1 to BLKz) will be described in more detail below with reference to FIG. 5.

[0057] FIG. 5 is a circuit diagram of a memory block according to an exemplary embodiment of the present invention. FIG. 5 illustrates an example of one of the memory blocks (BLK1 to BLKz) in the memory cell array of FIG. 4.

[0058] A memory block (BLKi) may include a plurality of cell strings (CS11 to CS41, CS12 to CS42). The plurality of cell strings (CS11 to CS41, CS12 to CS42) may be arranged in row and column directions to form rows and columns. Each of the cell strings (CS11 to CS41, CS12 to CS42) may include a ground select transistor (GST), memory cells (MC1 to MC6), and a string select transistor (SST). The ground select transistor (GST), memory cells (MC1 to MC6), and string select transistor (SST) included in each of the cell strings (CS11 to CS41, CS12 to CS42) may be stacked in a height direction substantially perpendicular to the substrate.

[0059] The columns of multiple cell strings (CS11 to CS41, CS12 to CS42) can each be connected to different string selection lines (SSL1 to SSL4). As an example, the string selection transistors (SST) of cell strings (CS11, CS12) can be commonly connected to the string selection line (SSL1). Additionally, the string selection transistors (SST) of cell strings (CS21, CS22) can be commonly connected to the string selection line (SSL2). Additionally, the string selection transistors (SST) of cell strings (CS31, CS32) can be commonly connected to the string selection line (SSL3). Additionally, the string selection transistors (SST) of cell strings (CS41, CS42) can be commonly connected to the string selection line (SSL4).

[0060] The rows of multiple cell strings (CS11 to CS41, CS12 to CS42) can each be connected to different bit lines (BL1, BL2). As an example, the string select transistors (SST) of the cell strings (CS11 to CS41) can be commonly connected to the bit line (BL1). Additionally, the string select transistors (SST) of the cell strings (CS12 to CS42) can be commonly connected to the bit line (BL2).

[0061] The columns of multiple cell strings (CS11 to CS41, CS12 to CS42) can each be connected to different ground select lines (GSL1 to GSL4). As an example, the ground select transistors (GST) of cell strings (CS11, CS12) can be commonly connected to the ground select line (GSL1). Additionally, the ground select transistors (GST) of cell strings (CS21, CS22) can be commonly connected to the ground select line (GSL2). Additionally, the ground select transistors (GST) of cell strings (CS31, CS32) can be commonly connected to the ground select line (GSL3). Additionally, the ground select transistors (GST) of cell strings (CS41, CS42) can be commonly connected to the ground select line (GSL4).

[0062] Memory cells placed at the same height as the substrate (or ground select transistor (GST)) may be commonly connected to one word line, and memory cells placed at different heights from the substrate may be connected to different word lines (WL1 to WL6). As an example, memory cells (MC1) may be commonly connected to word line (WL1). Also, memory cells (MC2) may be commonly connected to word line (WL2). Also, memory cells (MC3) may be commonly connected to word line (WL3). Also, memory cells (MC4) may be commonly connected to word line (WL4). Also, memory cells (MC5) may be commonly connected to word line (WL5). Also, memory cells (MC6) may be commonly connected to word line (WL6). In addition, the ground selection transistors (GST) of the cell strings (CS11 to CS41, CS12 to CS42) can be commonly connected to the common source line (CSL).

[0063] Memory controller architecture

[0064] FIG. 6a illustrates an example of a memory controller according to one embodiment of the present disclosure. The illustrated embodiment includes a memory controller (600) and a memory device (660). The memory controller (600) can receive a data block, program data into the memory device (660), and read the data block from the memory device (660).

[0065] The memory controller (600) may be an example of the memory controller (210) described with reference to FIGS. 1 through 3. According to a specific embodiment, the memory controller (600) may include a processor and internal memory and may be configured to operate the memory device (660). In some embodiments, the memory controller (600) may include a simplified memory controller architecture suitable for use in mobile architectures and for reduced power consumption. In some embodiments, each cell of the memory device (660) may be a 5-bit or 6-bit NAND flash memory cell.

[0066] The memory controller (600) may further include an error correction code (ECC) encoder (605), a constrained channel encoder (610), a reinforcement learning pulse programming (RLPP) component (615), an expectation maximization (EM) signal processing component (635), a constrained channel decoder (640), an ECC decoder (645), a machine learning interference succession removal component (650), and a neural network decoder (655).

[0067] The ECC encoder (605) may be configured to encode data for programming into a memory device (660). The ECC encoder (605) may take a block-sized data matrix as input and output an encoded matrix. In some embodiments, the ECC encoder (605) may be configured to encode data using an S-polar coding design, including a Reed Solomon (RS) coding design and a polar coding design. In some embodiments, the ECC encoder (605) may include a reduced frame size and a reduced redundancy level configured for a mobile architecture. Additionally, the ECC encoder (605) may be an example of the corresponding element(s) described with reference to FIG. 10, or may include aspects thereof.

[0068] The restricted channel encoder (610) may be configured to encode the output of the ECC encoder (605) based on one or more restrictions for programming the memory device (660). In some embodiments, the restricted channel encoder (610) may be configured to identify data from the next word line of the memory device (660) prior to encoding the output of the ECC encoder (605) for the current word line of the memory device (660). The restricted channel encoder (610) may receive the encoded matrix and the next-WL read (before programming) as inputs and output a restricted vector.

[0069] The restricted channel encoder (610) can encode a data block based on a restricted coding design. Additionally, the restricted channel encoder (610) can identify data from the next word line of the memory device (660), where the restricted coding design can be based on data from the next word line.

[0070] The RLPP (reinforcement learning pulse programming) component (615) can identify a programming algorithm for programming data into a memory device (660) and can be configured to program an encoded data block into the memory device (660) using the RLPP. In some embodiments, the RLPP component (615) may include a block agent (620), a word line agent (625), and a level agent (630).

[0071] The block agent (620) receives a WL voltage vector as input and can output a block policy (e.g., a target word line to be programmed). The word line agent (625) receives the restricted vector and the block policy and can output a word line policy (e.g., a target level to be programmed). The level agent (630) receives the word line policy and can output a level policy (including programming parameters such as an inhibit vector and pulse magnitude). The level agent (630) can also provide an error statistics vector to the word line agent (625).

[0072] The memory device (660) receives the level policy and can store voltage levels for representing bits of information. During a read operation (after receiving one or more read requests, such as multi-RD read requests), a noisy multi-wordline voltage vector can be provided to the EM signal processing component (635).

[0073] An EM (Exectation Maximization) signal processing component (635) may be configured to receive a noisy multi-word line voltage vector from a memory device (660) and classify each bit of the vector into an LLR (log Likelihood Ratio) value. In some embodiments, the EM signal processing component (635) may be configured to provide the LLR value to an ECC decoder (645). In some embodiments, the EM signal processing component (635) may be configured based on a reduced sample size for a mobile architecture. The EM signal processing component (635) may receive the noisy multi-word line voltage vector and output a restricted vector (or, may be referred to as a restricted vector) as well as LLR information for each bit.

[0074] A restricted channel decoder (640) may be configured to receive a restricted vector from an EM signal processing component (635) and generate an unrestricted vector (or, may be referred to as an unrestricted vector). In some embodiments, the restricted channel decoder (640) may decode a data block based on a restricted coding design. The restricted channel decoder (640) may receive a restricted vector and output an unrestricted vector.

[0075] The ECC decoder (645) may be configured to decode data containing an unrestricted vector. As an example, the ECC decoder (645) may decode a data block based on an ECC coding design. In some embodiments, the ECC coding design may include an S-polar coding design including an RS coding design and a polar (or polar) coding design. In some embodiments, the decoding process of the data block based on the ECC coding design may be performed based on LLR values. The ECC decoder may receive LLR information for each bit as well as the unrestricted vector and output word line data and voltage vectors. The ECC decoder (645) may receive the results of a neural network decoder. In some cases, the ECC decoder (645) transmits the noisy word line voltage vector to a machine learning interference successive erasure component (650) and receives the noise-removed word line voltage vector.

[0076] The machine learning interference successive removal component (650) may be configured to receive a noisy word line vector from the ECC decoder (645) and provide a noise-removed word line vector to the ECC decoder (645). In some embodiments, the machine learning interference successive removal component (650) may operate based on input from the EM signal processing component (635). However, in other embodiments, the EM signal processing component (635) may operate independently of the EM signal processing component (635).

[0077] In some cases, the machine learning interference continuation removal component (650) may determine that decoding based on the ECC coding design is insufficient. Additionally, the machine learning interference continuation removal component (650) may perform machine learning interference continuation removal based on the determination that the ECC decoder did not properly decode the data block. In some embodiments, machine-learning processing for NAND cells may be based on the removal of coupling effects within the EM.

[0078] The neural network decoder (655) receives the word line data vector and the word line voltage vector and can generate a recovered data vector. In some embodiments, the neural network decoder (655) includes a reduced number of nodes, and the reduced number of nodes may be selected for a mobile architecture. In some cases, the neural network decoder (655) transmits the result to the ECC decoder (645). That is, the neural network decoder (655) can output the recovered data vector.

[0079] In some cases, the neural network decoder (655) may determine that decoding based on an ECC coding design is insufficient. Additionally, the neural network decoder (655) may decode a data block using the neural network decoder (655). The neural network decoder (655) may be an example of the corresponding element(s) described with reference to FIG. 10, or may include an embodiment of the corresponding element(s).

[0080] FIG. 6b illustrates another example of a memory controller according to one embodiment of the present invention. The illustrated example includes a memory controller (601) and a memory device (660). The memory controller (601) can receive a data block, program data in the memory device (660), and read a data block from the memory device (660). The sub-components of the memory controller (601) may be similar to the sub-components of the memory controller (600) described with reference to FIG. 6A, and differences may exist below. FIG. 6a and FIG. 6b are both illustrated as examples, and embodiments of the present invention are not limited thereto.

[0081] Specifically, according to FIG. 6b, the memory controller (601) may include a reinforcement learning feedback component (613) that corresponds to a reinforcement learning pulse programming (RLPP) component (615) but provides feedback to a block signal filter component (611). The block signal filter component (611) may provide a block programming sequence to a word line signal filter (612) that can provide a word line programming sequence for programming to a memory device (660).

[0082] Additionally or alternatively, the machine learning interference successive removal component (650) can receive a noisy multi-wordline voltage vector directly from the memory device (660) and provide a noisy wordline data vector to the limited channel decoder (640).

[0083] Error correction coding

[0084] FIG. 7 illustrates an example of an ECC encoding design according to embodiments of the present disclosure. An S-polar coding design may be used to encode data for programming into a memory device. An S-polar coding design may include aspects of an RS (Reed Solomon) coding design and a polar coding design. Specifically, a data block (700) comprising an information bit (705), a fixed bit (710, e.g., based on a polar coding design), a polar code word (715), and an RS code word (720) is illustrated.

[0085] Error correction coding (ECC) and decoding operations can be performed on a data stream to correct communication errors such as interference or noise. A polar code is a linear block error correction code based on multiple recursive concatenation of short kernel codes that convert a physical channel into multiple virtual outer channels. Virtual channels tend to have high reliability or low reliability (e.g., polarization). Data bits are assigned to the most reliable channel, and unreliable channels may be "frozen" or set to zero.

[0086] RS codes also operate on data blocks, which can be processed into a set of finite field elements referred to as symbols. RS encoding design involves adding check symbols to the data. Using check symbols, RS codes can detect error symbols.

[0087] S-polar codes can be based on the concatenation of polar codes and RS codes. Features of S-polar codes can include high performance along with easy scalability through overhead reduction and code size adjustment. S-polar codes can utilize a multi-stage encoding process. Multiple RS codes can be encoded in parallel at the symbol level.

[0088] Fig. 7 is A data block with dimensions Dimensional Paula Code Word (715), Dimensional Polar Code Word (715) and Dimensional This indicates the case where a polar code word (715) is included. Thus, the S-polar code is of J dimensions. RS code word (720), Dimensional RS code word (720), and Dimensional It may include an RS code word (720).

[0089] Restrictive coding

[0090] In addition to ECC encoding, a constrained coding scheme may be applied. Constrained coding allows a programming task to be represented as a set of parameters and constraints. First, the user inputs a set of variables and defines a problem where all variables have a set of possible values. Then, constraints are applied, and, for example, specific values ​​may be determined to be usable or unusable. Subsequently, a solution is output. Next, either a decision-making operation or a constraint propagation operation is performed. New constraints are determined by the decision-making operation. Additionally, contradictions are determined by the constraint propagation operation, a new set of constraints is defined, and then resolved until the desired output is produced.

[0091] Therefore, a restricted coding design can set constraints that limit the use of specific bit patterns that are likely to cause interference when data is read from a memory device. These constraints can be applied to bits of word lines, and can also be applied across word lines.

[0092] According to the present disclosure, limiting coding may be for the mitigation of inter-pillar interference. Inter-pillar interference may refer to interference between adjacent cell pillars. That is, high voltage levels may cause interference in low-level pillars. As an example, the first eight lowest levels are the interfered levels and the last eight high levels are the interfered levels. On average, there are four layers of interfered levels and four layers of interfered levels. In one embodiment, limiting coding reduces the number of interfered high-level and low-level pillars and provides a deterministic process in each pillar having two interfered levels and two interfered levels.

[0093] Reinforcement Learning Pulse Programming

[0094] FIG. 8 illustrates a basic hierarchical reinforcement learning design according to one embodiment of the present disclosure.

[0095] Programming of a NAND flash device can be described by the following process. First, each cell of a word line (WL) has a voltage Vcell, and / Vcell is a vector of all voltages in the word line. After an erase operation, / Vcell = / Vstart. Then, each cell has a target voltage Vtarget, and / Vtarget is a vector of all target voltages in the word line, and the vector / Vcell may also be referred to as the word line state.

[0096] Then, the program agent can apply a series of pulses to the word line that change the state (Vcell). The agent's objective is to change / Vcell as close as possible to / Vtarget. After each pulse, / V(cell, new) = / V(cell, old) + / ΔVcell can be satisfied. In some cases, ΔVcell may depend on pulse parameters, such as pulse power and prohibition vector, selected by the agent. Pulses with selected parameters may be referred to as actions. The new word line state may depend only on the previous word line state and the last action performed. This type of process is known as a Markov Decision Process (MDP).

[0097] Accordingly, according to specific embodiments, NAND flash memory has a three-level hierarchy of blocks, word lines, and cells. The number of blocks may vary depending on the chip type, but generally, there may be several thousand per chip. A flash memory device may be composed of one or more such chips, and accordingly, the total number of blocks per flash memory device may vary significantly. The number of word lines per block may also vary. Different types of chips may contain 64, 128, or 256 word lines, and this may change in the future. A cell is a physical part of a word line, and as an example, a word line is essentially a long string of cells.

[0098] Levels are conceptual entities in that each cell is programmed to have a specific voltage level. Cells are then grouped into N groups based on their voltage levels, in which case there can be N levels in a word line. Cell voltage can determine which level a cell belongs to and, accordingly, what information the cell encodes. All cells of the same level store the same information. The number of levels per word line can vary depending on the recording design. The number of levels corresponds to the power of two of the number of bits per cell being recorded. For example, with 3 bits per cell, there can be 8 levels per word line, but the number of levels within the same block can vary depending on how many bits are recorded per cell in a specific word line.

[0099] Hierarchical reinforcement learning (HRL) is a framework for combining learning at different scales. According to embodiments of the present disclosure, there may be three different agents operating at three different scales—block, word-line, and cell scales—all combined under the HRL framework. A single action of a higher-level agent may be an entire episode of a lower-level agent, and, for example, an action of a higher-level agent may define parameters that allow the lower-level agent to execute a series of lower-level actions constituting the entire episode. However, each agent in the hierarchy may include a decision model that allows the agent to select an action. These models are policy networks, and an exemplary policy network may be an actor-critic model.

[0100] A prohibition vector can mark all cells that need to be programmed as 0 and cells that should not be programmed as 1. Since the prohibition vector can be very large (approximately 147K cells), the policy network cannot output cells as decisions, and, for example, can decide individually for each cell in the vector whether each cell should be 1 or 0. Therefore, embodiments of the present invention may use other solutions. Methods according to the embodiments may output a voltage threshold and place all cells whose voltage exceeds the selected threshold into the prohibition vector. The remaining cells may be left as 0. In this way, a network according to one embodiment may output only one number instead of 147K, excluding network power output, which is also a single number and may be separate from the prohibition vector.

[0101] Embodiments of the present disclosure can train an agent to program different voltage levels to different cells. However, because the state-action space is too large to perform forced reinforcement learning, embodiments of the present disclosure can utilize the hierarchical structure of NAND flash and divide the task into multiple subtasks at different levels. This approach can integrate groups of smaller subtasks and enables learning.

[0102] Embodiments of the RLPP components may include three distinct agents. A level rank agent can efficiently record each voltage level of a word line and minimize the distance to the target level. After the voltage level is recorded, control can be transferred to a word line agent. The word line rank agent determines the voltage level to be programmed for a given word line and can instruct a lower-level agent to program that level while minimizing interference between different levels within the same word line. The number of possible levels is 2n, where n corresponds to the number of bits per cell. After the entire word line is recorded, control can be transferred to a block agent. The block rank agent determines the word line to be programmed in the block and can minimize interference between word lines within the same block. After all word lines are recorded, NAND programming can be terminated.

[0103] As illustrated in FIG. 8, a method according to one embodiment may start with a block agent that programs the entire block. The block agent is a “block reinforcement algorithm” (812), obtains a “block state” (813) input from the chip, and can determine an action, such as which word line within the block will be currently programmed. This action is converted into a set of parameters that is transmitted as a block command (814) to a word line agent that starts operating. The word line agent is a word line reinforcement algorithm (822) that receives the block command (814), obtains a word line state (823) from the chip, determines the action itself, and transmits the action to a level agent as a word line command (824).

[0104] The level agent is a level reinforcement algorithm (832) that receives a word line command (824), obtains a level state (833) from the chip, and determines an action. This action is converted into a level command (834) for the flash chip (840). The level command (834) programs the flash chip (840) according to the action until it is completed, and then provides control to the word line agent indicating that the level agent's operation is complete. After the word line agent is also completed, the word line agent provides control to the block agent indicating that the word line agent's operation is complete. The block algorithm, word line algorithm, and level algorithm parameter rewards (811, 821, 831) in the leftmost column are used during agent training. Then, in addition to performing decisions, each training agent uses the rewards and performs updates and improvements on its own.

[0105] According to embodiments of the present invention, a reinforcement learning model may be based on existing algorithms or human expertise. For example, a reinforcement learning model according to an exemplary embodiment may learn through imitation from existing algorithms or experts. The reinforcement learning model may be improved at the word line level, and after finding a basic stable policy, the reinforcement learning model may be adapted to program blocks.

[0106] Maximizing expectations

[0107] In some cases, cells with 5 or 6 bits per cell may have relatively dense voltage levels (e.g., 156mv for 5 bpc (Bit Per Cell), 105mv for 6 bpc). This can introduce additional errors when reading out the cell's voltage levels. In other words, additional accuracy may be required, and the readout operation may be more sensitive to interference. Therefore, the EM signal processing component may be configured to receive a noisy multi-word line voltage vector from the memory device and classify each bit of the vector into an LLR value.

[0108] The Maximum Likelihood Estimation (MLE) algorithm can be used to estimate parameters in a statistical model of a memory device, where the statistical model may rely on unobserved latent variables. Given a set of data samples, x, model, It can estimate the values ​​of samples of some unobserved data or missing values. The MLE algorithm uses one or more parameters It can be optimized.

[0109] In some embodiments, the EM algorithm attempts to find the MLE of the marginal likelihood by iteratively applying two steps until convergence. First, the expectation step is It can be represented by. Second, the maximization step is A parameter that maximizes the amount given by You can find it. In some examples, this does not guarantee that it provides the total maximum value.

[0110] In some cases, the EM algorithm can utilize a Gaussian mixture by sampling from a set of normal distributions. The number of cells per level can be known in advance. In some cases, shaping may be supported. Cell counting can provide a course estimate for the level means used for initialization. A well-initialized session can result in fewer iterations.

[0111] In some cases, the noisy cancellation level (noisy cancellation level) may not be considered Gaussian, which can lead to suboptimal Gaussian estimation. Therefore, the noisy cancellation level can be estimated using the Johnson-SU distribution. To continue the EM, the estimation can be removed from the histogram.

[0112] In some cases, the output from the EM process can be used to improve a subsequent interference removal process (e.g., as described below with reference to Fig. 9). As an example, a machine learning process for interference removal on NAND memory cells can have a coupling effect with EM to further improve readout reliability.

[0113] Noise removal

[0114] FIG. 9 is a diagram illustrating the structure of a neural network for noise removal according to embodiments of the present disclosure. When storing multiple bits in a single memory cell, errors may occur in the stored data due to program noise. For example, in a VNAND memory device, when a word line is programmed, the programming may cause noise to occur in adjacent word lines, which may later cause errors when these word lines are read out. Particularly strong noise may be generated by memory cells located geometrically above each other (e.g., memory cells located in the same pillar or column).

[0115] According to specific embodiments, the noise removal component can extract voltage levels from each memory cell connected to a string select line (SSL), provide the voltage levels of the memory cells as inputs to a neural network, and perform noise removal on the string select line (SSL) by changing the voltage levels of the memory cells from a first voltage level to a second voltage level.

[0116] Noise removal can be performed based on deep learning using a database. Deep learning is a sub-concept of machine learning and is a type of neural network model of machine learning related to artificial intelligence. Various neural network architectures can be used in deep learning. For example, various neural network architectures can be used in deep learning, such as Artificial Neural Networks (ANN), Deep Neural Networks (DNN), Convolutional Neural Networks (CNN), Regressive Neural Networks (RNN), and Generative Adversarial Networks (GAN). However, network architectures that can be used in deep learning are not limited to these.

[0117] In exemplary embodiments, noise removal can be performed using a ResNet having multiple identical consecutive residual blocks. An example of such a ResNet is illustrated in FIG. 9. This configuration allows for an iterative noise removal process to be performed in which only the noise is learned (e.g., only the difference between clean data and noisy data is learned). As an example, the ResNet can learn to continuously remove noise from the data while learning only the noise delta of each iteration.

[0118] The input to the ResNet may be a single noise SSL, for example, one of SSL1, SSL2, SSL3, and SSL4, and the output may be a noise-removed string select line SSL. Since the exemplary embodiments use a single SSL whenever noise removal is performed, only the loss in the voltages (distance between the noiseed cell voltage and the clean cell voltage) can be measured in the exemplary embodiments. However, since the raw bit error rate is a non-monotonic measurement related to voltage distance, measuring only the loss in the voltages can reduce or minimize the raw BER.

[0119] In FIG. 9, the number of each input layer (901-907, 909-915, 917) represents the number of neurons in that layer. The notation "x1" in the input layer (901) and output layer (917) indicates the shape of these layers. For example, each of the input layer (901) and output layer (917) includes 25 neurons formed as a vector of 25. The width of the input layer is equal to the number of word lines (WL) connected to a single string selection line SSL (e.g., the number of word lines (WL) in a memory block divided by 4) (e.g., 25 in a 6 BPC design as shown in FIG. 6). The input layer (901) can correspond to noise SSL supplied to the neural network for noise removal.

[0120] In a neural network, each layer is of the fully connected type. That is, each neuron in each layer is connected to each neuron in the next layer. The connections between these neurons include corresponding weights, which can be learned during training. Once each layer is populated with some input from the previous layer, the layer can perform a non-linear operation (for example, the Rectifying Linear Unit (ReLU) function) on the input after multiplying it by some weights, before passing the results as input to the next layer.

[0121] The arrows between the layers indicate the type of activation function used for the neurons in that layer. In an exemplary embodiment, the Rectified Linear Unit (ReLU) function, which is a non-linear function, is used as the activation function between the layers (902 and 903, 903 and 904, 904 and 905, 905 and 906, 906 and 907, 909 and 910, 910 and 911, 911 and 912, 912 and 913, 913 and 914, 914 and 915). The ReLU activation function can determine whether to activate the neuron by calculating the weighted sum of the neuron inputs and adding a bias, thereby introducing non-linearity to the neuron's output. A linear function can be used as an activation function between the input layer (901) and operation (908), layer (907) and operation (908), operation (908) and layer (909), layer (909) and operation (916), layer (915) and operation (916), and operation (916) and output layer (917). That is, between these layers and operations, a non-linear activation function may not be performed.

[0122] Operation (908) can sum the output of layer (907) with the input layer (901) and supply this output to layer (909). Operation (916) can sum the output of layer (915) with layer (909) and supply this output to the output layer (917). The output layer (917) can output a noise-removed SSL.

[0123] The noise-removed SSL output by the output layer (917) can be used when data is output from a memory device (e.g., when read from a memory device). For example, referring to FIG. 6, it is assumed that data stored in a memory cell connected to SSL3 (e.g., one of the memory cells of word lines WL3, WL7, ..., WL99) is being read from a memory device. The data may be read from a memory device, for example, when accessed by a user or when passed to a subsequent stage of data processing. When the data is read from a memory device, the operations described in relation to the embodiment of FIG. 7 above may be performed to remove noise from the data (e.g., to correct the data) before the data is read from the memory device.

[0124] For example, when data is read from one of the memory cells of word lines WL3, WL7, ..., WL99, SSL3 can first remove noise by a neural network by changing the voltage level of at least one memory cell of the word lines WL3, WL7, ..., WL99. Here, the first voltage level can be classified as belonging to the first cluster (64 clusters in a 6 BPC design), and the second voltage level can be classified as belonging to the second cluster (64 clusters in a 6 BPC design).

[0125] It should be noted that since writing to memory cells can reintroduce noise for the same reasons described above, the voltage levels of such memory cells are effectively not altered within the current memory device. On the other hand, instead of the actual voltage levels of these memory cells within the memory device being output, the altered (corrected) voltage levels of these memory cells output by the neural network can be output by the memory device when the data from these memory cells is read from the memory device. That is, while a cleaner, noise-removed version of the data generated by the neural network is output by the memory device, the noisy version of the data actually stored in the memory device can remain intact within the memory device. Therefore, this process can be performed again whenever data is read from the memory device.

[0126] Level skip operations may be performed when reading data from a memory device, and voltage levels degraded by noise removal may not be changed when data is read (for example, voltage levels that were not actually changed in the memory device may be read from these memory cells). A cleaner, noise-removed version of the data (data that was not intentionally changed due to the level skip operation) may be converted into a digital form before being read from the memory device.

[0127] Since BER can be determined by the Grey Code mapping of levels for bits, reducing voltage error in some cases can potentially increase the number of wrong bits per cell. Therefore, exemplary embodiments can approximate the BER loss to a range where the BER loss is still monotone or otherwise has a constant loss.

[0128] Neural network decoder

[0129] FIG. 10 illustrates an example of a neural network decoder (1025) according to one embodiment of the present disclosure. The illustrated example may include information bits (1000), an ECC encoder (1005), a modulation (1010), a noise source (1015), a signal processing (1020), a neural network decoder (1025), an output processing (1045), and output information bits (1050).

[0130] Information bits (1000) can be encoded by an ECC encoder (1005) (e.g., using a polar coding design or an S-polar encoding design). In some cases, a modulation design such as binary phase-shift keying (BPSK) can be applied by modulation (1010) prior to transmitting or programming the data. When receiving (or reading) the data, the data may contain noise from a noise source (1015). A neural network decoder (1025) can be used to decode the data when noise from the noise source (1015) is present.

[0131] The ECC encoder (1005) and the neural network decoder (1025) may be examples of the corresponding elements described with reference to FIG. 6, or may include aspects thereof. The neural network decoder (1025) may include an input layer (1030), a hidden layer (1035), and an output layer (1040).

[0132] The neural network decoder (1025) can operate using weighted belief propagation (WBP) based on a message-passing algorithm. Belief propagation may be a calculated marginal distribution for unobserved variables based on observed variables. The neural network can learn the optimal weights for each message. The parameters of the neural network decoder (1025) can be updated based on a loss function, such as a loss function based on the cross-entropy of the decoded codeword and the original codeword.

[0133] According to one embodiment, a feed-forward artificial neural network (ANN) can be used as a neural network decoder (1025). An ANN is a hardware or software component comprising a number of connected nodes (e.g., artificial neurons) that correspond approximately to neurons in the human brain. Each connection or edge can transmit a signal from one node to another (e.g., physical synapses in the brain). When a node receives a signal, the node can process the signal and then transmit the processed signal to another connected node. In some cases, the signals between nodes may involve real numbers, and the output of each node may be calculated by a function of the sum of the inputs of each node. Each node and edge may be associated with one or more node weights that determine how the signal is processed and transmitted.

[0134] During the training process, these weights can be adjusted to improve the accuracy of the results (for example, by minimizing the loss function corresponding to the difference between the current result and the target result in some methods). Edge weights can increase or decrease the strength of signals transmitted between nodes. In some cases, nodes may have a threshold below which no signal is transmitted at all. Nodes may be aggregated into layers. Different layers may perform different transformations on their inputs. The initial layer is known as the input layer, and the final layer can be known as the output layer. In some cases, signals may pass through specific layers multiple times.

[0135] According to one embodiment, the loss function of the neural network may be the cross-entropy of the decoded codeword u and the original codeword o. Structured codes (e.g., polar codes) may be used to increase generalization properties.

[0136] Exemplary method

[0137] FIG. 11 illustrates an example of a process for programming data into a memory device according to embodiments of the present disclosure. In some embodiments, these operations may be performed by a system comprising a processor that executes a set of code to control functional elements of the device. Additionally or alternatively, the processes may be performed using special-purpose hardware. Generally, these operations may be performed according to the methods and processes described in accordance with embodiments of the present disclosure. For example, the operations may consist of various sub-steps or may be performed together with various other operations described herein.

[0138] In step 1100, the system receives a data block. In some cases, the operations of this step may be performed by or refer to a memory controller as described with reference to FIG. 6.

[0139] In operation 1105, the system encodes a data block based on an ECC coding design. In some cases, the operations of this step may be performed by an ECC encoder, which is described with reference to FIGS. 6 and 10.

[0140] In step 1110, the system encodes the data block based on a constrained coding scheme. In some cases, the operations of this step may be performed by or refer to the constrained channel encoder described with reference to FIG. 6.

[0141] In step 1115, the system programs the encoded data block into a memory device using RLPP. In some cases, the operations of this step may be performed by referring to or by the RLPP component described with reference to FIG. 6.

[0142] FIG. 12 illustrates an example of a process for reading data from a memory device according to embodiments of the present disclosure. In some embodiments, these operations may be performed by a system comprising a processor that executes a set of code to control functional elements of the device. Additionally or alternatively, the processes may be performed using special-purpose hardware. Generally, these operations may be performed according to the methods and processes described in accordance with embodiments of the present disclosure. For example, the operations may consist of various sub-steps or may be performed together with various other operations described herein.

[0143] In operation 1200, the system reads a data block from the memory device. In some cases, the operations of this step may be performed by or refer to the memory controller described with reference to FIG. 6.

[0144] In step 1205, the system processes the data block using EM signal processing and classifies each bit of the data block into an LLR value. In some cases, the operations of this step may be performed by referring to or by the EM signal processing component described with reference to FIG. 6.

[0145] In operation 1210, the system decodes data blocks based on a restricted coding design. In some cases, the operations of this step may be performed by or refer to the restricted channel decoder described with reference to FIG. 6.

[0146] In operation 1215, the system decodes the data block based on an ECC coding scheme. In some cases, the operations of this step may be performed by or refer to the ECC decoder described with reference to FIG. 6.

[0147] FIG. 13 illustrates an example of a process for performing interference removal according to embodiments of the present disclosure. In some embodiments, these operations may be performed by a system comprising a processor that executes a set of code to control functional elements of a device. Additionally or alternatively, the processes may be performed using special-purpose hardware. Generally, these operations may be performed according to the methods and processes described in accordance with embodiments of the present disclosure. For example, the operations may consist of various sub-steps or may be performed together with various other operations described herein.

[0148] In step 1300, the system reads a data block from the memory device. In some cases, the operations of this step may be performed by or refer to the memory controller described with reference to FIG. 6.

[0149] In step 1305, the system processes the data block using EM signal processing and classifies each bit of the data block into an LLR value. In some cases, the operations of this step may be performed by referring to or by the EM signal processing component described with reference to FIG. 6.

[0150] In operation 1310, the system decodes data blocks based on a restricted coding design. In some cases, the operations of this step may be performed by or refer to the restricted channel decoder described with reference to FIG. 6.

[0151] In step 1315, the system decodes the data block based on the ECC coding design. In some cases, the operations of this step may be performed by or refer to the ECC decoder described with reference to FIG. 6.

[0152] At step 1320, the system may determine that decoding based on the ECC coding design is insufficient. In some cases, the operations of this step may be performed by referring to or by the machine learning interference successive removal component described with reference to FIG. 6.

[0153] In step 1325, the system performs machine learning interference successive removal based on a judgment. In some cases, the operations of this step may be performed by referring to or by the machine learning interference successive removal component described with reference to FIG. 6.

[0154] FIG. 14 illustrates an example of a process for performing neural network decoding according to embodiments of the present disclosure. In some embodiments, these operations may be performed by a system comprising a processor that executes a set of code to control functional elements of a device. Additionally or alternatively, the process may be performed using special-purpose hardware. Generally, these operations may be performed according to the methods and processes described in accordance with embodiments of the present disclosure. For example, the operations may consist of various sub-steps or may be performed together with various other operations described herein.

[0155] In operation 1400, the system reads a data block from the memory device. In some cases, the operations of this step may be performed by or refer to the memory controller described with reference to FIG. 6.

[0156] In step 1405, the system processes the data block using EM signal processing to classify each bit of the data block into an LLR value. In some cases, the operations of this step may be performed by referring to or by the EM signal processing component described with reference to FIG. 6.

[0157] In step 1410, the system decodes the data block based on a restricted coding design. In some cases, the operations of this step may be performed by or refer to the restricted channel decoder described with reference to FIG. 6.

[0158] In step 1415, the system decodes the data block based on the ECC coding design. In some cases, the operations of this step may be performed by or refer to the ECC decoder described with reference to FIG. 6.

[0159] In step 1420, the system determines that decoding based on the ECC coding design is insufficient. In some cases, the operations of this step may be performed by or refer to the neural network decoder described with reference to FIGS. 6 and FIGS. 10.

[0160] In step 1425, the system decodes the data block using a neural network decoder. In some cases, the operations of this step may be performed by or refer to the neural network decoder described with reference to FIGS. 6 and FIGS. 10.

[0161] Accordingly, the present invention includes the following embodiments.

[0162] A mobile electronic device for storing data for a mobile device is described. Embodiments of the mobile electronic device may include a memory device, a processor and internal memory, a memory controller configured to operate the memory device, an error correction code (ECC) encoder configured to encode data for programming the memory device, a restriction channel encoder configured to encode the output of the ECC encoder based on one or more restrictions for programming the memory device, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data into the memory device, an expectation maximization (EM) signal processing component configured to receive a multi-word line voltage vector with noise from the memory device and classify each bit of the vector by a log likelihood ration (LLR) value, a restriction channel decoder configured to receive a restriction vector from the EM signal processing component and generate an unrestricted vector, and an ECC decoder configured to decode the unrestricted vector.

[0163] In some embodiments, the ECC encoder may be configured to encode data using an S-polar coding design, including an RS (Reed Solomon) coding design and a polar coding design. In some embodiments, the ECC encoder may include a reduced frame size and a reduced redundancy level configured for mobile architecture. In some embodiments, the restricted channel encoder may be configured to identify data from the next word line of the memory device before encoding the output of the ECC encoder for the current word line of the memory device.

[0164] In some embodiments, the RLPP component includes a word line agent, a level agent, and a block agent. In some embodiments, the EM signal processing component is configured to provide LLR values ​​to an ECC decoder. In some embodiments, the EM signal processing component is configured based on a reduced sample size for mobile architecture.

[0165] The embodiments of the mobile electronic device and method described above may further include a machine learning interference succession removal component configured to receive a word line vector having noise from an ECC decoder and provide a noise-removed word line vector to the ECC decoder.

[0166] Some embodiments of the mobile electronic device and method described above may further include a neural network decoder configured to receive a word line data vector and a word line voltage vector and to generate a recovered data vector. In some embodiments, the neural network decoder includes a reduced number of nodes, and the reduced number of nodes may be selected for a mobile architecture.

[0167] In some embodiments, each cell of the memory device includes a 5-bit or 6-bit NAND flash memory cell. In some embodiments, the memory controller may include a simplified memory controller architecture configured for reduced power consumption.

[0168] A method for storing data for a mobile device is described. Embodiments of the method may include receiving a data block, encoding the data block based on an ECC coding design, encoding the data block based on a restriction coding design, and programming the encoded data block into a memory device using RLPP.

[0169] In some embodiments, the ECC coding design includes an S-polar coding design including an RS coding design and a polar coding design. Some embodiments of the method described above may further include the step of identifying data from the next word line of a memory device, and the restriction coding design may be based on the data from the next word line.

[0170] A method for storing data for a mobile device is described. Embodiments of the method may include the steps of reading a data block from a memory device, processing the data block using EM signal processing to classify each bit of the data block into LLR values, decoding the data block based on a restricted coding design, and decoding the data block based on an ECC coding design.

[0171] In some embodiments, the ECC coding design includes an S-polar coding design that includes an RS coding scheme and a polar coding scheme. In some embodiments, the operation of decoding a data block based on the ECC coding design may be performed based on at least some of the LLR values.

[0172] Some embodiments of the method described above may further include a step of determining that decoding based on an ECC coding design is insufficient. Some embodiments may further include a step of performing machine learning interference continuation removal based on the determination. Some embodiments of the method described above may further include a step of determining that decoding based on an ECC coding design is insufficient. Some embodiments may further include a step of decoding a data block using a neural network decoder.

[0173] The descriptions and drawings provided herein represent exemplary configurations and do not represent all implementations within the scope of the claims. For example, operations and steps may be rearranged, combined, or otherwise modified. Additionally, structures and devices may be represented in the form of block diagrams to indicate relationships between components and to avoid obscuring the described concepts. Similar components or features may have the same name but may have different reference numbers corresponding to different drawings.

[0174] Some modifications to the present disclosure may be readily apparent to those skilled in the art, and the principles defined herein may be applied to various other variations without departing from the scope of the present disclosure. Accordingly, the present disclosure is not limited to the examples and designs described herein, but may be applied to the broadest extent consistent with the principles and novel features disclosed herein.

[0175] The methods described above may be implemented or performed by devices comprising a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, a conventional processor, a controller, a microcontroller, or a state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors associated with a DSP core, or any other configuration). Accordingly, the functions described herein may be implemented in hardware or software and may be executed by a processor, firmware, or any combination thereof. When implemented as software executed by a processor, the functions may be stored in the form of instructions or code on a computer-readable medium.

[0176] Computer-readable media may include both non-transient computer storage media and communication media that facilitate the transmission of code or data. Non-transient storage media may be any available media that can be accessed by a computer. For example, non-transient computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc (CD) or other optical disc storage devices, magnetic disc storage devices, or any other non-transient media for transmitting or storing data or code.

[0177] Additionally, connection components may be appropriately referred to as computer-readable media. For example, when transmitting code or data from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, or microwave signals, coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology may be included in the definition of media. A combination of media may also be included within the scope of computer-readable media.

[0178] In the present disclosure and the claims below, the word “or” may denote a comprehensive list, for example, a list of X, Y, or Z, meaning X or Y or Z or XY or XZ or YZ or XYZ. Additionally, the phrase “based on” is not used to denote a closed set of conditions, and, as an example, a step described as “based on condition A” may be based on both condition A and condition B. In other words, the expression “based on” may be interpreted to mean “based on at least some.” Additionally, terms indicated in the singular may be used to denote “at least one.”

Claims

Claim 1 A mobile electronic device comprises: a memory device; and a memory controller configured to operate the memory device, the memory controller comprising a processor and internal memory, wherein the memory controller comprises: an ECC (error correction code) encoder configured to encode data for programming the memory device; a restriction channel encoder configured to generate a restriction vector by encoding the output of the ECC encoder based on one or more restrictions for programming the memory device; a reinforcement learning pulse programming (RLPP) component configured to output programming parameters for programming data from the restriction channel encoder into the memory device; and a restriction channel decoder configured to receive and decode the restriction vector read from the memory device to generate an unrestricted vector. A mobile electronic device comprising an ECC decoder configured to generate decoded data by decoding the non-restricted vector from the restricted channel decoder, wherein the RLPP component comprises: a block agent that outputs a block policy including a target wordline to be programmed; a wordline agent that receives the restricted vector and the block policy and outputs a wordline policy including a target level to be programmed; and a level agent that receives the wordline policy and outputs a level policy including the programming parameters. Claim 2 A mobile electronic device according to claim 1, characterized in that the ECC encoder encodes the data using an S-polar coding design including a Reed Solomon coding design and a polar coding design. Claim 3 A mobile electronic device according to claim 2, wherein the ECC encoder comprises a reduced frame size and a reduced redundancy level configured for a mobile architecture in relation to a block size data matrix input. Claim 4 A mobile electronic device according to claim 1, wherein the limit channel encoder identifies data from the next word line of the memory device before encoding the output of the ECC encoder for the current word line of the memory device. Claim 5 delete Claim 6 A mobile electronic device according to claim 1, further comprising an expectation maximization (EM) signal processing component that receives a multi-word line voltage vector having noise from the memory device and classifies each bit of the multi-word line voltage vector having noise into an LLR (log Likelihood Ratio) value. Claim 7 delete Claim 8 A mobile electronic device according to claim 1, further comprising a machine learning interference successive removal component that receives a word line voltage vector having noise from the ECC decoder and provides a word line voltage vector with noise removed to the ECC decoder. Claim 9 A mobile electronic device according to claim 8, characterized in that the machine learning interference successive removal component operates based on input from an EM signal processing component. Claim 10 delete Claim 11 delete Claim 12 A mobile electronic device according to claim 1, characterized in that each cell of the memory device comprises a 5-bit or 6-bit NAND flash memory cell. Claim 13 A method for programming data in a memory device, comprising: receiving a data block; encoding the data block based on an ECC coding design by an error correction code (ECC) encoder; generating a restriction vector by encoding the output of the ECC encoder according to a restriction coding design based on one or more restrictions for programming in the memory device by a restriction channel encoder; and programming data from the restriction channel encoder into the memory device using a reinforcement learning pulse programming (RLPP) component configured to output programming parameters for programming in the memory device, wherein the RLPP component comprises: a block agent that outputs a block policy including a target word line to be programmed; a word line agent that receives the restriction vector and the block policy and outputs a word line policy including a target level to be programmed; and a level agent that receives the word line policy and outputs a level policy including the programming parameters. Claim 14 A method according to claim 13, characterized in that the ECC coding design includes an S-polar coding design including a Reed-Solomon (RS) coding design and a polar coding design. Claim 15 A method according to claim 13, further comprising the step of identifying data from the next word line of the memory device, wherein the restriction coding design is based on the data identified from the next word line. Claim 16 A method for reading data from a memory device, comprising: a step of reading a data block from the memory device; a step of processing the data block using expectation maximization (EM) signal processing to classify each bit of the data block into an LLR (log Likelihood ratio) value and outputting the LLR value; a step of receiving a restricted vector corresponding to the data block read from the memory device and decoding the data block based on the restricted coding design to output an unrestricted vector; a step of decoding the unrestricted vector by an ECC decoder based on an ECC (error correction code) coding design to output a decoded data block; and a step of receiving a word line voltage vector having noise from the ECC decoder and providing a word line voltage vector with noise removed to the ECC decoder to perform machine learning interference succession removal. Claim 17 A method according to claim 16, characterized in that the ECC coding design includes an S-polar coding design including a Reed-Solomon (RS) coding design and a polar coding design. Claim 18 A method according to claim 16, characterized in that the decoding of the data block based on the ECC coding design is performed at least partially based on the LLR value. Claim 19 delete Claim 20 delete

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