Buffer circuit having offset blocking circuit and display device including the same

Abstract

A buffer circuit according to one aspect of the technical concept of the present disclosure comprises: an operational amplifier that amplifies an input voltage to generate an output voltage; a slew rate compensation circuit that generates a compensation current based on the difference between the voltage level of the input voltage and the voltage level of the output voltage and provides the compensation current to the operational amplifier through a boosting transistor; and an offset blocking circuit that provides a blocking current to the slew rate compensation circuit, thereby turning off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is smaller than a reference voltage level.

Description

Technology Field

[0001] Buffer circuit having offset blocking circuit and display device including the same Background Technology

[0002] Display devices used in electronic devices that display images, such as TVs, laptop computers, monitors, and mobile devices, include Liquid Crystal Devices (LCDs) and Organic Light Emitting Devices (OLEDs). In particular, Liquid Crystal Devices are widely used as information processing devices because they are thinner, lighter, and have improved quality compared to Cathode Ray Tubes.

[0003] A display device may include a display panel having multiple pixels and a display driver for applying electrical signals to multiple pixels, and an image may be realized by the electrical signals provided by the display driver to the multiple pixels. Recently, various studies have been conducted to improve the performance of the display device, such as resolution and slew rate. The problem to be solved

[0004] The problem that the technical concept of the present disclosure aims to solve is to provide a buffer circuit that eliminates DC offset and improves the slew rate by including a slew rate compensation circuit and an offset blocking circuit.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] To achieve the above objectives, a buffer circuit according to one aspect of the present disclosure comprises an operational amplifier that amplifies an input voltage to generate an output voltage, a slew rate compensation circuit that generates a compensation current based on the difference between the voltage level of the input voltage and the voltage level of the output voltage and provides the compensation current to the operational amplifier through a boosting transistor, and an offset blocking circuit that provides a blocking current to the slew rate compensation circuit to turn off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is smaller than a reference voltage level.

[0007] To achieve the above objectives, a display device according to one aspect of the present disclosure comprises: a display panel including a plurality of pixels formed at the intersection points of gate lines arranged in a row direction and source lines arranged in a column direction; a controller that generates a source control signal based on control signals received from the outside and converts image data received from the outside; and a source driver that converts image data converted by the controller into an image signal in response to the source control signal received from the controller and provides the image signal to the source lines. The source driver comprises an operational amplifier that amplifies an input voltage to generate an output voltage; a slew rate compensation circuit that generates a compensation current based on the difference between the voltage level of the input voltage and the voltage level of the output voltage and provides the compensation current to the operational amplifier through a boosting transistor; and an offset blocking circuit that provides a blocking current to the slew rate compensation circuit, thereby turning off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is smaller than a reference voltage level.

[0008] To achieve the above objectives, a buffer circuit control method according to one aspect of the present disclosure comprises: comparing the difference between the input voltage level and the output voltage level of an operational amplifier in a slew rate compensation circuit with a reference voltage level; when the difference between the input voltage level and the output voltage level is greater than the reference voltage level, generating a compensation current based on the difference between the input voltage level and the output voltage level in the slew rate compensation circuit and providing the compensation current to the operational amplifier; and when the difference between the input voltage level and the output voltage level is smaller than the reference voltage level, turning off the boosting transistor of the slew rate compensation circuit by the blocking current provided by the offset blocking circuit to the slew rate compensation circuit. Effects of the invention

[0009] According to the technical concept of the present disclosure, by including a slew rate compensation circuit and an offset blocking circuit, a buffer circuit can be provided that eliminates the DC offset and improves the slew rate.

[0010] According to the technical concept of the present disclosure, by generating a compensation current based on the difference between the input voltage level and the output voltage level, a buffer circuit with increased operating speed and reduced power consumption can be provided.

[0011] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the description below. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure. FIG. 2 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure. FIG. 3 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. FIG. 4 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 5 is a circuit diagram of an offset blocking circuit according to exemplary embodiments of the present disclosure. FIG. 6 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. FIG. 7 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. FIG. 8 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 9 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 10 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 11 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 12 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 13 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. FIG. 14 is a circuit diagram of an offset blocking circuit according to exemplary embodiments of the present disclosure. FIG. 15 is a diagram illustrating voltages measured at nodes of a buffer circuit according to exemplary embodiments of the present disclosure. FIG. 16 is a block diagram of a source driver including a buffer circuit according to exemplary embodiments of the present disclosure. FIG. 17 is a block diagram of a display device according to exemplary embodiments of the present disclosure. FIG. 18 is a flowchart illustrating a method of operation of a buffer circuit according to exemplary embodiments of the present disclosure. Specific details for implementing the invention

[0013] Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings. In the drawings of this specification, only parts may be shown for the convenience of illustration. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof are omitted.

[0014] FIG. 1 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure.

[0015] Referring to FIG. 1, the buffer circuit (BF) may include an operational amplifier (10), a slew rate compensation circuit (20), and an offset blocking circuit (30).

[0016] The operational amplifier (10) can amplify the voltage level of the input voltage (VIN) to generate an output voltage (VOUT). The output voltage (VOUT) of the operational amplifier (10) can be input to the inverting input terminal of the operational amplifier (10) through a feedback loop. That is, the operational amplifier (10) can have a negative feedback structure in which the inverting input terminal and the output terminal are connected to each other. The operational amplifier (10) can have a rail-to-rail structure in which the input terminal has a dual structure.

[0017] The slew rate compensation circuit (20) compensates for the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) with a compensation current (I PUSH , I PULL ) can be generated. The slew rate compensation circuit (20) generates a compensation current (I) when the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) is greater than the reference voltage level. PUSH , I PULL) can be generated. The reference voltage level may include the voltage level of the threshold voltage of an N-channel Field Effect Transistor (NFET) or the voltage level of the threshold voltage of a P-channel Field Effect Transistor (PFET) constituting the slew rate compensation circuit (20). The slew rate compensation circuit (20) has a compensation current (I PUSH , I PULL ) can be provided to the operational amplifier (10).

[0018] The offset blocking circuit (30) is provided by the turn-on voltage (V) from the operational amplifier (10). ON Blocking current (I) based on ) BLK It can generate ) and blocking current (I BLK ) can be provided to the slew rate compensation circuit (20). The offset blocking circuit (30) can share a specific node with the operational amplifier (10). The offset blocking circuit (30) provides a turn-on voltage (V) through the specific node. ON Can receive ). Turn-on voltage (V ON The voltage level of the specific node may be equal to or higher than the threshold voltage level of the transistors constituting the offset blocking circuit (30). The specific node may be described below as a 'push-connected node' or a 'pull-connected node,' but is not limited thereto, and may be any node among the multiple nodes of the operational amplifier (10) that can provide a voltage equal to or higher than the threshold voltage level of the transistors constituting the offset blocking circuit (30).

[0019] The buffer circuit (BF) according to the present disclosure is a blocking current (I BLKBy including an offset blocking circuit (30) that provides ) to the slew rate compensation circuit (20), the DC offset can be removed and the slew rate improved. Below, with reference to FIG. 2, the components of the operational amplifier (10) and the relationship between the slew rate compensation circuit (20) and the offset blocking circuit (30) will be explained in detail.

[0020] FIG. 2 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure. Specifically, FIG. 2 is a drawing for explaining the operational amplifier (10) of FIG. 1 in detail.

[0021] Referring to FIG. 2, the operational amplifier (10) may include an input stage (11), an upper bias circuit (12), a lower bias circuit (13), a load stage (14), and an output stage (15).

[0022] The input terminal (11) can receive an input voltage (VIN) and an output voltage (VOUT). The output voltage (VOUT) can be input to the input terminal (11) through a feedback loop. The input terminal (11) can compare the voltage level of the input voltage (VIN) with the voltage level of the output voltage (VOUT). The input terminal (11) may include a first input terminal (IS1) and a second input terminal (IS2). The first input terminal (IS1) receives a pulling load current (I) from the load terminal (14). PLLI , I PLLO ) can receive, and the second input terminal (IS2) receives a pushing load current (I) from the load terminal (14). PSLI , I PSLO Can receive ).

[0023] The upper bias circuit (12) and the lower bias circuit (13) can provide the bias current required to drive the operational amplifier (10). The upper bias circuit (12) and the lower bias circuit (13) provide the bias current (I) to the input terminal (11). BU , I BL It can provide ).

[0024] The load terminal (14) is a compensation current (I) provided from the slew rate compensation circuit (20). PUSH , I PULL ) can be received. The load terminal (14) is a compensation current (I PUSH , I PULL The slew rate compensation operation can be performed using ). The load terminal (14) can perform load currents (I) based on the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT). PSLI , I PSLO , I PLLI , I PLLO ) can be generated. The load terminal (14) can generate a compensation current (I PUSH , I PULL Using ) load currents (I PSLI , I PSLO , I PLLI , I PLLO ) can be generated. The load terminal (14) can generate load currents (I PSLI , I PSLO , I PLLI , I PLLO ) can be provided to the input terminal (11).

[0025] The load terminal (14) turns on the offset blocking circuit (30) with a turn-on voltage (V ON...can be provided. The load terminal (14) may share a specific node with the offset blocking circuit (30) and the output terminal (15). The specific node may be described as a 'push-connected node' and a 'pull-connected node' with reference to FIG. 5, which will be described later. However, it is not limited thereto, and the load terminal (14) and the offset blocking circuit (30) may share a node among a plurality of nodes of the load terminal (14) that can provide a voltage level equal to or higher than the threshold voltage level of the transistors included in the offset blocking circuit (30).

[0026] The output terminal (15) can be connected to the load terminal (14). The output terminal (15) can be connected to the load terminal (14) through at least one of a 'push connection node' and a 'pull connection node'. That is, the load terminal (14), the output terminal (15), and the offset blocking circuit (30) can share at least one of a 'push connection node' and a 'pull connection node'. The output terminal (15) can generate an output voltage by buffering the output signal of the load terminal (14). The output terminal (15) can output the output voltage to the outside of the buffer circuit (BF).

[0027] Below, the operation of the buffer circuit (BF) is explained in detail with reference to the circuit diagram of the buffer circuit (BF).

[0028] FIGS. 3 to 5 are circuit diagrams of a buffer circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 3 is a circuit diagram of the operational amplifier (10) of FIG. 1 and FIG. 2, FIG. 4 is a circuit diagram of the slew rate compensation circuit (20) of FIG. 1 and FIG. 2, and FIG. 5 is a circuit diagram of the offset blocking circuit (30) of FIG. 1 and FIG. 2. The following description will be explained with reference to the aforementioned drawings.

[0029] Referring to Fig. 3, The operational amplifier (10) may include an input terminal (11), an upper bias circuit (12), a lower bias circuit (13), a load terminal (14), and an output terminal (15).

[0030] The input terminal (11) may have a rail-to-rail structure having a dual structure. The input terminal (11) may include a first input terminal (IS1) connected to transistors (P1, P2) and a second input terminal (IS2) connected to transistors (N1, N2). The first input terminal (IS1) receives a full load current (I) from the load terminal (14). PLLI , I PLLO ) can receive, and the second input terminal (IS2) receives a push load current (I) from the load terminal (14). PSLI , I PSLO ) can be received. In the following, including FIG. 3, the push load current (I PSLI , I PSLO Since ) flows from the input terminal (11) to the load terminal (14), the push load current (I PSLI , I PSLO Push load current (I) according to the flow of ) PSLI , I PSLO The indication of ) is shown in the direction of the load end (14).

[0031] The upper bias circuit (12) applies a first bias current (I) to the transistors (P1, P2) based on the first bias voltage (VB1). BU ) can be provided. The upper bias circuit (12) may include a transistor (P3) that provides a power supply voltage (VDD) to the input terminal (11) by being gated to a first bias voltage (VB1). Specifically, the drain terminal of the transistor (P3) may be connected to the source terminal of the transistors (P1, P2) of the input terminal (11).

[0032] The lower bias circuit (13) applies a second bias current (I) to the transistors (N1, N2) based on the second bias voltage (VB2). BL) can be provided. The lower bias circuit (13) may include a transistor (N3) that connects the ground voltage and the input terminal (11) by being gated to the second bias voltage (VB2). Specifically, the drain terminal of the transistor (N3) may be connected to the source terminal of the transistors (N1, N2) of the input terminal (11).

[0033] The load section (14) may include a push load circuit (PS), a pull load circuit (PL), a connection circuit (CC), a first capacitor (C1), and a second capacitor (C2).

[0034] The push load circuit (PS) may include transistors (P4, P5) connected in the form of a current mirror and transistors (P6, P7) connected between the transistors (P4, P5) and the connection circuit (CC) and operating in response to a third bias voltage (VB3).

[0035] The push load circuit (PS) receives the push compensation current (I) from the slew rate compensation circuit (20) through the first upper node (NU1). PUSH It can receive ). The push load circuit (PS) receives the push compensation current (I PUSH Based on ), push load current (I PSLI , I PSLO ) can generate. The push load circuit (PS) generates a push load current (I) through the drain terminal of transistor (P5) and the source terminal of transistor (P6), respectively. PSLI , I PSLO ) can be provided to the second input terminal (IS2).

[0036] The full load circuit (PL) may include transistors (N4, PN) connected in a current mirror form and transistors (N4, N5) connected between the connection circuit (CC) and transistors (N6, N7) that operate in response to a fourth bias voltage (VB4).

[0037] The full load circuit (PL) has a full compensation current (I) through the first lower node (NL1).PULL It can receive ). The full load circuit (PL) can receive the full compensation current (I PULL Based on ), full load current (I PLLI , I PLLO Can generate ). Full load current (I PLLI , I PLLO ) can flow from the first input terminal (IS1) to the drain terminal of the transistor (N5) and the source terminal of the transistor (N6).

[0038] A connection circuit (CC) may be placed between a push load circuit (PS) and a pull load circuit (PL). The connection circuit (CC) may electrically connect a second upper node (NU2) of the push load circuit (PS) and a second lower node (NL2) of the pull load circuit (PL), and may electrically connect a third upper node (NU3) of the push load circuit (PS) and a third lower node (NL3) of the pull load circuit (PL). The third upper node (NU3) of the push load circuit (PS) may be referred to as a 'push connection node', and the third lower node (NL3) of the pull load circuit (PL) may be referred to as a 'pull connection node'.

[0039] The connection circuit (CC) may include transistors (P8, P9, N8, N9), and the transistors (P8, P9, N8, N9) may each operate in response to fifth to eighth bias voltages (VB5 to VB8). The fifth to eighth bias voltages (VB5 to VB8) may be the same or different from each other. For example, the fifth to eighth bias voltages (VB5 to VB8) may all have different voltage levels. In another embodiment, at least two of the fifth to eighth bias voltages (VB5 to VB8) may have the same voltage level.

[0040] The first capacitor (C1) can be connected between the first upper node (NU1) and the output node (NOUT) of the push load circuit (PS), and the second capacitor (C2) can be connected between the first lower node (NL1) and the output node (NOUT) of the pull load circuit (PL).

[0041] The output terminal (15) may include transistors (P10, N10). The gate of transistor (P10) may be connected to the third upper node (NU3) of the push load circuit (PS). One end of transistor (P10) may be connected to the output node (NOUT) and a power supply voltage (VDD) may be applied from the other end. The gate of transistor (N10) may be connected to the third lower node (NL3) of the pull load circuit (PL). One end of transistor (N10) may be connected to the output node (NOUT) and a ground voltage may be applied from the other end.

[0042] In one embodiment according to the present disclosure, the transistors (P1 to P10) may include PFETs and the transistors (N1 to N10) may include NFETs, but the present invention is not limited thereto.

[0043] Referring to FIG. 4, the slew rate compensation circuit (20) may include a comparison circuit (21), a pull compensation current circuit (22), and a push compensation current circuit (23).

[0044] The comparison circuit (21) can receive an input voltage (VIN) and an output voltage (VOUT). The comparison circuit (21) may include transistors (N11, P11) to which the input voltage (VIN) is applied to the gate. The source terminal of transistor (N11) and the drain terminal of transistor (P11) may have the output voltage (VOUT) applied to them. The comparison circuit (21) can compare the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT), and depending on the comparison result, a comparison current (I DIFR , I DIFF It can generate ). That is, comparison current (IDIFR , I DIFF ) may be a current corresponding to the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT).

[0045] When the difference between the voltage level of the input voltage (VIN) of the operational amplifier (10) and the voltage level of the output voltage (VOUT) is greater than the reference voltage level, and the magnitude of the input voltage (VIN) is greater than the magnitude of the output voltage (VOUT), it can be said that the input voltage (VIN) is rising. For example, when the input voltage (VIN) rises, the input voltage (VIN) can transition from a logical low level to a logical high level. The reference voltage level may be the threshold voltage level of the transistors (N11, P11).

[0046] When the input voltage (VIN) rises, the comparison circuit (21) can turn on the transistor (N11) and turn off the transistor (P11). That is, it can activate the full compensation current circuit (22) and deactivate the push compensation current circuit (23). As the transistor (N11) is turned on, the comparison circuit (21) [reduces] the rising comparison current (I DIFR Can generate ).

[0047] In addition, when the difference between the voltage level of the input voltage (VIN) of the operational amplifier (10) and the voltage level of the output voltage (VOUT) is greater than the reference voltage level and the magnitude of the input voltage (VIN) is smaller than the magnitude of the output voltage (VOUT), it can be said that the input voltage (VIN) is falling. For example, when the input voltage (VIN) is falling, the input voltage (VIN) can transition from a logic high level to a logic low level.

[0048] When the input voltage (VIN) is polling, the comparison circuit (21) can turn on the transistor (P11) and turn off the transistor (N11). That is, the full compensation current circuit (22) can be disabled and the push compensation current circuit (23) can be enabled. As the transistor (P11) is turned on, the comparison circuit (21) polls the comparison current (I DIFF Can generate ).

[0049] The full compensation current circuit (22) is a rising comparison current (I DIFR A current mirror operation can be performed based on ). Accordingly, the full compensation current circuit (22) can perform a full compensation current (I PULL It can generate ) and full compensation current (I) to the operational amplifier (10). PULL It can provide ).

[0050] In detail, the full compensation current circuit (22) may include transistors (P12, P13, N12, N13). The transistors (P12, P13) may be connected in a current mirror configuration, and a power supply voltage (VDD) may be applied from one end. The transistors (N12, N13) may be connected in a current mirror configuration, and a ground voltage (VSS) may be applied from one end.

[0051] The drain node of transistor (P13), the drain node of transistor (N12), and the gates of transistors (N12, N13) can be connected. The node where the drain node of transistor (P13), the drain node of transistor (N12), and the gates of transistors (N12, N13) are connected is a pooling node (N PULL It can be referred to as ). The transistor (N13) can be referred to as a 'boosting transistor'.

[0052] The full compensation current circuit (22) provides a full compensation current (I) through the boosting transistor (N13). PULL ) can be output. Below, as shown in FIG. 4, the full compensation current (I) according to the flow of current PULL) is illustrated to flow from the first lower node (NL1) to the transistor (N13), but due to the operation of the full compensation current circuit (22), the uncompensated current (I PULL Since ) is generated, the full compensation current circuit (22) generates the full compensation current (I PULL It can be described as outputting ). That is, the full compensation current (I) from the full compensation current circuit (22). PULL ) can be supplied to the first lower node (NL1). Full compensation current (I PULL Since ) flows from the first lower node (NL1) to the boosting transistor (N13), the full compensation current circuit (22) receives the full compensation current (I) from the load terminal (14). PULL Can sync )

[0053] The voltage level of the first lower node (NL1) is the full compensation current (I PULL It can be further lowered by ). Therefore, the full compensation current (I PULL The transistor (N10) at the output terminal (15 in FIG. 3) can be quickly turned off by means of ). That is, the voltage level of the output voltage (VOUT) rises quickly, so the slew rate can be improved.

[0054] The push compensation current circuit (23) is a polling comparison current (I DIFF A current mirror operation can be performed based on ). Accordingly, the push compensation current circuit (23) can perform a push compensation current (I PUSH It can generate ) and push compensation current (I) to the operational amplifier (10). PUSH It can provide ).

[0055] In detail, the push compensation current circuit (23) may include transistors (N14, N15, P14, P15). The transistors (N14, N15) may be connected in a current mirror configuration, and a ground voltage (VSS) may be applied from one end. The transistors (P14, P15) may be connected in a current mirror configuration, and a power supply voltage (VDD) may be applied from one end.

[0056] The drain node of transistor (N15), the drain node of transistor (P14), and the gates of transistors (P14, P15) can be connected. The node to which the drain node of transistor (N15), the drain node of transistor (P14), and the gates of transistors (P14, P15) are connected is a push node (N PUSH It can be referred to as ). The transistor (P15) can be referred to as a 'boosting transistor'.

[0057] The push compensation current circuit (23) provides a push compensation current (I) through the boosting transistor (P15). PUSH ) can be output. That is, push compensation current (I) from push compensation current circuit (23) PUSH ) can be supplied to the first upper node (NU1). Push compensation current (I PUSH Since ) flows from the boosting transistor (P15) to the first upper node (NU1), the push compensation current circuit (23) pushes the compensation current (I) to the load terminal (14). PUSH Can supply ).

[0058] The voltage level of the first upper node (NU1) is the push compensation current (I PUSH It can be further increased by ). Therefore, the push compensation current (I PUSH The transistor (P10) of the output terminal (15) can be quickly turned off by ). That is, the voltage level of the output voltage (VOUT) drops quickly, so the slew rate can be improved.

[0059] In one embodiment according to the present disclosure, the transistors (P11 to P15) may include PFETs and the transistors (N11 to N15) may include NFETs, but the present invention is not limited thereto.

[0060] Referring to Fig. 5, The offset blocking circuit (30) may include a push blocking transistor (P16) and a pull blocking transistor (N16).

[0061] The gate of the push-blocking transistor (P16) can be connected to the third upper node (NU3) of the push-load circuit (PS). In other words, the gate of the push-blocking transistor (P16) can be connected to the push-connect node. Accordingly, the push-blocking transistor (P16) can be operated by the voltage provided by the operational amplifier (10). More specifically, the push-blocking transistor (P16) can be operated by the voltage provided by the load terminal (14) of the operational amplifier (10).

[0062] The push-blocking transistor (P16) can be turned on depending on the voltage of the third upper node (NU3). That is, the voltage level of the third upper node (NU3) may be a voltage level capable of turning on the push-blocking transistor (P16). The voltage level of the third upper node (NU3) may be equal to the voltage level of the threshold voltage of the push-blocking transistor (P16) or higher than the voltage level of the threshold voltage of the push-blocking transistor (P16). Accordingly, the push-blocking transistor (P16) can be turned on, and the push-blocking current (I BLK_PUSH ) can be generated.

[0063] One end of the push blocking transistor (P16) is the push node (N) of the push compensation current circuit (23). PUSH It can be connected to ), and a power supply voltage (VDD) can be applied from the other terminal. As the push-blocking transistor (P16) is turned on by the voltage provided from the load terminal (14), the push node (N PUSH Push blocking current (I) BLK_PUSH ) can flow. Accordingly, the push-blocking transistor (P16) push-blocking current (I) to the gates of the transistors (P15, P14) of the push-compensating current circuit (23). BLK_PUSH It can provide ).

[0064] When the input voltage (VIN) is polling and the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) is greater than the threshold voltage of the transistor (P11), the push compensation current circuit (23) polling comparison current (I DIFF Push compensation current (I) based on ) PUSH It can generate ) and push compensation current (I) to the operational amplifier (10). PUSH ) can be provided. At this time, push blocking current (I BLK_PUSH ) can be supplied from the push-blocking transistor (P16) to the boosting transistor (P15), but the push compensation current (I PUSH Since ) is strongly generated, the boosting transistor (P15) can remain in a turned-on state.

[0065] When the input voltage (VIN) is polling and the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) is smaller than the threshold voltage of the transistor (P11), the push compensation current circuit (23) may be disabled. Accordingly, the push compensation current circuit (23) polling comparison current (I DIFF Since it does not generate ), the push compensation current (I PUSH ) may also not be generated. In this case, the push-blocking current (I BLK_PUSH Since ) can be supplied from the push-blocking transistor (P16) to the boosting transistor (P15), the gate voltage of the boosting transistor (P15) rises, allowing the boosting transistor (P15) to remain in a turned-off state. Therefore, even if leakage current occurs in the push compensation current circuit (23), the push-blocking current (I BLK_PUSH Since the transistors (P15, P14) are turned off by ), leakage current flowing to the first upper node (NU1) of the push load circuit (PS) can be eliminated. In addition, DC offset can be eliminated, the operating speed of the buffer circuit can be improved, and it can be driven at low power.

[0066] The gate of the full blocking transistor (N16) can be connected to the third lower node (NL3) of the full load circuit (PL). In other words, the gate of the full blocking transistor (N16) can be connected to the full connection node. Accordingly, the full blocking transistor (N16) can be operated by the voltage provided by the operational amplifier (10). More specifically, the full blocking transistor (N16) can be operated by the voltage provided by the load terminal (14) of the operational amplifier (10).

[0067] The gate of the full blocking transistor (N16) can be turned on depending on the voltage of the third lower node (NL3). The voltage level of the third lower node (NL3) may have a voltage level capable of turning on the full blocking transistor (N16). That is, the voltage level of the third lower node (NL3) may be equal to the voltage level of the threshold voltage of the blocking transistor (N16) or higher than the voltage level of the threshold voltage of the full blocking transistor (N16). Accordingly, the full blocking transistor (N16) can be turned on, and the full blocking current (I BLK_PULL ) can be generated.

[0068] One end of the full blocking transistor (N16) is the full node (N) of the full compensation current circuit (23). PULL It can be connected to ), and a ground voltage (VSS) can be applied from the other terminal. As the full blocking transistor (N16) is turned on by the voltage provided from the load terminal (14), the full node (N PULL Full blocking current (I) from ) BLK_PULL ) can flow out. Accordingly, a full blocking current (I) can flow from the gates of the transistors (N12, N13) of the full compensation current circuit (22) toward the full blocking transistor (N16). BLK_PULL ) can flow. In the following, including Fig. 5, a full blocking current (I BLK_PULL Full blocking current (I) depending on the flow of ) BLK_PULL ) is a full node (NPULL It is depicted as flowing in the direction of the ground voltage (VSS) from ), but the full blocking current (I BLK_PULL Since ) is generated by the full-blocking transistor (N16) and affects the slew rate compensation circuit (20), the full-blocking transistor (N16) generates a full-blocking current (I) in the full-compensation current circuit (22). BLK_PULL It can be described as providing ).

[0069] When the input voltage (VIN) rises and the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) is greater than the threshold voltage of the transistor (N11), the full compensation current circuit (22) is a rising comparison current (I DIFR Based on ), full compensation current (I PULL It can generate ) and full compensation current (I) to the operational amplifier (10). PULL ) can be provided. At this time, the full blocking current (I BLK_PULL ) can be supplied from the full blocking transistor (N16) to the boosting transistor (N13), but the full compensation current (I PULL Since ) is strongly generated, the boosting transistor (N13) can remain in a turned-on state.

[0070] When the input voltage (VIN) rises and the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) is smaller than the threshold voltage of the transistor (N11), the full compensation current circuit (22) compares the rising current (I DIFR Since it does not generate ), the full compensation current (I PULL ) may also not be generated. In this case, the full blocking current (I BLK_PULL Since ) is generated, a full blocking current (I) is transferred from the boosting transistor (N13) to the full blocking transistor (N16). BLK_PULL) can flow out. Accordingly, the gate voltage level of the boosting transistor (N13) is lowered, so the boosting transistor (N13) can remain in a turned-off state. Therefore, even if leakage current occurs in the full compensation current circuit (22), the full blocking current (I BLK_PULL Since the boosting transistor (N13) is turned off by ), leakage current flowing to the first lower node (NL1) of the full load circuit (PL) can be eliminated. In addition, the DC offset can be eliminated, the operating speed of the buffer circuit can be improved, and it can be driven at low power.

[0071] In one embodiment according to the present disclosure, the gate of the push-blocking transistor (P16) is shown to be connected to the third upper node (NU3) and the gate of the full-blocking transistor (N16) is shown to be connected to the third lower node (NL3), but is not limited thereto. For example, the gates of the push-blocking transistor (P16) and the full-blocking transistor (N16) may be connected to any node among the nodes of the load terminal (14) that provides a voltage capable of turning on the push-blocking transistor (P16) and the full-blocking transistor (N16). For example, the gate of the push-blocking transistor (P16) may be connected to a node among the nodes of the load terminal (14) that provides a voltage level higher than the threshold voltage level of the push-blocking transistor (P16). For example, the gate of the full blocking transistor (N16) can be connected to a node among the nodes of the load section (14) that provides a voltage level higher than the threshold voltage level of the full blocking transistor (N16).

[0072] In one embodiment according to the present disclosure, the push-blocking transistor (P16) may include a PFET and the full-blocking transistor (N16) may include an NFET, but is not limited thereto. Hereinafter, various embodiments of the buffer circuit (BF) will be described.

[0073] FIG. 6 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. In detail, FIG. 6 is a circuit diagram for explaining an operational amplifier (10a) as another embodiment of FIG. 2 and FIG. 3. The following description refers to FIG. 1 to FIG. 3, and redundant descriptions are omitted.

[0074] Referring to FIG. 6, the operational amplifier (10a) may include an input terminal (11a), a lower bias circuit (13), a load terminal (14a), and an output terminal (15).

[0075] The input terminal (11a) may have a single structure in which transistors (P1, P2) are omitted. The input terminal (11a) may be connected to transistors (N1, N2), and a push load current (I) from the load terminal (14a) PSLI , I PSLO Can receive ).

[0076] The lower bias circuit (13) applies a second bias current (I) to the input terminal (11a) based on the second bias voltage (VB2). BL ) can be generated. Unlike the operational amplifier (10) of FIG. 3, the upper bias circuit (12) can be omitted.

[0077] The load section (14a) may include a push load circuit (PS), a pull load circuit (PLa), a connection circuit (CC), a first capacitor (C1), and a second capacitor (C2). The push load circuit (PS) receives a push compensation current (I) from the slew rate compensation circuit (20) through the first upper node (NU1). PUSH It can receive ), and push compensation current (I PUSH Based on ), push load current (I PSLI , I PSLO ) can generate. The push load circuit (PS) generates a push load current (I) through the drain terminal of transistor (P4) and the drain terminal of transistor (P5). PSLI , I PSLO) can be provided to the second input terminal (IS2). The full load circuit (PLa) provides the full compensation current (I) through the first lower node (NL1). PULL ) can be received, but the full load current (I) of FIG. 3 PLLI , I PLLO It may not provide ).

[0078] FIG. 7 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. In detail, FIG. 7 is a circuit diagram for explaining an operational amplifier (10b) as another embodiment of FIG. 2. The following description refers to FIG. 3, and redundant descriptions are omitted.

[0079] Referring to FIG. 7, the operational amplifier (10b) may include an input terminal (11b), an upper bias circuit (12), a load terminal (14b), and an output terminal (15).

[0080] The input terminal (11b) may have a single structure. The input terminal (11) may be connected to transistors (P1, P2) and a full load current (I) from the load terminal (14b). PLLI , I PLLO Can receive ).

[0081] The upper bias circuit (12) applies a first bias current (I) to the input terminal (11b) based on the first bias voltage (VB1). BU ) can be provided. Unlike the operational amplifier (10) of FIG. 3, the lower bias circuit (13) can be omitted.

[0082] The load section (14b) may include a push load circuit (PSa), a pull load circuit (PL), a connection circuit (CC), a first capacitor (C1), and a second capacitor (C2). The push load circuit (PS) provides a push compensation current (I) through the first upper node (NU1). PUSH ) can be received, but the push load current (I) of FIG. 3 PSLI , I PSLO) may not be provided. The full load circuit (PL) receives the full compensation current (I) from the slew rate compensation circuit (20) through the first lower node (NL1). PULL It can receive ), and full compensation current (I PULL Based on ), full load current (I PLLI , I PLLO ) can generate. The full load circuit (PL) generates a full load current (I) through the drain terminal of transistor (N4) and the drain terminal of transistor (N5). PLLI , I PLLO ) can be provided to the input terminal (11b).

[0083] FIG. 8 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 8 is a circuit diagram for explaining a slew rate compensation circuit (20a) as another embodiment of FIG. 4. The following description refers to FIG. 4, and redundant descriptions are omitted.

[0084] Referring to FIG. 8, the slew rate compensation circuit (20a) may include a comparison circuit (21), a pull compensation current circuit (22), a push compensation current circuit (23), and variable resistors (R1, R2).

[0085] The first variable resistor (R1) can be connected between the comparison circuit (21) and the full compensation current circuit (22). The second variable resistor (R2) can be connected between the comparison circuit (21) and the push compensation current circuit (23). The slew rate compensation circuit (20a) includes the variable resistors (R1, R2), thereby allowing the rising comparison current (I DIFR ) and Poling comparison current (I DIFF The amount of current can be controlled. That is, the slew rate compensation circuit (20a) can control the operating speed of the slew rate compensation circuit (20a) by including variable resistors (R1, R2), and accordingly, the operating speed of the operational amplifier (10) can be controlled.

[0086] FIG. 9 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 9 is a circuit diagram for explaining a slew rate compensation circuit (20b) as another embodiment of FIG. 4. The following description refers to FIG. 4, and redundant descriptions are omitted.

[0087] Referring to FIG. 9, the slew rate compensation circuit (20b) may include a comparison circuit (21), a pull compensation current circuit (22), a push compensation current circuit (23), and control transistors (P17, N17).

[0088] A ninth bias voltage (VB9) is applied to the gate of the first control transistor (P17), and one end can be connected to a comparison circuit (21) and the other end to a full compensation current circuit (22). By varying the ninth bias voltage (VB9), the rising comparison current (I DIFR The amount of current of ) can be controlled.

[0089] The second control transistor (N17) has a 10th bias voltage (VB10) applied to its gate, and one end can be connected to a comparison circuit (21) and the other end to a push compensation current circuit (23). By varying the 10th bias voltage (VB10), the falling comparison current (I DIFF The amount of current of ) can be controlled.

[0090] That is, the slew rate compensation circuit (20b) includes control transistors (P17, N17) so that the operating speed of the slew rate compensation circuit (20b) can be controlled, and accordingly, the operating speed of the operational amplifier (10) can be controlled.

[0091] FIG. 10 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 10 is a circuit diagram for explaining a slew rate compensation circuit (20c) as another embodiment of FIG. 4. The following description refers to FIG. 4, and redundant descriptions are omitted.

[0092] Referring to FIG. 10, the slew rate compensation circuit (20c) may include a comparison circuit (21), a pull compensation current circuit (22c), and a push compensation current circuit (23c).

[0093] The full compensation current generation circuit (22c) may include transistors (P12, P13, N12, N13, P18, P19) and a first current source (I1). The first current source (I1) may generate a first supply current in response to a first control signal (CNT1). The first control signal (CNT1) may be a signal provided from outside the slew rate compensation circuit (20d).

[0094] The transistors (P18, P19) can be connected in a current mirror configuration. One end of transistor (P18) can be connected to transistor (P12), and a power supply voltage (VDD) can be applied from the other end. One end of transistor (P19) can be connected to a first current source (I1), and a power supply voltage (VDD) can be applied from the other end.

[0095] The push compensation current generation circuit (23c) may include transistors (N14, N15, P14, P15, N18, N19) and a second current source (I2). The second current source (I2) may generate a second power current in response to a second control signal (CNT2). The second control signal (CNT2) may be a signal provided from outside the slew rate compensation circuit (20d).

[0096] The transistors (N18, N19) can be connected in a current mirror configuration. One end of transistor (N18) can be connected to transistor (N14), and a ground voltage (VSS) can be applied from the other end. One end of transistor (N19) can be connected to a second current source (I2), and a ground voltage (VSS) can be applied from the other end.

[0097] FIG. 11 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 11 is a circuit diagram for explaining a slew rate compensation circuit (20d) as another embodiment of FIG. 4. The following description refers to FIG. 3 and FIG. 4, and redundant descriptions are omitted.

[0098] Referring to FIG. 11, the slew rate compensation circuit (20d) may include a comparison circuit (21), a pull compensation current circuit (22d), and a push compensation current circuit (23d).

[0099] The full compensation current generation circuit (22d) may include transistors (P12, P13, N12, N13, P20). The gate of transistor (P20) may be connected to the second upper node (NU2) of the push load circuit (PS). One end of transistor (P20) may be connected to transistor (P12), and a power supply voltage (VDD) may be applied from the other end.

[0100] The push compensation current generation circuit (23d) may include transistors (N14, N15, P14, P15, N20). The gate of transistor (N20) may be connected to the second lower node (NL2) of the pull load circuit (PL). One end of transistor (N20) may be connected to transistor (N14), and a ground voltage (VSS) may be applied from the other end.

[0101] FIG. 12 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 12 is a circuit diagram for explaining a comparison circuit (21a) as another embodiment of the comparison circuit included in the slew rate compensation circuit of FIG. 4. The following description refers to FIG. 4, and redundant descriptions are omitted.

[0102] Referring to FIG. 12, the comparison circuit (21a) may include transistors (N11, P11, N21, P21, N22, P22, N23, P23).

[0103] The transistor (P21) can receive a first inverting enable signal (EN1b) at its gate, and one end is connected to the gate terminal of the transistor (N11) and an input voltage (VIN) can be applied from the other end.

[0104] The transistor (N21) can receive a first enable signal (EN1) at its gate, and one end is connected to the gate terminal of the transistor (N11) and an input voltage (VIN) can be applied from the other end. The first inverted enable signal (EN1b) may be a signal in which the first enable signal (EN1) is inverted. For example, when the first enable signal (EN1) has a high level, the first inverted enable signal (EN1b) may have a low level.

[0105] The transistor (P22) can receive a second inversion enable signal (EN2b) at its gate, and one end is connected to the gate terminal of the transistor (P11) and an input voltage (VIN) can be applied from the other end.

[0106] The transistor (N22) can receive the second enable signal (EN2) at its gate, and one end is connected to the gate terminal of the transistor (P11) and the input voltage (VIN) can be applied from the other end. The second inverted enable signal (EN2b) may be the second enable signal (EN2) inverted. For example, when the second enable signal (EN2) has a high level, the second inverted enable signal (EN2b) may have a low level.

[0107] The first enable signal (EN1), the first inverted enable signal (EN1b), the second enable signal (EN2), and the second inverted enable signal (EN2b) may be control signals for controlling the comparison circuit (21a). The first enable signal (EN1), the first inverted enable signal (EN1b), the second enable signal (EN2), and the second inverted enable signal (EN2b) may be signals provided from outside the slew rate compensation circuit (20). The first enable signal (EN1) and the second enable signal (EN2) may be signals having the same level. The first inverted enable signal (EN1b) and the second inverted enable signal (EN2b) may be signals having the same level.

[0108] The gate of transistor (N23) receives a first inverted enable signal (EN1b), one end is connected to the gate of transistor (N11) and a ground voltage (VSS) can be applied from the other end. The gate of transistor (P23) receives a second enable signal (EN2), one end is connected to the gate of transistor (P11) and a power supply voltage (VDD) can be applied from the other end.

[0109] Since the comparison circuit (21a) includes transistors (N21, P21, N22, P22, N23, P23), when the full compensation current circuit (22) or the push compensation current circuit (23) is deactivated, the comparison current (I DIFR , I DIFF It can be blocked so that ) is not generated. When the first and second enable signals (EN1, EN2) have a low level and the first and second inverted enable signals (EN1b, EN2b) have a high level, the gates of the transistors (N11, P11) may not be floating.

[0110] FIG. 13 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 13 is a circuit diagram for explaining a comparison circuit (21b) as another embodiment of the comparison circuit included in the slew rate compensation circuit of FIG. 4. The following description refers to FIG. 4, and redundant descriptions are omitted.

[0111] Referring to FIG. 13, the comparison circuit (21b) may include transistors (N11, P11). The gates of the transistors (N11, P11) may be electrically connected, and the bodies of the transistors (N11, P11) may be electrically connected to the output node (N0UT). Additionally, the source terminals of the transistors (N11, P11) may be electrically connected to the output node (N0UT).

[0112] As the body of the transistors (N11, P11) is electrically connected to the source terminal of the transistors (N11, P11), the level of the threshold voltage of the transistors (N11, P11) can be maintained constant even if the back-bias voltage applied to the body of the transistors (N11, P11) changes.

[0113] FIG. 14 is a circuit diagram of an offset blocking circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 14 is a circuit diagram for explaining an offset blocking circuit (30a) as another embodiment of FIG. 5. The following description refers to FIG. 5, and redundant descriptions are omitted.

[0114] Referring to FIG. 14, the offset blocking circuit (30a) may include a push blocking transistor (P16) and a pull blocking transistor (N16).

[0115] A first bias voltage (VB11) can be applied to the gate of the push-blocking transistor (P16), and at one end, the full node (N PULLIt is connected to ) and a power supply voltage (VDD) can be applied from the other terminal. The level of the 11th bias voltage (VB11) may be equal to the threshold voltage level of the push-blocking transistor (P16) or higher than the threshold voltage level of the push-blocking transistor (P16).

[0116] A 12th bias voltage (VB12) can be applied to the gate of the full blocking transistor (N16), and at one end, the push node (N PUSH It is connected to ) and a ground voltage (VSS) can be applied from the other end. The level of the 12th bias voltage (VB12) may be equal to the threshold voltage level of the full blocking transistor (N16) or higher than the threshold voltage level of the full blocking transistor (N16).

[0117] The offset blocking circuit (30a) can be controlled by applying bias voltages (VB11, VB12) to the gates of the push blocking transistor (P16) and the full blocking transistor (N16).

[0118] FIG. 15 is a diagram illustrating voltages measured at nodes of a buffer circuit according to exemplary embodiments of the present disclosure. More specifically, (a) a graph is a diagram illustrating the waveform of the output voltage (VOUT) of the buffer circuit (BF) according to the present disclosure in comparison with a conventional buffer circuit, and (b) a graph is a push node (N) in the buffer circuit (BF) according to the present disclosure when the input voltage (VIN) rises PUSH ) voltage (V PUSH (c) is a diagram illustrating the waveform of ) compared with a conventional buffer circuit, and the graph shows the full node (N) in the buffer circuit (BF) according to the present disclosure when the input voltage (VIN) is polling. PULL ) voltage (V PULL This is a diagram illustrating the waveform of ) compared with a conventional buffer circuit. In FIG. 15, the horizontal axis represents time and the vertical axis represents voltage. The following description refers to FIGS. 2 to 5.

[0119] Referring to FIG. 15, in graph (a), the output voltage (V1) of a buffer circuit (BF) including an operational amplifier (10), a slew rate compensation circuit (20), and an offset blocking circuit (30) according to the present disclosure has a shorter transition time than the output voltage (V2) of a buffer circuit in which the slew rate compensation circuit (20) and the offset blocking circuit (30) are omitted. That is, the rate of change of the output voltage, represented by the slope of graph (a), is greater at the output voltage (V1) than at the output voltage (V2). Since the output voltage changes more rapidly at the output voltage (V1), the slew rate of the buffer circuit (BF) according to the present disclosure is improved compared to the buffer circuit in which the slew rate compensation circuit (20) and the offset blocking circuit (30) are omitted.

[0120] Additionally, in graph (b), when the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) becomes smaller than the threshold voltage level of the transistor (N11) included in the comparison circuit (21), according to the present disclosure, the push node (N) of the buffer circuit (BF) including the slew rate compensation circuit (20) and the offset blocking circuit (30) PUSH The voltage level of 1) can be equal to the voltage level of the ground voltage (VSS). However, the push node (N) of the buffer circuit in which the slew rate compensation circuit (20) and the offset blocking circuit (30) are omitted PUSH The voltage level of 2) is the threshold voltage (V) of the transistor (N11). THN It can be equal to the voltage level of ).

[0121] (c) In the graph, when the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) becomes smaller than the threshold voltage level of the transistor (P11) included in the comparison circuit (21), the full node (N) of the buffer circuit (BF) including the slew rate compensation circuit (20) and the offset blocking circuit (30) according to the present disclosure PULLThe voltage level of 1) may be equal to the voltage level of the power supply voltage (VDD). However, the full node (N) of the buffer circuit in which the slew rate compensation circuit (20) and the offset blocking circuit (30) are omitted PULL The voltage level of 2) is the threshold voltage (V) of the transistor (P11). THP It can become equal to the voltage level of ).

[0122] According to an embodiment of the present disclosure, after the input voltage (VIN) rises or falls, the boosting transistor (N13, P15) can be turned off by the offset blocking circuit (30). Accordingly, the DC offset can be removed, so the slew rate can be improved.

[0123] FIG. 16 is a block diagram of a source driver including a buffer circuit according to exemplary embodiments of the present disclosure. More specifically, it is a diagram for explaining a source driver including a buffer circuit (BF) with reference to FIG. 1 to FIG. 14.

[0124] Referring to FIG. 16, the source driver (100) may include a shift register (110), a sampling latch (120), a holding latch (130), a decoder (140), and an output buffer circuit (150).

[0125] The shift register (110) can control the operation timing of each of the plurality of sampling circuits included in the sampling latch (120) in response to the horizontal synchronization signal (Hysnc). The horizontal synchronization signal (Hsync) may be a signal having a constant period.

[0126] The sampling latch (120) can sample image data according to the shift order of the shift register (110). The image data sampled by the sampling latch (120) can be stored in the holding latch (130).

[0127] The decoder (140) may include a digital-to-analog converter (DAC) and may receive a plurality of gamma voltages (VG). The decoder (140) may select at least one of the plurality of gamma voltages (VG) based on image data stored in the holding latch (130). The number of gamma voltages (VG) may be determined according to the number of bits in the image data. For example, if the image data is 8-bit data, the number of gamma voltages (VG) may be 256 or fewer, and if the image data is 10-bit data, the number of gamma voltages (VG) may be 1024 or fewer.

[0128] The output buffer circuit (150) may include a plurality of output buffers implemented as operational amplifiers, and the plurality of output buffers may be connected to a plurality of source lines (SL). Each of the plurality of output buffers may have a plurality of input terminals. The decoder (140) may select at least some of the gamma voltages (VG) based on image data and may provide the selected voltage as an input voltage to the input terminals of each of the plurality of output buffers. Each of the plurality of output buffers may output the input voltage received from the decoder unit (140) to the source line.

[0129] Each of the plurality of output buffers may include the operational amplifier, slew rate compensation circuit (151), and offset blocking circuit (152) described above with reference to FIGS. 1 to 14. By each of the plurality of output buffers including the slew rate compensation circuit (151) and the offset blocking circuit (152), the DC offset can be eliminated, the device can operate at low power, and the slew rate can be increased.

[0130] FIG. 17 is a block diagram of a display device according to exemplary embodiments of the present disclosure. In detail, it is a drawing for explaining a display device (200) including a source driver (100) of FIG. 16.

[0131] Referring to FIG. 17, the display device (200) may include a display panel (210), a controller (220), a gate driver (230), and a source driver (240).

[0132] The display panel (210) includes a plurality of pixels (PX) arranged in a matrix form and can display an image in frame units. The display panel (210) can be implemented as one of an LCD (liquid crystal display), an LED (light emitting diode) display, an OLED (organic LED) display, an AMOLED (active-matrix OLED) display, a micro LED display, an ECD (Electrochromic Display), a DMD (Digital Mirror Device), an AMD (Actuated Mirror Device), a GLV (Grating Light Value), a PDP (Plasma Display Panel), an ELD (Electro Luminescent Display), or a VFD (Vacuum Fluorescent Display), and can also be implemented as other types of flat panel displays or flexible displays. An OLED panel is described below as an example, but is not limited thereto.

[0133] The display panel (210) may have gate lines (GL1~GLn) arranged in a row direction, source lines (SL1~SLm) arranged in a column direction, and pixels (PX) formed at the intersection points of the gate lines (GL1~GLn) and source lines (SL1~SLm).

[0134] In the display panel (210), pixels (PX) that output red (R), green (G), and blue (B) light may be arranged in a repeating sequence. For example, the pixels (PX) may be arranged in a repeating sequence of R, G, B or B, G, R. Alternatively, the pixels (PX) may be arranged in a repeating sequence of R, G, B, G or B, G, R, G, etc.

[0135] Pixels (PX) may include a light-emitting diode and a driving circuit that independently drives the light-emitting diode. Specifically, a pixel (PX) may have a diode driving circuit connected to either a gate line and a source line, and a light-emitting diode connected between the diode driving circuit and a power supply voltage (e.g., ground voltage).

[0136] The diode driving circuit may include a switching element, such as a thin-film transistor, connected to a gate line. When a gate-on signal is applied from the gate line and the switching element is turned on, the diode driving circuit can supply an image signal received from a source line connected to the diode driving circuit to a light-emitting diode. The diode can output an optical signal corresponding to the image signal.

[0137] The controller (220) can receive control signals from an external source. For example, the controller (220) can receive a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), a clock signal (DCLK), and a data enable signal (DE) from an external source. Based on the received control signals, the controller (220) can generate control signals (CONT1, CONT2, CLS) to control the gate driver (230) and the source driver (240). Various operation timings of the gate driver (230) and the source driver (240) can be controlled according to the control signals (CONT1, CONT2, CLS).

[0138] Additionally, the controller (220) can receive image data (RGB) from an external source and process the received image data (RGB) or convert the image data (RGB) to fit the structure of the display panel (210). The controller (220) can transmit the converted image data (DATA) to the source driver (240).

[0139] A controller (220) according to an embodiment of the present disclosure can determine the driving order of groups of pixels in a single horizontal line of a display panel (210). That is, the controller (220) can drive each of a plurality of pixel groups by dividing a single horizontal period into time divisions.

[0140] The gate driver (230) can sequentially supply gate-on signals to gate lines (GL1~GLn) in response to a gate control signal (CTRL1) received from the controller (220). For example, the gate control signal (CTRL1) may include a gate start pulse (GSP) indicating the start of output of the gate-on signal and a gate shift clock (GSC) controlling the timing of output of the gate-on signal. When the gate start pulse (GSP) is applied, the gate driver (230) can sequentially generate gate-on signals (e.g., a logic low level gate voltage) in response to the gate shift clock (GSC) and sequentially supply gate-on signals to gate lines (GL1~GLn). At this time, during the period when gate-on signals are not supplied to the gate lines (GL1~GLn), a gate-off signal (e.g., a logic high level gate voltage) may be supplied to the gate lines (GL1~GLn).

[0141] The source driver (240) can convert image data (DATA) into image signals (e.g., grayscale voltage corresponding to pixel data) in response to a source control signal (CTRL2) received from the controller (220), and output the image signals through a plurality of channels (CH1~CHk). For example, the source control signal (CTRL2) may include a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE) signal, etc. The source driver (240) may include a plurality of driving units that provide an image signal for one horizontal line to source lines (SL1~SLm) during one horizontal period. Each driving unit can activate the source lines connected to each driving unit.

[0142] The source driver (240) may include the source driver (100) described above with reference to FIG. 16. Accordingly, the output buffer included in the source driver (240) may include a slew rate compensation circuit (241) and an offset blocking circuit (242).

[0143] Meanwhile, although not illustrated, the display device (200) may further be equipped with a voltage generation circuit and an interface. The voltage generation circuit can generate various voltages used in the display panel (210) and driving circuits. The interface may include, for example, an RGB interface, a CPU interface, a serial interface, an MDDI (Mobile display digital interface), an I2C (inter integrated circuit) interface, a SPI (serial pheripheral interface), an MCU (micro controller unit) interface, a MIPI (Mobile industry processor interface), an eDP (embedded displayport) interface, a D-sub (D-subminiature), an optical interface (4076), or one of D-sub (D-subminiature) or HDMI (high-definition multimedia interface). In addition, the interface may include various other serial or parallel interfaces.

[0144] According to an embodiment, the controller (220) and the source driver (240) are implemented on a single semiconductor chip, and the gate driver (230) can be integrated on a display panel (210).

[0145] According to an embodiment, the semiconductor chip may include a semiconductor substrate comprising single crystal silicon. Accordingly, the display device (200) may include a driving element and / or a switch composed of a single crystal silicon thin-film transistor.

[0146] According to an embodiment, the display panel (210) may include a semiconductor substrate comprising amorphous silicon (a-Si) or polycrystalline silicon (poly-Si). Accordingly, the display panel (210) may include a driving element and / or switch composed of an amorphous silicon thin-film transistor, or a driving element and / or switch composed of a polycrystalline silicon thin-film transistor.

[0147] According to an embodiment, a pad connecting the source driver (240) and the display panel (210) may be provided. For example, the source driver (240) may include a plurality of output pads, and the display panel (210) may include a plurality of input pads.

[0148] FIG. 18 is a flowchart illustrating a method of operation of a buffer circuit according to exemplary embodiments of the present disclosure. More specifically, it is a flowchart illustrating a method of operation of a buffer circuit (BF) described above with reference to FIG. 1 to 5. The following description will be made with reference to FIG. 1 to 5.

[0149] Referring to FIG. 18, in step (S10), the input voltage level (VL IN ) and output voltage level (VL OUT The difference of ) can be compared with the reference voltage level (VL1). Input voltage level (VL IN ) and output voltage level (VL OUT The difference of ) can be compared in the comparator (21). The reference voltage level (VL1) may include the threshold voltage level of the transistors (N11, P11) constituting the comparator (21).

[0150] In step (S20), the input voltage level (VL IN ) and output voltage level (VL OUT If the difference ) is greater than the reference voltage level (VL1), the input voltage level (VL IN ) and output voltage level (VL OUTCompensation current (I) in the slew rate compensation circuit (20) based on the difference of ) PULL , I PUSH ) can be generated. For example, when the input voltage rises, the full compensation current (I) in the slew rate compensation circuit (20) PULL ) can be generated, and when the input voltage polls, the push compensation current (I) in the slew rate compensation circuit (20) PUSH ) can generate. The slew rate compensation circuit (20) can generate a compensation current (I PULL , I PUSH ) can be provided to the load terminal (14) of the operational amplifier (10).

[0151] In step (S30), the load terminal (14) receives a compensation current (I) provided from the slew rate compensation circuit (20). PUSH , I PULL The slew rate compensation operation can be performed using ). That is, the load terminal (14) can perform the compensation current (I PUSH , I PULL Based on ), load currents (I PSLI , I PSLO , I PLLI , I PLLO ) can be generated. The load terminal (14) can generate load currents (I PSLI , I PSLO , I PLLI , I PLLO ) can be provided to the input terminal (11) of the operational amplifier (10).

[0152] In step (S40), the input voltage can be buffered to generate an output voltage.

[0153] In step (S50), the input voltage level (VL IN ) and output voltage level (VL OUT If the difference is smaller than the reference voltage level (VL1), the slew rate compensation circuit (20) may be disabled. Regardless of whether the slew rate compensation circuit (20) is disabled, the offset blocking circuit (30) may be enabled by the turn-on voltage or external bias voltage provided from the operational amplifier (10).

[0154] In step (S60), the offset blocking circuit (30) blocks the current (I BLK_PUSH , I BLK_PULL It can generate ) and provide it to the slew rate compensation circuit (20). Specifically, blocking current (I BLK_PUSH , I BLK_PULL ) can be provided to the gate of the boosting transistor (N13, P15) of the slew rate compensation circuit (20).

[0155] In step (S70), the boosting transistor (N13, P15) of the slew rate compensation circuit (20) may be turned off. Accordingly, leakage current generated in the slew rate compensation circuit (20) may not flow to the operational amplifier (10), and the DC offset may be eliminated. Additionally, a buffer circuit that has an increased slew rate and operates at low power may be provided.

[0156] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An operational amplifier that amplifies an input voltage to generate an output voltage; a slew rate compensation circuit that generates a compensation current based on the difference between the voltage level of the input voltage and the voltage level of the output voltage and provides the compensation current to the operational amplifier through a boosting transistor; and an offset blocking circuit configured to provide a blocking current to the boosting transistor, wherein the boosting transistor receives the blocking current when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than a reference voltage level, is turned on based on the difference between the voltage level of the input voltage and the voltage level of the output voltage being greater than the reference voltage level, and is turned off based on the blocking current when the difference between the voltage level of the input voltage and the voltage level of the output voltage is less than the reference voltage level. Claim 2 A buffer circuit according to claim 1, wherein the offset blocking circuit generates the blocking current based on a turn-on voltage provided from the operational amplifier or a bias voltage input from the outside. Claim 3 A buffer circuit according to claim 1, characterized in that the reference voltage level is at the same level as the voltage level of the threshold voltage of a transistor constituting the slew rate compensation circuit. Claim 4 A buffer circuit according to claim 1, wherein the slew rate compensation circuit provides the compensation current to the operational amplifier when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level. Claim 5 In claim 1, the slew rate compensation circuit comprises: a comparator that compares the voltage level of the input voltage with the voltage level of the output voltage and generates a comparison current corresponding to the difference between the voltage level of the input voltage and the voltage level of the output voltage; a push compensation current circuit that generates a push compensation current that supplies current to the operational amplifier by performing a current mirror operation on the comparison current; and a full compensation current circuit that generates a full compensation current that syncs the current of the operational amplifier by performing a current mirror operation on the comparison current. Claim 6 A buffer circuit according to claim 5, wherein, when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage rises, the slew rate compensation circuit provides the full compensation current to the operational amplifier as the full compensation current circuit is activated, and when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage falls, the slew rate compensation circuit provides the push compensation current to the operational amplifier as the push compensation current circuit is activated. Claim 7 In claim 5, the operational amplifier comprises: an input stage that receives the input voltage and output voltage and includes a first input terminal composed of PFETs and a second input terminal composed of NFETs; a load stage that includes a pull load circuit that provides a pull load current generated based on the pull compensation current to the first input terminal, a push load circuit that provides a push load current generated based on the push compensation current to the second input terminal, and a connection circuit that connects a pull connection node of the pull load circuit and a push connection node of the push load circuit; and an output stage that is electrically connected to the pull connection node and the push connection node and buffers the output signal of the load stage to generate the output voltage. Claim 8 A buffer circuit according to claim 7, wherein the boosting transistor is respectively included in the push compensation current circuit and the pull compensation current circuit, and the offset blocking circuit comprises: a PFET (P-channel Field Effect Transistor) whose gate is connected to the push connection node, one end is connected to the gate of the boosting transistor included in the push compensation current circuit, and a power supply voltage is applied from the other end; and an NFET (N-channel Field Effect Transistor) whose gate is connected to the pull connection node, one end is connected to the gate of the boosting transistor included in the pull compensation current circuit, and a ground voltage is applied from the other end. Claim 9 A display device comprising: a plurality of pixels formed at the intersection points of gate lines arranged in a row direction and source lines arranged in a column direction; a controller that generates a source control signal based on control signals received from the outside and converts image data received from the outside; and a source driver that converts image data converted by the controller into an image signal in response to the source control signal received from the controller and provides the image signal to the source lines, wherein the source driver comprises: an operational amplifier that amplifies an input voltage to generate an output voltage; a slew rate compensation circuit configured to generate a compensation current based on the difference between the voltage level of the input voltage and the voltage level of the output voltage and to provide the compensation current to the operational amplifier through a boosting transistor; and a buffer circuit comprising an offset blocking circuit that provides a blocking current to the slew rate compensation circuit, thereby turning off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is smaller than a reference voltage level, wherein the offset blocking circuit generates the blocking current based on a turn-on voltage provided from the operational amplifier. Claim 10 A display device according to claim 9, wherein the offset blocking circuit provides the blocking current to the gate of the boosting transistor. Claim 11 A display device according to claim 9, characterized in that the reference voltage level is the same level as the voltage level of the threshold voltage of the transistor constituting the slew rate compensation circuit. Claim 12 A display device according to claim 9, wherein the slew rate compensation circuit provides the compensation current to the operational amplifier when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level. Claim 13 A display device according to claim 9, wherein the slew rate compensation circuit comprises: a comparator that compares the voltage level of the input voltage with the voltage level of the output voltage and generates a comparison current corresponding to the difference between the voltage level of the input voltage and the voltage level of the output voltage; a push compensation current circuit that generates a push compensation current that supplies current to the operational amplifier by performing a current mirror operation on the comparison current; and a full compensation current circuit that generates a full compensation current that syncs the current of the operational amplifier by performing a current mirror operation on the comparison current. Claim 14 A display device according to claim 13, wherein, when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage rises, the slew rate compensation circuit provides the full compensation current to the operational amplifier as the full compensation current circuit is activated, and when the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage falls, the slew rate compensation circuit provides the push compensation current to the operational amplifier as the push compensation current circuit is activated. Claim 15 A display device according to claim 13, wherein the operational amplifier comprises: an input stage that receives the input voltage and output voltage and includes a first input terminal composed of PFETs and a second input terminal composed of NFETs; a load stage that includes a pull load circuit that provides a pull load current generated based on the pull compensation current to the first input terminal, a push load circuit that provides a push load current generated based on the push compensation current to the second input terminal, and a connection circuit that connects a pull connection node of the pull load circuit and a push connection node of the push load circuit; and an output stage that is electrically connected to the pull connection node and the push connection node and buffers the output signal of the load stage to generate the output voltage. Claim 16 A display device according to claim 15, wherein the boosting transistor is respectively included in the push compensation current circuit and the pull compensation current circuit, and the offset blocking circuit comprises: a PFET (P-channel Field Effect Transistor) whose gate is connected to the push connection node, one end is connected to the gate of the boosting transistor included in the push compensation current circuit, and a power supply voltage is applied from the other end; and an NFET (N-channel Field Effect Transistor) whose gate is connected to the pull connection node, one end is connected to the gate of the boosting transistor included in the pull compensation current circuit, and a ground voltage is applied from the other end. Claim 17 A buffer circuit control method comprising: a step of comparing the difference between an input voltage level and an output voltage level of an operational amplifier in a slew rate compensation circuit with a reference voltage level; a step of generating a compensation current based on the difference between the input voltage level and the output voltage level in the slew rate compensation circuit and providing the compensation current to the operational amplifier when the difference between the input voltage level and the output voltage level is greater than the reference voltage level; and a step of turning off a boosting transistor of the slew rate compensation circuit by a blocking current provided by an offset blocking circuit to the slew rate compensation circuit when the difference between the input voltage level and the output voltage level is smaller than the reference voltage level, wherein the step of turning off the boosting transistor of the slew rate compensation circuit includes the step of the offset blocking circuit generating the blocking current based on a turn-on voltage provided from the operational amplifier or a bias voltage input from an external source. Claim 18 A buffer circuit control method according to claim 17, wherein the step of turning off the boosting transistor of the slew rate compensation circuit includes the step of inputting the blocking current to the gate of the boosting transistor. Claim 19 A buffer circuit control method according to claim 17, characterized in that the reference voltage level is the same level as the voltage level of the threshold voltage of the transistor constituting the slew rate compensation circuit. Claim 20 A buffer circuit control method according to claim 17, further comprising: a step of generating a push compensation current that supplies current to the operational amplifier among the compensation currents when the difference between the input voltage level and the output voltage level is greater than the reference voltage level and the input voltage is rising; and a step of generating a pull compensation current that syncs the current of the operational amplifier among the compensation currents when the difference between the input voltage level and the output voltage level is greater than the reference voltage level and the input voltage is falling.

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