Handling operation system (OS) in a system for predicting and managing faulty memories based on page faults

Abstract

Operating system (OS) handling of a system that predicts memory failures based on page failures and manages predicted memory failures is initiated. The system includes a processor and memory coupled to the processor that provides system physical addresses corresponding to virtual addresses used by a virtual machine. The OS stores instructions that, at runtime, cause the system to recognize bad pages that cause page failures during application execution, identify potential bad address types appearing in the system physical addresses of the bad pages' memory, and prevent bad physical addresses associated with the specific potential bad address types from being used in address translation.

Description

Technology Field

[0001] The present invention relates to data processing systems, and more specifically, to a system for predicting memory failures based on page failures and managing predicted memory failures, and a method for handling the operating system thereof. Background Technology

[0002] Data processing systems, such as data centers, are hosted by many enterprises and their computer systems. Data centers are used to distribute hosted applications and / or transactions and consist of networked computer resources, often referred to as the cloud, such as servers, disks, and virtual machines. In this configuration, enterprises are clients of the data center. Data centers provide clients with many benefits, including reduced costs, easy scalability, and reduced management burden.

[0003] Data centers face an increasing demand for high-capacity memory to ensure stable and rapid real-time processing of large volumes of data. However, the performance quality of memory can change over time. For example, page failures caused by failed memory may occur while applications and / or transactions are allocated and using memory. If such page failures occur frequently, they can disrupt the normal flow of instruction execution, leading to availability constraints such as the aborting and restarting of initiated tasks. Accordingly, if it is possible to identify failed memory based on page failures and if such a facility is available, it would be possible to predict memory failures caused by these failed memories. Furthermore, proactively managing anticipated memory failures would be beneficial for maintaining data center availability. The problem to be solved

[0004] The object of the present invention is to a system for predicting memory failures based on page failures and managing predicted memory failures, and a method for handling the operating system thereof. means of solving the problem

[0005] A method of operation of a system executing an application and an operating system (OS) according to embodiments of the present invention comprises: a step in which, when the system is operating, the OS provides machine virtualization to execute an application in cooperation with a processor and memory; a step in which the OS in the virtual machine performs address translation between virtual addresses processed by the application and system physical addresses for memory; a step in which the OS recognizes bad pages that cause page failures during application execution; a step in which the OS observes row address bits and column address bits identified in the system physical addresses of the bad pages, predicts potential bad address attributes appearing in the same bad address bits, and specifies a bad type for system physical addresses having potential bad address attributes; and a step in which the OS does not provide bad system physical addresses associated with a specific bad type when performing address translation.

[0006] A computer-readable recording medium according to embodiments of the present invention stores instructions that, at execution, cause a system to execute an application in cooperation with the system’s processor and memory, identify bad pages that cause page faults during application execution, identify a potential bad address type appearing in the system physical addresses of memory of the bad pages, prevent bad physical addresses associated with the identified potential bad address type from being used in address translation, and prevent system execution from being interrupted when identifying the identified potential bad address type.

[0007] A system according to embodiments of the present invention comprises a processor for performing virtual machines, a memory coupled to the processor and providing system physical addresses corresponding to virtual addresses used in the virtual machine, and a storage medium comprising instructions that cause the system to cooperate with the processor to perform address translation between virtual addresses and system physical addresses, to identify bad pages that cause page faults during application execution, to identify potential bad address types appearing in the system physical addresses of the bad pages, and to prevent bad physical addresses associated with the specific potential bad address type from being used in address translation. Effects of the invention

[0008] According to embodiments of the present invention, bad physical addresses associated with bad pages that cause page failures during system operation are identified, and bad physical addresses are not provided during address translation, thereby maintaining system availability so that system operation continues without interruption. Additionally, by rescuing bad physical addresses during system booting, memory resources can be utilized with maximum efficiency. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram conceptually illustrating a system according to embodiments of the present invention. FIG. 2 is a diagram illustrating an address mapping that can be referenced to perform address translation for the memory of FIG. 1. Figure 3 is a diagram illustrating the address mapping table of Figure 2 as an example. FIG. 4 is a diagram illustrating an exemplary page table entry (PTE) of the address mapping table of FIG. 3. Figure 5 is a diagram illustrating the row-like failure attributes shown in the address mapping table of Figure 3. Figure 6 is a diagram illustrating the columnar fault attributes shown in the address mapping table of Figure 3. Figure 7 is a diagram illustrating the blocking defect attributes shown in the address mapping table of Figure 3. FIG. 8 is a flowchart illustrating a runtime OS handling method of a system according to one embodiment of the present invention. Figure 9 is a conceptual diagram illustrating the repair operation performed during the system boot of Figure 1. FIGS. 10 to 12 are drawings illustrating a repair operation performed in the memory device of FIG. 1. FIG. 13 is a flowchart illustrating a booting method of a system according to one embodiment of the present invention. Specific details for implementing the invention

[0010] FIG. 1 is a block diagram conceptually illustrating an exemplary system that can be used to predict memory failures based on page failures and to manage predicted memory failures according to embodiments of the present invention.

[0011] Referring to FIG. 1, the system (100) may be a data center composed of dozens of host machines or servers running hundreds of virtual machines (VMs). The system (100) is illustrated with a number of hardware configurations described more specifically below with reference to FIG. 1, but is not limited thereto and other configurations are possible. The system (100) may include a processor (110), memory (120), and BIOS (Basic Input / Output System, 130) memory.

[0012] The processor (110) can be communicatively connected to the memory (120) through the memory interface (140). The processor (110) can be connected to the BIOS memory (130) through various interfaces (150), such as a Serial Peripheral Interface (SPI) or a Low Pin Count (LPC) bus. The memory (120) and the BIOS memory (130) connected to the processor (110) may be referred to as system memory.

[0013] Some examples may be described using the expressions "connected" and / or "coupled" along with their derivatives. These terms are not necessarily intended to be synonyms for one another. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. Additionally, the terms "connected" and / or "coupled" may also imply that two or more elements are not in direct contact with each other but still cooperate or interact with one another.

[0014] According to some embodiments, the system (100) may be, for example, a computing device, a virtual machine, or its virtual computing device, such as a laptop computer, a desktop computer, a server computer, a workstation, a portable communication terminal, a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a smartphone, a tablet PC, and other suitable computers. Or the system (100) may be some of the components included in a computing system, such as a graphics card.

[0015] The processor (110) is a functional block that performs general computer operations within the system (100) and may be any type of processor, such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a network processor, an Application Processor (AP), or other device for executing code.

[0016] A processor (110) may be configured to execute instructions or pieces of software, firmware, or combinations thereof that are executable on one or more machines. The processor (110) may include any number of processor cores. For example, the processor (110) may include a single core or a multi-core such as a dual core, quad core, or hexa-core. Although FIG. 1 illustrates a system (100) including one processor (110), according to the embodiment, the system (100) may include a plurality of processors.

[0017] The processor (110) can execute software in a virtualized environment. Accordingly, virtual machines (VMs) in the system (100) may include applications (APPs) and operating systems (OS). Since virtual machines (VMs) can change dynamically during their use, which is initiated and stopped by a user, the number of virtual machines (VMs) that can be executed on the processor (110) may vary. Software entities such as OSs may potentially regard the processor (110) as a logical processor or processing element capable of simultaneously executing virtual machines (VMs). For example, n (where n is a natural number) OSs may regard the processor (110) as n logical processors or processing elements.

[0018] Each application (APP) in the virtual machines (VMs) uses a virtual address space, and accordingly uses a virtual address (VA, i.e., an address that can be used by software). The OS in each virtual machine (VM) can control which application (APP) accesses a specific memory (120) at a specific time, and can control the addresses accessed by the application (APP) to at least some extent. The OS in the virtual machine (VM) can perform and manage mapping between virtual addresses (VA) and physical addresses (PA) in the virtual machine (VM). The physical address generated by the OS is the system physical address (PA, i.e., an address that can be used by the memory controller (112)) of the physical address space spanning the memory (120) of the actual system (100). The OS can perform address translation (e.g., address mapping) between the virtual address (VA) and the system physical address (PA).

[0019] FIG. 1 illustrates two virtual machines (160, 161) to briefly illustrate machine virtualization in a system (100), and each of the virtual machines (160, 161) includes one or more application(s) (APP) and an OS. According to an embodiment, multiple virtual machines (VMs) may be executed, and the processor (110) may execute and implement many applications (APPs) and / or transactions in terms of time and memory footprint through hardware acceleration using hardware and a combination of software. Hereinafter, for convenience of explanation, the system (100) will be described with respect to an application (170) and an OS (180) that access memory (120) based on a first virtual machine (160).

[0020] The BIOS memory (130) can store BIOS code for booting the system (100). The BIOS memory (130) can be implemented as a non-volatile memory device. The non-volatile memory device can be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, RRAM (Resistive RAM), MRAM (Magnetic RAM), PRAM (Phase change RAM), FRAM (Ferroelectric RAM), NFGM (Nano Floating Gate Memory), PoRAM (Polymer RAM), or similar memory.

[0021] The BIOS code is a Power On Self Test (POST) code and / or part of the POST code for detecting hardware of the system (100), such as the system (100) board, memory (120), disk drive, input / output (I / O) devices, and verifying whether they are operating normally. The BIOS code may include various algorithms configured to enable the processor (110) to interoperate normally with the memory (120).

[0022] For the sake of brevity of the drawing, the memory interface (140) is depicted as being connected between the processor (110) and the memory (120) by a single signal line, but in reality, it may be connected through multiple signal lines. The memory interface (140) includes connectors for connecting the memory controller (112) and the memory (120), and the connectors may be implemented as pins, balls, signal lines, or other hardware components. For example, clock, command, address, data, etc., may be transmitted and received between the memory controller (112) and the memory (120) through the memory interface (140). The memory interface (140) may be implemented as a single channel including multiple signal lines, or as multiple channels. Additionally, one or more memories (120) may be connected to each channel.

[0023] The processor (110) may include a memory controller (112) that controls the transmission and reception of data to and from memory (120). The memory controller (112) may access memory (120) in response to a memory request from the processor (110), and a system physical address may be provided for memory access. The memory controller (112) may include a Memory Physical Layer Interface, i.e., a memory PHY, for memory interfacing, such as selecting rows and columns corresponding to memory cells, writing data to memory cells, or reading written data. The actual physical implementation of the memory controller (112) that performs the functions exemplified above may take many forms. For example, the memory controller (112) may be implemented by one or more hardware components (e.g., analog circuits, logic circuits), software and / or firmware program code. A memory controller (112) can be commonly integrated into the processor(s) (110) to ensure consistent access to memory (120) by the processor(s) (110).

[0024] The memory (120) can record or load data used for the operation of the system (100). The memory (120) can store or read data that has been processed or will be processed by the processor (110). The memory (120) may include volatile memory such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), etc., and / or non-volatile memory such as flash memory, RRAM, MRAM, PRAM, FRAM, etc.

[0025] The memory (120) may include memory cells for storing data. Memory cells may be identified and indicated based on a value called an address. Write data may be written to the memory cell indicated by the address, and read data may be loaded from the memory cell indicated by the address. In the present disclosure, one memory region within the memory (120) may include a memory cell array in which a plurality of memory cells, each indicated by a plurality of addresses, are arranged.

[0026] The memory (120) can be configured to repair a failed cell into a redundancy cell when a memory cell in the memory area is defective. The memory (120) is capable of Post Package Repair (PPR) to repair additional failed cells that occur due to continuous use into redundancy cells.

[0027] The processor (110) may provide an address to the memory (120) to exchange data items that are read from the memory (120) and stored in the memory (120) during the execution of the application (170). The memory (120) may store or read data based on a request (e.g., a command and an address) received from the processor (110).

[0028] Meanwhile, the address processed by the application (170) may be called a virtual address (VA), and the address for the memory (120) may be called a system physical address (PA). The OS (180) can perform address conversion between the virtual address (VA) processed by the application (APP) and the system physical address (PA) for the memory (120).

[0029] FIG. 2 is a diagram illustrating an address mapping that can be referenced to perform address translation for the memory (120) of FIG. 1.

[0030] Referring to FIGS. 1 and 2, memory (120) has a range of system physical addresses (PA) from address zero (0) up to above it. An application (170) may have a range of virtual addresses (VA) starting from the top of memory (120). Each address Pa of the virtual address (VA) has an entry mapped to an address (or address space) Pg of the system physical address (PA) of memory (120). The OS (180) may allocate a page requested for memory access by the application (170) to a page of memory (120). At this time, a reference specified from virtual address Pa to the corresponding system physical address Pg may be stored as a Page Table Entry (PTE) in an address mapping table (200). A page may be a unit of address translation. That is, each address in a virtual page may be translated into a corresponding physical page. Pages can have various sizes ranging from 4 kilobytes to up to megabytes or even gigabytes.

[0031] It should be noted that the address locations and sizes shown in FIG. 2 are provided as examples and are not necessarily actual memory addresses. Additionally, the exemplary memory shown in FIG. 2 does not imply or represent any limitation to the present disclosure.

[0032] FIG. 3 is a diagram showing an exemplary address mapping table (200) of FIG. 2.

[0033] Referring to FIGS. 2 and 3, the OS (180) can manage an address mapping table (200). Page table entries (PTEs) of the address mapping table (200) may contain information regarding the mapping relationship between virtual addresses (VAs) and system physical addresses (PAs). For example, the address mapping table (200) may be implemented as a type of look-up table. The OS (180) can convert virtual addresses (VAs) into system physical addresses (PAs) by referring to the page table entries (PTEs) of the address mapping table (200).

[0034] For example, the Va1 virtual address may correspond to the Pa1 system physical address. When the OS (180) receives the Va1 virtual address from the application (170), the OS (180) may map the Va1 virtual address to the Pa1 system physical address. The OS (180) may process the request received from the application (170) along with the Va1 virtual address in association with the memory cell indicated by the Pa1 system physical address.

[0035] Similarly, according to the corresponding information of the address mapping table (200), the OS (180) can map the virtual addresses Va2 and Va3 to the system physical addresses Pa2 and Pa3, map the virtual addresses Vb1, Vb2, and Vb3 to the system physical addresses Pb1, Pb2, and Pb3, and map the virtual addresses Vc1, Vc2, Vc3, Vc4, and Vc5 to the system physical addresses Pc1, Pc2, Pc3, Pc4, and Pc5. The OS (180) can process a request from an application (170) in association with a memory cell indicated by the system physical address (Pa2, Pa3, Pb1, Pb2, Pb3, Pc1, Pc2, Pc3, Pc4, Pc5) corresponding to the virtual address (Va2, Va3, Vb1, Vb2, Vb3, Vc1, Vc2, Vc3).

[0036] FIG. 4 is a diagram illustrating an exemplary page table entry (PTE) of the address mapping table (200) of FIG. 3.

[0037] Referring to FIG. 4, the page table entry (PTE) of the address mapping table (200) may be a table of conversion data that can be used to convert a virtual address (VA) to a system physical address (PA). The conversion table may store conversion data in any manner. For example, depending on the conversion level, various subsets of virtual address (VA) bits or system physical address (PA) may be used to index the levels of the table. And, each level may be the end of the conversion (i.e., storing the actual page number for the conversion) or may point to another table in a hierarchical manner (indexed by another set of address bits).

[0038] A page table entry (PTE) may contain pointers to other page tables in a hierarchical manner. A page table entry (PTE) may indicate the level in the page table hierarchy where translation must be initiated for requests mapped to the entry, for example, page map level 2, 3, or 4. Accordingly, a page table entry (PTE) of a page map level 2, 3, or 4 table may contain any number of bit entries.

[0039] The page table entry (PTE) illustrated in FIG. 4 is a 1-level translation table at the end of the translation, and is provided with fields relating to address translation. It should be noted that in other embodiments, single-bit fields and / or multiple-bit fields may be provided for other purposes (e.g., specifying the translation level, depth of the tables, indicating whether the translation is invalid or valid, etc.). In this embodiment, the page table entry (PTE) relates to the translation of virtual page address bits into actual system physical page address bits, and is, for example, a 64-bit entry.

[0040] A page table entry (PTE) may include a virtual address (VA) field and a system physical address (PA) field. The virtual address (VA) field is configured to allow for a large virtual address space to be used by the application (170), and the system physical address (PA) field indicates the address of available physical memory (120) corresponding to the virtual address (VA). For example, the system physical address (PA) field may be composed of PTE[11:0] bits, and the virtual address (VA) field may be composed of PTE[63:12] bits. The system physical address (PA) field may be composed of row address (R[5:0]) bits and column address (C[5:0]) bits.

[0041] Figure 5 is a diagram illustrating the row-like failure attributes shown in the address mapping table of Figure 3.

[0042] Referring to FIG. 5, depending on the virtual addresses (Va1, Va2, Va3) where an application (170) running on the processor (110) is running, the OS (180) may provide system physical addresses (Pa1, Pa2, Pa3) corresponding to the virtual addresses (Va1, Va2, Va3) for accessing memory (120). For example, the system physical address Pa1 corresponding to the virtual address Va1 may be provided with a row address (R[5:0]) 011000 bits and a column address (C[5:0]) 000001 bits. The processor (110) may execute the application (170) by accessing the memory cell indicated by the row address (R[5:0]) 011000 bits and the column address (C[5:0]) 000001 bits of the system physical address Pa1 through the memory controller (112).

[0043] Similarly, the Pa2 system physical address corresponding to the Va2 virtual address is provided with 011000 bits for the row address (R[5:0]) and 000010 bits for the column address (C[5:0]), and the Pa3 system physical address corresponding to the Va3 virtual address can be provided with 011000 bits for the row address (R[5:0]) and 000100 bits for the column address (C[5:0]). The processor (110) can execute an application (170) by accessing, through the memory controller (112), memory cells indicated by the 011000 bits of the row address (R[5:0]) of the Pa2 system physical address and the 000010 bits of the column address (C[5:0]) of the Pa3 system physical address and the 011000 bits of the column address (C[5:0]) of the Pa3 system physical address.

[0044] However, execution associated with the Pa2 system physical address of memory (120) may not operate correctly. Additionally, execution associated with the Pa3 system physical address may not operate correctly. In other words, a page fault may occur. Among the execution paths of multiple applications (170), an error may occur in, for example, the execution path for memory (120). Specifically, memory errors may occur in the Pa2 and Pa3 system physical addresses. One of the main causes of these memory errors is when the memory cells addressed in the Pa2 and Pa3 system physical addresses are defective, that is, when a hardware exception condition is detected.

[0045] Generally, if these exception events occur frequently, the pending system (100) may be interrupted and system (100) resumption operations may be attempted. This solution does not realize acceleration of the system (100). The OS (180) may perform control to handle exception events without needing to interrupt the system (100). The OS (180) may combine hardware support in the processor (110) with OS code so that the operation of the system (100) may continue even when exception events occur. As described in more detail below, a mechanism of the OS (180) for this function may be provided.

[0046] The OS (180) can be aware of bad pages in the Pa2 and Pa3 system physical addresses. The OS (180) observes the row address (R[5:0]) bits and column address (C[5:0]) bits identified in the Pa2 and Pa3 system physical addresses and can see that the row address (R[5:0]) 011000 bits of the Pa2 and Pa3 system physical addresses are identical. Since the memory cells addressed in the Pa2 and Pa3 system physical addresses have the same row address, the OS (180) can expect that there is a high probability that there is a defect in the memory cells accessed at this row address. Accordingly, the OS (180) can predict or consider the memory cells accessed at the row address (R[5:0]) 011000 bits within the memory area of ​​the memory (120) as potential row defects. Below, the low address (R[5:0]) bits 011000 may be referred to as bad low address (FRA).

[0047] Memory cells accessed at bits 011000 of the low address (R[5:0]) of the Pa1 system physical address of memory (120) are not defective, but the OS (180) may be given the privilege of identifying memory cells accessed at bits 011000 of the low address (R[5:0]) as defective low addresses. When the OS (180) converts the virtual address (VA) where an application (170) running on the processor (110) is running to the corresponding system physical address (PA), it may not provide defective low addresses (FRA) to the system physical address (PA) in order to prevent defective low memory cells from being selected. In addition, the OS (180) may store defective low addresses (FRA) in the BIOS memory (130, FIG. 1).

[0048] Figure 6 is a diagram illustrating the columnar fault attributes shown in the address mapping table of Figure 3.

[0049] Referring to FIG. 6, depending on the virtual addresses (Vb1, Vb2, Vb3) where an application (170) running on the processor (110) is running, the OS (180) may provide system physical addresses (Pb1, Pb2, Pb3) corresponding to the virtual addresses (Vb1, Vb2, Vb3) for accessing memory (120). For example, the system physical address Pb1 corresponding to the virtual address Vb1 may be provided as a row address (R[5:0]) of 100000 bits and a column address (C[5:0]) of 000011 bits. The processor (110) can execute an application (170) by accessing a memory cell indicated by the 100000 bits of the row address (R[5:0]) and the 000011 bits of the column address (C[5:0]) of the Pb1 system physical address through the memory controller (112).

[0050] Similarly, the Pb2 system physical address corresponding to the Vb2 virtual address is provided with 010000 bits for the row address (R[5:0]) and 000011 bits for the column address (C[5:0]), and the Pb3 system physical address corresponding to the Vb3 virtual address can be provided with 001000 bits for the row address (R[5:0]) and 000011 bits for the column address (C[5:0]). The processor (110) can execute an application (170) by accessing, through the memory controller (112), memory cells indicated by the 010000 bits of the row address (R[5:0]) of the Pb2 system physical address and the 000011 bits of the column address (C[5:0]) of the Pb3 system physical address and the 001000 bits of the column address (C[5:0]) of the Pb3 system physical address.

[0051] However, the execution associated with the Pb2 system physical address and the execution associated with the Pb3 system physical address of memory (120) may not operate correctly. During the execution of the application (170), memory errors may occur at the Pb2 and Pb3 system physical addresses. The OS (180) may recognize bad pages at the Pb2 and Pb3 system physical addresses. The OS (180) may observe the row address (R[5:0]) bits and column address (C[5:0]) bits identified at the Pb2 and Pb3 system physical addresses of the bad pages. The OS (180) may see that the column address (C[5:0]) bits 000011 of the Pb2 and Pb3 system physical addresses are identical. Since the memory cells addressed at the Pb2 and Pb3 system physical addresses have the same column address, the OS (180) may expect that there is a high probability that the memory cells accessed at this column address are defective. Accordingly, the OS (180) can predict that memory cells accessed at bits 000011 of column address (C[5:0]) within the memory area of ​​memory (120) are potential column defects. Hereinafter, bits 000011 of column address (C[5:0]) may be referred to as defective column address (FCA).

[0052] Memory cells accessed at bits 000011 of the column address (C[5:0]) of the Pb1 system physical address of memory (120) are not defective, but the OS (180) may be granted the privilege of identifying memory cells accessed at bits 000011 of the column address (C[5:0]) as column-defective. When the OS (180) provides a system physical address (PA) corresponding to a virtual address (VA) where an application (170) running on the processor (110) is running, it may not provide a defective column address (FCA) to the system physical address (PA) in order to prevent the memory cells that are column-defective from being selected. In addition, the OS (180) may store the defective column address (FCA) in the BIOS memory (130, FIG. 1).

[0053] As illustrated in FIGS. 5 and 6, the OS (180) describes a privilege to handle row-related or column-related failures of the OS (180) by referring to two bad pages, but such privilege may be granted when the number of bad pages exceeds a threshold value. In the present embodiments, the threshold value may be set to n (where n is a natural number greater than or equal to 2). According to other embodiments, the threshold value may be set differently and may also be changed.

[0054] Figure 7 is a diagram illustrating the blocking defect attributes shown in the address mapping table of Figure 3.

[0055] Referring to FIG. 7, depending on the virtual addresses (Vc, Vc2, Vc3, Vc4, Vc5) on which an application (170) running on the processor (110) is running, the OS (180) may provide system physical addresses (Pc1, Pc2, Pc3, Pc4, Pc5) corresponding to the virtual addresses (Vc1, Vc2, Vc3, Vc4, Vc5) for accessing memory (120). For example, the system physical address Pc1 corresponding to the virtual address Vc1 may be provided with 110001 bits for the row address (R[5:0]) and 111000 bits for the column address (C[5:0]). The Pc2 system physical address corresponding to the Vc2 virtual address is provided with 110010 bits for the row address (R[5:0]) and 111010 bits for the column address (C[5:0]), the Pc3 system physical address corresponding to the Vc3 virtual address is provided with 110100 bits for the row address (R[5:0]) and 110000 bits for the column address (C[5:0]), the Pc4 system physical address corresponding to the Vc4 virtual address is provided with 111000 bits for the row address (R[5:0]) and 110010 bits for the column address (C[5:0]), and the Pc5 system physical address corresponding to the Vc5 virtual address is provided with 111111 bits for the row address (R[5:0]) and 110100 bits for the column address (C[5:0]). The processor (110) can execute an application (170) by accessing memory cells indicated by system physical addresses Pc1 to Pc5 through a memory controller (112).

[0056] However, execution associated with the system physical addresses Pc1 to Pc5 of memory (120) may not operate correctly. During the execution of the application (170), memory errors may occur in the system physical addresses Pc1 to Pc5. The OS (180) may recognize bad pages in the system physical addresses Pc1 to Pc5. The OS (180) may observe the row address (R[5:0]) bits and column address (C[5:0]) bits identified in the system physical addresses Pc1 to Pc5 of the bad pages. The OS (180) may see that the upper 2 bits of the row address (R[5:0]) of the system physical addresses Pc1 to Pc5, namely R[5:4] 11 bits, are identical, and the upper 2 bits of the column address (C[5:0]), namely C[5:4] 11 bits, are identical.

[0057] Generally, the memory (120) may be configured to sequentially decode row address bits using a row decoder to access memory cells, generate a decoded row address signal, and activate a word line corresponding to the decoded row address signal. Here, the decoded row address signal lines may be arranged in a row direction from the bottom or top of the memory area, and the upper bits of the row address may act as a signal addressing a specific area on the upper or lower side relative to the center of the memory area. Similarly, the memory (120) may be configured to sequentially decode column address bits using a column decoder to generate a decoded column address signal, and activate bit lines corresponding to the decoded column address signal. Here, the decoded column address signal lines may be arranged in a column direction from the left or right of the memory area, and the upper bits of the column address may act as a signal addressing a specific area on the left or right side relative to the center of the memory area.

[0058] The OS (180) can anticipate that there may be defects in memory cells accessed to the same upper row address bits and upper column address bits because memory cells addressed to system physical addresses Pc1 to Pc5 have the same upper row address bits and upper column address bits. Accordingly, the OS (180) can anticipate that memory cells accessed to the upper row address R[5:4] 11 bits and upper column address C[5:4] 11 bits within the memory region of memory (120) are potential block defects. Hereinafter, the upper row address R[5:4] 11 bits and upper column address C[5:4] 11 bits may be referred to as bad block addresses (FBA).

[0059] The OS (180) may be granted the privilege of identifying memory cells accessed in the upper row address R[5:4] 11 bits and the upper column address C[5:4] 11 bits as block-like faults. When the OS (180) provides a system physical address (PA) corresponding to a virtual address (VA) where an application (170) running on the processor (110) is running, the OS (180) may not provide a bad block address (FBA) in the system physical address (PA) in order to prevent the block-like faulty memory cells from being selected. In addition, the OS (180) may store the bad block address (FBA) in the BIOS memory (130, FIG. 1).

[0060] As illustrated in FIG. 7, the OS (180) describes a privilege to handle blocking failures of the OS (180) by referring to five bad pages, but such a privilege may be granted when the number of bad pages exceeds a threshold value. In this embodiment, the threshold value may be set to n (where n is a natural number greater than or equal to 5). According to other embodiments, the threshold value may be set to a different value and may also be changed.

[0061] FIG. 8 is a flowchart illustrating a runtime OS handling method of a system (100) according to one embodiment of the present invention.

[0062] Referring to FIGS. 1, 2 and 8, when the system (100) is operating, the OS (180) may be executed by providing machine virtualization in cooperation with the processor (110) to execute the application (170) (S810). The OS (180) in the virtual machine (VM) may perform address translation between virtual addresses (VA) processed by the application (170) and system physical addresses (PA) for memory (120). During the execution of the application (170), the OS (180) may detect bad pages of the system physical addresses (PA) (S812). For example, a page failure may occur.

[0063] The OS (180) counts the bad pages and can determine whether the number of bad pages exceeds a reference value (S813). If the result of the determination is that it exceeds the reference value, the OS (180) can observe the row address (RA) bits and column address (CA) bits identified in the system physical addresses (PA) of the bad pages (S814). If the result of the determination is that it does not exceed the reference value, the OS (180) moves to step S812.

[0064] The OS (180) can foresee potential bad address attributes appearing in the same bad address bits in the system physical addresses (PA) of bad pages (S815). The OS (180) can identify system physical addresses (PA) having potential bad address attributes as row bad, column bad, or block bad. By this identification, when the OS (180) performs address translation between virtual addresses (VA) and system physical addresses (PA) for memory (120), it may not provide bad system physical addresses associated with a specific type of bad (e.g., row bad, column bad, or block bad) (S816). And, the OS (180) may store the bad system physical addresses in the BIOS memory (130).

[0065] During the handling of page failures of the OS (180), the system (100) operation proceeds without interruption and continues, moving to step S810. Accordingly, the availability of the system (100) can be maintained.

[0066] FIG. 9 is a conceptual diagram for explaining the repair operation performed when booting the system (100) of FIG. 1.

[0067] Referring to FIG. 9, the BIOS memory (130) can store BIOS code for booting the system (100). Additionally, the BIOS memory (130) can store bad addresses, namely bad row addresses (FRA), bad column addresses (FCA), and / or bad block addresses (FBA), identified based on bad memory management privileges in the OS (180). The bad row addresses (FRA), bad column addresses (FCA), and / or bad block addresses (FBA) can be stored in a non-volatile memory unit (930). The non-volatile memory unit (930) is part of the non-volatile memory device that constitutes the BIOS memory (130).

[0068] The system (100) can execute boot operations in which a portion of the BIOS code of the BIOS memory (130) is executed by the processor (110) upon power-up. Among the boot operations in which the BIOS code is executed by the processor (110), memory training for the memory (120) may be included. Memory training may be performed by the memory controller (112) to determine optimal parameters for the core parameters and / or peripheral circuit parameters of the memory (120). Hereinafter, for convenience of explanation, the memory (120) is referred to as DRAM (120). DRAM 120 includes SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), GDDR SDRAM (Graphics Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, Wide I / O DRAM, HBM (High Bandwidth Memory), and HMC (Hybrid Memory). Cube).

[0069] The memory controller (112) can initialize the DRAM (120) according to an algorithm set in the Register Control Word (RCW) when the system (100) boots, and perform memory training on the DRAM (120). Memory training can be performed using a memory PHY provided for signals, frequencies, timing, driving, detailed operation parameters, and functionality required for efficient communication between the memory controller (112) and the DRAM (120). After memory training of the DRAM (120), the memory controller (112) can provide the bad row address (FRA), bad column address (FCA), and / or bad block address (FBA) stored in the non-volatile memory unit (930) of the BIOS memory (130) to the DRAM (120).

[0070] The DRAM (120) can repair defective cells exhibiting defective characteristics in a memory cell array. The memory cell array may include multiple word lines, multiple bit lines, and multiple memory cells formed at the intersection of the word lines and bit lines. The DRAM (120) may include a repair control circuit (920) configured to repair defective cells into redundancy cells. The repair control circuit (920) can perform repairs to rescue defective cells detected through testing after the semiconductor manufacturing process of the DRAM (120). Additionally, the repair control circuit (920) can perform post-package repair (PPR) to repair defective cells that occur during the continuous use of the DRAM (120) into redundancy cells.

[0071] The repair control circuit (920) can perform PPR to replace each of the bad row address (FRA), bad column address (FCA), and / or bad block address (FBA) provided in the BIOS memory (130) with the redundancy row address (RRA), redundancy column address (RCA), and / or redundancy block address (RBA). During the PPR, the repair control circuit (920) can store information about the source addresses that needed to be repaired (S_ADDR, i.e., bad row address (FRA), bad column address (FCA), and / or bad block address (FBA)) and the replaced destination addresses (D_ADDR, i.e., redundancy row address (RRA), redundancy column address (RCA), and / or redundancy block address (RBA)) in the address storage table (921).

[0072] The address storage table (921) may, for example, be composed of an anti-fuse array or a Content Addressable Memory (CAM). An anti-fuse is a resistive fuse element having electrical characteristics opposite to those of a fuse element, having a high resistance value when unprogrammed, while having a low resistance value when programmed. A CAM is a special memory structure in which an applied address is compared simultaneously with source addresses (S_ADDR) stored in each CAM entry, and the output of the CAM indicates, if any, that the source address (S_ADDR) matches the destination address (D_ADDR).

[0073] The repair control circuit (920) can provide the address storage table (921) to the memory controller (112). The memory controller (112) can store the address storage table (921) information as memory management information (910) for consistent processor(s) (110) access to the DRAM (120). The address storage table (921) information can be shared with the processor(s) (110). When the processor(s) (110) perform memory allocation operations during the execution of applications (170), they can perform memory allocation operations based on the address storage table (921) information. Accordingly, the processor(s) (110) can use the memory management information (910) to manage the address space of the OS (180) within the DRAM (120) and perform a function commonly known as a memory manager, which evenly distributes memory areas to other virtual machines (VMs) using the DRAM (120).

[0074] FIGS. 10 to 12 are drawings illustrating a repair operation performed in the memory (120) of FIG. 1.

[0075] In FIG. 10, it is assumed that a bad row address (FRA) is repaired to a redundancy row address (RRA). A memory cell array (1000a) may include a normal cell array (NMCA) and a redundancy cell array (RMCA). The normal cell array (NMCA) may include memory cells connected to word lines and bit lines, and the redundancy cell array (RMCA) may include memory cells connected to redundancy word lines and redundancy bit lines. A repair control circuit (920) may include a row repair unit (922) that determines a redundancy row address (RRA) so that redundancy resources for repairing the bad row address (FRA) do not overlap with each other.

[0076] The row repair unit (922) can perform a repair operation so that the redundancy row address (RRA) is selected instead of the bad row address (FRA). When the access row address applied to memory specifies the bad row address (FRA) of the normal cell array (NMCA), the redundancy cells corresponding to the redundancy row address (RRA) of the redundancy cell array (RMCA) are selected. The row repair unit (922) disables the word line corresponding to the bad row address (FRA) and instead enables the redundancy word line corresponding to the redundancy row address (RRA). Accordingly, the redundancy cells corresponding to the redundancy row address (RRA) are selected instead of the memory cells corresponding to the bad row address (FRA).

[0077] In FIG. 11, it is assumed that a bad column address (FCA) is repaired to a redundancy column address (RCA). A memory cell array (1000b) may include a normal cell array (NMCA) and a redundancy cell array (RMCA). The normal cell array (NMCA) may include memory cells connected to word lines and bit lines, and the redundancy cell array (RMCA) may include memory cells connected to word lines and redundancy bit lines. A repair control circuit (920) may include a column repair unit (924) that determines the redundancy column address (RCA) so that redundancy resources for repairing the bad column address (FCA) do not overlap with each other.

[0078] The column repair unit (924) can perform a repair operation so that the redundancy column address (RCA) is selected instead of the faulty column address (FCA). When the access column address applied to the memory (120) specifies the faulty column address (FCA) of the normal cell array (NMCA), redundancy cells corresponding to the redundancy column address (RCA) of the redundancy cell array (RMCA) are selected. The column repair unit (924) prevents the bit line corresponding to the faulty column address (FCA) from being selected, and instead selects the redundancy bit line corresponding to the redundancy column address (RCA). Accordingly, redundancy cells corresponding to the redundancy column address (RCA) are selected instead of the memory cells corresponding to the faulty column address (FCA).

[0079] In FIG. 12, it is assumed that a bad block address (FBA) is repaired to a redundancy column address (RCA). A memory cell array (1000c) may include a normal cell array (NMCA) and a redundancy cell array (RMCA). The normal cell array (NMCA) may include memory cells connected to word lines and bit lines, and the redundancy cell array (RMCA) may include memory cells connected to redundancy word lines and redundancy bit lines. A repair control circuit (920) may include a block repair unit (926) that determines a redundancy block address (RBA) so that redundancy resources for repairing the bad block address (FBA) do not overlap with each other.

[0080] The block repair unit (926) can perform a repair operation so that a redundancy block address (RBA) is selected instead of a bad block address (FBA). When the access row address and access column address applied to the memory (120) specify a bad block address (FBA) representing a certain area of ​​the normal cell array (NMCA), redundancy cell areas corresponding to the redundancy block address (RBA) of the redundancy cell array (RMCA) are selected. The block repair unit (926) prevents the memory cells of the memory area corresponding to the bad block address (FBA) from being selected, and instead selects the redundancy cells of the memory area corresponding to the redundancy block address (RBA).

[0081] FIG. 13 is a flowchart illustrating a booting method of a system according to one embodiment of the present invention.

[0082] Referring to FIGS. 1, FIG. 9 and FIG. 13, when the system (100) is powered up S (1310), the memory (120) may execute boot operations S (1312) by the processor (110) to execute a portion of the BIOS code of the BIOS memory (130). Among the boot operations that execute the BIOS code by the processor (110), memory training for the memory (120) may be performed S (1313). Memory training may be performed by the memory controller (112) to determine optimal parameters for the core parameters and / or peripheral circuit parameters of the memory (120). After memory training (S1313), bad system physical addresses (e.g., bad row address (FRA), bad column address (FCA) and / or bad block address (FBA)) stored in the BIOS memory may be transferred to the memory (120) (S1320).

[0083] Memory (120) can perform the operation of repairing bad system physical addresses (1314). As described above, memory (120) can repair a bad row address (FRA) to a redundancy row address (RRA) (Fig. 10). Memory (120) can repair a bad column address (FCA) to a redundancy column address (RCA) (Fig. 11). Memory (120) can repair a bad block address (FBA) to a redundancy block address (RBA) (Fig. 12). Memory (120) can repair bad system physical addresses to utilize memory (120) resources with maximum efficiency.

[0084] Embodiments of the present invention may be implemented in many different system types. Additionally, embodiments of the present invention may be implemented in code and may be stored in a machine-readable storage medium (an article comprising a machine-readable storage medium) that stores instructions that can be used to program a system to execute instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid-state drives (SSDs), compact disk read-only memory (CD-ROM), compact disk rewrite (CD-RW), and magneto-optical disks; random access memory (RAM) such as read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM); semiconductor devices such as eraseable and programmable read-only memory (EPROM), flash memory, and electrically eraseable and programmable read-only memory (EEPROM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0085] Although the present invention has been described in relation to a limited number of embodiments illustrated in the drawings, this is merely illustrative and those skilled in the art will recognize that various modifications and variations and equivalent other embodiments are possible therefrom. Accordingly, the appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

Claims

Claim 1 A method of operation of a system running a virtual machine that executes an application and an operating system (OS), comprising: a step of performing a first address conversion by the OS of the virtual machine into a plurality of first physical addresses accessing memory for a plurality of first virtual addresses processed by the application; a step of identifying a plurality of defective physical addresses among the plurality of first physical addresses by the OS of the virtual machine, wherein each of the plurality of defective physical addresses corresponds to a first physical address associated with a defective memory cell of the memory among the plurality of first physical addresses; a step of determining by the OS of the virtual machine whether the number of the plurality of defective physical addresses exceeds a reference value; a step of analyzing the row address and column address of each of the plurality of defective physical addresses by the OS of the virtual machine, and determining the defect type of the plurality of defective physical addresses based on the analysis of the row address and column address of each of the plurality of defective physical addresses, wherein the defect type includes a row defect, a column defect, or a block defect; A method of operation of a system comprising the step of performing a second address conversion of a plurality of second virtual addresses, excluding bad physical addresses, into a plurality of second physical addresses by the OS of the virtual machine, wherein the bad physical addresses correspond to the bad type of the plurality of bad physical addresses and include a bad row address of a bad row, a bad column address of a bad column, or a bad block address of a bad block. Claim 2 A method of operation of a system characterized in that, in claim 1, the operation of the system is not interrupted when specifying the type of defect of the plurality of defective physical addresses. Claim 3 delete Claim 4 A method of operation of a system according to claim 1, wherein the method of operation of the system further includes the step of storing the plurality of bad physical addresses in the BIOS memory of the system by the OS. Claim 5 In claim 4, the method of operation of the system further comprises the step of rebooting the system after storing the plurality of bad physical addresses, and the step of rebooting the system further comprises the step of reading the plurality of bad physical addresses from the BIOS memory and providing the plurality of bad physical addresses to the memory; and the step of performing an operation to repair the plurality of bad physical addresses in the memory. Claim 6 In claim 5, the step of performing the operation of repairing the plurality of defective physical addresses comprises the step of replacing the defective row address of the plurality of defective addresses with a redundancy row address. Claim 7 In claim 5, the step of performing the operation of repairing the plurality of defective physical addresses comprises the step of replacing the defective column address of the plurality of defective addresses with a redundancy column address. Claim 8 In claim 5, the step of performing the operation of repairing the plurality of defective physical addresses comprises the step of replacing the defective block address of the plurality of defective addresses with a redundancy block address. Claim 9 A computer-readable recording medium storing computer execution instructions for performing a method of operation of a system running a virtual machine that executes an application and an operating system (OS), wherein the method comprises: executing the application using the processor and memory of the system; performing a first address conversion by the OS of the virtual machine into a plurality of first physical addresses accessing the memory from a plurality of first virtual addresses assigned to the application; identifying a plurality of bad physical addresses among the plurality of first physical addresses converted from the plurality of first virtual addresses by the OS of the virtual machine while the application is executed; determining by the OS of the virtual machine whether the number of the plurality of bad physical addresses exceeds a reference value; and specifying the type of defect of the plurality of bad physical addresses by the OS of the virtual machine, wherein the type of defect includes row defect, column defect, or block defect; A recording medium comprising the step of performing a second address conversion to a plurality of second physical addresses by means of the OS of the virtual machine, wherein the plurality of second virtual addresses excluding bad physical addresses correspond to the bad type of the plurality of bad addresses, and the recording medium comprising a bad row address of a bad row, a bad column address of a bad column, or a bad block address of a bad block. Claim 10 A system operating in a virtual machine environment comprises: memory; and a processor operatively connected to said memory, wherein the processor executes an application in cooperation with said memory; performs a first address translation of a plurality of first virtual addresses processed by said application into a plurality of first physical addresses accessing said memory; identifies a plurality of defective physical addresses among said plurality of first physical addresses, wherein each of said plurality of defective addresses corresponds to a corresponding first physical address associated with a defective memory cell of said memory among said plurality of first physical addresses; determines whether the number of said plurality of defective physical addresses exceeds a reference value; and specifies the defect type of said plurality of defective addresses of said memory, wherein said defect type includes row defect, column defect, or block defect; A system comprising the step of performing a second address conversion to a plurality of second physical addresses from a plurality of second virtual addresses excluding bad physical addresses, and preventing the bad physical addresses from being used in the second address conversion, wherein the bad physical addresses correspond to the bad type of the plurality of bad addresses and include a bad row address of the bad row of the bad row, a bad column address of the bad column of the bad column, or a bad block address of the bad block of the bad block, and further configured such that the processor identifies the bad type, stores the bad address, and performs the second address conversion without rebooting the system.

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