Semiconductor device and method of fabricating semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided, comprising forming a semiconductor layer including a two-dimensional semiconductor material, forming a sacrificial layer on the semiconductor layer, forming a metal contact layer on the sacrificial layer, and removing the sacrificial layer, wherein after the sacrificial layer is removed, the semiconductor layer and the metal contact layer can be joined through Van Der Waals bonding.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device comprising a two-dimensional semiconductor material and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry advances, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality. To meet these requirements, the internal structures of semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more highly integrated.

[0003] As semiconductor devices become more highly integrated, the scale-down of transistors is accelerating, and two-dimensional semiconductor materials are attracting attention. Two-dimensional semiconductor materials are a type of natural semiconductor with an atomic-scale thickness. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and a method for manufacturing the same.

[0005] Another problem that the present invention aims to solve is to provide a structurally simplified semiconductor device and a method for manufacturing the same.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A method for manufacturing a semiconductor device according to embodiments of the present invention for solving the technical problems described above may include forming a semiconductor layer comprising a two-dimensional semiconductor material, forming a sacrificial layer on the semiconductor layer, forming a metal contact layer on the sacrificial layer, and removing the sacrificial layer. After the sacrificial layer is removed, the semiconductor layer and the metal contact layer may be joined through Van Der Waals bonding.

[0008] A semiconductor device according to embodiments of the present invention for solving the aforementioned technical problems may include a semiconductor layer and a first metal contact layer on the semiconductor layer. The semiconductor layer may include a two-dimensional semiconductor material. The semiconductor layer and the first metal contact layer may be joined through Van Der Waals bonding.

[0009] A semiconductor device according to embodiments of the present invention for solving the aforementioned technical problems may include a first semiconductor layer, a first metal contact layer bonded on the first semiconductor layer, a second semiconductor layer, and a second metal layer bonded on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer may be made of the same two-dimensional semiconductor material. The first metal layer and the second metal layer may be made of the same metal material. A first gap between the first semiconductor layer and the first metal layer may be larger than a second gap between the second semiconductor layer and the second metal layer. Effects of the invention

[0010] A semiconductor device according to embodiments of the present invention is formed such that a metal contact layer and a semiconductor layer are joined through a weak bond, specifically a van der Waals bond, and the crystal structure of the metal contact layer and the semiconductor layer may not be deformed due to the bonding force between the elements of the metal contact layer and the semiconductor layer at the interface between the metal contact layer and the semiconductor layer. In other words, a semiconductor device with few crystal defects can be provided.

[0011] In addition, a pn junction can be provided within a single semiconductor layer, and a structurally simple semiconductor device can be provided. Furthermore, first and second metal contact layers bonded to the semiconductor layer can be formed using the same structure and the same material, and different types of semiconductor regions can be provided within the semiconductor layer simply by varying the bonding between the first and second metal contact layers and the semiconductor layer. That is, a structurally simple semiconductor device can be provided.

[0012] Furthermore, the first and second transistors can be formed using the same structure and the same material, and different types of gate electrodes can be provided within the semiconductor layer simply by varying the bonding between the first and second metal contact layers and the semiconductor layer. That is, a structurally simple semiconductor device can be provided. Brief explanation of the drawing

[0013] FIG. 1 is a cross-sectional view for illustrating a semiconductor device according to embodiments of the present invention. Figure 2 is an enlarged view of area A of Figure 1. FIG. 3 is a cross-sectional view illustrating a semiconductor device according to embodiments of the present invention. Figure 4 is an enlarged view of area B of Figure 3. Figure 5 is an enlarged view of area C of Figure 3. FIG. 6 is a perspective view for explaining a semiconductor device according to embodiments of the present invention. FIG. 7 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIG. 8 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, corresponding to line I-I' of FIG. 6. FIGS. 9 to 12 are drawings for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 13 to 15 are drawings for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. Specific details for implementing the invention

[0014] A semiconductor device according to the concept of the present invention is described with reference to the drawings.

[0015] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to embodiments of the present invention. FIG. 2 is an enlarged view of area A of FIG. 1.

[0016] Referring to FIGS. 1 and 2, a semiconductor layer (10) may be provided. The semiconductor layer (10) may include a two-dimensional semiconductor material. For example, the semiconductor layer (10) may have a two-dimensional crystal structure. Here, a two-dimensional crystal structure refers to a crystal structure having a layered structure in which bonds between constituent atoms are formed only on a two-dimensional plane, and weak van der Waals bonding is formed between molecular layers formed by constituent atoms. Depending on the shape of the semiconductor layer (10), the molecular layers (ML) of the semiconductor layer (10) may be parallel to the upper surface (10a) of the semiconductor layer (10). That is, the semiconductor layer (10) may have a structure in which its molecular layers (ML) are stacked in a direction perpendicular to the upper surface (10a) of the semiconductor layer (10). More specifically, as shown in FIG. 2, the semiconductor layer (10) may be composed of first elements (11). At this time, the first elements (11) located within one molecular layer (ML) may have a first atomic bond (BD1). The first atomic bond (BD1) may be a covalent bond. The first element (11) of one molecular layer (ML) and the first element (11) of another molecular layer (ML) adjacent thereto may have a second atomic bond (BD2). In other words, adjacent molecular layers (ML) may be bonded to each other using the second atomic bond (BD2) of the first elements (11). The second atomic bond (BD2) may be a van der Waals bond. The first atomic bond (BD1), which is a covalent bond, may be a stronger bond than the second atomic bond (BD2), which is a van der Waals bond. Accordingly, the first distance (d1) between the first elements (11) within one molecular layer (ML) may be smaller than the second distance (d2) between the molecular layers (ML). The semiconductor layer (10) may be a mono-molecular layer having one molecular layer, or a multi-molecular layer having multiple molecular layers.The above two-dimensional semiconductor material may include two-dimensional transition metal dichalcogenides (TMDs), graphene, or phosphorene. For example, the semiconductor layer (10) may include MoS2, MoSe2, WS2, or WSe2. However, the present invention is not limited thereto, and the semiconductor layer (10) may include a material with a two-dimensional crystal structure that can be used as a semiconductor material.

[0017] A contact layer (20) may be provided on a semiconductor layer (10). The contact layer (20) may include a metallic material such as tungsten (W), titanium (Ti), or tantalum (Ta). That is, the second elements (21) constituting the contact layer (20) may be metallic atoms of the metallic material. At this time, the second elements (21) of the contact layer (20) may have a third atomic bond (BD3). The third atomic bond (BD3) may be a metallic bond. The third atomic bond (BD3), which is a metallic bond, may be a stronger bond than the second atomic bond (BD2), which is a van der Waals bond. The third distance (d3) between the second elements (21) may be different from the second distance (d2) between the molecular layers (ML) of the semiconductor layer (10) and the first distance (d1) between the first elements (11). For example, the third distance (d3) may be smaller than the second distance (d2) and the first distance (d1).

[0018] The contact layer (20) may be in contact with the upper surface (10a) of the semiconductor layer (10). The contact layer (20) and the semiconductor layer (10) may be bonded to each other. For example, there may be bonding between the second elements (21) of the contact layer (20) and the first elements (11) of the semiconductor layer (10) at the interface (10a) between the contact layer (20) and the semiconductor layer (10). Since the interface (10a) between the contact layer (20) and the semiconductor layer (10) exists at substantially the same location as the upper surface (10a) of the semiconductor layer (10), the same reference number is used. More specifically, as illustrated in FIG. 2, the first elements (11) in the molecular layer (ML) of the semiconductor layer (10) closest to the contact layer (20) and the second elements (21) in the molecular layer of the contact layer (20) closest to the semiconductor layer (10) may have a fourth atomic bond (BD4). Alternatively, the second elements (21) located on the surface of the contact layer (20) may be bonded to each other using the fourth atomic bond (BD4) with the molecular layer (ML) located on the surface of the semiconductor layer (10). The fourth atomic bond (BD4) may be a van der Waals bond. Here, saying that the fourth atomic bond (BD4) is a van der Waals bond means that the main cause of the bonding between the semiconductor layer (10) and the contact layer (20) is a van der Waals bond. The fourth atomic bond (BD4), which is a van der Waals bond, may be a weaker bond than the first atomic bond (BD1), which is a covalent bond, and the third atomic bond (BD3), which is a metallic bond. Accordingly, the gap between the semiconductor layer (10) and the contact layer (20), that is, the fourth distance (d4) between the semiconductor layer (10) and the contact layer (20), may be smaller than the first distance (d1) between the first elements (11) and the third distance (d3) between the second elements (21) within the one molecular layer (ML). Here, the fourth distance (d4) between the semiconductor layer (10) and the contact layer (20) refers to the distance between the second elements (21) located on the surface of the contact layer (20) and the first elements (11) located on the surface of the semiconductor layer (10).

[0019] According to embodiments of the present invention, as the first distance (d1) between the first elements (11) and the second distance (d2) between the second elements (21) are different, the first elements (11) and the second elements (21) may not be aligned with each other on the interface (10a) between the contact layer (20) and the semiconductor layer (10). That is, there may be a lattice mismatch between the semiconductor layer (10) and the contact layer (20). More specifically, the contact layer (20) and the semiconductor layer (10) may be bonded through a weak bond, such as a van der Waals bond. Accordingly, the crystal structure of the first elements (11) may not be distorted by the second elements (21) on the interface (10a), nor may the crystal structure of the second elements (21) not be distorted by the first elements (11). In other words, the crystal structure of the second elements (21) and the first elements (11) may not be deformed by the bonding force between the first elements (11) and the second elements (21) at the interface (10a). That is, a semiconductor device with few crystal defects may be provided. For example, the number (or concentration) of crystal defects within the semiconductor layer (10) may be substantially the same or similar inside the semiconductor layer (10) and near the interface (10a).

[0020] In the above embodiments, it is disclosed that the contact layer (20) comprises a metal material, but the present invention is not limited thereto. For example, the contact layer (20) may comprise a conductive two-dimensional, conductive semiconductor material such as graphene, a conductive metal nitride, a metal oxide, a metal nitride, or a metal oxynitride. When the contact layer (20) comprises the conductive two-dimensional material, the bonding of elements within one molecular layer of the contact layer (20) may have covalent bonds, which may be stronger than the fourth atomic bond (BD4), which is a van d'Arce bond. Alternatively, when the contact layer (20) comprises the semiconductor material or the conductive metal nitride, the bonding of elements within the contact layer (20) may have covalent bonds or ionic bonds, which may be stronger than the fourth atomic bond (BD4), which is a van d'Arce bond. That is, as the contact layer (20) and the semiconductor layer (10) are bonded through a weak bond, the crystal structure of the semiconductor layer (10) and the contact layer (20) can be prevented from being distorted by lattice mismatch between the semiconductor layer (10) and the contact layer (20).

[0021] At least one of the semiconductor layer (10) and the contact layer (20) may contain impurities. The concentration of the impurities may decrease as it moves further away from the interface (10a) between the semiconductor layer (10) and the contact layer (20). The impurities may have a binding energy lower than the binding energy of the first element (11) of the semiconductor layer (10) and the binding energy of the second element (21) of the contact layer (20). For example, the impurities may include sulfur (S), selenium (Se), tellurium (Te), chlorine (Cl), bromine (Br), iodine (I), mercury (Hg), cesium (Cs), potassium (K), phosphorus (P), sodium (Na), arsenic (As), magnesium (Mg), lithium (Li), rubidium (Rb), cadmium (Cd), zinc (Zn), strontium (Sr), or calcium (Ca). However, the present invention is not limited thereto, and both the semiconductor layer (10) and the contact layer (20) may not contain the above impurities.

[0023] FIG. 3 is a cross-sectional view illustrating a semiconductor device according to embodiments of the present invention. FIG. 4 is an enlarged view of region B of FIG. 3. FIG. 5 is an enlarged view of region C of FIG. 3. In the following embodiments, the components described in the embodiments of FIG. 1 and FIG. 2 use the same reference numerals, and for convenience of explanation, descriptions thereof are omitted or briefly described. That is, the description focuses on the differences between the embodiments of FIG. 1 and FIG. 2 and the embodiments below.

[0024] Referring to FIGS. 3 to 5, a semiconductor layer (10) may be provided. The semiconductor layer (10) may have a first surface (10b) and a second surface (10c) facing each other. The first surface (10b) and the second surface (10c) may be parallel to each other. The semiconductor layer (10) may include a two-dimensional semiconductor material. The semiconductor layer (10) may have a structure in which its molecular layers (ML) are stacked in a direction perpendicular to the first surface (10b) and the second surface (10c) of the semiconductor layer (10). First elements (11) located within a molecular layer (ML) may have a first atomic bond (BD1). The first atomic bond (BD1) may be a covalent bond. Adjacent molecular layers (ML) may be bonded to each other using a second atomic bond (BD2) of the first elements (11). The second atomic bond (BD2) can be a van der Waals bond.

[0025] A first contact layer (20) may be provided on a first surface (10b) of a semiconductor layer (10). The first contact layer (20) may be substantially the same as the contact layer (20) described with reference to FIGS. 1 and 2. The first contact layer (20) may include a metallic material such as tungsten (W), titanium (Ti), or tantalum (Ta). The second elements (21) of the first contact layer (20) may have a third atomic bond (BD3). The third atomic bond (BD3) may be a metallic bonding. The third distance (d3) between the second elements (21) may be smaller than the second distance (d2) between the molecular layers (ML) of the semiconductor layer (10) and the first distance (d1) between the first elements (11).

[0026] The first contact layer (20) and the semiconductor layer (10) can be bonded to each other. For example, as shown in FIG. 4, the molecular layer (ML) of the semiconductor layer (10) closest to the first contact layer (20) and the molecular layer of the first contact layer (20) closest to the semiconductor layer (10) may have a fourth atomic bond (BD4). The fourth atomic bond (BD4) may be a van der Waals bond. The fourth distance (d4) between the semiconductor layer (10) and the first contact layer (20) may be smaller than the first distance (d1) between the first elements (11) and the third distance (d3) between the second elements (21) within the molecular layer (ML).

[0027] The crystal structure of the second elements (21) and the first elements (11) may not be deformed by the bonding force between the first elements (11) and the second elements (21) at the first interface (10b) between the semiconductor layer (10) and the first contact layer (20). That is, there may be fewer crystal defects in the first region (NR) of the semiconductor layer (10) adjacent to the first contact layer (20). For example, the number (or concentration) of crystal defects within the first region (NR) of the semiconductor layer (10) may be substantially the same inside the first region (NR) and near the first interface (10b).

[0028] A second contact layer (30) may be provided on a second surface (10c) of the semiconductor layer (10). The second contact layer (30) may contain the same material as the first contact layer (20). For example, the second contact layer (30) may contain a metallic material such as tungsten (W), titanium (Ti), or tantalum (Ta). Alternatively, the second contact layer (30) may contain a different material from the first contact layer (20). The third elements (31) of the second contact layer (30) may have a third atomic bond (BD3). The third atomic bond (BD3) may be a metallic bonding. The third distance (d3) between the third elements (31) may be smaller than the second distance (d2) between the molecular layers (ML) of the semiconductor layer (10) and the first distance (d1) between the first elements (11).

[0029] The second contact layer (30) and the semiconductor layer (10) can be bonded to each other. For example, as shown in FIG. 5, the molecular layer (ML) of the semiconductor layer (10) closest to the second contact layer (30) and the molecular layer of the second contact layer (30) closest to the semiconductor layer (10) may have a fifth atomic bond (BD5). The fifth atomic bond (BD5) may be a stronger bond than the fourth atomic bond (BD4). For example, the fifth atomic bond (BD5) may be a covalent bond, an ionic bond, or a mixture thereof. The fifth distance (d5) between the semiconductor layer (10) and the second contact layer (30) may be smaller than the fourth distance (d4) between the semiconductor layer (10) and the first contact layer (20).

[0030] The semiconductor layer (10) and the second contact layer (30) may have a lattice mismatch. The crystal structure of the first elements (11) of the semiconductor layer (10) may be deformed by the bonding force between the first elements (11) and the third elements (31) near the second interface (10c) of the semiconductor layer (10) and the second contact layer (30). More specifically, as the first elements (11) and the third elements (31) form a covalent bond that is a strong bond on the second interface (10c), the first elements (11) adjacent to the second contact layer (30) may be aligned with the third elements (31). Since the first distance (d1) between the first elements (11) and the third distance (d3) between the third elements (31) are different, the crystal structure of the first elements (11) of the semiconductor layer (10) may be distorted near the second interface (10c). For example, the first atomic bond (BD1) between some of the first elements (11) may be broken near the second interface (10c), and a crystal defect (DS1) may be formed. That is, there may be many crystal defects in the second region (PR) of the semiconductor layer (10) adjacent to the second contact layer (30). For example, the number (or concentration) of crystal defects within the second region (PR) of the semiconductor layer (10) may be greater near the second interface (10c) than inside the second region (PR). In particular, the number (or concentration) of crystal defects in the second region (PR) of the semiconductor layer (10) may be greater than the number (or concentration) of crystal defects in the first region (NR) of the semiconductor layer (10).

[0031] When the number of crystal defects is large at the second region (PR) of the semiconductor layer (10) and the second interface (10c) of the second contact layer (30), the Schottky barrier between the semiconductor layer (10) and the second contact layer (30) cannot be freely controlled according to the type of the second contact layer (30). More specifically, as the amount of defects on the junction surface increases, the Fermi level between the semiconductor layer (10) and the second contact layer (30) can be fixed, and a Schottky barrier can be formed regardless of the work function of the second contact layer (30) bonded to the semiconductor layer (10). In particular, the more crystal defects there are at the second interface (10c) between the semiconductor layer (10) and the second contact layer (30), the more difficult it becomes to control the height of the Schottky barrier formed according to the work function. This means that even if a metal with an appropriate work function is used, a semiconductor device of the desired type cannot be manufactured.

[0032] On the other hand, the number of crystal defects may be small at the first interface (10b) between the first region (NR) of the semiconductor layer (10) and the first contact layer (20), and a Schottky barrier may be freely formed between the semiconductor layer (10) and the first contact layer (20) according to the work function. This means that by controlling the Schottky barrier using a metal with an appropriate work function, a desired type of semiconductor device, such as an n-type or p-type, can be fabricated.

[0033] Accordingly, even if a first contact layer (20) and a second contact layer (30) of the same material are bonded to the semiconductor layer (10), the Schottky barrier between the semiconductor layer (10) and the first contact layer (20) and the Schottky barrier between the semiconductor layer (10) and the second contact layer (30) may be different from each other. By utilizing this, the first region (NR) of the semiconductor layer (10) and the second region (PR) of the semiconductor layer (20) may be configured to have different types. For example, depending on the number (or concentration) of crystal defects within the semiconductor layer (10), the first region (NR) may be an n-type semiconductor region and the second region (PR) may be a p-type semiconductor region. That is, the first region (NR) and the second region (PR) of the semiconductor layer (10) may form a pn junction.

[0034] According to embodiments of the present invention, a first contact layer (20) and a second contact layer (30) may be connected to a semiconductor layer (10). The fourth atomic bond (BD4) between the semiconductor layer (10) and the first contact layer (20) and the fifth atomic bond (BD5) between the semiconductor layer (10) and the second contact layer (30) may be different from each other. Accordingly, a pn junction may be provided within a single semiconductor layer (10), and a structurally simple semiconductor device may be provided. Furthermore, the first contact layer (20) and the second contact layer (30) connected to the semiconductor layer (10) may be formed using the same structure and the same material, and different types of semiconductor regions may be provided within the semiconductor layer (10) simply by varying the bonding between the first and second contact layers (20, 30) and the semiconductor layer (10). That is, a structurally simple semiconductor device may be provided.

[0035] At least one of the semiconductor layer (10) and the first contact layer (20) may contain impurities. The concentration of the impurities may decrease as it moves further away from the first interface (10b) between the semiconductor layer (10) and the first contact layer (20). The impurities may have a binding energy lower than the binding energy of the first element (11) of the semiconductor layer (10) and the binding energy of the second element (21) of the first contact layer (20). The second contact layer (30) may not contain the impurities.

[0037] FIG. 6 is a perspective view for explaining a semiconductor device according to embodiments of the present invention. FIG. 7 is a plan view for explaining a semiconductor device according to embodiments of the present invention. FIG. 8 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, corresponding to line I-I' of FIG. 6.

[0038] Referring to FIGS. 6 through 8, a substrate (100) may be provided. The substrate (100) may have an active region. The substrate (100) may be a semiconductor substrate. For example, the semiconductor substrate may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG). In this case, the bulk silicon substrate may be doped with n-type or p-type impurities. Alternatively, the semiconductor substrate may be a III-V compound semiconductor substrate. For example, a III-V compound semiconductor substrate may include at least one of gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0039] First and second transistors (T1, T2) having different threshold voltages may be provided on a substrate (100). The following description is based on the provision of two transistors, but the present invention is not limited thereto.

[0040] The first and second transistors (T1, T2) may be provided in the first and second regions (R1, R2) of the substrate (100), respectively. The first and second transistors (T1, T2) may be fin-type transistors (e.g., fin-FETs) having a three-dimensional channel. The first and second transistors (T1, T2) may have different threshold voltages. The first transistor (T1) may be a P-type transistor, and the second transistor (T2) may be an n-type transistor. However, the present invention is not limited thereto, and the first and second transistors (T1, T2) may be transistors of the same type. FIG. 8 does not show the boundary where the first and second transistors (T1, T2) are in direct contact, and the first and second transistors (T1, T2) may be electrically isolated.

[0041] Hereinafter, the configuration of the first and second transistors (T1, T2) will be described based on the first transistor (T1), and the second transistor (T2) will be described in comparison with the first transistor (T1). Hereinafter, the first transistor (T1) will be described with reference to FIG. 6, but the second transistors (T2) may also be substantially identical or similar to the structure of FIG. 6.

[0042] Referring to FIGS. 6 to 8, the first transistor (T1) may include a first pin (F1), a first trench (114), a first interface film (116), a first dielectric layer (120), and a first gate electrode (GE1) provided on a first region (R1) of a substrate (100).

[0043] A first pin (F1) may be provided on a substrate (100). The first pin (F1) may extend in a first direction (D1) on the substrate (100). In this case, the first pin (F1) may be part of the substrate (100) and may be an epitaxial layer grown from the substrate (100). The first pin (F1) may include a semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the first pin (F1) may include a compound semiconductor such as a group IV compound semiconductor or a group III-V compound semiconductor. For example, a group IV compound semiconductor may be a binary compound, a ternary compound, or a compound doped with a group IV element containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, a III-V compound semiconductor may be one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0044] A first interlayer insulating film (110) may be disposed on a substrate (100). A first trench (114) may be provided within the first interlayer insulating film (110). The first trench (114) may extend in a second direction (D2) that intersects a first direction (D1).

[0045] A first interface film (116) may be disposed within the first trench (114). The first interface film (116) may cover the bottom surface within the first trench (114) and expose the inner wall of the first trench (114). The first interface film (116) may include a silicon oxide film (SiO).

[0046] A first dielectric layer (120) may be disposed along the inner wall of the first trench (114). That is, the first dielectric layer (120) may conformally cover the inner wall and bottom surface of the first trench (114). The first dielectric layer (120) may include a high dielectric constant insulating film. For example, the first dielectric layer (120) may include hafnium (Hf) or zirconium (Zr). Specifically, the first dielectric layer (120) may include at least one of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BSTO), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), lead scandium tantalum oxide (PST), or lead zinc niobate (PZN).

[0047] A first gate electrode (GE1) may be disposed within the first trench (114). The first gate electrode (GE1) may include a first semiconductor layer (130) and a first metal layer (140).

[0048] The first semiconductor layer (130) may be disposed on the first dielectric layer (120) within the first trench (114). The first semiconductor layer (130) may be provided along the sidewalls and bottom surface of the first gate electrode (GE1). The first semiconductor layer (130) may be a work function control layer for controlling the work function of the first gate electrode (GE1). The first semiconductor layer (130) may comprise a two-dimensional semiconductor material. For example, the first semiconductor layer (130) may have a two-dimensional crystal structure. The molecular layers of the first semiconductor layer (130) may be parallel to the inner sidewalls and bottom surface of the first trench (114).

[0049] The first metal layer (140) may be disposed on the first semiconductor layer (130) within the first trench (114). The first metal layer (140) may fill the remainder of the first trench (114). The first metal layer (140) may include a metallic material such as tungsten (W), titanium (Ti), or tantalum (Ta).

[0050] The first metal layer (140) and the first semiconductor layer (130) can be bonded to each other. The bonding of the first metal layer (140) and the first semiconductor layer (130) may be the same or similar to the bonding of the contact layer (20) and the semiconductor layer (10) described with reference to FIGS. 1 and 2. For example, the first metal layer (140) and the first semiconductor layer (130) may be bonded by van der Waals bonding between the metal elements constituting the first metal layer (140) and the semiconductor elements constituting the first semiconductor layer (130) at the interface between the first metal layer (140) and the first semiconductor layer (130). The crystal structure of the first semiconductor layer (130) and the first metal layer (140) may not be deformed by the bonding force between the metal elements and the semiconductor elements at the interface between the first semiconductor layer (130) and the first metal layer (140). That is, there may be fewer crystal defects within the first semiconductor layer (130) adjacent to the first metal layer (140).

[0051] The second transistor (T2) may have substantially similar components to the first transistor (T1).

[0052] The second transistor (T2) may include a second pin (F2), a second trench (214), a second interface film (216), a second dielectric layer (220), and a second gate electrode (GE2) provided on a second region (R2) of the substrate (100). The second gate electrode (GE2) of the second transistor (T2) may include a second semiconductor layer (230) and a second metal layer (240). The second semiconductor layer (230) may include the same material as the first semiconductor layer (130). The second metal layer (240) may include the same material as the first metal layer (140).

[0053] The second metal layer (240) and the second semiconductor layer (230) can be bonded to each other. The bonding of the second metal layer (240) and the first semiconductor layer (130) may be the same or similar to the bonding of the second contact layer (30) and the semiconductor layer (10) described with reference to FIGS. 3 to 5. For example, the second metal layer (240) and the second semiconductor layer (230) may be bonded by covalent bonding between the metal elements constituting the second metal layer (240) and the semiconductor elements constituting the second semiconductor layer (230) at the interface between the second metal layer (240) and the second semiconductor layer (230). The gap between the second metal layer (240) and the second semiconductor layer (230) may be smaller than the gap between the first metal layer (140) and the first semiconductor layer (130). The crystal structure of the second semiconductor layer (230) and the second metal layer (240) may be deformed by the bonding force between the metal elements and the semiconductor elements at the interface between the second semiconductor layer (230) and the second metal layer (240). That is, there may be many crystal defects within the second semiconductor layer (230) adjacent to the second metal layer (240).

[0054] The number (or concentration) of crystal defects in the first semiconductor layer (130) and the number (or concentration) of crystal defects in the second semiconductor layer (230) may be different from each other. For example, the number (or concentration) of crystal defects in the first semiconductor layer (130) may be smaller than the number (or concentration) of crystal defects in the second semiconductor layer (230). Accordingly, the first gate electrode (GE1) of the first transistor (T1) and the second gate electrode (GE2) of the second transistor (T2) may have different threshold voltages.

[0055] According to embodiments of the present invention, a first transistor (T1) and a second transistor (T2) can be formed using the same structure and the same material, and different types of first and second gate electrodes (GE1, GE2) can be provided on a substrate (100) simply by varying the coupling between the first semiconductor layer (130) and the first metal layer (140) and the coupling between the second semiconductor layer (230) and the second metal layer (240). That is, a structurally simple semiconductor device can be provided.

[0057] FIGS. 9 to 12 are drawings for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. Here, FIGS. 9 and 11 are cross-sectional views for explaining a method for manufacturing a semiconductor device, and FIGS. 10 and 12 are drawings showing enlarged views of region D of FIG. 9 and region E of FIG. 10, respectively.

[0058] Referring to FIGS. 9 and FIGS. 10, a semiconductor layer (10) may be formed. The semiconductor layer (10) may include a two-dimensional semiconductor material. For example, the semiconductor layer (10) may have a two-dimensional crystal structure. Depending on the shape of the semiconductor layer (10), the molecular layers (ML) of the semiconductor layer (10) may be parallel to the upper surface (10a) of the semiconductor layer (10). That is, the semiconductor layer (10) may have a structure in which its molecular layers (ML) are stacked in a direction perpendicular to the upper surface (10a) of the semiconductor layer (10). More specifically, as shown in FIG. 10, the semiconductor layer (10) may be composed of first elements (11). At this time, the first elements (11) located within a molecular layer (ML) may be bonded to each other using a first atomic bond (BD1) which is a covalent bond. Adjacent molecular layers (ML) can be bonded to each other using a second atomic bond (BD2) which is a van der Waals bond. The two-dimensional semiconductor material may include two-dimensional transition metal dichalcogenides (TMD), graphene, or phosphorene. For example, the semiconductor layer (10) may include MoS2, MoSe2, WS2, or WSe2.

[0059] A sacrificial layer (40) may be formed on a semiconductor layer (10). For example, a sacrificial layer (40) may be formed by depositing a fourth element (41) material on the semiconductor layer (10). The sacrificial layer (40) may be formed using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). The sacrificial layer (40) may be formed to have a small number of molecular layers. For example, as shown in FIG. 10, a sacrificial layer (40) having one molecular layer may be formed. Or, a sacrificial layer (40) having two to five molecular layers may be formed. The binding energy of the fourth element (41) constituting the sacrificial layer (40) may be lower than the binding energy of the first element (11) of the semiconductor layer (10) and the binding energy of the second element (21) constituting the contact layer (20) formed in the post-process. For example, the vaporization point of the fourth element (41) may be lower than the vaporization point of the first element (11) and the vaporization point of the second element (21). The sacrificial layer (40) may include sulfur (S), selenium (Se), tellurium (Te), chlorine (Cl), bromine (Br), iodine (I), mercury (Hg), cesium (Cs), potassium (K), phosphorus (P), sodium (Na), arsenic (As), magnesium (Mg), lithium (Li), rubidium (Rb), cadmium (Cd), zinc (Zn), strontium (Sr), or calcium (Ca).

[0060] A contact layer (20) may be formed on a sacrificial layer (40). For example, a second element (21) material may be deposited on the sacrificial layer (40) to form the contact layer (20). The contact layer (20) may be formed using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). At this time, the second elements (21) of the contact layer (20) may be bonded to each other using a third atomic bond (BD3) which is a metallic bonding. The third atomic bond (BD3) which is a metallic bonding may be a stronger bond than the second atomic bond (BD2) which is a van der Waals bond. The distance between the second elements (21) may be smaller than the distance between the first elements (11) of the semiconductor layer (10). The contact layer (20) may include a metallic material such as tungsten (W), titanium (Ti), or tantalum (Ta).

[0061] According to embodiments of the present invention, a sacrificial layer (40) may be formed between the semiconductor layer (10) and the contact layer (20). The fourth elements (41) of the sacrificial layer (40) may have a weaker bonding force compared to the first elements (11) of the semiconductor layer (10) and the second elements (21) of the contact layer (20). The sacrificial layer (40) may mitigate lattice mismatch that may occur between the semiconductor layer (10) and the contact layer (20). That is, the sacrificial layer (40) may be a buffer layer between the semiconductor layer (10) and the contact layer (20). For example, crystal defects (DS2) caused by lattice mismatch between the semiconductor layer (10) and the contact layer (20) may not occur in the semiconductor layer (10) and the contact layer (20), but may occur within the sacrificial layer (40). Accordingly, the crystal structure of the first elements (11) of the semiconductor layer (10) and the second elements (21) of the contact layer (20) may not be deformed. The number (or concentration) of crystal defects within the semiconductor layer (10) may be substantially the same or similar near the interface between the semiconductor layer (10) and the contact layer (20) and inside the semiconductor layer (10).

[0062] Referring to FIGS. 11 and 12, the sacrificial layer (40) can be removed. For example, a heat treatment process may be performed on the sacrificial layer (40). By the heat treatment process, only the sacrificial layer (40), which has a weaker bonding force compared to the semiconductor layer (10) and the contact layer (20), may be evaporated, and the sacrificial layer (40) may be removed between the semiconductor layer (10) and the contact layer (20). However, the method of removing the sacrificial layer (40) is not limited to this, and various methods such as an etching process that can remove only the sacrificial layer (40) while leaving the semiconductor layer (10) and the contact layer (20) intact may be used. As the sacrificial layer (40) is removed, the atomic bonds between the sacrificial layer (40) and the semiconductor layer (10) and the atomic bonds between the sacrificial layer (40) and the contact layer (20) may be broken. The surface of the semiconductor layer (10) and the surface of the contact layer (20) may have an electric charge, and the semiconductor layer (10) and the contact layer (20) may be bonded to each other by a fourth atomic bond (BD4) which is a van der Waals bonding.

[0063] After the sacrificial layer (40) is removed, the gap between the semiconductor layer (10) and the contact layer (20) may be greater than the distance between the first elements (11) of the semiconductor layer (10) and the distance between the second elements (21) of the contact layer (20). After the sacrificial layer (40) is removed, the number (or concentration) of crystal defects within the semiconductor layer (10) may be substantially the same or similar near the interface between the semiconductor layer (10) and the contact layer (20) and inside the semiconductor layer (10).

[0064] After removing the sacrificial layer (40), some of the atoms of the fourth element (41) of the sacrificial layer (40) may remain between the semiconductor layer (10) and the contact layer (20). Alternatively, some of the atoms of the fourth element (41) may diffuse into the semiconductor layer (10) and the contact layer (20). In this case, the concentration of the fourth element (41) may decrease as it moves further away from the interface between the semiconductor layer (10) and the contact layer (20). Alternatively, the fourth element (41) may not remain between the semiconductor layer (10), the contact layer (20), and between the semiconductor layer (10) and the contact layer (20).

[0065] A semiconductor device described above with reference to FIGS. 1 and FIGS. 2 can be manufactured.

[0067] FIGS. 13 to 15 are drawings for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.

[0068] Referring to FIGS. 13 to 15, a semiconductor layer (10) may be formed. The semiconductor layer (10) may have a first surface (10b) and a second surface (10c) facing each other. The semiconductor layer (10) may include a two-dimensional semiconductor material. Depending on the shape of the semiconductor layer (10), the molecular layers (ML) of the semiconductor layer (10) may be parallel to the first surface (10b) and the second surface (10c) of the semiconductor layer (10). That is, the semiconductor layer (10) may have a structure in which its molecular layers (ML) are stacked in a direction perpendicular to the first surface (10b) and the second surface (10c) of the semiconductor layer (10). More specifically, as shown in FIG. 14, the semiconductor layer (10) may be composed of first elements (11). At this time, the first elements (11) located within one molecular layer (ML) can be bonded to each other using a first atomic bond (BD1) which is a covalent bond. Adjacent molecular layers (ML) can be bonded to each other using a second atomic bond (BD2) which is a van der Waals bond. The two-dimensional semiconductor material may include two-dimensional transition metal dichalcogenides (TMD), graphene, or phosphorene.

[0069] A sacrificial layer (40) may be formed on the first surface (10b) of the semiconductor layer (10). For example, a sacrificial layer (40) may be formed by depositing a fourth element (41) material on the first surface (10b) of the semiconductor layer (10). The sacrificial layer (40) may be formed using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). The sacrificial layer (40) may be formed to have a small number of molecular layers. The binding energy of the fourth element (41) constituting the sacrificial layer (40) may be lower than the binding energy of the first element (11) of the semiconductor layer (10) and the binding energy of the second element (21) constituting the first contact layer (20) formed in a post-process. For example, the vaporization point of the fourth element (41) may be lower than the vaporization point of the first element (11) and the vaporization point of the second element (21).

[0070] A first contact layer (20) may be formed on a sacrificial layer (40). For example, a second element (21) material may be deposited on the sacrificial layer (40) to form the first contact layer (20). The first contact layer (20) may be formed using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). At this time, the second elements (21) of the first contact layer (20) may be bonded to each other using a third atomic bond (BD3) which is a metallic bonding.

[0071] The fourth elements (41) of the sacrificial layer (40) may have a weaker bonding force compared to the first elements (11) of the semiconductor layer (10) and the second elements (21) of the first contact layer (20). The sacrificial layer (40) can mitigate lattice mismatch that may occur between the semiconductor layer (10) and the first contact layer (20). For example, crystal defects (DS2) caused by lattice mismatch between the semiconductor layer (10) and the first contact layer (20) may not occur in the semiconductor layer (10) and the first contact layer (20), but may occur within the sacrificial layer (40). Accordingly, the crystal structure of the first elements (11) of the semiconductor layer (10) and the second elements (21) of the first contact layer (20) may not be deformed. The number (or concentration) of crystal defects in the semiconductor layer (10) may be small near the interface (10b) between the semiconductor layer (10) and the sacrificial layer (40).

[0072] A second contact layer (30) may be formed on a second surface (10c) of a semiconductor layer (10). For example, a second contact layer (30) may be formed by depositing a third element (31) material on the second surface (10c) of the semiconductor layer (10). The second contact layer (30) may be formed using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). At this time, the third elements (31) of the second contact layer (30) may be bonded to each other using a third atomic bond (BD3) which is a metallic bonding.

[0073] The semiconductor layer (10) and the second contact layer (30) may have a lattice mismatch. The crystal structure of the first elements (11) of the semiconductor layer (10) may be deformed by the bonding force between the first elements (11) and the third elements (31) near the interface (10c) of the semiconductor layer (10). Due to the lattice mismatch, the crystal structure of the first elements (11) of the semiconductor layer (10) may be distorted near the interface (10c). For example, the first atomic bond (BD1) between some of the first elements (11) may be broken near the interface (10c), and a crystal defect (DS1) may be formed. The number (or concentration) of crystal defects in the semiconductor layer (10) may be small near the interface (10c) between the semiconductor layer (10) and the second contact layer (30).

[0074] In particular, the number (or concentration) of crystal defects in the first portion of the semiconductor layer (10) adjacent to the first contact layer (20) may be greater than the number (or concentration) of crystal defects in the second portion of the semiconductor layer (10) adjacent to the second contact layer (30). Depending on the number (or concentration) of crystal defects in the semiconductor layer (10), the first portion may be an n-type semiconductor region and the second portion may be a p-type semiconductor region. That is, the first portion and the second portion of the semiconductor layer (10) may form a pn junction.

[0075] Subsequently, the sacrificial layer (40) can be removed. For example, a heat treatment process may be performed on the sacrificial layer (40). By the heat treatment process, only the sacrificial layer (40), which has a weaker bonding force compared to the semiconductor layer (10) and the first contact layer (20), may be evaporated, and the sacrificial layer (40) may be removed between the semiconductor layer (10) and the first contact layer (20). As the sacrificial layer (40) is removed, the atomic bonds between the sacrificial layer (40) and the semiconductor layer (10) and the atomic bonds between the sacrificial layer (40) and the first contact layer (20) may be broken. The surface of the semiconductor layer (10) and the surface of the first contact layer (20) may be charged, and the semiconductor layer (10) and the first contact layer (20) may be bonded to each other by a fourth atomic bond (BD4) which is a van der Waals bond.

[0076] As described above, a semiconductor device can be manufactured with reference to FIGS. 3 to 5.

[0077] According to embodiments of the present invention, a pn junction can be formed on a single semiconductor material layer through a simple process.

[0079] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0080] 10: Semiconductor layer 20, 30: Metal contact layer 40: Sacrifice layer DS1, DS2: Crystal defects

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: forming a semiconductor layer including a two-dimensional semiconductor material; forming a sacrificial layer on the semiconductor layer; forming a metal contact layer on the sacrificial layer; and removing the sacrificial layer, wherein after the sacrificial layer is removed, the semiconductor layer and the metal contact layer are joined through Van Der Waals bonding, and after the sacrificial layer is removed, the gap between the semiconductor layer and the metal contact layer is greater than the interatomic distance within a single molecular layer of the two-dimensional semiconductor material and the interatomic distance of the metal material constituting the metal contact layer. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the two-dimensional semiconductor material comprises two-dimensional transition metal dichalcogenides. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the binding energy of the material constituting the sacrificial layer is lower than the binding energy of the two-dimensional semiconductor material and the binding energy of the metal material constituting the metal contact layer. Claim 4 delete Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein removing the sacrificial layer comprises performing a heat treatment process to evaporate the sacrificial layer. Claim 6 A method for manufacturing a semiconductor device according to claim 1, wherein after the sacrificial layer is removed, the concentration of defects within the semiconductor layer is the same as that within the semiconductor layer and near the interface between the semiconductor layer and the metal contact layer. Claim 7 A semiconductor device comprising: a semiconductor layer; and a first metal contact layer on the semiconductor layer, wherein the semiconductor layer comprises a two-dimensional semiconductor material, the semiconductor layer and the first metal contact layer are joined through Van Der Waals bonding, and the gap between the semiconductor layer and the first metal contact layer is greater than the interatomic distance within a molecular layer of the two-dimensional semiconductor material and the interatomic distance of the metal material constituting the first metal contact layer. Claim 8 delete Claim 9 In claim 7, the concentration of defects within the semiconductor layer is the same in the semiconductor device, both inside the semiconductor layer and near the interface between the semiconductor layer and the first metal contact layer. Claim 10 A semiconductor device comprising: a first semiconductor layer; a first metal layer bonded on the first semiconductor layer; a second semiconductor layer; and a second metal layer bonded on the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are made of the same two-dimensional semiconductor material, the first metal layer and the second metal layer are made of the same metal material, the first gap between the first semiconductor layer and the first metal layer is larger than the second gap between the second semiconductor layer and the second metal layer, and the first gap between the first semiconductor layer and the first metal layer is larger than the interatomic distance within a molecular layer of the two-dimensional semiconductor material and the interatomic distance of the metal material constituting the first metal layer.

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