3D memory device including inverted stairs and method of manufacturing the same

Abstract

The device structure comprises an alternating stack of insulating layers and composite layers disposed on a source layer, wherein each of the composite layers comprises a combination of a dielectric material layer and an electrically conductive layer; the alternating stack, wherein a memory opening extends vertically through the alternating stack; a memory opening filling structure disposed in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; and a contact via structure extending vertically through each subset of the dielectric material layer and the insulating layer in the alternating stack and contacting the horizontal surface of each of the electrically conductive layers in the alternating stack.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit of, for all purposes, by reference, the full contents of U.S. Regular Application No. 18 / 357,676, filed with the U.S. Patent and Trademark Office on July 24, 2023, which is titled "THREE-DIMENSIONAL MEMORY DEVICE CONTAINING INVERTED STAIRCASE AND METHOD OF MAKING THE SAME" and claims priority to U.S. Provisional Application No. 63 / 482,105, filed on January 30, 2023.

[0003] Technology field

[0004] The present disclosure generally relates to the field of semiconductor devices, and in particular to a three-dimensional memory device comprising an inverse step and contact via structure and a method for forming the same. Background Technology

[0005] A three-dimensional memory device comprising a three-dimensional vertical NAND string having 1 bit per cell is disclosed in the literature [T. Endoh et al., "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36]. Support circuitry for performing write, read, and erase operations of memory cells in the vertical NAND string is typically provided by a complementary metal-oxide-semiconductor (CMOS) device formed on the same substrate as the three-dimensional memory device.

[0006] According to one aspect of the present disclosure, a device structure is disclosed comprising: an alternating stack of insulating layers and composite layers disposed over a source layer, wherein each of the composite layers comprises a combination of a dielectric material layer and an electrically conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure disposed in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; and a contact via structure extending vertically through each subset of the dielectric material layer and the insulating layer in the alternating stack and contacting a horizontal surface of each of the electrically conductive layers in the alternating stack.

[0007] According to another aspect of the present disclosure, a method for forming a device structure comprises: forming an alternating stack of a sacrificial material layer and an insulating layer comprising a dielectric material on a carrier substrate; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; forming a lateral isolation trench and an access via cavity in the alternating stack, wherein each of the sacrificial material layers is exposed to each of the lateral isolation trenches and the access via cavity has varying depths; forming a lateral recess by isotropically recessing the sacrificial material layer around the lateral isolation trench and the access via cavity, wherein the lateral range of the lateral recess is different and the remainder of the sacrificial material layer comprises a dielectric material layer; forming an electrically conductive layer in the lateral recess; and forming a lateral isolation trench filling structure and a via filling pillar structure in the lateral isolation trench and the access via cavity, respectively. A step of forming contact via cavities on the horizontal surface of each of the electrically conductive layers through each subset of the dielectric material layer and through each subset of the insulating layer; and a step of forming a contact via structure in the contact via cavities in contact with the electrically conductive layer. Brief explanation of the drawing

[0008] FIG. 1 is a schematic vertical cross-sectional view of an exemplary structure after the formation of a source-level insulating layer, a source layer, and an alternating stack of insulating layer and sacrificial material layer on a carrier substrate according to an embodiment of the present disclosure. FIG. 2a is a vertical cross-sectional view of an exemplary structure after the formation of a supporting column structure and a supporting wall structure according to an embodiment of the present disclosure. FIG. 2b is a plan view of the exemplary structure of FIG. 2a. The vertical plane A - A' is the plane of the vertical section of FIG. 2a. FIG. 2c is a zoomed-out plan view of the exemplary structure of FIG. 2a and 2b. Vertical plane A - A' is the plane of the vertical section of FIG. 2a. FIG. 3a is a vertical cross-sectional view of an exemplary structure after the formation of a memory opening according to an embodiment of the present disclosure. FIG. 3b is a plan view of the exemplary structure of FIG. 3a. The vertical plane A - A' is the plane of the vertical section of FIG. 3a. FIG. 3c is a zoomed-out plan view of the exemplary structure of FIG. 3a and 3b. Vertical plane A - A' is the plane of the vertical section of FIG. 3a. FIGS. 4a through 4f are sequential schematic vertical cross-sectional views of a memory opening within an exemplary structure during the formation of a memory opening filling structure inside according to an embodiment of the present disclosure. FIG. 5a is a vertical cross-sectional view of an exemplary structure after the formation of a memory opening filling structure according to an embodiment of the present disclosure. FIG. 5b is a plan view of the exemplary structure of FIG. 5a. The vertical plane A - A' is the plane of the vertical section of FIG. 5a. FIG. 5c is a zoomed-out plan view of the exemplary structure of FIG. 5a and 5b. Vertical plane A - A' is the plane of the vertical section of FIG. 5a. FIG. 6a is a vertical cross-sectional view of an exemplary structure after the formation of a patterned hard mask according to an embodiment of the present disclosure. FIG. 6b is a plan view of the exemplary structure of FIG. 6a. The vertical plane A - A' is the plane of the vertical section of FIG. 6a. FIG. 6c is a zoomed-out plan view of the exemplary structure of FIG. 6a and 6b. Vertical plane A - A' is the plane of the vertical section of FIG. 6a. FIGS. 7a through 7e are sequential vertical cross-sectional views of exemplary structures during the formation of a lateral isolation trench and an access via trench according to an embodiment of the present disclosure. FIG. 8a is a vertical cross-sectional view of an exemplary structure after the formation of a lateral recess according to an embodiment of the present disclosure. FIG. 8b is a plan view of the exemplary structure of FIG. 8a. The vertical plane A - A' is the plane of the vertical section of FIG. 8a. FIG. 8c is a zoomed-out plan view of the exemplary structure of FIG. 8a and 8b. Vertical plane A - A' is the plane of the vertical section of FIG. 8a. FIG. 8d is a vertical cross-sectional view of an exemplary structure along the vertical plane D-D' of FIG. 8b, FIG. 8c, FIG. 8f, and FIG. 8g. FIG. 8e is another vertical cross-sectional view of an exemplary structure along the vertical plane A - A' of FIG. 8a, wherein the location of the area omitted from the drawing is laterally shifted relative to the drawing of FIG. 8a. FIG. 8f is a horizontal cross-sectional view of an exemplary structure along the horizontal plane F - F' of FIG. 8a, FIG. 8d, and FIG. 8e. FIG. 8g is a horizontal cross-sectional view of an exemplary structure along the horizontal plane G - G' of FIG. 8a, FIG. 8d, and FIG. 8e. FIG. 9a is a vertical cross-sectional view of an exemplary structure after the formation of an electrically conductive layer in a lateral recess according to an embodiment of the present disclosure. FIG. 9b is a plan view of the exemplary structure of FIG. 9a. The vertical plane A - A' is the plane of the vertical section of FIG. 9a. FIG. 9c is a zoomed-out plan view of the exemplary structure of FIG. 9a and 9b. Vertical plane A - A' is the plane of the vertical section of FIG. 9a. FIG. 9d is a vertical cross-sectional view of an exemplary structure along the vertical plane D-D' of FIG. 9b, FIG. 9c, FIG. 9f, and FIG. 9g. FIG. 9e is another vertical cross-sectional view of an exemplary structure along the vertical plane A - A' of FIG. 9a, wherein the location of the area omitted from the drawing is laterally shifted relative to the drawing of FIG. 9a. FIG. 9f is a horizontal cross-sectional view of an exemplary structure along the horizontal plane F - F' of FIG. 9a, 9d, and 9e. FIG. 9g is a horizontal cross-sectional view of an exemplary structure along the horizontal plane G - G' of FIG. 9a, FIG. 9d, and FIG. 9e. FIG. 10a is a vertical cross-sectional view of an exemplary structure after the formation of a lateral isolation trench filling structure and a via filling column structure according to an embodiment of the present disclosure. FIG. 10b is a plan view of the exemplary structure of FIG. 10a. The vertical plane A - A' is the plane of the vertical section of FIG. 10a. FIG. 10c is a zoomed-out plan view of the exemplary structure of FIG. 10a and FIG. 10b. Vertical plane A - A' is the plane of the vertical section of FIG. 10a. FIG. 10d is a vertical cross-sectional view of an exemplary structure along the vertical plane D-D' of FIG. 10b and FIG. 10c. FIG. 11 is a vertical cross-sectional view of an exemplary structure after the formation of a metal interconnect structure and a memory-side bonding pad according to an embodiment of the present disclosure. FIG. 12 is a vertical cross-sectional view of an exemplary structure after bonding a logic die to a memory die according to an embodiment of the present disclosure. FIG. 13 is a vertical cross-sectional view of an exemplary structure after removal of a carrier substrate according to an embodiment of the present invention. FIG. 14a is a vertical cross-sectional view of an exemplary structure after the formation of a layer contact via structure and a source contact via structure according to an embodiment of the present disclosure. FIG. 14b is a horizontal cross-sectional view of an exemplary structure along the horizontal plane B - B' of FIG. 14a. The vertical plane A - A' is the plane of the vertical cross-section of FIG. 14a. FIG. 15 is a vertical cross-sectional view of an exemplary structure after the formation of a back metal interconnection structure and a back bonding pad according to an embodiment of the present disclosure. FIGS. 16a, FIGS. 16b, FIGS. 16c, FIGS. 16d, and FIGS. 16e are sequential vertical cross-sectional views of steps during the manufacture of an alternative exemplary structure according to an alternative embodiment of the present disclosure. Specific details for implementing the invention

[0009] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device including an inverse step and contact via structure and a method for forming the same, and various aspects thereof are described below. Various structures including a multi-level memory structure can be formed using embodiments of the present disclosure, and non-limiting examples include semiconductor devices such as a three-dimensional memory array device including a plurality of NAND memory strings.

[0010] The drawings are not drawn to scale. Where a single instance of an element is depicted, multiple instances of the element may be duplicated, except where it is clearly explained or clearly indicated that there is no overlap of elements. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and various ordinal numbers may be used throughout the specification and claims of this disclosure. Identical reference numbers refer to identical or similar elements. Unless otherwise indicated, elements having the same reference number are presumed to have the same configuration. Unless otherwise indicated, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element placed on a second element may be placed outside the surface of the second element or inside the second element. As used herein, where physical contact exists between the surface of the first element and the surface of the second element, the first element is placed "directly" on the second element. As used herein, a “prototype” structure or “in-process” structure refers to a transitional structure that is subsequently modified in the shape or composition of at least one component within it. As used herein, a first electric component is electrically connected to a second electric component where an electrically conductive path exists between the first electric component and the second electric component.

[0011] As used herein, “layer” refers to a portion of material comprising a region having thickness. The layer may extend over the entire structure placed below or above, or may have a range smaller than that of the structure placed below or above. Furthermore, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, the layer may be positioned between the upper and lower surfaces of the continuous structure or between any pair of horizontal planes above it. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer and may contain one or more layers within it, or may have one or more layers on, above, and / or below it.

[0012] The "semiconductor material" used herein is 1.0 x 10 -6 S / cm to 1.0 x 10 5 It refers to a material having an electrical conductivity in the range of S / cm. As used herein, "semiconductor material" refers to 1.0 x 10⁻⁶ in the absence of an electrical dopant. -6 S / cm to 1.0 x 10 5 It refers to a material having electrical conductivity in the range of S / cm, and when appropriately doped with an electrical dopant, it ranges from 1.0 S / cm to 1.0 x 10⁻⁶ 5 Doped materials having electrical conductivity in the range of S / cm can be produced. As used herein, "electric dopant" means a p-type dopant that adds holes to the valence band within the band structure or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to 1.0 x 10⁻⁶ 5 It refers to a material having an electrical conductivity greater than S / cm. As used herein, "insulating material" or "dielectric material" refers to 1.0 x 10⁻⁶ -6It refers to a material having an electrical conductivity of less than S / cm. As used herein, "highly doped semiconductor material" refers to a material that becomes a conductive material when doped with an electrical dopant to a sufficiently high atomic concentration and formed as a crystalline material, or when converted into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., 1.0 x 10⁻⁶ 5 It refers to semiconductor materials having an electrical conductivity greater than S / cm. "Doped semiconductor materials" are semiconductor materials doped to a high concentration, or 1.0 x 10⁻⁶ -6 S / cm to 1.0 x 10 5 A semiconductor material may be one containing an electric dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration that provides electrical conductivity in the range of S / cm. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electric dopant. Thus, a semiconductor material may be semiconductive or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconductive or conductive depending on the atomic concentration of the electric dopant within it. As used herein, "metallic material" means a conductive material containing at least one metal element. All measurements of electrical conductivity are performed under standard conditions.

[0013] Generally, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a series of pins or solder balls. A semiconductor package may include a single semiconductor chip (or "chip") or multiple semiconductor chips bonded together, for example, by flip-chip bonding or other chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit capable of independently executing external commands or reporting status. Typically, a package or chip having multiple dies can execute as many external commands simultaneously as the total number of dies within it. Each die includes one or more planes. With some limitations, the same simultaneous operation may be executed on each plane within the same die. If the die is a memory die, that is, a die containing memory elements, simultaneous read operations, simultaneous write operations, or simultaneous erase operations may be performed on each plane within the same memory die. Each plane includes multiple memory blocks (or "blocks"), which are the smallest units capable of being erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming.

[0014] Referring to FIG. 1, an exemplary structure according to one embodiment of the present disclosure is illustrated, comprising a carrier substrate (9), a source-level insulating layer (8), a source layer (10), and an alternating stack (32, 46) of an insulating layer (32) and a sacrificial material layer (42). The carrier substrate (9) may comprise any substrate that can be used to provide structural support while forming a memory die thereon. For example, the carrier substrate (9) may comprise a semiconductor substrate, an insulating substrate, a conductive substrate, or a combination thereof. In one embodiment, the carrier substrate (9) may comprise a commercially available single-crystal silicon wafer. The source-level insulating layer (8) comprises an insulating material. For example, the source-level insulating layer (8) may comprise silicon oxide and may have a thickness in the range of 50 nm to 1,000 nm, but smaller and larger thicknesses may also be used.

[0015] The source layer (10) is formed within or on top of the source-level insulating layer (8). In one embodiment, the source-level insulating layer (8) may contain the source layer (10). The source layer (10) comprises a highly doped semiconductor material (e.g., polysilicon, silicon-germanium alloy, or III-V compound semiconductor material) having a doping of a conductivity type opposite to the conductivity type of the vertical semiconductor channel to be subsequently formed. If the vertical semiconductor channel has a doping of a first conductivity type, the source layer (10) may have a doping of a second conductivity type opposite to the first conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of the dopant of the second conductivity type in the source layer (10) is 5.0 x 10⁻⁶ 18 / cm 3 Up to 2.0 x 10 21 / cm 3 (e.g., 1.0 x 10 19 / cm 3 Up to 1.0 x 10 21 / cm3 ) may be, but smaller or larger atomic concentrations may also be used. The thickness of the source layer (10) may be in the range of 100 nm to 500 nm, but smaller or larger thicknesses may also be used. In one embodiment, the upper surface of the source layer (10) may be formed within a horizontal plane including the upper surface of the source-level insulating layer (8).

[0016] An alternating stack of insulating layers (32) and sacrificial material layers (42) is formed on a source layer (10). The insulating layer (32) comprises an insulating material such as a silicon oxide-based insulating material. As used herein, a silicon oxide-based insulating material refers to an insulating material comprising undoped silicate glass, doped silicate glass, organic silicate glass, or silicon oxynitride with or without a dopant inside. In the above, the lowest layer of the insulating layer (32) is referred to as the lowest insulating layer (32B). In the above, the uppermost layer of the insulating layer (32) is referred to as the uppermost insulating layer (32T).

[0017] The insulating layer (32) comprises and / or is essentially composed of insulating materials. Insulating materials that may be used for the insulating layer (32) include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, etc. In one embodiment, the insulating layer (32) may essentially be composed of silicon oxide such as undoped silicate glass or doped silicate glass.

[0018] The sacrificial material layer (42) comprises a sacrificial material that can be selectively removed from the insulating material of the insulating layer (32). As used herein, if the removal process removes the first material at a rate at least twice the removal rate of the second material, the removal of the first material is "selective" to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material to the second material. Non-limiting examples of sacrificial materials include silicon nitride, borosilicate glass, organosilicate glass, and polymer materials. In one embodiment, the sacrificial material layer (42) may comprise silicon nitride.

[0019] The insulating layer (32) and the sacrificial material layer (42) may be deposited, for example, by chemical vapor deposition (CVD). The thickness of the insulating layer (32) and the sacrificial material layer (42) may be in the range of 20 nm to 50 nm, but smaller or larger thicknesses may be used for each insulating layer (32) and each sacrificial material layer (42). The number of repetitions of the pair of insulating layer (32) and sacrificial material layer (42) may be in the range of 2 to 1,024, typically 8 to 256, but more repetitions may also be used.

[0020] An exemplary structure may include a memory array region (100) in which a memory stack structure is subsequently formed, and at least one contact region (300) in which a contact via structure is subsequently formed.

[0021] Referring to FIGS. 2a through 2c, a lithographic material stack (not shown) comprising at least a photoresist layer can be formed on the top insulating layer (32T) and lithographically patterned to form an opening inside. The opening includes a distinct circular or elliptical opening formed in the contact area (300) and an elongated opening formed adjacent to the boundary between the memory array area (100) and the contact area (300). In one embodiment, the elongated opening includes a moat-shaped opening having a pair of widthwise opening segments extending laterally along a first horizontal direction (e.g., word line direction) (hd1) and a pair of longitudinal opening segments extending laterally along a second horizontal direction (e.g., bit line direction) (hd2). In another embodiment, the elongated opening includes a gap-shaped opening.

[0022] A pattern within a lithography material stack can be transferred through an alternating stack (32, 42) and a source-level insulating layer (8) by at least one anisotropic etching using the patterned lithography material stack as an etching mask. A portion of the alternating stack (32, 42) and the source-level insulating layer (8) located below an opening within the patterned lithography material stack is etched to form a support opening and a support trench. A carrier substrate (9) may be used as an etch stop structure. As used herein, "support opening" refers to an opening where a support structure (e.g., a support pillar structure) that mechanically supports another element is subsequently formed. The support opening may include a cylindrical or rectangular opening. As used herein, "support trench" refers to a trench where a trench-shaped support structure (e.g., a trench-shaped wall structure) that mechanically supports another element is subsequently formed. The support trench may include a linear slender trench, a curved slender trench, or a moat-shaped trench that surrounds a portion of the alternating stack (32, 42). The trench-shaped support structure may include a linear wall, a curved wall, or a moat-shaped wall that surrounds a portion of the alternating stack (32, 42).

[0023] Dielectric filler material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, can be deposited in the support opening and support trench by an conformal deposition process, such as a low-pressure chemical vapor deposition process. Excess portion of the dielectric filler material can be removed from the horizontal plane including the upper surface of the top insulating layer (32T). For example, a recess etching process may be used. The remainder of the dielectric filler material filling the support opening forms the support pillar structure (20). The remainder of the dielectric filler material filling the support moat trench forms the support wall structure (120). Each of the support pillar structure (20) and the support wall structure (120) may essentially consist of at least one dielectric filler material. Each support pillar structure (20) may have a horizontal cross-sectional shape of a circular, elliptical, or square shape, and the support wall structure (120) may have a shape of a linear wall, a curved wall, or a rectangular wall frame, which may optionally have rounded corners.

[0024] The support column structure (20) and the support wall structure (120) may be formed as a periodic structure having periodicity along the second horizontal direction (hd2). In this case, a unit pattern comprising a series of support column structures (20) and a series of support wall structures (120) may be repeated along the second horizontal direction (hd2). In the invention, each repeating unit pattern of the structure is referred to as a repeating unit (RU). According to one embodiment of the invention, each support wall structure (120) may have a length along the second horizontal direction (hd2) that is smaller than the width of the repeating unit (RU) along the second horizontal direction (hd2). In one embodiment, the support column structure (20) and the support wall structure (120) may be in contact with the upper surface of the carrier substrate (9). In one embodiment, the support column structure (20) and the support wall structure (120) may have an upper surface that is coplanar with the upper surface of the top insulating layer (32T).

[0025] Referring to FIGS. 3a through 3c, a lithography material stack (not shown) including at least a photoresist layer can be formed on the top insulating layer (32T) and lithographically patterned to form an opening inside. The opening includes a separate opening formed in the memory array region (100) within the region where the source layer (10) exists. In one embodiment, a cluster of openings can be formed as a two-dimensional periodic array of openings formed within each repeating unit (RU).

[0026] A pattern in a lithography material stack can be transferred to the upper surface of at least a source layer (10) through an alternating stack (32, 42) and by at least one anisotropic etching using the patterned lithography material stack as an etching mask. A portion of the alternating stack (32, 42) located below the opening in the patterned lithography material stack is etched to form a memory opening. As used herein, "memory opening" refers to a structure in which a memory element, such as a memory stack structure, is subsequently formed.

[0027] The memory opening (49) extends through the entire alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch through the material of the alternating stack (32, 42) can be alternated to optimize the etching of the material in the alternating stack (32, 42). The anisotropic etching may be, for example, a series of reactive ion etchings. The sidewalls of the memory opening (49) may be substantially vertical or tapered. The patterned lithographic material stack may be subsequently removed, for example, by ashing. In one embodiment, the memory opening (49) may extend from the upper surface of the alternating stack (32, 42) to at least a horizontal plane including the upper surface of the source layer (10). In one embodiment, over-etching into the source layer (10) can be optionally performed after the upper surface of the source layer (10) is physically exposed at the bottom of each memory opening (49). Over-etching can be performed before or after the removal of the lithography material stack. That is, the recessed surface of the source layer (10) can be vertically offset from the unrecessed upper surface of the source layer (10) by a recess depth. The recess depth may be, for example, in the range of 1 nm to 50 nm, but smaller or larger recess depths may also be used. This method is optional and can be omitted. If over-etching is not performed, the lower surface of the memory opening (49) may form a common plane with the upper surface of the source layer (10).

[0028] A two-dimensional array of memory openings (49) can be formed in the memory array area (100). Multiple rows of memory openings (49) can be formed such that each row of memory openings (49) is arranged along a first horizontal direction (hd1). Multiple rows of memory openings (49) can be spaced apart laterally along a second horizontal direction (hd2) perpendicular to the first horizontal direction (hd1).

[0029] FIGS. 4a through 4f are sequential schematic vertical cross-sectional views of a memory opening (49) in an exemplary structure while forming a memory opening filling structure (58) inside, according to an embodiment of the present disclosure.

[0030] Referring to FIG. 4a, the memory opening (49) is shown after the processing step described with reference to FIG. 3a to 3c.

[0031] Referring to FIG. 4b, a series of material layers may be conformally deposited, which may include an optional blocking dielectric layer (52), a memory material layer (54), and an optional dielectric liner (56). The blocking dielectric layer (52) may include at least one blocking dielectric material, such as silicon oxide and / or a dielectric metal oxide. The memory material layer (54) may include any memory material capable of storing memory bits. For example, the memory material layer (54) may include a charge storage layer, such as a silicon nitride layer. Alternatively, the memory material layer (54) may include a ferroelectric memory material, a resistive memory material, a phase change memory material, or any other memory material known in the art. In some embodiments, the memory material layer (54) may include a vertical stack of individual memory material portions formed at the level of the sacrificial material layer (42). Generally, the memory material layer (54) may include a vertical stack of memory elements formed at the level of the sacrificial material layer (42). In one embodiment, the vertical stack of memory elements includes a portion of a memory material layer (54) placed at the level of a sacrificial material layer (42). An optional dielectric liner (56), if present, may provide electrical isolation between the memory material layer (54) and a semiconductor channel subsequently formed. If the memory material layer (54) comprises a charge storage material, the optional dielectric liner (56) may comprise a tunneling dielectric layer.

[0032] Referring to FIG. 4c, an anisotropic etching process can be performed to remove the horizontally extended portions of the selective blocking dielectric layer (52), the memory material layer (54), and the selective dielectric liner (56). The combination of the vertically extended portions of the selective blocking dielectric layer (52), the memory material layer (54), and the selective dielectric liner (56) remaining within each memory opening (49) constitutes a memory film (50).

[0033] Referring to FIG. 4d, a semiconductor channel layer (60L) can be deposited on a memory film (50). The semiconductor channel layer (60L) comprises a semiconductor material such as at least one elemental semiconductor material, at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer (60L) comprises amorphous silicon or polysilicon. The semiconductor channel layer (60L) can be formed by an conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). In one embodiment, the semiconductor channel layer (60L) can be deposited as an amorphous semiconductor material. The thickness of the semiconductor channel layer (60L) may be in the range of 2 nm to 10 nm, but smaller or larger thicknesses may also be used. A memory cavity is formed within the volume of each memory opening (49) that is not filled with the deposited material layer (52, 54, 56, 60L).

[0034] Referring to FIG. 4e, a dielectric core layer can be deposited to fill any remaining portion of the memory cavity within each memory opening. The dielectric core layer comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by an conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating. Subsequently, the dielectric core layer can be selectively recessed from the material of the semiconductor channel layer (60L), for example, by recess etching. The material of the dielectric core layer is recessed vertically below a horizontal plane including the upper surface of the top insulating layer (32T). Each remaining portion of the dielectric core layer constitutes a dielectric core (62).

[0035] Referring to FIG. 4f, a doped semiconductor material having a second conductivity type doping can be deposited in each recess cavity disposed on the dielectric core (62). The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. In one embodiment, the doped semiconductor material can be deposited as an amorphous semiconductor material. The dopant concentration in the doped semiconductor material having a second conductivity type doping is 5.0 x 10⁻⁶ 18 / cm 3 Up to 2.0 x 10 21 / cm 3 It may be within the range, but smaller or larger dopant concentrations can also be used.

[0036] A planarization process can be performed to form a drain region (63) by removing a portion of the doped semiconductor material having a second conductivity type doping and a semiconductor channel layer (60L) from the upper surface of the top insulating layer (32T) by, for example, chemical mechanical planarization (CMP) or recess etching. Each remaining portion of the semiconductor material having a second conductivity type doping constitutes the drain region (63). Each remaining portion of the semiconductor channel layer (60L) constitutes a vertical semiconductor channel (60). When a vertical NAND device containing vertical semiconductor channels (60) is turned on, current can flow through each vertical semiconductor channel (60). Within each memory opening (49), a dielectric liner (56) is surrounded by a memory material layer (54) and laterally surrounds the vertical semiconductor channel (60). Each adjacent series of blocking dielectric layers (52), memory material layers (54), and dielectric liners (56) collectively constitutes a memory film (50) capable of storing charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer (52) may not be present in the memory film (50) at this stage, and the blocking dielectric layer may be subsequently formed after forming a lateral recess. As used herein, a macroscopic retention time refers to a retention time suitable for the memory device to operate as a permanent memory device, such as a retention time exceeding 24 hours. Each combination of the memory film (50) and the vertical semiconductor channel (60) constitutes a memory stack structure (55).

[0037] Each adjacent combination of a vertical semiconductor channel (60) and a memory film (50) constitutes a memory stack structure (55). Accordingly, each memory stack structure (55) may include a plurality of memory elements comprising a portion of a vertical semiconductor channel (60), a dielectric liner (56), and a memory material layer (54), and an optional blocking dielectric layer (52). Each combination of a memory stack structure (55), a dielectric core (62), and a drain region (63) within a memory opening (49) is referred to herein as a memory opening filling structure (58). Generally, each memory opening filling structure (58) comprises a respective vertical stack of memory elements (including a portion of the memory material layer (54)) and a respective vertical semiconductor channel (60). In one embodiment, each memory opening filling structure (58) comprises a respective drain region (63) in contact with the top of each vertical semiconductor channel (60).

[0038] Referring to FIGS. 5a through 5c, an exemplary structure is illustrated after forming a memory opening filling structure (58) within a memory opening (49). An example of the memory opening filling structure (58) may be formed within each of the memory openings (49) of the structures of FIGS. 3a through 3c.

[0039] Referring to FIGS. 6a through 6c, a patterned hard mask layer (38) may be formed on the top insulating layer (32T). The patterned hard mask layer may comprise a semiconductor material such as amorphous silicon and / or a metallic material such as TiN. An opening within the patterned hard mask layer (38) may have a pattern of all lateral isolation trenches and subsequently formed access via cavities. An opening within the patterned hard mask layer (38) may include an elongated opening (77) extending laterally from one end of the memory array region (100) to the other end of the memory array region (100) along a first horizontal direction (hd1), such that each end of the elongated opening (77) overlaps in area with one of the supporting wall structures (120) placed underneath. Additionally, the openings within the patterned hard mask layer (38) include a row of individual openings (27) formed within the contact area (300) of each of the repeating units (RU).

[0040] In one embodiment, each repeating unit (RU) may include two elongated openings (77) and one row of individual openings (27) per contact area (300). Thus, when two contact areas (300) are adjacent to a memory array area (100), each repeating unit (RU) may include two rows of two elongated openings (77) and two individual openings (27) as shown in FIG. 6c. In one embodiment, each row of individual openings (27) may be arranged along a first horizontal direction (hd1) with a uniform pitch (p), as shown in FIG. 6a and FIG. 6b. In one embodiment, the elongated openings (77) may have a uniform width along a second horizontal direction (hd2), which may be in the range of 200 nm to 2 microns, but smaller and larger widths may also be used. Each elongated opening (77) may have a horizontal cross-sectional shape of a rectangle or a rounded rectangle. The individual openings (27) may have lateral dimensions (such as length or width) in the range of 200 nm to 2 microns, but smaller and larger lateral dimensions may also be used. In one embodiment, the individual openings (27) may have a horizontal cross-sectional shape of any other two-dimensional shape having a circular, elliptical, rectangular, rounded rectangle, or closed periphery.

[0041] Referring to FIGS. 7a through 7d, a series of unit processing steps can be repeatedly performed with a change in the masking pattern using patterned photoresist layers (271, 272, 273). The series of processing steps includes a patterned photoresist forming step of forming each patterned photoresist layer (271, 272, 273) that covers each subset of individual openings (27) without covering the elongated opening (77); and an anisotropic etching step of etching a portion of the alternating stack (32, 42) that is not masked by the patterned hard mask layer (38) or each patterned photoresist layer (271, 272, 273).

[0042] In one embodiment, a combination of each masking process and each anisotropic etching process may be repeated multiple times to etch each subset of sacrificial material layers (42) and each subset of insulating layers (32) located under each opening (79, 29) of a patterned hard mask layer (38). Each masking process may use each patterned photoresist layer (271, 272, 273, etc.) that masks each subset of openings (79, 29) within the patterned hard mask layer (38) without masking each complementary subset of openings. Each anisotropic etching process etches each number of sacrificial material layers (42) and each number of insulating layers (32) located under each opening within the patterned hard mask layer (38) that are not masked by each patterned photoresist layer. In one embodiment, the etching depth of the anisotropic etching step varies between unit processing steps within a series of unit processing steps. The patterned photoresist layers (271, 272, 273, etc.) can be removed, for example, by ashing after each anisotropic etching process.

[0043] In one embodiment, the number of etched sacrificial material layers (42) and etched insulating layers (32) under unmasked openings within the patterned hard mask layer (38) may be non-negative integer powers of 2, i.e., 1, 2, 4, 8, 16, 32, 64, etc. By employing a combination of various masking patterns for the patterned photoresist layer, the total depth of the access via cavity (29) can be changed to enable physical exposure of the upper surface of the sacrificial material layer (42) at each level of the electrically conductive layer (46). The patterned hard mask layer (38) can then be removed. The lateral dimension (e.g., diameter) of the access through the cavity (29) may be in the range of 30 nm to 300 nm, but smaller and larger lateral dimensions may also be used. Generally, the access via cavity (29) can be extended vertically through an alternating stack of insulating layers (32) and sacrificial material layers (42).

[0044] According to an embodiment of the present disclosure, a pattern of patterned photoresist layers (271, 272, 273, etc.) is selected such that the region of the elongated opening (77) within the patterned hard mask layer (38) is not masked by any of the patterned photoresist layers (271, 272, 273, etc.). Lateral isolation trenches (79) may be formed below each elongated opening (77) within the patterned hard mask layer (38). Generally, a pattern of patterned photoresist layers (271, 272, 273, etc.) is selected such that the access via cavity (29) below each row of individual openings (27) within the patterned hard mask layer (38) is formed at different depths. Additionally, the depth of the access via cavity (29) within each row of the access via cavity (29) decreases as a lateral distance from the nearest boundary between the contact region (300) and the memory array region (100). Additionally, a pattern of patterned photoresist layers (271, 272, 273, etc.) can be selected so that each sacrificial material layer (42) can be physically exposed to each access via cavity (29) in each row of access via cavities (29) disposed within each repeating unit (RU) and within each contact area (300). In one embodiment, all insulating layers (32) other than the top insulating layer (32T) may have each top surface that is physically exposed to each access via cavity (29) for each row of access via cavities (29) disposed within each repeating unit (RU) and within each contact area (300). Each sacrificial material layer (42) may be physically exposed to each lateral isolation trench (79). In one embodiment, each lateral isolation trench (79) may extend vertically through the sacrificial material layer (42). The lateral isolation trench (79) may or may not extend vertically to the upper surface of the source layer (10).

[0045] Referring to FIG. 7e, the patterned hard mask layer (38) can be removed by performing an isotropic etching process to selectively remove the material of the patterned hard mask layer (38) from the material of the insulating layer (32) and the sacrificial material layer (42), for example. For example, if the patterned hard mask layer (38) includes a semiconductor material, a wet etching process can be performed to selectively etch the semiconductor material from the material of the insulating layer (32) and the sacrificial material layer (42).

[0046] Generally, lateral isolation trenches (79) and access via cavities (29) can be formed within alternating stacks (32, 42). Each sacrificial material layer (42) is exposed to each lateral isolation trench (79). The access via cavities (29) within each row of access via cavities (29) may have different depths and may be arranged along a first horizontal direction (hd1) within a uniform pitch (p). Each sacrificial material layer (42) may be physically exposed to each access via cavity (29) within each row of access via cavities (29), and the depth of the access via cavity (29) may be reduced by a lateral distance from the nearest boundary between the memory array region (100) and the contact region (300) where the row of access via cavities (29) is placed.

[0047] According to an embodiment of the present disclosure, the pattern of the lateral isolation trench (79) can be selected so that each patterned portion of the sacrificial material layer (42) can be continuously extended into a single contact area (300) through the gap between each pair of adjacent support wall structures (120) that are laterally spaced along the second horizontal direction (hd2). In one embodiment, each support wall structure (120) can be placed between each lateral isolation trench (79) and each row of the access via cavity (29). In one embodiment, each support wall structure (120) may include a section perpendicular to the longitudinal direction of the lateral isolation trench (79) (i.e., the first horizontal direction (hd1)).

[0048] In one embodiment, for each support wall structure (120), each row of lateral isolation trenches (79) and access via cavities (29) may be formed on the opposite side of the support wall structure (120). In one embodiment, each adjacent pair of lateral isolation trenches (79) may cross each support wall structure (120). Each support wall structure (120) may be physically exposed to each subset of lateral isolation trenches (79), such as the pair of lateral isolation trenches (79). In one embodiment, at least one lateral isolation trench (79) may cut through each support wall structure (120). In one embodiment, at least one support wall structure (120) may be cut through by each pair of lateral isolation trenches (79) and divided into pairs of dielectric material portions, i.e., support wall segments.

[0049] Referring to FIGS. 8a through 8g, by providing an etching medium within the lateral isolation trench (79) and the access via cavity (29), an isotropic etching process can be performed to selectively etch the material of the sacrificial material layer (42) onto the material of the insulating layer (32). For example, if the sacrificial material layer (42) comprises silicon nitride, a wet etching process using high-temperature phosphoric acid can be performed by providing phosphoric acid within the lateral isolation trench (79) and the access via cavity (29) to remove a portion of the sacrificial material layer (42) adjacent to the lateral isolation trench (79) and the access via cavity (29). A lateral recess (43) can be formed within each volume that etches a portion of each sacrificial material layer (42). The duration of the isotropic etching process can be selected such that the lateral etching distance of the isotropic etching process is greater than half the lateral spacing between adjacent pairs of lateral isolation trenches (79). In this case, the sacrificial material layer (42) can be completely removed from the memory array region (100). Additionally, the duration of the isotropic etching process can be selected so that each sacrificial material layer (42) includes the remaining portion within each contact region (300) after the isotropic etching process. Each remaining portion of the sacrificial material layer (42) is referred to herein as a dielectric material layer (41). A dielectric material layer (41) can be formed at each level where the sacrificial material layer (42) is provided.

[0050] Generally, a lateral recess (43) can be performed by isotropically recessing the sacrificial material layer (42) around the lateral isolation trench (79) and the access via cavity (29). The lateral range of the lateral recess (43) may differ for different levels, that is, as a function of the depth of the access via cavity (29) relative to the substrate (9). As previously described, the depth of the access via cavity (29) may be reduced by a lateral distance from the nearest boundary between the memory array region (100) and the contact region (300) (i.e., further from the boundary, making the depth of the access via cavity (29) shallower, as illustrated in FIG. 8a and FIG. 8e). In one embodiment, the depth of the access via cavity (29) may be reduced by a lateral distance from the nearest support wall structure (120). In this case, for each pair of lateral recesses (43) placed in each contact area (300), the upper lateral recess (43) has a larger lateral range than the lower lateral recess (43). In one embodiment, the lateral range of the lateral recess (43) increases with a vertical distance from the upper surface of the substrate (9). In one embodiment, the lateral range of the dielectric material layer (41) decreases with a vertical distance from the top of the substrate (9).

[0051] According to an embodiment of the present disclosure, the isotropic etching process etches the material of the sacrificial material layer (42) isotropically, that is, at an etching rate independent of the etching direction. As a result, each dielectric material layer (41) may include a sidewall segment that is equidistant from the periphery of the nearest access via cavity (29). In one embodiment, vertically adjacent pairs of boundaries between each lateral recess (43) and each dielectric material layer (41) within the same horizontal plane in the contact area (300) may be laterally offset from each other by a uniform pitch (p). In one embodiment illustrated in FIG. 8f, a subset of boundaries between each lateral recess (43) and each dielectric material layer (41) may include each pair of longitudinal boundary segments (43A, 43B) that extend laterally along the first horizontal direction (hd1) and are isolated along the second horizontal direction (hd2), and each pair of vertically straight and horizontally concave surface segments (43C). Each lateral recess (43) may extend continuously along the entire length of the memory array region (100) along the first horizontal direction (hd1), extend laterally through the gap (120G) between each pair of support wall structures (120), and extend laterally through each part of the contact region (300) along the first horizontal direction (hd1) such that the lateral range of each part of the lateral recess (43) is smaller than the total lateral range of the contact region (300) along the first horizontal direction (hd1). In one embodiment, each lateral recess (43) may laterally surround at least one access via cavity (29) within each row of the access via cavity (29). Each lateral recess (43) laterally surrounds each two-dimensional array of the memory opening filling structure (58) and each subset of the support pillar structure (20).

[0052] Referring to FIGS. 9a through 9g, a back-side blocking dielectric layer (not shown) may be optionally formed within the lateral recess (43) by an conformal deposition process. At least one conductive material, such as at least one metal material, may be conformally deposited within the lateral recess (43). The at least one conductive material may include, for example, a combination of a metal barrier material and a metal filler material. The metal barrier material may include, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof. The metal filler material may include, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or alloys or layer stacks thereof. At least one conductive metal material may be deposited in the periphery of the lateral recess (43) and the lateral isolation trench (79) and in the access via cavity (29) by performing at least one conformal deposition process, such as at least one atomic layer deposition and / or at least one chemical vapor deposition. Lateral isolation trenches (79) and access via cavities (29) may be used as conduits for transporting precursor materials for the deposition of at least one conductive material. While the duration of at least one conformal deposition process may be selected so that the lateral recesses (43) are filled with at least one conductive material, each lateral isolation trench (79) and access via cavity (29) includes a central void that is not filled with at least one conductive material.

[0053] Excess portion of at least one conductive material deposited within the lateral isolation trench (79) and access via cavity (29) or on the top insulating layer (32T) may be removed by performing an etch-back process that may include an isotropic etching process and / or an anisotropic etching process. The remaining portions of the electrically conductive layer (46) and at least one dielectric material layer (41) that are in direct contact with the electrically conductive layer (46) or are laterally spaced from the electrically conductive layer (46) only by a vertical extension of a back-blocking dielectric layer (not shown) constitute a composite layer (41, 46).

[0054] An alternating stack of insulating layers (32) and composite layers (46, 41) {32, (46, 41)} can be formed on the source layer (10) and on the substrate (9). Each composite layer (46, 41) comprises at least a combination of each dielectric material layer (41) and each electrically conductive layer (46). In the alternating stack {32, (46, 41)}, the lateral extension of the electrically conductive layer (46) increases with a vertical distance from the upper surface of the substrate (9) (e.g., increases from a horizontal plane including the interface between the source layer (10) and the alternating stack {32, (46, 41)}).

[0055] Referring to FIGS. 10a through 10d, at least one filling material may be deposited within the lateral isolation trench (79) and the access via cavity (29). A via filling pillar structure (24, 26) may be formed in each access via cavity (29), and a lateral isolation trench filling structure (74, 76) may be formed in each lateral isolation trench (79). Generally, the via filling pillar structure (24, 26) and the lateral isolation trench filling structure (74, 76) include a dielectric surface in contact with each alternating stack {32, (46, 41)} of the insulating layer (32) and the composite layer (46, 41) and each subset layer.

[0056] In an urban example, an insulating filler material, such as undoped silicate glass or doped silicate glass, may be deposited conformally within the lateral isolation trench (79) and access via cavity (29) by an conformal deposition process. An anisotropic etching process may be optionally performed. A conductive filler material and / or a highly doped semiconductor filler material may be deposited on the remaining volume of the lateral isolation trench (79) and access via cavity (29). A portion of the conductive filler material and / or semiconductor filler material lying on a horizontal plane including the upper surface of the top insulating layer (32T), and any remaining portion of the insulating filler material (if present) lying on a horizontal plane including the upper surface of the top insulating layer (32T) may be removed by performing a planarization process. The planarization process may include a recess etching process and / or a chemical mechanical polishing (CMP) process. Each remainder of the insulating filler material, conductive filler material, and / or semiconductor filler material filling the access via cavity (29) forms a via fill pillar structure (24, 26). Each remainder of the insulating filler material, conductive filler material, and / or semiconductor filler material filling the lateral isolation trench (79) forms a lateral isolation trench fill structure (74, 76), and each via fill pillar structure (24, 26) includes an insulating via filler material portion (24) containing the remainder of the insulating filler material, and an optional internal via filler material portion (26) containing the remainder of the conductive filler material or the highly doped semiconductor filler material. Each lateral isolation trench fill structure (74, 76) may include an insulating trench filler material portion (74) containing the remainder of the insulating filler material, and optionally an internal trench filler material portion (76) containing the remainder of the conductive filler material or the highly doped semiconductor filler material.

[0057] Generally, lateral isolation trench filling structures (74, 76) and via filling pillar structures (24, 26) may be formed within the lateral isolation trench (79) and access via cavity (29), respectively. Each via filling pillar structure (24, 26) extends vertically through and contacts each subset of the electrically conductive layer (46), has an upper surface in a first horizontal plane (HP1) that may include the upper surface of the top insulating layer (32T), and has a lower surface at a different vertical distance from the first horizontal plane (HP1).

[0058] Lateral isolation trench filling structures (74, 76) are disposed in each lateral isolation trench (79). The lateral isolation trench (79) extends vertically through each of the composite layers (46, 41) within the alternating stack {32, (46, 41)} and extends laterally along the first horizontal direction (hd1). In one embodiment, the lateral isolation trench filling structures (74, 76) and the via filling pillar structures (24, 26) each comprise the same set of at least one filling material comprising an insulating filling material.

[0059] In one embodiment, the support wall structure (120) may be in contact with each subset of the lateral isolation trench filling structure (74, 76) and may be in contact with the interface between each insulating layer (32) and each electrically conductive layer (46) within the composite layer (46, 41). The support wall structure (120) may be extended vertically through each layer within the alternating stack {32, (46, 41)}.

[0060] Referring to FIG. 11, a contact-level dielectric layer (80) can be formed on an alternating stack {32, (46, 41)} by depositing a dielectric material such as silicon oxide. The thickness of the contact-level dielectric layer (80) may be in the range of 100 nm to 600 nm, but smaller or larger thicknesses may also be used.

[0061] A photoresist layer (not shown) can be applied over the contact-level dielectric layer (80) and lithographically patterned to form an opening. An anisotropic etching process can be performed to transfer the pattern of the opening from the photoresist layer to the upper surface of each drain region (63) through the contact-level dielectric layer (80). A drain contact via cavity can be formed through the contact-level dielectric layer (80). For example, the photoresist layer can be subsequently removed by ashing.

[0062] At least one conductive material, such as a combination of a metal barrier material and a metal filler material, can be deposited in the drain contact via cavity. Excess portion of at least one conductive material can be removed from a horizontal plane including the upper surface of the contact-level dielectric layer (80) by a planarization process that may employ a recess etching process and / or a chemical mechanical polishing process. The remainder of the at least one conductive material filling the drain contact via cavity forms a drain contact via structure (88).

[0063] A memory-side dielectric material layer (960) and a memory-side metal interconnect structure (980) may be formed on a contact-level dielectric layer (80). The memory-side dielectric material layer (960) may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line-and-via-level dielectric layer. The memory-side metal interconnect structure (980) may include a metal via structure, a metal line structure, and / or an integrated metal line-and-via structure. The metal line structure may include a bit line (108) that is electrically in contact with a drain contact via structure (i.e., drain electrodes) (88) through one or more metal via structures (not shown for clarity). A metal bonding pad, referred herein as a memory-side bonding pad (988), may be formed on the uppermost level of the additional dielectric material layer (960). Memory-side bonding pads (988) can be electrically connected to various nodes of a three-dimensional memory array comprising a memory-side metal interconnect structure (980), an alternating stack of insulating layers (32) and composite layers (46, 41) {32, (46, 41)}, and a memory opening filling structure (58). Generally, a memory-side dielectric material layer (960) is placed on top of the alternating stack {32, (46, 41)}, and the memory-side metal interconnect structure (980) and the memory-side bonding pads (988) are embedded within the memory-side dielectric material layer (960). The above steps form a memory die (900).

[0064] Referring to FIG. 12, a logic die (700) is provided. The logic die (700) comprises a logic-side substrate (709), a semiconductor device (720) disposed on the logic-side substrate (709) and including a logic-side semiconductor device (e.g., a field-effect transistor), a logic-side metal interconnect structure (780) embedded within a logic-side dielectric material layer (760), and a logic-side bonding pad (778). The semiconductor device (720) may include a peripheral circuit configured to control the operation of a memory array within a memory die (900). In one embodiment, the peripheral circuit may be configured to drive various electrical components within the memory array, including but not limited to bit lines (108) (i.e., the peripheral circuit may include a bit line driver circuit). In one embodiment, the peripheral circuit may be configured to control the operation of a vertical stack of memory elements within the memory array in the memory die (900).

[0065] A logic die (700) can be attached to a memory die (900), for example, by bonding a logic-side bonding pad (778) to a memory-side bonding pad (988) at a bonding interface (800). Bonding between the memory die (900) and the logic die (700) can be performed using a wafer-to-wafer bonding process in which a two-dimensional array of the memory die (900) is bonded to a two-dimensional array of the logic die (700) by a die-to-die bonding process. A logic-side bonding pad (788) within each logic die (700) can be bonded to a memory-side bonding pad (988) within each memory die (900).

[0066] Referring to FIG. 13, the carrier substrate (9) can be removed, for example, through grinding, polishing, cutting, isotropic etching and / or anisotropic etching processes. The distal portion of the source-level insulating layer (8) can be physically exposed. As used herein, the distal side of an element within a bonded assembly refers to a side distal from a horizontal plane containing the bonding interface (800) of the bonded assembly.

[0067] Referring to FIGS. 14a and 14b, a photoresist layer (not shown) can be applied over a source-level insulating layer (8). The photoresist layer can be lithographically patterned to form distinct openings over a region of the source layer (10) and over a portion of the electrically conductive layer (46) that is not under any other electrically conductive layer (46) (i.e., within a stepped portion of the contact region (300). An anisotropic etching process can be performed to etch through the unmasked portions of the optional source-level insulating layer (8), insulating layer (32), and dielectric material layer (41) in the material of the electrically conductive layer (46) and the source layer (10). At least one source contact cavity is formed on the back side (i.e., distal side) of the source layer (10), and layer contact via cavities are formed through each subset of the layers among the source-level insulating layer (8), insulating layer (32), and dielectric material layer (41). The electrically conductive layer (46) within the stepped portion of the contact area (300) acts as an etching stop layer during the formation of the layer contact via cavity. For example, the photoresist layer can be subsequently removed by ashing.

[0068] At least one conductive filler material may be deposited in at least one source contact cavity and at least one layer contact via cavity. For example, at least one conductive filler material may include a metal barrier liner material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a metal filler material (such as W, Ti, Ta, Co, Ru, Mo, Cu, etc.). Excess portion of at least one conductive filler material disposed on a horizontal plane including the back surface of the source-level insulating layer (8) (i.e., the distal surface from the bonding interface (800)) may be removed by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remainder of at least one conductive filler material filling each source contact cavity forms a source contact via structure (82). Each remainder of at least one conductive filler material filling each layer contact via cavity forms a layer contact via structure (86). Each electrically conductive layer (46) can be contacted by each layer contact via structure (86). Since the sidewalls of the conductive layer contact via structure (86) are in contact only with dielectric materials (i.e., insulating layer (32) and dielectric material layer (41)), insulating sidewall spacers surrounding the structure (86) can be omitted.

[0069] Generally, contact via cavities (e.g., layer contact via cavities) can be formed on the lower (i.e., distal) surface of each of the electrically conductive layers (46) through each subset of the dielectric material layer (41) and through each subset of the insulating layer (32) from the lower part of the alternating stack {32, (46, 41)} (i.e., from the side far from the bonding interface (800)). Contact via cavities can be arranged as rows of contact via cavities formed within each repeating unit (RU) within each contact area (300). In one embodiment, the via filling pillar structures (24, 26) may be arranged along a first horizontal direction (hd1) within a uniform pitch (p), and the contact via cavities may be arranged along the first horizontal direction (hd1) with a uniform pitch (p) and laterally offset from the row of the via filling pillar structures (24, 26) (located within the row (29) of the access via cavities) along a second horizontal direction (hd2). Thus, the layer contact via structures (86) may be arranged along a first horizontal direction (hd1) having a uniform pitch (p) and laterally offset from the via filling pillar structures (24, 26) along a second horizontal direction (hd2).

[0070] In one embodiment, the source-level insulating layer (8) encloses the source layer (10). A layer contact via structure (86) extends vertically through the source-level insulating layer (8). In one embodiment, the lower surface (i.e., distal surface) of the layer contact via structure (86) is positioned within a horizontal plane (referred to herein as a second horizontal plane (HP2)) that includes the lower surface (i.e., distal surface) of the source-level insulating layer (8). It is understood that the exemplary structure may be inverted, and depending on the orientation of the exemplary structure, the upper surface may become the lower surface and the lower surface may become the upper surface.

[0071] The layer contact via structure (86) extends vertically through each subset of dielectric material layers (41) in alternating stacks {32, (46, 41)} and contacts the lower surface (i.e., distal surface) of each electrically conductive layer (46) in alternating stacks {32, (46, 41)}. In one embodiment, the layer contact via structure (86) is arranged along a first horizontal direction (hd1) having a uniform pitch (p); via filling pillar structures (24, 26) are arranged along the first horizontal direction (hd1) with a uniform pitch (p) and are laterally offset from the contact via structure (86) along a second horizontal direction (hd2); and each contact via structure (86) is laterally offset from each via filling pillar structure (24, 26) by a lateral offset distance (lod).

[0072] Referring to FIG. 15, a back dielectric material layer (360) can be formed on the distal surface (i.e., back surface) of the source-level insulating layer (8). A back metal interconnect structure (380) is formed within the back dielectric material layer (360). The back metal interconnect structure (380) can be electrically connected to various additional conductive via structures (not shown) that extend vertically through the electrically conductive layer (46), the source layer (10), the insulating layer (32), and the dielectric material layer (41). For example, a first subset of the back metal interconnect structure (380) can be electrically connected to each layer contact via structure (86), and a second subset of the back metal interconnect structure (380) can be electrically connected to the source layer (10). The back metal interconnect structure (380) may include a back metal line structure and a back metal via structure. A back bonding pad (388) can be formed on the back side (i.e., the distal side) of the back dielectric material layer (360).

[0073] The second logic die (750) can be bonded to the back bonding pad (388). The second logic die (750) includes a second peripheral circuit (722) configured to control the operation of a memory array within the memory die (900). For example, the second peripheral circuit (722) may include a word line driver circuit for driving a word line (46) through a contact via structure (86), and a source bias circuit for biasing a source layer (10). The second logic die (750) includes a second logic side bonding pad (798) that is electrically bonded to the back bonding pad (389).

[0074] FIGS. 16a, FIGS. 16b, FIGS. 16c, FIGS. 16d, and FIGS. 16e are sequential vertical cross-sectional views of steps during the manufacture of an alternative exemplary structure according to an alternative embodiment of the present disclosure.

[0075] An alternative exemplary structure of FIG. 16a can be derived from the exemplary structure of FIG. 10d by omitting the steps shown in FIG. 4e and FIG. 4f, such as omitting the formation of the source layer (10) in the step shown in FIG. 1, recessing the dielectric core (62), and omitting the formation of the drain region (63).

[0076] Referring to FIG. 16b, the source layer (10) is formed on an alternating stack {(32), (41, 46)} and contacts the top of a vertical semiconductor channel region (60) disposed within a memory aperture filling structure (58). The source layer (10) can be formed by depositing at least one electrically conductive layer, such as a highly doped semiconductor layer (e.g., polysilicon or amorphous silicon) and an optional metal or metal alloy capping layer, and by optionally patterning at least one electrically conductive layer so that the source layer (10) is maintained within at least the memory array region (100). A capping dielectric layer (90), such as a silicon oxide or silicon nitride layer, can be formed on the source layer (10).

[0077] Referring to FIG. 16c, the carrier substrate (9) and the insulating layer (8) are removed as described above in relation to FIG. 13. During the removal of the carrier substrate (9) and the insulating layer (8), a temporary handle substrate may be attached to the capping dielectric layer (90) for support.

[0078] Referring to FIG. 16d, a drain region (63) is formed by contacting a vertical semiconductor channel (60) within a memory opening filling structure (58) using the steps described above in relation to FIG. 4e and FIG. 4f. A drain region (63) is formed by contacting the bottom of the vertical semiconductor channel (60) exposed after the removal of the carrier substrate (9) and the insulating layer (8). Thus, in an alternative embodiment, the source layer (10) and the drain region (63) are formed on opposite ends of the memory opening filling structure (58) from their positions in the exemplary structure of the embodiment shown in FIG. 13 to FIG. 15.

[0079] Referring to FIG. 16e, a drain contact via structure (88) is formed in contact with the drain region (63) as described in FIG. 11. Subsequently, as described above in relation to FIG. 11, a memory-side dielectric layer (960), a memory-side interconnect structure (980) (including a bit line (108)), and a bonding pad (988) are formed on the drain region (63) and the drain contact via structure (88). Then, the logic die (700) is bonded to the bonding pad (988) as described above in relation to FIG. 12.

[0080] In this alternative embodiment, the second logic die (750) may be omitted. In this case, the logic die includes both a bit line driver circuit and a word line driver circuit that are electrically connected to the word line (46) and the bit line (108), respectively. In an alternative exemplary structure of the embodiment of FIG. 16e, the electrically conductive layer (46) having the longest lateral length is positioned further from the bonding interface (800) with the logic die (700) than the electrically conductive layer (46) having the shortest lateral length. In contrast, in an exemplary structure of the embodiment shown in FIG. 15, the electrically conductive layer (46) having the longest lateral length is positioned closer to the bonding interface (800) with the logic die (700) than the electrically conductive layer (46) having the shortest lateral length.

[0081] In an alternative exemplary structure of the embodiment of FIG. 16e, the lateral range of the electrically conductive layer (46) within the alternating stack (32, (46, 41)) is reduced by a vertical distance from a horizontal plane containing the interface between the source layer (10) and the alternating stack (32, (46, 41)). In contrast, in an exemplary structure of the embodiment shown in FIG. 15, the lateral range of the electrically conductive layer (46) within the alternating stack (32, (46, 41)) is increased by a vertical distance from a horizontal plane containing the interface between the source layer (10) and the alternating stack (32, (46, 41)).

[0082] Referring collectively to all embodiments of the present disclosure, the device structure comprises: an alternating stack {32, (46, 41)} of insulating layers (32) and composite layers (46, 41) disposed over a source layer (10), wherein each of the composite layers (46, 41) comprises a combination of a dielectric material layer (41) and an electrically conductive layer (46); a memory opening (49) extending vertically through the alternating stack {32, (46, 41)}; a memory opening filling structure (58) disposed within the memory opening (49)—each of which comprises a vertical stack of memory elements (e.g., a portion of a memory film (50)) and a vertical semiconductor channel (60); and includes a contact via structure (86) that extends vertically through each subset of the dielectric material layer (41) and the insulating layer (32) in the alternating stack (32, (46, 41)) and contacts each horizontal surface of the electrically conductive layer (46) in the alternating stack (32, (46, 41)).

[0083] In the exemplary structure of the embodiment shown in FIG. 15, the lateral range of the electrically conductive layer (46) within the alternating stack (32, (46, 41)) increases by a vertical distance from the horizontal plane containing the interface between the source layer (10) and the alternating stack (32, (46, 41)). In contrast, in the alternative exemplary structure of the embodiment of FIG. 16e, the lateral range of the electrically conductive layer (46) within the alternating stack (32, (46, 41)) decreases by a vertical distance from the horizontal plane containing the interface between the source layer (10) and the alternating stack (32, (46, 41)).

[0084] In the embodiment of FIG. 15, the lateral range of the dielectric material layer (41) is reduced to a vertical distance from a horizontal plane including the interface between the source layer (10) and the alternating stack {32, (46, 41)}. In contrast, in the alternative embodiment of FIG. 16e, the lateral range of the dielectric material layer (41) is increased to a vertical distance from a horizontal plane including the interface between the source layer (10) and the alternating stack {32, (46, 41)}.

[0085] In one embodiment, the device structure comprises via-fill pillar structures (24, 26) that extend vertically through each subset of electrically conductive layers (46), have an upper surface in a first horizontal plane (HP1), and have a lower surface at a different vertical distance from the first horizontal plane (HP1). In one embodiment, contact via structures (86) are arranged along a first horizontal direction (hd1) having a uniform pitch (p); via-fill pillar structures (24, 26) are arranged along the first horizontal direction (hd1) with a uniform pitch (p) and are laterally offset from the contact via structures (86) along a second horizontal direction (hd2); and each contact via structure (86) is laterally offset from each via-fill pillar structure (24, 26) by a lateral offset distance (lod). In one embodiment, each dielectric material layer (41) includes a sidewall segment that is equidistant from the periphery of each via-filled pillar structure (24, 26).

[0086] In one embodiment, the device structure comprises: a lateral isolation trench (79) that extends vertically through each of the composite layers (46, 41) within the alternating stack {32, (46, 41)} and extends laterally along a first horizontal direction (hd1); and a lateral isolation trench filling structure (74, 76) disposed in each lateral isolation trench (79), wherein each lateral isolation trench filling structure (74, 76) and via filling pillar structure (24, 26) comprises the same set of at least one filling material comprising an insulating filling material. In one embodiment, the device structure includes a support wall structure (120) that is in contact with each subset of the lateral isolation trench filling structure (74, 76), in contact with the interface between each insulating layer (32) and each electrically conductive layer (46) within the composite layer (46, 41), and extends vertically through each layer within the alternating stack {32, (46, 41)}.

[0087] In one embodiment, the device structure also includes a memory-side dielectric material layer (960) placed on an alternating stack {32, (46, 41)}; and a memory-side metal interconnect structure (980) comprising a bit line (108) and a memory-side bonding pad (988) embedded within the memory-side dielectric material layer (960). In one embodiment, the device structure also includes a first logic die (700) comprising a first logic-side bonding pad (788) electrically bonded to the memory-side bonding pad (988).

[0088] In the embodiment of FIG. 15, a back dielectric material layer (380) is disposed below the source layer (10) and embeds a back metal interconnect structure (380) and a back bonding pad (388). A first subset of the back metal interconnect structure (380) is electrically connected to each of the contact via structures (86), and a second subset of the back metal interconnect structure (380) is electrically connected to the source layer (10). In the embodiment of FIG. 15, the device structure also includes a second logic die (750) comprising a second logic side bonding pad (798) that is electrically bonded to the back bonding pad (388). The first logic die includes a bit line driver circuit (720) that is electrically connected to a bit line (108); and the second logic die (750) includes a word line driver circuit (722) that is electrically connected to an electrically conductive layer (46) through the contact via structure (86).

[0089] In an alternative embodiment of FIG. 16e, the first logic die (700) includes a bit line driver circuit (720) electrically connected to a bit line (108) and a word line driver circuit (720) electrically connected to an electrically conductive layer (46) through a contact via structure (86).

[0090] Various embodiments of the present disclosure provide a layer contact via structure (86) in reverse steps in an electrically conductive layer (46). The layer contact via structure (86) extends through an alternating stack of insulating layers (32) and dielectric material layers (41). Thus, there is no need to form a large reverse-step dielectric layer (e.g., a silicon oxide layer) over the end of the stepped portion of the contact area (300). By omitting the reverse-step dielectric layer, the subsidence of the device layer is reduced, the high-cost, large-area planarization of the reverse-step dielectric layer is omitted, and support openings and memory openings can be formed through the alternating stack using cryogenic reactive ion etching. In contrast, the use of cryogenic reactive ion etching to form openings through reverse-step dielectric layers is relatively difficult. Additionally, the possibility of bending of the back trench (79), which could result in undesirable contact between the support column structure (20) and the back trench and cause the electrically conductive layer (46) to sag laterally and sink vertically, is reduced through the reverse steps.

[0091] While the foregoing refers to specific preferred embodiments, it will be understood that the claims are not so limited. Those skilled in the art will understand that various modifications may be made to the disclosed embodiments, and that such modifications are intended to be included within the scope of the claims. Compatibility is assumed between all embodiments, not alternatives to one another. The words “comprise” or “include” encompass all embodiments in which the words “comprise” or “include” are replaced with “essentially constitute” or “constitute” unless explicitly stated otherwise. Where embodiments using a specific structure and / or configuration are exemplified in this disclosure, it is understood that the claims may be practiced with any other functionally equivalent compatible structure and / or configuration unless such substitution is explicitly prohibited or known to those skilled in the art as impossible. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

Claim 1 A device structure comprising: an alternating stack of insulating layers and composite layers disposed on a source layer, wherein each of the composite layers comprises a combination of a dielectric material layer and an electrically conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure disposed in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; a contact via structure extending vertically through each subset of the dielectric material layer and the insulating layer in the alternating stack and contacting a horizontal surface of each of the electrically conductive layers in the alternating stack; and a via filling pillar structure extending vertically through each subset of the electrically conductive layers, having an upper surface within a first horizontal plane and a lower surface at a different vertical distance from the first horizontal plane. Claim 2 A device structure comprising: an alternating stack of insulating layers and composite layers disposed on a source layer, wherein each of the composite layers comprises a combination of a dielectric material layer and an electrically conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure disposed in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; and a contact via structure extending vertically through each subset of the dielectric material layer and the insulating layer in the alternating stack and contacting the horizontal surface of each of the electrically conductive layers in the alternating stack, wherein the lateral range of the electrically conductive layer in the alternating stack increases by a vertical distance from a horizontal plane comprising an interface between the source layer and the alternating stack; and the lateral range of the dielectric material layer decreases by the vertical distance from the horizontal plane comprising an interface between the source layer and the alternating stack. Claim 3 A device structure comprising: an alternating stack of insulating layers and composite layers disposed on a source layer, wherein each of the composite layers comprises a combination of a dielectric material layer and an electrically conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure disposed in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; and a contact via structure extending vertically through each subset of the dielectric material layer and the insulating layer in the alternating stack and contacting the horizontal surface of each of the electrically conductive layers in the alternating stack, wherein the lateral range of the electrically conductive layer in the alternating stack decreases by a vertical distance from a horizontal plane comprising an interface between the source layer and the alternating stack; and the lateral range of the dielectric material layer increases by the vertical distance from the horizontal plane comprising an interface between the source layer and the alternating stack. Claim 4 delete Claim 5 A device structure according to claim 1, wherein the contact via structure is arranged along a first horizontal direction with a uniform pitch; the via filling pillar structure is arranged along the first horizontal direction with the uniform pitch and is laterally offset from the contact via structure along a second horizontal direction perpendicular to the first horizontal direction; and each of the contact via structures is laterally offset from each of the via filling pillar structures by a lateral offset distance. Claim 6 A device structure according to claim 1, wherein each of the dielectric material layers comprises a sidewall segment equidistant from the periphery of each of the via-filled pillar structures. Claim 7 In claim 5, additionally: a lateral isolation trench extending vertically through each of the composite layers within the alternating stack and extending laterally along a first horizontal direction; and a lateral isolation trench filling structure disposed in each of the lateral isolation trenches, wherein each of the lateral isolation trench filling structure and the via filling pillar structure comprises the same set of at least one filling material comprising an insulating filling material. Claim 8 A device structure according to claim 7, further comprising a support wall structure that contacts each subset of the lateral isolation trench filling structure, contacts the interface between each insulating layer and each electrically conductive layer in the composite layer, and extends vertically through each layer in the alternating stack. Claim 9 A device structure according to claim 1, further comprising: a memory-side dielectric material layer placed on the alternating stack; and a memory-side metal interconnect structure including bit lines and memory-side bonding pads embedded within the memory-side dielectric material layer. Claim 10 A device structure according to claim 9, further comprising a first logic die including a first logic side bonding pad electrically bonded to the memory side bonding pad. Claim 11 As a device structure, an alternating stack of insulating layers and composite layers disposed over a source layer, wherein each of the composite layers comprises a combination of a dielectric material layer and an electrically conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure disposed in the memory opening, wherein each of the memory opening filling structures comprises a vertical stack of memory elements and a vertical semiconductor channel; a contact via structure extending vertically through each subset of the dielectric material layer and the insulating layer in the alternating stack and contacting the horizontal surface of each of the electrically conductive layers in the alternating stack; a memory-side dielectric material layer disposed over the alternating stack; a memory-side metal interconnect structure comprising a bit line and a memory-side bonding pad embedded within the memory-side dielectric material layer; and a first logic die comprising a first logic-side bonding pad electrically bonded to the memory-side bonding pad. A device structure comprising a back dielectric material layer disposed below the source layer and embedding a back metal interconnect structure and a back bonding pad, wherein a first subset of the back metal interconnect structure is electrically connected to each of the contact via structures and a second subset of the back metal interconnect structure is electrically connected to the source layer. Claim 12 A device structure according to claim 11, further comprising a second logic die including a second logic side bonding pad electrically bonded to the back bonding pad. Claim 13 A device structure according to claim 12, wherein the first logic die comprises a bit line driver circuit electrically connected to the bit line; and the second logic die comprises a word line driver circuit electrically connected to the electrically conductive layer through the contact via structure. Claim 14 In claim 10, the device structure comprises a first logic die including a bit line driver circuit electrically connected to the bit line, and a word line driver circuit electrically connected to the electrically conductive layer through the contact via structure. Claim 15 A method for forming a device structure, comprising: forming an alternating stack of a sacrificial material layer and an insulating layer including a dielectric material on a carrier substrate; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein each of the memory opening filling structures includes a vertical stack of memory elements and a vertical semiconductor channel; forming a lateral isolation trench and an access via cavity in the alternating stack, wherein each of the sacrificial material layers is exposed to each of the lateral isolation trenches and the access via cavity has varying depths; forming a lateral recess by isotropically recessing the sacrificial material layer around the lateral isolation trench and the access via cavity, wherein the lateral range of the lateral recess is different and the remainder of the sacrificial material layer includes a dielectric material layer; forming an electrically conductive layer in the lateral recess; forming a lateral isolation trench filling structure and a via filling pillar structure in the lateral isolation trench and the access via cavity, respectively; and forming a contact via cavity through each subset of the dielectric material layer and A method comprising: forming on the horizontal surface of each of the electrically conductive layers through each subset of the insulating layers; and forming a contact via structure in the contact via cavity in contact with the electrically conductive layer. Claim 16 A method according to claim 15, further comprising the step of forming a source layer in contact with the memory opening filling structure. Claim 17 In claim 16, the source layer is formed on or above the carrier substrate; the method further comprises the step of removing the carrier substrate, wherein the contact via cavity is formed after the removal of the carrier substrate. Claim 18 In claim 16, the alternating stack is formed on a carrier substrate; the source layer is formed on the alternating stack; and the method further comprises the step of removing the carrier substrate after forming the source layer. Claim 19 A method according to claim 15, wherein the access via cavity is arranged along a first horizontal direction within a uniform pitch; and the contact via cavity is arranged along the first horizontal direction with the uniform pitch and laterally offset from the access via cavity along a second horizontal direction perpendicular to the first horizontal direction. Claim 20 A method according to claim 15, further comprising the step of forming a support wall structure including an insulating material through the alternating stack, wherein the lateral isolation trench and the access via cavity are formed on opposite sides of the support wall structure; each of the support wall structures includes a cross section perpendicular to the longitudinal direction of the lateral isolation trench; each of the support wall structures is intersected by each pair of the lateral isolation trenches; and the lateral recess is formed by performing an isotropic etching process that isotropically recesses the sacrificial material layer optionally in the insulating material of the support wall structure.

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