Display device

Abstract

A display device according to one embodiment comprises: a substrate having a display area including a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and having a scan line connected to the pixel and extended along a first direction; and a second conductive layer disposed on the first conductive layer and having a high-voltage power line connected to the pixel disposed thereon, wherein the high-voltage power line includes a hole outer high-voltage power line surrounding the sensor non-display area in a planar manner.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] An organic light-emitting display device comprises organic light-emitting diodes composed of a hole injection electrode, an organic light-emitting layer, and an electron injection electrode. Each organic light-emitting diode emits light due to the energy generated when an exciton, created by the combination of an electron and a hole within the organic light-emitting layer, falls from an excited state to a ground state, and the organic light-emitting display device displays a predetermined image using this light emission.

[0003] Organic light-emitting displays (OLEDs) possess self-luminous characteristics and, unlike liquid crystal displays (LCDs), do not require a separate light source, allowing for reduced thickness and weight. Furthermore, OLEDs are attracting attention as next-generation display devices due to their high-quality characteristics, such as low power consumption, high brightness, and fast response speeds.

[0004] Meanwhile, organic light-emitting display devices require a process of encapsulating pixels using a glass substrate or the like to protect them. However, due to the thickness and weight of glass substrates, technology is currently being developed to form a thin film encapsulation (TFE) layer by alternately stacking inorganic and organic films one or more times. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device with improved high-voltage power supply stability.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A display device according to one embodiment for solving the above problem comprises: a substrate having a display area including a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and having a scan line connected to the pixel and extended along a first direction; and a second conductive layer disposed on the first conductive layer and having a high-voltage power line connected to the pixel disposed thereon, wherein the high-voltage power line includes a hole outer high-voltage power line surrounding the sensor non-display area in a planar manner.

[0008] A display device according to another embodiment for solving the above problem comprises: a substrate having a display area including a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and including a scan line connected to the pixel and extended along a first direction; a second conductive layer disposed on the first conductive layer; and a third conductive layer disposed on the second conductive layer and including a data line connected to the pixel and extended along a second direction intersecting the first direction, wherein the high-voltage power line includes a hole-outside high-voltage power line surrounding the sensor non-display area in a planar manner, and the hole-outside high-voltage power line is composed of two or more layers.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0010] According to the display device according to the embodiments, the stability of the supply of high-voltage power can be improved.

[0011] In addition, at the intersection point between the hole-outside high-voltage power wiring and the scan wiring, the hole-outside high-voltage power wiring includes a connecting high-voltage power wiring section, thereby preventing a short circuit between the scan wiring and the hole-outside high-voltage power wiring.

[0012] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0013] FIG. 1 is a plan view of a display device according to one embodiment. FIG. 2 is a plan view showing in detail the high-voltage power wiring, data wiring, and scan wiring of the display device according to FIG. 1. Figure 3 is a cross-sectional view taken along the lines I-I' and II-II' of Figure 1. Figure 4 is an enlarged plan view of area A of Figure 2. Figure 5 is an enlarged plan view of area B of Figure 4. Figure 6 is a cross-sectional view taken along the lines III-III' and IV-IV' of Figure 5. FIG. 7 is a plan view of a display device according to another embodiment. FIG. 8 is a plan view of a display device according to another embodiment. Figure 9 is a cross-sectional view taken along the lines III-III' and IV-IV' of Figure 8. FIG. 10 is a plan view of a display device according to another embodiment. FIG. 11 is a plan view of a display device according to another embodiment. FIG. 12 is a cross-sectional view taken along the lines III-III' and IV-IV' of FIG. 11. FIG. 13 is a plan view of a display device according to another embodiment. FIG. 14 is a cross-sectional view of a display device according to another embodiment. FIG. 15 is a cross-sectional view of a display device according to another embodiment. Specific details for implementing the invention

[0014] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0015] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0016] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0017] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0018] Specific embodiments will be described below with reference to the attached drawings.

[0019] FIG. 1 is a plan view of a display device according to one embodiment.

[0020] Referring to FIG. 1, the display device according to one embodiment may be an organic light-emitting display device, but is not limited thereto and may be a liquid crystal display device or an inorganic light-emitting display device. Hereinafter, the description will focus on the fact that the display device according to one embodiment is an organic light-emitting display device. The organic light-emitting display device may include a display panel (100). The display panel (100) may include a display area (DA), a first non-display area (NDA1) located around the display area (DA), and a second non-display area (NDA2) (or sensor non-display area) surrounded by the display area (DA). The display area (DA) and the non-display areas (NDA1, NDA2) may each be defined on a substrate (101) to be described later. Meanwhile, the display panel (100) may further include a sensor hole (SH) (or sensor hole area) surrounded by the second non-display area (NDA2). The sensor hole (SH) may be completely surrounded by the second non-display area (NDA2) on a plane. A sensor may be placed in the sensor hole (SH). The sensor may be a camera sensor, but is not limited thereto and may include various sensors in the field of the art, such as an infrared sensor. Although the sensor hole (SH) is shown as one in FIG. 1, it is not limited thereto and may be provided in multiple sensor holes (SH).

[0021] The display area (DA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix array manner. The display area (DA) may have a rectangular shape including long sides extended along a first direction (DR1) and short sides extended along a second direction (DR2), but is not limited thereto.

[0022] The first non-display area (NDA1) may surround the display area (DA) in a planar manner. The first non-display area (NDA1) may include a pad area. The pad area may be positioned on the other end of the second direction (DR2) of the display panel (100). However, it is not limited thereto.

[0023] A chip-on-film (200) may be attached to the pad area. A driving chip (D_IC) may be mounted on the chip-on-film (200). A printed circuit board (300) may be attached to the other end of the second direction (DR2) of the chip-on-film (200). In FIG. 1, the driving chip (D_IC) is shown mounted on the chip-on-film (200) as an example, but is not limited thereto, and the driving chip (D_IC) may be mounted directly on the display panel (100). A plurality of chip-on-films (200) may be provided and arranged along the first direction (DR1).

[0024] A power management integrated circuit (PMIC: Power Management IC, 310) and a controller (330) may be mounted on the printed circuit board (300). The controller (330) can perform overall control functions related to the driving of the display panel (100) and can control the operation of the driving chip (D_IC) and the gate driver (GD). The power management integrated circuit (310) can supply various voltages or currents to the driving chip (D_IC) and the gate driver (GD), or control various voltages or currents to be supplied. The gate driver (GD) may, for example, be placed on one side of the first direction (DR1) of the display area (DA) or on the first non-display area (NDA1) on the other side of the first direction (DR1), but is not limited thereto.

[0025] The gate driver (GD) supplies a scan signal (SC) to the gate line (GL) according to the gate control signal (GCS) supplied from the controller (400). The gate driver (GD) may be positioned on one or both sides of the display panel (100) in a GIP (Gate In Panel) manner.

[0026] The gate driver (GD) sequentially outputs gate signals to a plurality of gate lines (see SL1 and SL2 in FIG. 2) under the control of the controller (400). The gate driver (GD) can sequentially supply the signals to the gate lines (see SL1 and SL2 in FIG. 2) by shifting the gate signals using a shift register.

[0027] The gate signal may include a scan signal (SC) and a light emission control signal (EM) in an organic light-emitting display device. The scan signal (SC) includes a scan pulse that swings between a gate-on voltage (VGL) and a gate-off voltage (VGH). The light emission control signal may include a light emission control signal pulse that swings between a gate-on voltage (VEL) and a gate-off voltage (VEH).

[0028] The scan pulse selects the pixels on the line to be written to, synchronized with the data voltage. The light emission control signal defines the light emission time of the pixels.

[0029] The gate driver (GD) may include a light emission control signal driver (GD1), a first scan driver (GD2), and a second scan driver (GD3).

[0030] The light emission control signal driving unit (GD1) outputs a light emission control signal pulse in response to a start pulse and a shift clock from the controller (400), and sequentially shifts the light emission control signal pulse according to the shift clock.

[0031] The first scan drive unit (GD2) and the second scan drive unit (GD3) output a scan pulse in response to a start pulse and a shift clock from the controller (400), and shift the scan pulse in accordance with the shift clock timing.

[0032] Referring to FIG. 1, the light emission control signal driver (GD1) may be positioned at the outermost side of the gate driver (GD). However, it is not limited thereto, and depending on the embodiment, it may be positioned between the first scan driver (GD2) and the second scan driver (GD3), or between the first scan driver (GD2) and the second scan driver (GD3) and the display panel (100).

[0033] FIG. 2 is a plan view showing in detail the high-voltage power wiring, data wiring, and scan wiring of the display device according to FIG. 1.

[0034] Referring to FIG. 2, the display panel (100) may include high-voltage power wiring, data wiring, and scan wiring. The high-voltage power wiring, the data wiring, and the scan wiring may each be electrically connected to a pixel (PX).

[0035] The above scan wiring is connected to a gate driver (GD) and can be extended along a first direction (DR1). The above scan wiring may be provided in multiple numbers and arranged spaced apart along a second direction (DR2). The multiple scan wirings may include, for example, a first scan wiring (SL1) and a second scan wiring (SL2). The first scan wiring (SL1) may be extended along the first direction (DR1) without being bent, whereas the second scan wiring (SL2) may generally be extended along the first direction (DR1) but may be extended by bypassing a planar sensor hole (SH) in a second non-display area (NDA2). In the second non-display area (NDA2), the second scan wiring (SL2) may have a planar curved shape.

[0036] The above data wiring is connected to a driving chip (D_IC) and can be extended along a second direction (DR2). The data wiring may be provided in multiple numbers and arranged spaced apart along a first direction (DR1). The multiple data wirings may include, for example, a first data wiring (DL1) and a second data wiring (DL2). The first data wiring (DL1) may be extended along the second direction (DR2) without being bent, whereas the second data wiring (DL2) may generally be extended along the second direction (DR2) but may be extended by bypassing a planar sensor hole (SH) in a second non-display area (NDA2). In the second non-display area (NDA2), the second data wiring (DL2) may have a planar curved shape.

[0037] The above high-voltage power wiring is connected to a pixel (PX) and can be electrically connected to the anode electrode (AND in FIG. 3) of the organic light-emitting element (OLED in FIG. 3) of the pixel (PX).

[0038] As shown in FIG. 2, the above high-voltage power wiring may include a fan-out power wiring (VDDL_F), a main power wiring (VDDL_M), a first power wiring (VDDL1), a second power wiring (VDDL2), a third power wiring (VDDL3), and a hole-out power wiring (VDDL_R). The fan-out power wiring (VDDL_F) may connect the power management integrated circuit (310) and the main power wiring (VDDL_M). The fan-out power wiring (VDDL_F) may pass through the chip-on-film (200). The fan-out power wiring (VDDL_F) may receive a high-voltage power signal from the power management integrated circuit (310) and provide it to the main power wiring (VDDL_M). The main power wiring (VDDL_M) may be placed in the non-display area (NDA). The main power wiring (VDDL_M) may surround the display area (DA) in a planar manner. The main power wiring (VDDL_M) can completely surround the planar display area (DA). Power wiring (VDDL1, VDDL2, VDDL3, VLDDL_R) can connect the main power wiring (VDDL_M) on one side of the second direction (DR2) with the main power wiring (VDDL_M) on the other side of the second direction (DR2). For example, the first power wiring (VDDL1) can directly connect the main power wiring (VDDL_M) on one side of the second direction (DR2) with the main power wiring (VDDL_M) on the other side of the second direction (DR2). The first power wiring (VDDL1) can be extended along the second direction (DR2) and can be provided in multiple numbers. Multiple first power wirings (VDDL1) can be spaced apart and arranged along the first direction (DR1).

[0039] The second power wiring (VDDL2), like the first power wiring (VDDL1), directly connects the main power wiring (VDDL_M) on one side of the second direction (DR2) and the main power wiring (VDDL_M) on the other side of the second direction (DR2), and can also directly contact the adjacent outer hole power wiring (VDDL_R).

[0040] The third power line (VDDL3) can be connected to one end of the second direction (DR2) and the other end of the second direction (DR20) of the hole outer power line (VDDL_R), respectively.

[0041] The power wiring around the hole (VDDL_R) can completely surround the sensor hole (SH) on the plane. The power wiring around the hole (VDDL_R) can completely surround the second non-display area (NDA2) on the plane and can be placed in the display area (DA).

[0042] Figure 3 is a cross-sectional view taken along the lines I-I' and II-II' of Figure 1.

[0043] Referring to FIG. 3, a display panel (100 of FIG. 1) comprises a substrate (101), a barrier layer (111) on the substrate (101), a light-blocking layer (LS) on the barrier layer (111), a buffer layer (112) on the light-blocking layer (LS), a semiconductor layer (ACT) on the buffer layer (112), a gate insulating layer (113) on the semiconductor layer (ACT), a first conductive layer (120) on the gate insulating layer (113), a first interlayer insulating layer (114) on the first conductive layer (120), a second conductive layer (130) on the first interlayer insulating layer (114), a second interlayer insulating layer (115) on the second conductive layer (130), a third conductive layer (140) on the second interlayer insulating layer (115), a flattening layer (132) on the third conductive layer (140), an anode electrode (ANO) on the flattening layer (116), and a pixel on the anode electrode (ANO). It may include a pixel definition film (151), an organic layer (OL) on the pixel definition film (151), a cathode electrode (CAT) on the organic layer (OL), a capping layer (CPL) on the cathode electrode (CAT), and an encapsulation layer (160) on the capping layer (CPL).

[0044] The substrate (101) can support each layer placed thereon. The base substrate can be placed across the display area (DA), sensor hole (SH), and non-display area (NDA1, NDA2). The substrate (101) can be made of an insulating material such as a polymer resin. Examples of the above polymer materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate (101) may be a flexible substrate capable of bending, folding, rolling, etc. Examples of materials that make up a flexible substrate include polyimide (PI), but are not limited thereto. The substrate (101) may be a rigid substrate made of glass, quartz, etc.

[0045] A barrier layer (111) may be disposed on the substrate (101). The barrier layer (111) may be disposed across the entire display area (DA) and non-display areas (NDA1, NDA2). The barrier layer (111) may not be disposed in the sensor hole (SH). The barrier layer (111) can prevent the diffusion of impurity ions and prevent the penetration of moisture or external air.

[0046] The barrier layer (111) may include multiple layers, unlike what is illustrated. That is, the barrier layer (111) may be composed of layers in which silicon nitride (SiNx) and silicon oxide (SiOx) are alternately stacked at least once.

[0047] A light-blocking layer (LS) may be disposed on the barrier layer (111). The light-blocking layer (LS) may overlap with the semiconductor layer (ACT) in the thickness direction. By overlapping with the semiconductor layer (ACT) from below, the light-blocking layer (LS) can prevent light from being incident on the semiconductor layer (ACT).

[0048] A buffer layer (112) may be disposed on the light-blocking layer (LS). The buffer layer (112) may be disposed across the entire display area (DA) and non-display areas (NDA1, NDA2). The buffer layer (112) may not be disposed in the sensor hole (SH). The buffer layer (112) can prevent the diffusion of impurity ions and prevent the penetration of moisture or outside air.

[0049] The buffer layer (112) may include multiple layers, unlike what is shown. That is, the buffer layer (112) may be composed of layers in which silicon nitride (SiNx) and silicon oxide (SiOx) are alternately stacked at least once.

[0050] A semiconductor layer (ACT) may be disposed on the buffer layer (112). The semiconductor layer (ACT) may include polycrystalline silicon. The semiconductor layer (ACT) may have a channel region, a source region, and a drain region. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of the crystallization method include, but are not limited to, the rapid thermal annealing (RTA) method, solid phase crystallization (SPC) method, excimer laser annealing (ELA) method, metal induced crystallization (MIC) method, metal induced lateral crystallization (MILC) method, and sequential lateral solidification (SLS) method. In some embodiments, the semiconductor layer (ACT) may include an oxide semiconductor. The oxide semiconductor may include, for example, binary compounds (ABx), ternary compounds (ABxCy), and quaternary compounds (ABxCyDz) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc.

[0051] A gate insulating layer (113) may be disposed on the semiconductor layer (ACT). The gate insulating layer (113) may generally be disposed across the display area (DA) and the non-display area (NDA1, NDA2), but may not be disposed in the sensor hole (SH). The gate insulating layer (113) may be a gate insulating film having a gate insulating function. The gate insulating layer (113) may include silicon compounds, metal oxides, etc. For example, the gate insulating layer (113) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These may be used alone or in combination with each other. Although the drawing shows the gate insulating layer (113) as being composed of a single film, in some cases, the gate insulating layer (113) may be a multilayer film composed of stacked films of different materials.

[0052] A first conductive layer (120) can be disposed on the gate insulating layer (113).

[0053] In one embodiment, the first conductive layer (120) may include a gate electrode (GE) and a first electrode of a holding capacitor. In addition, the first conductive layer (120) may further include scan lines (SL1, SL2 in FIG. 2) that transmit a scan signal to the gate electrode (GE). The gate electrode (GE) may be positioned to overlap with the channel region of the semiconductor layer (ACT). Meanwhile, the first conductive layer (120) may further include a first connecting electrode (CNE1) connected to a light-blocking layer (LS).

[0054] The gate electrode (GE) and the first electrode of the holding capacitor can be formed from the same material under the same process. For example, the first conductive layer (120) may each include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Additionally, although the drawing only illustrates the case where the first conductive layer (120) is a single film, the first conductive layer (120) may, in some cases, be formed as a multilayer film. In this case, the multilayer film of the first conductive layer (120) may be formed as a stack of different metals among the metals described above.

[0055] A first interlayer insulating layer (114) may be disposed on the first conductive layer (120). The first interlayer insulating layer (114) may be disposed across the display area (DA) and the non-display area (NDA), but may not be disposed in the sensor hole (SH).

[0056] The first interlayer insulating layer (114) can insulate the first conductive layer (120) and the second conductive layer (130). The first interlayer insulating layer (114) may be an interlayer insulating film.

[0057] The first interlayer insulating layer (114) may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, or organic insulating materials such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB). Although the first interlayer insulating layer (114) is shown as a single film in the drawing, it is not limited thereto and may be a multilayer film composed of laminated films containing different materials.

[0058] A second conductive layer (130) may be disposed on the first interlayer insulating layer (114). The second conductive layer (130) may include a second electrode of a holding capacitor. The second electrode may overlap with the first electrode with the first interlayer insulating layer (114) in between. That is, the first electrode and the second electrode may form a holding capacitor (Cst) in which the first interlayer insulating layer (114) is a dielectric film. In addition, the second conductive layer (130) may include high-voltage power wiring (VDDL_F, VDDL_M, VDDL1, VDDL2, VDDL3, VDDL_R). That is, the high-voltage power wiring (VDDL_F, VDDL_M, VDDL1, VDDL2, VDDL3, VDDL_R) may be composed of the second conductive layer (130).

[0059] The second conductive layer (130) may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). In one embodiment, the second conductive layer (130) may be made of the same material as the first conductive layer (120) described above.

[0060] In the drawing, a second conductive layer (130) of a single film is shown, but in some cases, the second conductive layer (130) may be made of a multilayer film.

[0061] A second interlayer insulating layer (115) is disposed on the second conductive layer (130). The second interlayer insulating layer (115) can insulate the second conductive layer (130) and the third conductive layer (140).

[0062] The second interlayer insulating layer (115) may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, or organic insulating materials such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB).

[0063] The second interlayer insulating layer (115) generally covers the second conductive layer (130) of the display area (DA) and may also be placed in the non-display area (NDA1, NDA2). The second interlayer insulating layer (115) may not be placed in the sensor hole (SH).

[0064] A third conductive layer (140) may be disposed on the second interlayer insulating layer (115). In one embodiment, the third conductive layer (140) may include a first source-drain electrode (SD1) and a second source-drain electrode (SD2). The first source-drain electrode (SD1) may be connected to the source region of the semiconductor layer (ACT), and the second source-drain electrode (SD2) may be connected to the drain region of the semiconductor layer (ACT). The second source-drain electrode (SD2) may also be connected to the first connecting electrode (CNE1) of the first conductive layer (120). In addition, the third conductive layer (140) may further include the data line (DL) of FIG. 2.

[0065] The third conductive layer (140) may include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and molybdenum (Mo). The third conductive layer (140) may each be a single film as shown in the drawing. However, it is not limited thereto, and the third conductive layer (140) may be a multilayer film. For example, the third conductive layer (140) may be formed with a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0066] A flattening layer (116) may be disposed on the third conductive layer (140). The flattening layer (116) may include an organic insulating material such as an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ethers resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0067] The flattening layer (116) is placed in the display area (DA) and may not be placed in the second non-display area (NDA2) and the sensor hole (SH).

[0068] The anode electrode (ANO) may be disposed on the planarization layer (116). The anode electrode (ANO) may include a connecting electrode (CNE). The connecting electrode (CNE) may be connected to the source electrode (SDE) described above by penetrating the planarization layer (116) and the passivation layer (131).

[0069] The anode electrode (ANO) may include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and molybdenum (Mo). The anode electrode (ANO) may each be a single film as shown in the drawing. However, it is not limited thereto, and the anode electrode (ANO) may be a multilayer film. For example, the anode electrode (ANO) may be formed with a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0070] A pixel defining film (151) may be disposed on the anode electrode (ANO). The pixel defining film (151) may include an opening that exposes the anode electrode (ANO). The pixel defining film (151) may be made of an organic insulating material or an inorganic insulating material. In one embodiment, the pixel defining film (151) may include materials such as photoresist, polyimide-based resin, acrylic-based resin, silicone compound, or polyacrylic-based resin.

[0071] An organic layer (OL) may be disposed within the upper surface of the anode electrode (ANO) and the opening of the pixel defining film (151). Although the drawing shows the organic layer (OL) disposed only within the opening of the pixel defining film (151), it is not limited thereto, and the organic layer (OL) may be disposed extending from the opening of the pixel defining film (151) to the upper surface of the pixel defining film (151).

[0072] The organic layer (OL) may include an organic light-emitting layer, a hole injection / transport layer, and an electron injection / transport layer.

[0073] The organic layer (OL) can be placed on the display area (DA).

[0074] A cathode electrode (CAT) is disposed on the organic layer (OL) and the pixel definition film (151). The cathode electrode (CAT) may be a common electrode disposed across a plurality of pixels (PX) of the display area (DA). The organic layer (OL), the anode electrode (ANO), and the cathode electrode (CAT) may form an organic light-emitting diode (OLED).

[0075] An encapsulation layer (160) is disposed on the cathode electrode (CAT). The encapsulation layer (160) can cover an organic light-emitting diode (OLED). The encapsulation layer (160) may be a laminated film in which an inorganic film and an organic film are alternately stacked. For example, the encapsulation layer (160) may include a first inorganic film (161), an organic film (162), and a second inorganic film (163) that are sequentially stacked. The first inorganic film (161), the organic film (162), and the second inorganic film (163) may be disposed across the entire display area (DA) and may also be disposed in the second non-display area (NDA2). However, they may not be disposed in the sensor hole (SH).

[0076] As described above, no upper stacked structure other than the substrate (101) may be disposed in the sensor hole (SH). However, this is not limited thereto, and a barrier layer (111) may be disposed on the sensor hole (SH).

[0077] FIG. 4 is an enlarged plan view of area A of FIG. 2. FIG. 15 is an enlarged plan view of area B of FIG. 4. FIG. 6 is a cross-sectional view taken along the lines III-III' and IV-IV' of FIG. 15.

[0078] Referring to FIGS. 4 to 6, the second scan line (SL2) may intersect in a plane with the second power wiring (VDDL2) and the outer power wiring (VDDL_R), and may also intersect with the first and second data lines (DL1, DL2).

[0079] The first data line (DL1) may intersect the hole outer power wiring (VDDL_R) and the second scan line (SL2) in a plane.

[0080] The second data line (DL2) can intersect the second scan line (SL2) in a plane.

[0081] The third power wiring (VDDL3) may include a third-1 power wiring section (VDDL3a) and a third-2 power wiring section (VDDL3b). The third-1 power wiring section (VDDL3a) and the third-2 power wiring section (VDDL3b) may each extend along the second direction (DR2). The third-1 power wiring section (VDDL3a) may be connected to one end of the second direction (DR2) of the hole outer power wiring (VDDL_R), and the third-2 power wiring section (VDDL3b) may be connected to the other end of the second direction (DR2) of the hole outer power wiring (VDDL_R). That is, the hole outer power wiring section (VDDL_R) may be positioned between the third-1 power wiring section (VDDL3a) and the third-2 power wiring section (VDDL3b).

[0082] Conventionally, the outer power wiring section (VDDL_R) was not positioned around the sensor hole (SH), so the 3-1 power wiring section (VDDL3a) and the 3-2 power wiring section (VDDL3b) were physically separated. The magnitude of the high-voltage power supplied to the integrally formed 1st or 2nd power wiring (VDDL1, VDDL2) and the magnitude of the high-voltage power supplied to the 3-1 power wiring section (VDDL3a) and the 3-2 power wiring section (VDDL3b), respectively, could be significantly different. In this case, the magnitude of the luminance of light generated in the pixel (PX in FIG. 2) connected to the 3-1 power wiring section (VDDL3a) and the pixel (PX in FIG. 2) connected to the 3-2 power wiring section (VDDL3b) may be significantly different from the magnitude of the luminance of light generated in the pixel (PX in FIG. 2) connected to the 1st or 2nd power wiring (VDDL1, VDDL2), so luminance non-uniformity may occur between pixels (PX) within the display area (DA).

[0083] However, in the case of a display device (1) according to one embodiment, a hole-outer power wiring section (VDDL_R) that completely surrounds the sensor hole (SH) in a plane is further disposed between the third-1 power wiring section (VDDL3a) and the third-2 power wiring section (VDDL3b) which are spaced apart with the sensor hole (SH) in between, and the third-1 power wiring section (VDDL3a) can be connected to one end of the second direction (DR2) of the hole-outer power wiring (VDDL_R), and the third-2 power wiring section (VDDL3b) can be connected to the other end of the second direction (DR2) of the hole-outer power wiring (VDDL_R), thereby preventing in advance the occurrence of non-uniformity in brightness between pixels (PX) within the above-mentioned display area (DA).

[0084] As illustrated in FIG. 6, the second scan line (SL2) can be placed in the first conductive layer (see 120 in FIG. 3), the third power line (VDDL3) and the hole outer power line (VDDL_R) can be placed in the second conductive layer (see 130 in FIG. 3), the hole outer power line (VDDL_R) can overlap with the second scan line (SL2), and the second data line (DL2) can be placed in the third conductive layer (see 140 in FIG. 3) and can overlap with the second scan line (SL2).

[0085] In the case of a display device (1) according to one embodiment, the width (W2) of the outer power wiring section (VDDL_R) of the hole may be the same as the width (W1) of each of the first or second power wiring sections (VDDL1, VDDL2) or the width (W1) of the third power wiring section (VDDL3a, VDDL3b).

[0086] Hereinafter, other embodiments of the display device (1) according to one embodiment will be described.

[0087] FIG. 7 is a plan view of a display device according to another embodiment.

[0088] Referring to FIG. 7, the display device according to FIG. 15 is different in that the width (W2_1) of the outer power wiring section (VDDL_R) of the hole is different from the width (W1_1) of each of the first or second power wiring (VDDL1, VDDL2) or the width (W1_1) of the third power wiring section (VDDL3a, VDDL3b).

[0089] To explain more specifically, the width (W2_1) of the outer power wiring section (VDDL_R) of the hole may be larger than the width (W1_1) of each of the first or second power wiring sections (VDDL1, VDDL2) or the width (W1_1) of the third power wiring section (VDDL3a, VDDL3b).

[0090] The length of the line leading to the third-1 power wiring section (VDDL3a), the hole outer power wiring section (VDDL_R), and the third-2 power wiring section (VDDL3b) according to the present embodiment may be longer than the length of each of the first or second power wirings (VDDL1, VDDL2). Since the sensor hole (SH) of the hole outer power wiring section (VDDL_R) is completely surrounded, the actual length of the line leading to the third-1 power wiring section (VDDL3a), the hole outer power wiring (VDDL_R), and the third-2 power wiring section (VDDL3b) may be much longer than the length of each of the first or second power wirings (VDDL1, VDDL2).

[0091] In this case, there may be a difference in internal resistance between the lines leading to the 3-1 power wiring section (VDDL3a), the hole outer power wiring (VDDL_R), and the 3-2 power wiring section (VDDL3b), and the respective lines of the 1st or 2nd power wiring (VDDL1, VDDL2). This difference in internal resistance between each power wiring may cause luminance non-uniformity among pixels (PX) within the display area (DA).

[0092] However, in the case of the display device (1) according to the present embodiment, by designing the width (W2_1) of the hole outer power wiring section (VDDL_R) to be larger than the width (W1_1) of each of the first or second power wiring (VDDL1, VDDL2) or the width (W1_1) of the third power wiring section (VDDL3a, VDDL3b), the difference in internal resistance between the line leading to the third-1 power wiring section (VDDL3a), the hole outer power wiring (VDDL_R), and the third-2 power wiring section (VDDL3b) and the line of each of the first or second power wiring (VDDL1, VDDL2) can be reduced. As a result, there is an advantage in that luminance non-uniformity between pixels (PX) within the display area (DA) can be prevented in advance.

[0093] FIG. 8 is a plan view of a display device according to another embodiment. FIG. 9 is a cross-sectional view taken along the lines III-III' and IV-IV' of FIG. 8.

[0094] Referring to FIGS. 8 and 9, the hole outer power wiring (VDDL_R_1) is different from the display device according to FIG. 15 in that it includes a first hole outer power wiring section (VDDL_R_1a) and a second hole outer power wiring section (VDDL_R_1b).

[0095] More specifically, the hole outer power wiring (VDDL_R_1) may include a first hole outer power wiring section (VDDL_R_1a) and a second hole outer power wiring section (VDDL_R_1b). The first hole outer power wiring section (VDDL_R_1a) may be located on one side of the second direction (DR2) of the second scan line (SL2), and the second hole outer power wiring section (VDDL_R_1b) may be located on the other side of the second direction (DR2) of the second scan line (SL2). The first hole outer power wiring section (VDDL_R_1a) and the second hole outer power wiring section (VDDL_R_1b) may be spaced apart on a plane with the second scan line (SL2) in between.

[0096] The hole outer power wiring (VDDL_R_1) may further include a connecting wiring section (VDDL_CN). The connecting wiring section (VDDL_CN) may intersect the second scan line (SL2) in a planar manner. The connecting wiring section (VDDL_CN) may be placed on the third conductive layer (140 in FIG. 3). The connecting wiring section (VDDL_CN) may be placed on the same layer as the second data line (DL2). One end of the second direction (DR2) of the connecting wiring section (VDDL_CN) may be connected to the first hole outer power wiring section (VDDL_R_1a) through the first contact hole (CNT1), and the other end of the second direction (DR2) of the connecting wiring section (VDDL_CN) may be connected to the second hole outer power wiring section (VDDL_R_1b) through the second contact hole (CNT2). The contact holes (CNT1, CNT2) can penetrate the second interlayer insulating layer (115).

[0097] According to the present embodiment, by including a connecting wiring portion (VDDL_CN) disposed in the third conductive layer (140) in the area where the hole outer power wiring (VDDL_R_1) intersects the second scan line (SL2), the separation distance in the thickness direction from the second scan line (SL2) can be increased compared to when the first hole outer power wiring portion (VDDL_R_1a) or the second hole outer power wiring portion (VDDL_R_1b) is disposed in the area intersecting the second scan line (SL2). As a result, there is an advantage in that a short circuit between the hole outer power wiring (VDDL_R_1) and the second scan line (SL2) can be prevented in advance.

[0098] Other explanations are described in detail in FIGS. 5 and FIGS. 6, so further detailed explanations will be omitted.

[0099] FIG. 10 is a plan view of a display device according to another embodiment.

[0100] Referring to FIG. 10, the second power wiring (VDDL2_1) is different from the display device according to FIG. 8 in that it includes a second-1 power wiring section (VDDL2_1a) and a second-2 power wiring section (VDDL2_1b).

[0101] More specifically, the second power wiring (VDDL2_1) may include a second-1 power wiring section (VDDL2_1a) and a second-2 power wiring section (VDDL2_1b). The second-1 power wiring section (VDDL2_1a) may be located on one side of the second direction (DR2) of the second scan line (SL2), and the second-2 power wiring section (VDDL2_1b) may be located on the other side of the second direction (DR2) of the second scan line (SL2). The second-1 power wiring section (VDDL2_1a) and the second-2 power wiring section (VDDL2_1b) may be spaced apart on a plane with the second scan line (SL2) in between.

[0102] The second power wiring (VDDL2_1) may further include a connecting wiring section (VDDL_CNa). The connecting wiring section (VDDL_CNa) may intersect the second scan line (SL2) in a planar manner. The connecting wiring section (VDDL_CNa) may be placed on the third conductive layer (140 in FIG. 3). The connecting wiring section (VDDL_CNa) may be placed on the same layer as the second data line (DL2) and the connecting wiring section (VDDL_CN). One end of the second direction (DR2) of the connecting wiring section (VDDL_CNa) may be connected to the second-1 power wiring section (VDDL2_1a) through the third contact hole (CNT3), and the other end of the second direction (DR2) of the connecting wiring section (VDDL_CNa) may be connected to the second-2 power wiring section (VDDL2_1b) through the fourth contact hole (CNT4). The contact holes (CNT3, CNT4) can penetrate the second interlayer insulation layer (115).

[0103] According to the present embodiment, by including a connecting wiring portion (VDDL_CNa) disposed in the third conductive layer (140) in the area where the second power wiring (VDDL2_1) intersects the second scan line (SL2), the separation distance in the thickness direction from the second scan line (SL2) can be increased compared to when the second-1 power wiring portion (VDDL2_1a) or the second-2 power wiring portion (VDDL2_1b) is disposed in the area where it intersects the second scan line (SL2). As a result, there is an advantage in that a short circuit between the second power wiring (VDDL2_1) and the second scan line (SL2) can be prevented in advance.

[0104] Other explanations are detailed in Fig. 8, so further detailed explanations will be omitted below.

[0105] FIG. 11 is a plan view of a display device according to another embodiment. FIG. 12 is a cross-sectional view taken along the lines III-III' and IV-IV' of FIG. 11.

[0106] Referring to FIGS. 11 and 12, the display device according to the present embodiment differs from the display device according to FIGS. 8 and 9 in that the power wiring outside the hole can be composed of two or more layers.

[0107] To explain more specifically, the hole outer power wiring according to the present embodiment may include a first hole outer power wiring layer (VDDL_R) and a second hole outer power wiring layer (VDDL_R_2). Since the first hole outer power wiring layer (VDDL_R) has the same structure as the hole outer power wiring (VDDL_R) of FIGS. 8 and FIGS. 9, a detailed description will be omitted.

[0108] The second hole outer power wiring layer (VDDL_R_2) may include a second-1 hole outer power wiring section (VDDL_R_2a) and a second-2 hole outer power wiring section (VDDL_R_2b). The second-1 hole outer power wiring section (VDDL_R_2a) may be located on one side of the second direction (DR2) of the second scan line (SL2), and the second-2 hole outer power wiring section (VDDL_R_2b) may be located on the other side of the second direction (DR2) of the second scan line (SL2). The second-1 hole outer power wiring section (VDDL_R_2a) and the second-2 hole outer power wiring section (VDDL_R_2b) may be spaced apart on a plane with the second scan line (SL2) in between. The 2-1 hole outer power wiring section (VDDL_R_2a) and the 2-2 hole outer power wiring section (VDDL_R_2b) can be placed on the same floor as the 2 scan line (SL2).

[0109] The 2-1 hole outer power wiring section (VDDL_R_2a) or the 2-2 hole outer power wiring section (VDDL_R_2b) can be connected to the 1 hole outer power wiring layer (VDDL_R) through the 5th contact hole (CNT5). The 5th contact hole (CNT5) can penetrate the 1st interlayer insulation layer (114).

[0110] According to the present embodiment, the hole outer power wiring is composed of a first hole outer power wiring layer (VDDL_R) and a second hole outer power wiring layer (VDDL_R_2) disposed on different layers, thereby having the advantage of lowering the resistance of the hole outer power wiring.

[0111] FIG. 13 is a plan view of a display device according to another embodiment.

[0112] Referring to FIG. 13, the display device according to the present embodiment is different from the display device according to FIG. 11 and FIG. 12 in that the second power wiring of the display device according to the present embodiment can be composed of two or more layers.

[0113] To explain more specifically, the second power wiring according to the present embodiment may include a first power wiring layer (VDDL2) and a second power wiring layer (VDDL2_2). Since the first power wiring layer (VDDL2) has the same structure as the second power wiring (VDDL2) of FIG. 11, a detailed description will be omitted.

[0114] The second power wiring layer (VDDL2_2) may include a second-1 power wiring section (VDDL2_2a) and a second-2 power wiring section (VDDL2_2b). The second-1 power wiring section (VDDL2_2a) may be located on one side of the second direction (DR2) of the second scan line (SL2), and the second-2 power wiring section (VDDL2_2b) may be located on the other side of the second direction (DR2) of the second scan line (SL2). The second-1 power wiring section (VDDL2_2a) and the second-2 power wiring section (VDDL2_2b) may be spaced apart on a plane with the second scan line (SL2) in between. The second-1 power wiring section (VDDL2_2a) and the second-2 power wiring section (VDDL2_2b) may be placed on the same layer as the second scan line (SL2).

[0115] The 2-1 power wiring section (VDDL2_2a) or the 2-2 power wiring section (VDDL2_2b) can be connected to the 1 power wiring layer (VDDL2) through the 6th contact hole (CNT6). The 6th contact hole (CNT6) can penetrate the 1st interlayer insulation layer (114).

[0116] According to the present embodiment, the second power wiring is composed of a first power wiring layer (VDDL2) and a second power wiring layer (VDDL2_2) placed on different layers, thereby having the advantage of being able to lower the resistance of the power wiring outside the hole.

[0117] Hereinafter, cross-sectional views of a display device according to another embodiment will be described.

[0118] FIG. 14 is a cross-sectional view of a display device according to another embodiment.

[0119] Referring to FIG. 14, a thin-film transistor (TFT) for driving a light-emitting element (OLED) may be disposed on a substrate (701) in a display area (AA). The thin-film transistor (TFT) may include a semiconductor layer (715), a gate electrode (725), and source and drain electrodes (740). The thin-film transistor (TFT) is a driving transistor (DT, see FIG. 4). For convenience of explanation, only the driving transistor (DT) among the various thin-film transistors that may be included in a display device is illustrated, but other thin-film transistors such as switching transistors may also be included in the display device. Furthermore, although the thin-film transistor (TFT) in the present invention is described as having a coplanar structure, the thin-film transistor may be implemented in other structures such as a staggered structure, but is not limited thereto.

[0120] The driving transistor (DT) receives a high-potential driving voltage (EVDD) in response to a data signal supplied to the gate electrode (725) of the driving transistor (DT) and controls the current supplied to the light-emitting element (OLED) to regulate the amount of light emitted by the light-emitting element (OLED), and can maintain the light emitted by the light-emitting element (OLED) by supplying a constant current until the data signal of the next frame is supplied by the voltage charged in the storage capacitor (not shown). The high-potential supply line can be formed parallel to the data line.

[0121] As shown in FIG. 14, the thin film transistor (TFT) may have a semiconductor layer (715) disposed on a first insulating layer (710), a gate electrode (725) that overlaps the semiconductor layer (715) with a second insulating layer (720) in between, and source and drain electrodes (740) formed on a third insulating layer (735) and in contact with the semiconductor layer (715).

[0122] The semiconductor layer (715) may be a region where a channel is formed when driving a thin-film transistor (TFT). The semiconductor layer (715) may be formed of an oxide semiconductor, or may be formed of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or pentacene, but is not limited thereto. The semiconductor layer (715) may be formed on the first insulating layer (710). The semiconductor layer (715) may have a channel region, a source region, and a drain region. The channel region may overlap with the gate electrode (725) with the first insulating layer (710) in between to form a channel region between the source and drain electrodes (740). The source region is electrically connected to the source electrode (740) through a contact hole penetrating the second insulating layer (720) and the third insulating layer (735). The drain region can be electrically connected to the drain electrode (740) through a contact hole penetrating the second insulating layer (720) and the third insulating layer (735). A buffer layer (705) and a first insulating layer (710) may be disposed between the semiconductor layer (715) and the substrate (701). The buffer layer (705) can delay the diffusion of moisture and / or oxygen that has penetrated into the substrate (701). The first insulating layer (710) protects the semiconductor layer (715) and can block various types of defects entering from the substrate (701).

[0123] The top layer of the buffer layer (705) in contact with the first insulating layer (710) may be formed of a material with different etching characteristics from the remaining layers of the buffer layer (705), the first insulating layer (710), the second insulating layer (720), and the third insulating layer (735). The top layer of the buffer layer (705) in contact with the first insulating layer (710) may be formed of either silicon nitride (SiNx) or silicon oxide (SiOx). The remaining layers of the buffer layer (705), the first insulating layer (710), the second insulating layer (720), and the third insulating layer (735) may be formed of either silicon nitride (SiNx) or silicon oxide (SiOx). For example, the top layer of the buffer layer (705) in contact with the first insulating layer (710) may be formed of silicon nitride (SiNx), and the remaining layers of the buffer layer (705), the first insulating layer (710), the second insulating layer (720), and the third insulating layer (735) may be formed of silicon oxide (SiOx), but are not limited thereto.

[0124] The gate electrode (725) is formed on the second insulating layer (720) and may overlap with the channel region of the semiconductor layer (715) with the second insulating layer (720) in between. The gate electrode (725) may be formed from a first conductive material that is a single layer or a multilayer made of any one of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.

[0125] The source electrode (740) may be connected to the source region of the semiconductor layer (715) exposed through a contact hole penetrating the second insulating layer (720) and the third insulating layer (735). The drain electrode (740) may be connected to the drain region of the semiconductor layer (715) through a contact hole penetrating the second insulating layer (720) and the third insulating layer (735) facing the source electrode (740). These source and drain electrodes (740) may be formed from a second conductive material that is a single layer or a multilayer made of one or more alloys of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but is not limited thereto.

[0126] A connecting electrode (755) may be disposed between the first intermediate layer (750) and the second intermediate layer (760). The connecting electrode (755) may be exposed through a connecting electrode contact hole (156) penetrating the protective film (745) and the first intermediate layer (750) and connected to the drain electrode (740). The connecting electrode (755) may be made of a material with low resistivity that is the same or similar to that of the drain electrode (740), but is not limited thereto.

[0127] Referring to FIG. 14, a light-emitting device (OLED) including a light-emitting layer (772) may be disposed on the second intermediate layer (760) and the bank layer (765). The light-emitting device (OLED) may have an anode electrode (771), at least one light-emitting layer (772) formed on the anode electrode (771), and a cathode electrode (773) formed on the light-emitting layer (772).

[0128] The anode electrode (771) is placed on the first intermediate layer (750) through a contact hole penetrating the second intermediate layer (760) and can be electrically connected to a connecting electrode (755) exposed above the second intermediate layer (760).

[0129] The anode electrode (771) of each pixel is formed to be exposed by the bank layer (765). The bank layer (765) may be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer (765) may include a light-blocking material composed of at least one of color pigment, organic black, and carbon, but is not limited thereto.

[0130] Referring to FIG. 14, at least one light-emitting layer (772) may be formed on an anode electrode (771) of a light-emitting region provided by a bank layer (765). The at least one light-emitting layer (772) may be formed by stacking a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer (772), an electron injection layer, an electron blocking layer, and an electron transport layer on the anode electrode (771), and may be formed by stacking sequentially or in reverse order according to the light-emitting direction. In addition, the light-emitting layer (772) may have first and second light-emitting stacks facing each other with a charge generation layer in between. In this case, one of the first and second light-emitting stacks, the light-emitting layer (772), may generate blue light, and the other of the first and second light-emitting stacks, the light-emitting layer (772), may generate yellow-green light, thereby generating white light through the first and second light-emitting stacks. The white light generated in this light-emitting stack is incident on a color filter located above or below the light-emitting layer (772), thereby enabling the realization of a color image. As another example, a color image may be realized by generating color light corresponding to each pixel in each light-emitting layer (772) without a separate color filter. For example, the light-emitting layer (772) of the red pixel may generate red light, the light-emitting layer (772) of the green pixel may generate green light, and the light-emitting layer (772) of the blue pixel may generate blue light.

[0131] Referring to FIG. 14, the cathode electrode (773) is formed to face the anode electrode (771) with the light-emitting layer (772) in between and can receive a high potential driving voltage (EVDD).

[0132] The encapsulation layer (780) can block external moisture or oxygen from penetrating the light-emitting element (OLED), which is vulnerable to external moisture or oxygen. To this end, the encapsulation layer (780) may have at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the present invention, the structure of the encapsulation layer (780) in which the first encapsulation layer (781), the second encapsulation layer (782), and the third encapsulation layer (183) are sequentially stacked will be described as an example.

[0133] A first encapsulation layer (781) is formed on a substrate (701) on which a cathode electrode (773) is formed. A third encapsulation layer (183) is formed on the substrate (701) on which a second encapsulation layer (782) is formed, and may be formed to surround the upper surface, lower surface, and side of the second encapsulation layer (782) together with the first encapsulation layer (781). These first encapsulation layer (781) and third encapsulation layer (183) can minimize or prevent external moisture or oxygen from penetrating into the light-emitting element (OLED). The first encapsulation layer (781) and third encapsulation layer (183) may be formed from an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer (781) and the third encapsulation layer (183) are deposited in a low-temperature atmosphere, it is possible to prevent damage to the light-emitting element (OLED), which is vulnerable to high-temperature atmospheres, during the deposition process of the first encapsulation layer (781) and the third encapsulation layer (183).

[0134] The second encapsulation layer (782) acts as a buffer to relieve stress between layers due to bending of the display device and can flatten the step difference between layers. This second encapsulation layer (782) may be formed on a substrate (701) on which the first encapsulation layer (781) is formed using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon oxycarbon (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited thereto. When the second encapsulation layer (782) is formed using an inkjet method, a dam may be placed to prevent the second encapsulation layer (782) in liquid form from spreading to the edges of the substrate (701). The dam (DAM) can be positioned closer to the edge of the substrate (701) than the second encapsulation layer (782). By this dam (DAM), the second encapsulation layer (782) can be prevented from spreading into the pad area where the conductive pad is positioned at the outermost edge of the substrate (701).

[0135] The dam is designed to prevent the diffusion of the second encapsulation layer (782), but if the second encapsulation layer (782) is formed to exceed the height of the dam during the process, the second encapsulation layer (782), which is an organic layer, may be exposed to the outside, making it easy for moisture, etc., to penetrate into the light-emitting element. Therefore, to prevent this, the dam may be formed in duplicate at least 10 times.

[0136] Referring to FIG. 14, the dam (DAM) can be placed on the protective shield (745) of the non-marked area (NA).

[0137] Additionally, the dam (DAM) can be formed simultaneously with the first intermediate layer (750) and the second intermediate layer (760). When the first intermediate layer (750) is formed, the lower layer of the dam (DAM) is formed together, and when the second intermediate layer (760) is formed, the upper layer of the dam (DAM) is formed together, so that it can be formed by stacking in a double structure.

[0138] Therefore, the dam (DAM) may be composed of the same material as the first intermediate layer (750) and the second intermediate layer (760), but is not limited thereto.

[0139] Referring to FIG. 14, the dam (DAM) can be formed by overlapping with the low-potential driving power line (VSS). For example, the low-potential driving power line (VSS) can be formed in the lower layer of the area where the dam (DAM) is located in the non-displayed area (NA).

[0140] The gate driver (GD), configured in the form of a low-potential driving power line (VSS) and a GIP (Gate In Panel), is formed to surround the outer edge of the display panel, and the low-potential driving power line (VSS) may be located further outward than the gate driver (GD). Additionally, the low-potential driving power line (VSS) may be connected to the anode electrode (771) to apply a common voltage. Although the gate driver (GD) is simply depicted in the planar and cross-sectional drawings, it may be configured using a thin-film transistor (TFT) having the same structure as the thin-film transistor (TFT) in the display area (AA).

[0141] Referring to FIG. 14, the low-potential driving power line (VSS) is positioned outside the gate driving unit (GD). The low-potential driving power line (VSS) is positioned outside the gate driving unit (GD) and surrounds the display area (AA). The low-potential driving power line (VSS) may be made of the same material as the source and drain electrodes (740) of the thin-film transistor (TFT), but is not limited thereto. For example, the low-potential driving power line (VSS) may be made of the same material as the gate electrode (725).

[0142] Additionally, the low-potential driving power line (VSS) can be electrically connected to the anode electrode (771). The low-potential driving power line (VSS) can supply a low-potential driving voltage (EVSS) to a plurality of pixels of the display area (AA).

[0143] A touch layer (790) may be disposed on the encapsulation layer (780). In the touch layer (790), a touch buffer film (791) may be positioned between a touch sensor metal comprising touch electrode connection lines (792, 794) and touch electrodes (795, 796) and a cathode electrode (773) of a light-emitting element (OLED).

[0144] The touch buffer film (791) can block chemical solutions (developer or etching solution, etc.) used during the manufacturing process of the touch sensor metal placed on the touch buffer film (791) or moisture from the outside from penetrating into the light-emitting layer (772) containing organic material. Accordingly, the touch buffer film (791) can prevent damage to the light-emitting layer (772), which is vulnerable to chemical solutions or moisture.

[0145] The touch buffer film (791) is formed from an organic insulating material having a low dielectric constant of 1 to 3 and capable of being formed at a low temperature (e.g., 100°C) or lower to prevent damage to the light-emitting layer (772) containing organic material that is vulnerable to high temperatures. For example, the touch buffer film (791) can be formed from an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film (791), which has flattening performance as an organic insulating material, can prevent damage to the encapsulation layer (780) due to bending of the organic light-emitting display device and breakage of the touch sensor metal formed on the touch buffer film (791).

[0146] According to the mutual-capacitance-based touch sensor structure, touch electrodes (795, 796) are disposed on a touch buffer film (791), and the touch electrodes (795, 796) can be disposed intersecting each other.

[0147] The touch electrode connection lines (792, 794) can electrically connect the touch electrodes (795, 796). The touch electrode connection lines (792, 794) and the touch electrodes (795, 796) can be located on different layers with the touch insulating film (193) in between.

[0148] The touch electrode connection lines (792, 794) are arranged to overlap with the bank layer (765) so as to prevent the aperture ratio from decreasing.

[0149] Meanwhile, the touch electrodes (795, 796) can be electrically connected to a touch driving circuit (not shown) through a touch pad (198) by passing a part of the touch electrode connection line (792) through the upper and side of the encapsulation layer (780) and the upper and side of the dam.

[0150] A portion of the touch electrode connection line (792) can receive a touch driving signal from a touch driving circuit and transmit it to the touch electrodes (795, 796), and can also transmit a touch sensing signal from the touch electrodes (795, 796) to the touch driving circuit.

[0151] A touch protective film (197) may be placed on the touch electrodes (795, 796). Although the touch protective film (197) is shown in the drawing as being placed only on the touch electrodes (795, 796), it is not limited thereto, and the touch protective film (197) may be extended to the front or back of the dam and placed on the touch electrode connection line (792).

[0152] Additionally, a color filter (not shown) may be further disposed on the envelope layer (780), and the color filter may be located on the touch layer (790) or between the envelope layer (780) and the touch layer (790).

[0153] The stacked structure or components on the cross-sectional view of the display device of FIG. 14 described above can be applied to the display device (1) according to FIG. 1 to FIG. 3. Since the stacked structure or components of the display device of FIG. 14 belong to the same technical field as the display device (1) according to FIG. 1 to FIG. 3, it is obvious that they can be combined. That is, the stacked structure or components on the cross-sectional view of the non-display area (NA) of the display device of FIG. 14 can be applied to the first non-display area (NDA1) of the display device (1) according to FIG. 3, and the stacked structure or components on the cross-sectional view of the display area (AA) can be applied to the display area (DA) of the display device (1) of FIG. 3.

[0154] FIG. 15 is a cross-sectional view of a display device according to another embodiment.

[0155] Referring to FIG. 15, the optical region (OA) includes a through hole (TH) and a peripheral region (SA), and a display region (AA) may be located at the outer edge of the peripheral region (SA). The display region (AA) corresponds to the display region (DA) of FIG. 3, the through hole (TH) corresponds to the sensing hole (SH) of FIG. 3, and the peripheral region (SA) may correspond to the second non-display region (NDA2) of FIG. 3.

[0156] An optical electronic device may be located in the through hole (TH), which is positioned below the display panel and has at least a portion of its area overlapping with the through hole (TH).

[0157] Referring to FIG. 15, a display device according to embodiments may include “dam structures” such as an outer dam (DMO) located in a display area (AA) and an inner dam (DMI) located in a surrounding area (SA). Such dam structures may have a triple-layer structure formed perpendicularly to a substrate (SUB). For example, the dam structures may include a first layer formed of a flattening layer (PLN), a second layer formed of a bank, and a third layer formed of a spacer (not shown).

[0158] Referring to FIG. 15, the aforementioned first flattening layer (PLN1) and second flattening layer (PLN2) are briefly illustrated as flattening layer (PLN). In such a dam structure, at least a portion of the light-emitting layer (EL) may be located on a spacer.

[0159] Some components constituting a light-emitting element may be stacked on top of the inner dam (DMI). For example, a light-emitting layer (EL) and a common electrode (not shown) may be stacked in a shape that runs over the inner dam (DMI).

[0160] An uneven pattern (RP) is located on the inside and outside of this inner dam (DMI). The uneven pattern (RP) may include a mountain containing an insulating layer (e.g., ILD1, ILD2-1, ILD2-2, etc.) and a valley in which at least a portion of the insulating layer has been removed.

[0161] A light-emitting layer (EL) may be located in at least some area of ​​the uneven pattern (RP). This light-emitting layer (EL) may be an organic light-emitting layer containing an organic material. The light-emitting layer (EL) may extend from the display area (AA) to at least some area of ​​the surrounding area (SA).

[0162] Referring to FIG. 15, the light-emitting layer (EL) is discontinuously located in the inner uneven pattern (IRP) and the outer uneven pattern (ORP). According to this, even if moisture introduced from the through hole (TH) penetrates into the light-emitting layer (EL) located in the surrounding area (SA), the moisture does not penetrate to the light-emitting layer (EL) located in the display area (AA). In other words, as the light-emitting layer (EL) exists discontinuously in the uneven pattern (RP), there is an effect of extending the moisture penetration path, and also an effect of preventing moisture introduced into the light-emitting layer (EL) from spreading to the display area (AA).

[0163] Meanwhile, referring to FIG. 15, the height of the mountain in the inner irregular pattern (IRP) and the outer irregular pattern (ORP) may differ. The height of the mountain in the inner irregular pattern (IRP) may be higher than the height of the mountain in the outer irregular pattern (ORP).

[0164] The reason the height of the mountain differs in the inner irregular pattern (IRP) and the outer irregular pattern (ORP) may be due to the fact that the interlayer insulating films (e.g., ILD1, ILD2-1, ILD2-2) included in the mountain in the inner irregular pattern (IRP) and the outer irregular pattern (ORP) are different.

[0165] For example, referring to FIG. 15, the mountain of the inner irregular pattern (IRP) may include the second-2 interlayer insulating film (ILD2-2) and may not include the second-1 interlayer insulating film (ILD2-1) and the first interlayer insulating film (ILD1). The mountain of the outer irregular pattern (ORP) may include the second-1 interlayer insulating film (ILD2-1) and the first interlayer insulating film (ILD1), and may not include the second-2 interlayer insulating film (ILD2-2).

[0166] Meanwhile, referring to FIG. 15, the bottom surface of the valley located in the outer irregular pattern (ORP) may be located lower than the bottom surface of the valley located in the inner irregular pattern (IRP).

[0167] For example, in the outer irregular pattern (ORP), the valley may be one in which at least a portion of the first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2) (e.g., the second-1 interlayer insulating film (ILD2-1)) has been removed.

[0168] Referring to FIG. 15, in the process of removing the first interlayer insulating film (ILD1) from the outer irregular pattern (ORP) to form a valley of the irregular pattern (RP), there is a risk that the gate insulating film (GI) may be damaged or that insulating films located below the gate insulating film (GI), such as ABUF, MBUF, etc., may be damaged.

[0169] Accordingly, a metal pattern (MP) is located in the valley situated on the outer irregular pattern (ORP).

[0170] Referring to FIG. 15, a metal pattern (MP) can be placed in a surrounding area (SA) with a shape identical to the shape of a valley located in an outer uneven pattern (ORP), for example. A metal pattern (MP) located corresponding to a valley of an uneven pattern (RP) can function as an “etching stopper.”

[0171] Alternatively, the metal pattern (MP) may be positioned overlapping the mountain located on the outer irregular pattern (ORP). That is, the metal pattern (MP) may be positioned widely below the outer irregular pattern (ORP). In this case, the metal pattern (MP) may also perform the function of preventing microcracks generated in the through hole (TH) from spreading to the marked area (AA). In this case, the metal pattern (MP) may perform the function of a crack stopper as well as an etching stopper.

[0172] A metal pattern (MP) may be located on a gate insulating film (GI). This metal pattern (MP) may be formed of the same material as the gate electrode (GATE) of the driving transistor (DRT) of FIG. 3 described above.

[0173] The metal pattern (MP) is made of a different material from the insulating film above and below the metal pattern (MP) (e.g., gate insulating film (GI), first interlayer insulating film (ILD1)). Accordingly, even if the insulating film covering the metal pattern (MP) (e.g., first interlayer insulating film (ILD1)) is removed in a process such as etching, the insulating film below the metal pattern (MP) (e.g., gate insulating film (GI)) can be protected.

[0174] Meanwhile, an alignment mark (MNT) may be located in the surrounding area (SA). The alignment mark (MNT) is also referred to as an “align key.” The alignment mark (MNT) may be placed on the substrate (SUB) to form a through-hole (TH) by etching a preset area on the substrate (SUB).

[0175] These alignment marks (MNT) may be positioned in a surrounding area (SA) with a shape corresponding to the shape of the through hole (TH), or they may be positioned around the through hole (TH) with a shape different from the shape of the through hole (TH). For example, the alignment marks (MNT) may be located only in some of the upper, lower, left, or right areas of the through hole (TH).

[0176] Meanwhile, the alignment mark (MNT) may be located on the same layer as the metal pattern (MP). For example, the alignment mark (MNT) may be formed of the same material as the gate electrode (GATE). The alignment mark (MNT) may be located on the gate insulating film (GI). The alignment mark (MNT) may be located while covered by the first interlayer insulating film (ILD1).

[0177] The alignment mark (MNT) may be located in an area overlapping with, for example, the inner dam (DMI). The alignment mark (MNT) may be located between, for example, the inner irregular pattern (IRP) and the outer irregular pattern (ORP).

[0178] The stacked structure or components on the cross-sectional view of the display device of FIG. 15 described above can be applied to the display device (1) according to FIG. 1 to FIG. 3. Since the stacked structure or components of the display device of FIG. 15 belong to the same technical field as the display device (1) according to FIG. 1 to FIG. 3, it is obvious that they can be combined. That is, the stacked structure or components on the cross-sectional view of the peripheral area (SA) of the display device of FIG. 15 can be applied to the second non-display area (NDA2) of the display device (1) according to FIG. 3, and the stacked structure or components on the cross-sectional view of the display area (AA) can be applied to the display area (DA) of the display device (1) of FIG. 3.

[0179] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0180] 1: Display device 100: Display panel SH: Sensor hole VDDL1, VDDL2, VDDL3: 1st to 3rd power wiring VDDL_R: Hall outer power wiring

Claims

Claim 1 A substrate having a display area comprising a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and having a scan line extending along a first direction and connected to the pixels; and a second conductive layer disposed on the first conductive layer and having a high-voltage power line connected to the pixels disposed thereon, wherein the high-voltage power line comprises a first high-voltage power line, a second high-voltage power line, and a hole outer high-voltage power line surrounding the sensor non-display area in a planar manner, wherein the first high-voltage power line and the second high-voltage power line each extend along a second direction intersecting the first direction, the first high-voltage power line is spaced apart from the hole outer high-voltage power line, and the second high-voltage power line is connected to the hole outer high-voltage power line. Claim 2 delete Claim 3 A display device comprising: a substrate having a display area including a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and including a scan line connected to the pixel and extended along a first direction; and a second conductive layer disposed on the first conductive layer and having a high-voltage power line connected to the pixel disposed therein, wherein the high-voltage power line includes a first high-voltage power line, a second high-voltage power line, and a hole-outside high-voltage power line surrounding the sensor non-display area in a planar manner, wherein the first high-voltage power line and the second high-voltage power line each extend along a second direction intersecting the first direction, the first high-voltage power line is spaced apart from the hole-outside high-voltage power line, and the width of the hole-outside high-voltage power line is greater than the width of the first high-voltage power line. Claim 4 In claim 1, the display device wherein the high-voltage power wiring does not overlap with the sensor non-display area. Claim 5 A display device according to claim 1, wherein the scan wiring extends along the first direction and then bypasses the sensor hole area in a planar manner relative to the sensor non-display area. Claim 6 A display device according to claim 1, further comprising: a 3-1 power wiring section disposed on the upper side of the plane of the hole-outside high-voltage power wiring and connected to the hole-outside high-voltage power wiring; and a 3-2 power wiring section disposed on the lower side of the plane of the hole-outside high-voltage power wiring and connected to the hole-outside high-voltage power wiring. Claim 7 In claim 6, the 3-1 power wiring section and the 3-2 power wiring section are each a display device extended along the second direction. Claim 8 In claim 1, the scan wiring is a display device that intersects the high-voltage power wiring outside the hole in a plane. Claim 9 A display device comprising: a substrate having a display area including a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and having a scan line extending along a first direction and connected to the pixel; a second conductive layer disposed on the first conductive layer and having a high-voltage power line disposed thereon connected to the pixel; and a third conductive layer disposed on the second conductive layer and having a data line connected to the pixel, wherein the high-voltage power line comprises a first high-voltage power line, a second high-voltage power line, and a hole outer high-voltage power line surrounding the sensor non-display area in a planar manner. Claim 10 In claim 9, the hole outer high voltage power wiring comprises a first hole outer high voltage power wiring section and a second hole outer high voltage power wiring section spaced apart from each other with the scan wiring in between on a plane. Claim 11 In claim 10, the hole outer high-voltage power wiring further comprises a connecting high-voltage power wiring portion disposed in the third conductive layer, and the connecting high-voltage power wiring portion is a display device connected to the first hole outer high-voltage power wiring portion and the second hole outer high-voltage power wiring portion, respectively. Claim 12 In claim 11, the connecting high-voltage power wiring is a display device that intersects the scan wiring in a plane. Claim 13 A display device comprising: a substrate having a display area including a plurality of pixels, a sensor hole area disposed within the display area, and a sensor non-display area between the display area and the sensor hole area; a first conductive layer disposed on the substrate and including a scan line extended along a first direction connected to the pixel; a second conductive layer disposed on the first conductive layer; and a third conductive layer disposed on the second conductive layer and including a data line extended along a second direction intersecting the first direction connected to the pixel, and further comprising a high-voltage power line connected to the pixel, wherein the high-voltage power line includes a hole-outside high-voltage power line surrounding the sensor non-display area in a planar manner, and the hole-outside high-voltage power line is composed of two or more layers. Claim 14 In claim 13, the hole-outside high-voltage power wiring comprises a first hole-outside high-voltage power wiring disposed in the first conductive layer and a second hole-outside high-voltage power wiring disposed in the second conductive layer. Claim 15 In claim 14, the display device comprises a first hole outer high-voltage power wiring section and a second hole outer high-voltage power wiring section spaced apart from each other on a plane with the scan wiring in between. Claim 16 In claim 15, the first hole outer high-voltage power wiring section and the second hole outer high-voltage power wiring section are electrically connected to a display device.

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