Non-volatile memory device, manufacturing method for the same, and electronic system including the same

Abstract

The present invention provides a non-volatile memory device with improved performance and reliability. The non-volatile memory device of the present invention comprises: a cell substrate including a cell array region, an extension region, and a pad region, and having a front surface and a rear surface facing each other, and including a common source plate and an insulating pattern; a mold structure disposed on the front surface of the cell substrate and having a plurality of gate electrodes and a plurality of mold insulating films that are alternately stacked, stacked sequentially in the cell array region and stacked in a stepped manner in the extension region; a channel structure connected to a common source plate by penetrating the mold structure on the cell array region; a cell contact connected to at least one of a plurality of gate electrodes by penetrating the mold structure on the extension region; a first interlayer insulating film disposed on the front surface of the cell substrate and covering the mold structure; a second interlayer insulating film disposed on the rear surface of the cell substrate; an input / output pad provided on the second interlayer insulating film of the pad region; an input / output contact penetrating the first interlayer insulating film on the pad region; and an input / output via on the pad region that connects the input / output contact and the input / output pad to each other by etching the second interlayer insulating film and the cell substrate, wherein the common source plate is connected to the cell contact and the input / output contact and the cell It is non-overlapping in the first direction perpendicular to the front surface of the substrate.

Description

Technology Field

[0001] The present invention relates to a non-volatile memory device, a method for manufacturing the same, and an electronic system including the same. Background Technology

[0002] To meet the superior performance and low prices demanded by consumers, it is necessary to increase the integration density of non-volatile memory devices. Since integration density is a critical factor in determining product prices for non-volatile memory devices, particularly increased integration density is required.

[0003] Meanwhile, in the case of two-dimensional or planar non-volatile memory devices, the integration density is primarily determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional non-volatile memory devices is increasing but remains limited. Accordingly, three-dimensional non-volatile memory devices equipped with memory cells arranged in three dimensions are being proposed. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a non-volatile memory device with improved performance and reliability.

[0005] Another technical problem that the present invention aims to solve is to provide an electronic system including a non-volatile memory device with improved performance and reliability.

[0006] Another technical problem that the present invention aims to solve is to provide a method for manufacturing a non-volatile memory device with improved performance and reliability.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0008] A non-volatile memory device according to some embodiments of the present invention for achieving the above technical problem comprises: a cell substrate including a cell array region, an extension region, and a pad region, and including a front surface and a rear surface facing each other, and including a common source plate and an insulating pattern; a mold structure including a plurality of gate electrodes and a plurality of mold insulating films disposed on the front surface of the cell substrate, stacked sequentially in the cell array region, stacked in a stepped manner in the extension region, and alternately stacked; a channel structure connected to a common source plate by penetrating the mold structure on the cell array region; a cell contact connected to at least one of a plurality of gate electrodes by penetrating the mold structure on the extension region; a first interlayer insulating film disposed on the front surface of the cell substrate and covering the mold structure; a second interlayer insulating film disposed on the rear surface of the cell substrate; an input / output pad provided on the second interlayer insulating film of the pad region; an input / output contact penetrating the first interlayer insulating film on the pad region; and an input / output via on the pad region for connecting the input / output contact and the input / output pad to each other by etching the second interlayer insulating film and the cell substrate, wherein the common source plate is a cell The contacts and input / output contacts are non-overlapping in a first direction perpendicular to the front surface of the cell substrate.

[0009] A non-volatile memory device according to some embodiments of the present invention for achieving the above technical problem comprises a cell structure including a first surface and a second surface facing each other, and a ferri structure bonded to the cell structure and including a third surface bonded to the second surface and a fourth surface facing the third surface; the cell structure comprises a cell substrate including a cell array region, an extension region, and a pad region, and having a front surface and a rear surface facing each other, and including a common source plate and an insulating pattern, wherein the front surface of the cell substrate faces the ferri structure, a mold structure disposed on the front surface of the cell substrate and having a plurality of gate electrodes stacked sequentially in the cell array region and stacked in a stepped manner in the extension region and alternately stacked, and a plurality of mold insulating films, a channel structure penetrating the mold structure on the cell array region and connected to the common source plate, a cell contact penetrating the mold structure on the extension region and connected to at least one of the plurality of gate electrodes, a first interlayer insulating film disposed on the front surface of the cell substrate and covering the mold structure, and penetrating the first interlayer insulating film on the pad region The invention includes an input / output contact, a second interlayer insulating film disposed on the rear surface of a cell substrate, a cell pad provided on the second interlayer insulating film of a cell array region, an extension pad provided on the second interlayer insulating film of an extension region, an input / output pad provided on the second interlayer insulating film of a pad region, a cell via connecting the common source plate and the cell pad to each other by penetrating the second interlayer insulating film on the common source plate of the cell array region, an extension via connecting the cell contact and the extension pad to each other by etching the second interlayer insulating film and an insulating pattern on the extension region, and an input / output via connecting the input / output contact and the input / output pad to each other by etching the second interlayer insulating film and an insulating pattern on the pad region, wherein the bottom surface of the extension via and the bottom surface of the input / output via are provided between the front surface of the cell substrate and the rear surface of the cell substrate.The insulation pattern overlaps the cell contact and the input / output contact in a first direction perpendicular to the front surface of the cell substrate, and the common source plate does not overlap the cell contact and the input / output contact in the first direction.

[0010] An electronic system according to some embodiments of the present invention for achieving the above technical problem comprises a main board, a non-volatile memory device on the main board, and a controller electrically connected to the non-volatile memory device on the main board. The non-volatile memory device comprises a cell board including a cell array region, an extension region, and a pad region, and having a front surface and a rear surface facing each other, and including a common source plate and an insulating pattern; a mold structure disposed on the front surface of the cell board and having a plurality of gate electrodes and a plurality of mold insulating films that are alternately stacked, stacked sequentially in the cell array region and stacked in a stepped manner in the extension region; a channel structure connected to a common source plate by penetrating the mold structure on the cell array region; a cell contact connected to at least one of the plurality of gate electrodes by penetrating the mold structure on the extension region; a first interlayer insulating film disposed on the front surface of the cell board and covering the mold structure; a second interlayer insulating film disposed on the rear surface of the cell board; an input / output pad provided on the second interlayer insulating film of the pad region; an input / output contact penetrating the first interlayer insulating film on the pad region; and a second interlayer on the pad region The insulating film and the cell substrate are etched to include an input / output via that connects the input / output contact and the input / output pad to each other, and the common source plate is non-overlapping in a first direction perpendicular to the cell contact and the input / output contact and the front surface of the cell substrate.

[0011] A method for manufacturing a non-volatile memory device according to some embodiments of the present invention for achieving the above technical problem comprises: providing a free cell substrate including a front surface and a rear surface facing each other; forming a mold structure on the front surface of the free cell substrate in which a plurality of mold insulating films and a plurality of gate electrodes are alternately stacked; forming an interlayer insulating film covering the mold structure; forming a cell contact that penetrates the mold structure and is connected to at least one of a plurality of gate electrodes; the upper surface of the cell contact is provided between the front surface and the rear surface of the free cell substrate; forming an input / output contact that penetrates the interlayer insulating film; the upper surface of the input / output contact is provided between the front surface and the rear surface of the free cell substrate; removing the free cell substrate to form a cell substrate; the cell substrate includes a front surface and a rear surface facing each other and includes a common source plate and an insulating pattern; the common source plate is non-overlapping with the input / output contact and the cell contact in a first direction perpendicular to the front surface of the cell substrate; the insulating pattern is overlapping with the input / output contact and the cell contact in the first direction; and etching the cell substrate to input / output It includes forming an input / output via connected to a contact, and the bottom surface of the input / output via is provided between the front and back surfaces of the cell substrate.

[0012] Specific details of other embodiments are included in the description of the invention and the drawings. Brief explanation of the drawing

[0013] FIG. 1 is an exemplary block diagram for illustrating a non-volatile memory device according to some embodiments. FIG. 2 is an exemplary circuit diagram for illustrating a non-volatile memory device according to some embodiments. FIG. 3 is an exemplary layout diagram for illustrating a non-volatile memory device according to some embodiments. Figure 4 is a cross-sectional view taken along the line AA' of Figure 3. Figure 5 is a cross-sectional view taken along the line BB' of Figure 3. Figure 6 is an enlarged cross-sectional view to illustrate region P of Figure 5. Figure 7 is an enlarged cross-sectional view to illustrate the Q region of Figure 4. FIGS. 8 to 11 are exemplary drawings for illustrating a non-volatile memory device according to some embodiments. FIGS. 12 and FIGS. 13 are exemplary drawings for illustrating a non-volatile memory device according to some embodiments. FIGS. 14 to 27 are drawings sequentially illustrating the process of manufacturing a non-volatile memory device having the cross-section of FIG. 4. FIG. 28 is an exemplary block diagram for illustrating an electronic system according to some embodiments. FIG. 29 is an exemplary perspective view for illustrating an electronic system according to some embodiments. FIG. 30 is a schematic cross-sectional view taken along line II of FIG. 29. Specific details for implementing the invention

[0014] Hereinafter, in order to explain the present invention more specifically, it will be described in more detail with reference to the attached drawings according to some embodiments of the present invention.

[0015] Hereinafter, a non-volatile memory device according to exemplary embodiments is described with reference to FIGS. 1 to 13.

[0016] FIG. 1 is an exemplary block diagram for illustrating a non-volatile memory device according to some embodiments.

[0017] Referring to FIG. 1, a non-volatile memory device (10) according to some embodiments includes a memory cell array (20) and peripheral circuits (30).

[0018] A memory cell array (20) may include a plurality of memory cell blocks (BLK1 to BLKn). Each of the memory cell blocks (BLK1 to BLKn) may include a plurality of memory cells. The memory cell array (20) may be connected to a peripheral circuit (30) via a bit line (BL), a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Specifically, the memory cell blocks (BLK1 to BLKn) may be connected to a row decoder (33) via the word line (WL), the string select line (SSL), and the ground select line (GSL). Additionally, the memory cell blocks (BLK1 to BLKn) may be connected to a page buffer (35) via the bit line (BL).

[0019] The peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the non-volatile memory device (10), and can transmit and receive data (DATA) with a device outside the non-volatile memory device (10). The peripheral circuit (30) may include control logic (37), a row decoder (33), and a page buffer (35). Although not illustrated, the peripheral circuit (30) may further include various sub-circuits such as an input / output circuit, a voltage generation circuit that generates various voltages required for the operation of the non-volatile memory device (10), and an error correction circuit for correcting errors in data (DATA) read from the memory cell array (20).

[0020] The control logic (37) can be connected to the row decoder (33), the input / output circuit, and the voltage generation circuit. The control logic (37) can control the overall operation of the non-volatile memory device (10). The control logic (37) can generate various internal control signals used within the non-volatile memory device (10) in response to a control signal (CTRL). For example, the control logic (37) can adjust the voltage levels provided to the word line (WL) and bit line (BL) when performing memory operations such as program operation or erase operation.

[0021] The row decoder (33) can select at least one of a plurality of memory cell blocks (BLK1 to BLKn) in response to an address (ADDR), and can select at least one word line (WL), at least one string select line (SSL), and at least one ground select line (GSL) of the selected memory cell blocks (BLK1 to BLKn). Additionally, the row decoder (33) can transmit a voltage for performing memory operations to the word line (WL) of the selected memory cell blocks (BLK1 to BLKn).

[0022] The page buffer (35) can be connected to the memory cell array (20) via a bit line (BL). The page buffer (35) can operate as a writer driver or a sense amplifier. Specifically, when performing a program operation, the page buffer (35) can operate as a writer driver to apply a voltage to the bit line (BL) according to the data (DATA) to be stored in the memory cell array (20). Meanwhile, when performing a read operation, the page buffer (35) can operate as a sense amplifier to detect the data (DATA) stored in the memory cell array (20).

[0023] FIG. 2 is an exemplary circuit diagram for illustrating a non-volatile memory device according to some embodiments.

[0024] Referring to FIG. 2, a memory cell array (e.g., 20 in FIG. 1) of a non-volatile memory device according to some embodiment includes a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR).

[0025] A common source line (CSL) may be extended in a first direction (X). In some embodiments, a plurality of common source lines (CSLs) may be arranged in two dimensions. For example, a plurality of common source lines (CSLs) may be spaced apart from each other and each may be extended in a first direction (X). The common source lines (CSLs) may be electrically identically voltaged, or they may be controlled separately by applying different voltages.

[0026] Multiple bit lines (BL) can be arranged in two dimensions. For example, the bit lines (BL) can be spaced apart from each other and each can extend in a second direction (Y) that intersects a first direction (X). Multiple cell strings (CSTR) can be connected in parallel to each bit line (BL). The cell strings (CSTR) can be connected in common to a common source line (CSL). That is, multiple cell strings (CSTR) can be placed between the bit lines (BL) and the common source line (CSL).

[0027] Each cell string (CSTR) may include a ground select transistor (GST) connected to a common source line (CSL), a string select transistor (SST) connected to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the ground select transistor (GST) and the string select transistor (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCT) may be connected in series in a third direction (Z). In this specification, the first direction (X), the second direction (Y), and the third direction (Z) may be substantially perpendicular to each other.

[0028] A common source line (CSL) can be connected in common to the sources of ground select transistors (GST). Additionally, a ground select line (GSL), multiple word lines (WL1 to WLn), and a string select line (SSL) can be arranged between the common source line (CSL) and the bit line (BL). The ground select line (GSL) can be used as the gate electrode of a ground select transistor (GST), the word lines (WL1 to WLn) can be used as the gate electrode of a memory cell transistor (MCT), and the string select line (SSL) can be used as the gate electrode of a string select transistor (SST).

[0029] In some embodiments, an erase control transistor (ECT) may be placed between a common source line (CSL) and a ground select transistor (GST). The common source line (CSL) may be connected in common to the sources of the erase control transistors (ECT). Additionally, an erase control line (ECL) may be placed between the common source line (CSL) and the ground select line (GSL). The erase control line (ECL) may be used as the gate electrode of the erase control transistor (ECT). The erase control transistors (ECT) may perform an erase operation of the memory cell array by generating Gate Induced Drain Leakage (GIDL).

[0030] FIG. 3 is an exemplary layout diagram for illustrating a non-volatile memory device according to some embodiments. FIG. 4 is a cross-sectional view taken along the line AA' of FIG. 3. FIG. 5 is a cross-sectional view taken along the line BB' of FIG. 3. FIG. 6 is an enlarged cross-sectional view for illustrating region P of FIG. 5. FIG. 7 is an enlarged cross-sectional view for illustrating region Q of FIG. 4.

[0031] Referring to FIGS. 3 through 7, a non-volatile memory device according to some embodiments includes a cell structure (CELL) and a peer structure (PERI).

[0032] A non-volatile memory device according to some embodiments may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip containing a cell structure on a first wafer, fabricating a lower chip containing a peer structure on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0033] More specifically, the cell structure (CELL) may include a first surface (CELL_a) and a second surface (CELL_b) facing each other. The peri structure (PERI) may include a third surface (PERI_a) and a fourth surface (PERI_b) facing each other. The second surface (CELL_b) of the cell structure (CELL) may face the third surface (PERI_a) of the peri structure (PERI). The second surface (CELL_b) of the cell structure (CELL) and the third surface (PERI_a) of the peri structure (PERI) may be bonded to each other. As a result, the cell structure (CELL) and the peri structure (PERI) may be bonded to each other.

[0034] In some embodiments, the cell structure (CELL) may include a cell substrate (100), a mold structure (MS), a first interlayer insulating film (140), a second interlayer insulating film (103), an upper insulating film (104), a channel structure (CH), a wordline cutting structure (WLC), a bit line (BL), a cell contact (150), a source contact (160), and a first input / output contact (170).

[0035] A non-volatile memory device according to some embodiments may include a cell array region (R1), an extension region (R2), and a pad region (R3). A memory cell array (e.g., 20 of FIG. 1) including a plurality of memory cells may be formed in the cell array region (R1). For example, a channel structure (CH), bit lines (BL), and gate electrodes (ECL, GSL, WL1~WLn, SSL), which will be described later, may be disposed in the cell array region (R1).

[0036] An extension region (R2) may be placed around a cell array region (R1). In the extension region (R2), gate electrodes (ECL, GSL, WL1~WLn, SSL) described later may be stacked in a stepped manner.

[0037] The pad area (R3) may be positioned inside the cell array area (R1) and the extension area (R2), or outside the cell array area (R1) and the extension area (R2). Source contacts (160) and first input / output contacts (170), which will be described later, may be positioned in the pad area (R3).

[0038] The cell substrate (100) may include a common source plate (101) and an insulating pattern (102). The common source plate (101) may be provided on a part of the cell array region (R1) and the pad region (R3). The common source plate (101) may not be provided on the extension region (R2). The common source plate (101) may be connected to a channel structure (CH) and a source contact (160).

[0039] For example, the common source plate (101) may be connected to a semiconductor pattern (130) of a channel structure (CH) in a cell array region (R1). The common source plate (101) may be connected to a source contact (160) in a pad region (R3). This common source plate (101) may be provided as a common source line (e.g., CSL of FIG. 2) of a non-volatile memory device. The common source plate (101) may comprise, for example, impurity-doped polysilicon or a metal, but is not limited thereto.

[0040] In some embodiments, the common source plate (101) may not overlap with the cell contact (150) and the first input / output contact (170) in the third direction (Z).

[0041] The insulation pattern (102) may be provided on a portion of the extension region (R2) and the pad region (R3). The insulation pattern (102) may not be provided on the cell array region (R1). The insulation pattern (102) may enclose a portion of the cell contact (150) and a portion of the first input / output contact (170). The insulation pattern (102) may overlap the cell contact (150) and the first input / output contact (170) in a third direction (Z). Additionally, the insulation pattern (102) may enclose a portion of the extension via (EX_VA) and the input / output via (IO_VA) to be described later.

[0042] The insulating pattern (102) may include an oxide-based insulating material. For example, the insulating pattern (102) may include silicon oxide (SiO2). Specifically, the insulating pattern (102) may include, for example, FOX (Flowable oxide), TOSZ (Tonen Silazen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphosilica Glass), PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma), PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD), or a combination thereof.

[0043] The cell substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. The front surface (100a) of the cell substrate (100) may face the peristructure (PERI). The rear surface (100b) of the cell substrate (100) may face the peristructure (PERI). The front surface of the common source plate (101) and the front surface of the insulation pattern (102) may be the front surface (100a) of the cell substrate (100). The rear surface of the common source plate (101) and the rear surface of the insulation pattern (102) may be the rear surface (100b) of the cell substrate (100).

[0044] A mold structure (MS) may be provided on the front surface (100a) of a cell substrate. The mold structure (MS) may include a plurality of gate electrodes (ECL, GSL, WL1~WLn, SSL) and a plurality of mold insulating films (110) that are alternately stacked on the cell substrate (100). Each of the gate electrodes (ECL, GSL, WL1~WLn, SSL) and each of the mold insulating films (110) may be a layered structure extending parallel to the front surface (100a) of the cell substrate (100). The gate electrodes (ECL, GSL, WL1~WLn, SSL) may be stacked sequentially on the cell substrate (100) and spaced apart from each other by the mold insulating films (110).

[0045] The gate electrodes (ECL, GSL, WL1–WLn, SSL) may be stacked in a stepped manner in an extended region (R2). For example, the gate electrodes (ECL, GSL, WL1–WLn, SSL) may have different lengths and steps in a first direction (X). In some embodiments, the gate electrodes (ECL, GSL, WL1–WLn, SSL) may have steps in a second direction (Y). Accordingly, each gate electrode (ECL, GSL, WL1–WLn, SSL) may include an exposed region (not shown) exposed from other gate electrodes. The exposed region may refer to an area where the cell contact (150) and the gate electrodes (ECL, GSL, WL1–WLn, SSL) come into contact.

[0046] The height of the gate electrodes (ECL, GSL, WL1~WLn, SSL) in contact with the cell contact (150) in the above exposed area in the third direction (Z) may be higher than the height of other gate electrodes (ECL, GSL, WL1~WLn, SSL) in the third direction (Z). The third direction (Z) may be a direction perpendicular to the front surface (100a) of the cell substrate (100). As a result, the contact area of ​​the cell contact (150) and the gate electrodes (ECL, GSL, WL1~WLn, SSL) may be increased. However, the technical concept of the present invention is not limited thereto.

[0047] In some embodiments, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may include an erase control line (ECL), a ground select line (GSL), and a plurality of word lines (WL1 to WLn) that are stacked sequentially on the cell substrate (100). In some other embodiments, the erase control line (ECL) may be omitted.

[0048] Mold insulating films (110) may be stacked in a stepped manner in an extended region (R2). For example, the mold insulating films (110) may have steps by extending at different lengths in a first direction (X). In some embodiments, the mold insulating films (110) may have steps in a second direction (Y).

[0049] The gate electrodes (ECL, GSL, WL1 to WLn, SSL) may each include a conductive material, such as a metal like tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material like silicon, but are not limited thereto. For example, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may each include tungsten (W). Unlike what is illustrated, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may be multilayer films. For example, if the gate electrodes (ECL, GSL, WL1 to WLn, SSL) are multilayer films, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may include a gate electrode barrier film and a gate electrode filling film. The gate electrode barrier film may include, for example, titanium nitride (TiN), and the gate electrode filling film may include tungsten (W), but are not limited thereto.

[0050] The mold insulating film (110) may include at least one of an insulating material, for example, silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the mold insulating film (110) may include silicon oxide.

[0051] The first interlayer insulating film (140) may be provided on the front surface (100a) of the cell substrate (100). The first interlayer insulating film (140) may cover the mold structure (MS). The first interlayer insulating film (140) may include an oxide-based insulating material. The first interlayer insulating film (140) may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0052] A channel structure (CH) may be provided within a mold structure (MS) of a cell array region (R1). The channel structure (CH) may extend in a third direction (Z) intersecting the front surface (100a) of the cell substrate (100) and penetrate the mold structure (MS). For example, the channel structure (CH) may be in the shape of a pillar (e.g., a cylinder) extending in the third direction (Z). Accordingly, the channel structure (CH) may intersect with each of the gate electrodes (ECL, GSL, WL1~WLn, SSL).

[0053] The channel structure (CH) may include a semiconductor pattern (130) and an information storage film (132).

[0054] The semiconductor pattern (130) can extend in a third direction (Z) and penetrate the mold structure (MS). Although the semiconductor pattern (130) is illustrated as being cup-shaped, this is merely illustrative. For example, the semiconductor pattern (130) may have various shapes, such as a cylindrical shape, a rectangular shape, or a solid filler shape. The semiconductor pattern (130) may include semiconductor materials such as, for example, single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0055] The information storage film (132) may be interposed between the semiconductor pattern (130) and each gate electrode (ECL, GSL, WL1~WLn, SSL). For example, the information storage film (132) may extend along the outer surface of the semiconductor pattern (130). The information storage film (132) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0056] In some embodiments, a plurality of channel structures (CH) may be arranged in a zigzag shape. For example, as shown in FIG. 3, a plurality of channel structures (CH) may be arranged staggered with respect to each other in a first direction (X) and a second direction (Y). A plurality of channel structures (CH) arranged in a zigzag shape can further improve the integration density of a non-volatile memory device. In some embodiments, a plurality of channel structures (CH) may be arranged in a honeycomb shape.

[0057] In some embodiments, a dummy channel structure (DCH) may be formed within the mold structure (MS) of the extension region (R2). The dummy channel structure (DCH) may be formed with a shape similar to the channel structure (CH) to reduce the stress applied to the mold structure (MS) in the extension region (R2).

[0058] In some embodiments, the information storage film (132) may be formed as a multilayer film. For example, as shown in FIG. 6, the information storage film (132) may include a tunnel insulating film (132a), a charge storage film (132b), and a blocking insulating film (132c) that are stacked sequentially on the outer surface of the semiconductor pattern (130).

[0059] The tunnel insulating film (132a) may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). The charge storage film (132b) may include, for example, silicon nitride. The blocking insulating film (132c) may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)).

[0060] In some embodiments, the channel structure (CH) may further include a filling pattern (134). The filling pattern (134) may be formed to fill the interior of a cup-shaped semiconductor pattern (130). The filling pattern (134) may include an insulating material, for example, silicon oxide, but is not limited thereto.

[0061] In some embodiments, the channel structure (CH) may further include a channel pad (136). The channel pad (136) may be formed to be connected to the semiconductor pattern (130). For example, the channel pad (136) may be provided within the first interlayer insulating film (140) and connected to the upper portion of the semiconductor pattern (130). The channel pad (136) may include, for example, impurity-doped polysilicon, but is not limited thereto.

[0062] In some embodiments, the semiconductor pattern (130) may be connected to a common source plate (101) on a cell array region (R1). A portion of the semiconductor pattern (130) may overlap with the common source plate (101) in a first direction (X) and a second direction (Y). The upper surface (130US) of the semiconductor pattern (130) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100). The upper surface (130US) of the semiconductor pattern (130) may face the peristructure (PERI). A portion of the semiconductor pattern (130) may be provided within the common source plate (101). The upper surface (130US) of the semiconductor pattern (130) may be in contact with the common source plate (101). A portion of the side of the semiconductor pattern (130) may be in contact with the common source plate (101).

[0063] In some embodiments, the upper surface (132US) of the information storage film (132) may be placed in the same plane as the front surface (100a) of the cell substrate (100). The upper surface (132US) of the information storage film (132) may face the Peri structure (PERI). The information storage film (132) may not be provided within the common source plate (101). The information storage film (132) may not overlap with the common source plate (101) in the first direction (X) and the second direction (Y). However, the technical concept of the present invention is not limited thereto.

[0064] A wordline cutting structure (WLC) can be extended in a first direction (X) to cut a mold structure (MS). The mold structure (MS) can be cut by a plurality of wordline cutting structures (WLC) to form a plurality of memory cell blocks (e.g., BLK1 to BLKn in FIG. 1). For example, two adjacent wordline cutting structures (WLC) can define a single memory cell block between them. A plurality of channel structures (CH) can be disposed within each memory cell block defined by the wordline cutting structures (WLC).

[0065] In FIG. 3, only nine channel structures (CH) arranged in a zigzag pattern along the second direction (Y) within a single memory cell block are illustrated, but this is merely an example. Of course, the number of channel structures (CH) arranged within each memory cell block is not limited to what is illustrated and can vary.

[0066] In some embodiments, the wordline cutting structure (WLC) may extend in a first direction (X) to cut the mold insulating films (110) and gate electrodes (ECL, GSL, WL1 to WLn, SSL). The wordline cutting structure (WLC) may include an insulating material. For example, the insulating material may fill the wordline cutting structure (WLC). The insulating material may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

[0067] A bit line (BL) can be formed within a mold structure (MS) and a first interlayer insulating film (140). The bit line (BL) can be extended in a second direction (Y) and intersect with a wordline cutting structure (WLC). Additionally, the bit line (BL) can be extended in a second direction (Y) and connected to a plurality of channel structures (CH) arranged along the second direction (Y). For example, a bit line contact plug (BLPG) connected to the upper portion of each channel structure (CH) can be formed within the first interlayer insulating film (140). The bit line (BL) can be electrically connected to the channel structures (CH) through the bit line contact plug (BLPG).

[0068] A cell contact (150) may be provided on an extension region (R2). The cell contact (150) may extend in a third direction (Z) in the extension region (R2) and penetrate the first interlayer insulating film (140) and the mold structure (MS). The cell contact (150) may be connected to each of the gate electrodes (ECL, GSL, WL1~WLn, SSL) in the extension region (R2). The cell contact (150) may be in contact with the gate electrode positioned at the top of the stepped stacked gate electrodes (ECL, GSL, WL1~WLn, SSL).

[0069] For example, the cell contact (150) may contact the sidewall of the gate electrode positioned at the top. The gate electrode positioned at the top may be a gate electrode that contacts the first interlayer insulating film (140). The thickness of the sidewall of the gate electrode that contacts the cell contact (150) may be greater than the thickness of the sidewall of the gate electrode that does not contact the cell contact (150), but the technical concept of the present invention is not limited thereto. For convenience of explanation, the cell contact (150) is illustrated as having seven members, but is not limited thereto.

[0070] In some embodiments, the upper surface (150US) of the cell contact (150) may be positioned within the insulating pattern (102). That is, the upper surface (150US) of the cell contact (150) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100). The cell contact (150) may not overlap with the common source plate (101) in the third direction (Z). A portion of the cell contact (150) may overlap with the common source plate (101) in the first direction (X) and the second direction (Y). The common source plate (101) may include a portion that does not overlap with the cell contact (150) in the first direction (X) and the second direction (Y). That is, the cell contact (150) does not completely penetrate the cell substrate (100).

[0071] In some embodiments, the cell contact (150) may be electrically connected to the bit line (BL) through the first contact (155). The first contact (155) may include a conductive material. The first contact (155) may include, for example, tungsten (W) or copper (Cu), but is not limited thereto.

[0072] The cell contact (150) may include a conductive material. The cell contact (150) may include, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), but the type of metal is not limited thereto. For example, the cell contact (150) may include tungsten (W).

[0073] An insulating ring (125) may be provided within a mold structure (MS). The insulating ring (125) may be interposed between the cell contact (150) and each of the gate electrodes (ECL, GSL, WL1–WLn, SSL). The insulating ring (125) may electrically insulate the cell contact (150) from some of the gate electrodes (ECL, GSL, WL1–WLn, SSL). For example, the insulating ring (125) may be an annular structure surrounding the cell contact (150).

[0074] The insulating ring (125) can electrically isolate other gate electrodes among the gate electrodes (ECL, GSL, WL1~WLn, SSL) that are not exposed in the exposed area from the cell contact (150). For example, the insulating ring (125) can prevent the remaining gate electrodes, excluding the top gate electrode connected to the cell contact (150), from coming into contact with the cell contact (150).

[0075] The insulating ring (125) may include an insulating material. The insulating ring (125) may include, for example, an oxide-based insulating material. For example, the insulating ring (125) may include silicon oxide, but is not limited thereto.

[0076] A source contact (160) may be provided on a pad area (R3). The source contact (160) may be formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to a common source plate (101). The source contact (160) may be electrically connected to a bit line (BL) through a second contact (165). The second contact (165) may include a conductive material. The second contact (165) may include, for example, tungsten (W) or copper (Cu), but is not limited thereto.

[0077] In some embodiments, the upper surface (160US) of the source contact (160) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100). The source contact (160) does not overlap with the insulation pattern (102) in the third direction (Z). The source contact (160) includes a portion that overlaps with the insulation pattern (102) in the first direction (X) and the second direction (Y). The insulation pattern (102) includes a portion that does not overlap with the source contact (160) in the first direction (X) and the second direction (Y). That is, the source contact (160) does not completely penetrate the cell substrate (100).

[0078] The first input / output contact (170) can be connected to the first input / output pad (IO_PAD) to be described later by penetrating the first interlayer insulating film (140). The first input / output contact (170) can be provided on the pad area (R3). According to some embodiments, the common source plate (101) may not be placed in the area where the first input / output contact (170) is placed. An insulating pattern (102) may be placed in the area where the first input / output contact (170) is placed. The first input / output contact (170) and the common source plate (101) may not overlap in the third direction (Z). The first input / output contact (170) may overlap with the insulating pattern (102) in the third direction (Z).

[0079] Additionally, the first input / output pad (IO_PAD) may not overlap with the gate electrodes (ECL, GSL, WL1~WLn, SSL) in the third direction (Z). The first input / output contact (170) may be electrically connected to the bit line (BL) through the third contact (175). The third contact (175) may include a conductive material. The third contact (175) may include, for example, tungsten (W) or copper (Cu), but is not limited thereto.

[0080] A second interlayer insulating film (103) may be provided on the back surface (100b) of the cell substrate (100). The second interlayer insulating film (103) may include an oxide-based insulating material. For example, the second interlayer insulating film (103) may include silicon oxide (SiO2). Specifically, the second interlayer insulating film (103) may include, for example, FOX (Flowable oxide), TOSZ (Tonen Silazen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphosilica Glass), PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma), PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD), or a combination thereof.

[0081] An upper insulating film (104) may be provided on a second interlayer insulating film (103). The upper insulating film (104) may comprise a material having an etch selectivity ratio with respect to the second interlayer insulating film (103). The upper insulating film (104) may comprise, for example, silicon nitride (SiN), but is not limited thereto.

[0082] A non-volatile memory device according to some embodiments may further include a first input / output pad (IO_PAD), an extension pad (EX_PAD), a cell pad (C_PAD), an input / output via (IO_VA), an extension via (EX_VA), and a cell via (C_VA).

[0083] A first input / output pad (IO_PAD) may be provided on an upper insulating film (104) of a pad region (R3). The first input / output pad (IO_PAD) may be connected to an input / output via (IO_VA) and a first input / output contact (170). The first input / output pad (IO_PAD) may be electrically connected to a peer structure (PERI) through the first input / output contact (170) and the input / output via (IO_VA). Additionally, the first input / output pad (IO_PAD) may electrically connect an external device and a non-volatile memory device to each other. The first input / output pad (IO_PAD) may include a conductive material. For example, the first input / output pad (IO_PAD) may include aluminum (Al), but is not limited thereto.

[0084] An extension pad (EX_PAD) may be provided on the upper insulating film (104) of the extension region (R2). The extension pad (EX_PAD) may be connected to an extension via (EX_VA) and a cell contact (150). The extension pad (EX_PAD) may be electrically connected to a bit line (BL) through the cell contact (150) and the extension via (EX_VA). The extension pad (EX_PAD) may include a conductive material. For example, the extension pad (EX_PAD) may include aluminum (Al), but is not limited thereto.

[0085] A cell pad (C_PAD) may be provided on the upper insulating film (104) of the cell array region (R1). The cell pad (C_PAD) may be connected to a cell via (C_VA) and a common source plate (101). The cell pad (C_PAD) may be electrically connected to the common source plate (101) through the cell via (C_VA). The cell pad (C_PAD) may include a conductive material. For example, the cell pad (C_PAD) may include aluminum (Al), but is not limited thereto.

[0086] The input / output via (IO_VA) can be provided by penetrating the upper insulating film (104) and the second interlayer insulating film (103) and etching a portion of the insulating pattern (102). The input / output via (IO_VA) can be provided on the pad area (R3). The input / output via (IO_VA) does not overlap with the common source plate (101) in the third direction (Z). The input / output via (IO_VA) overlaps with the insulating pattern (102) on the pad area (R3) in the third direction (Z). A portion of the input / output via (IO_VA) may overlap with the common source plate (101) in the first direction (X) and the second direction (Y). A portion of the common source plate (101) may not overlap with the input / output via (IO_VA) in the first direction (X) and the second direction (Y). That is, the input / output via (IO_VA) may not completely penetrate the cell substrate (100).

[0087] The input / output via (IO_VA) can electrically connect the first input / output contact (170) and the first input / output pad (IO_PAD) to each other. The first input / output contact (170) and the first input / output pad (IO_PAD) may not be directly connected. That is, the first input / output contact (170) and the first input / output pad (IO_PAD) can be electrically connected to each other through the input / output via (IO_VA).

[0088] A portion of the input / output via (IO_VA) may be provided within the insulating pattern (102) of the pad area (R3). For example, as shown in FIG. 7, the bottom surface (IO_VA_BS) of the input / output via (IO_VA) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100).

[0089] In some embodiments, a portion of the input / output via (IO_VA) may enclose a portion of the first input / output contact (170). For example, the level of the bottom surface (IO_VA_BS) of the input / output via (IO_VA) may differ from the level of the top surface (170US) of the first input / output contact (170). The height from the rear surface (100b) of the cell substrate (100) to the bottom surface (IO_VA_BS) of the input / output via (IO_VA) may be greater than the height from the rear surface (100b) of the cell substrate (100) to the top surface (170US) of the first input / output contact (170). However, the technical concept of the present invention is not limited thereto.

[0090] An extension via (EX_VA) can be provided by penetrating the upper insulating film (104) and the second interlayer insulating film (103) and etching a portion of the insulating pattern (102). An extension via (EX_VA) can be provided on the extension region (R2). An extension via (EX_VA) does not overlap with the common source plate (101) in the third direction (Z). An extension via (EX_VA) overlaps with the insulating pattern (102) in the third direction (Z). A portion of the extension via (EX_VA) may overlap with the common source plate (101) in the first direction (X) and the second direction (Y). A portion of the common source plate (101) may not overlap with the extension via (EX_VA) in the first direction (X) and the second direction (Y). That is, the extension via (EX_VA) may not completely penetrate the cell substrate (100).

[0091] An extension via (EX_VA) can electrically connect an extension pad (EX_PAD) and a cell contact (150) to each other. A non-volatile memory device according to some embodiments can control the operation of the cell contact (150) using the extension via (EX_VA) and the extension pad (EX_PAD). However, the technical concept of the present invention is not limited thereto. In addition, in some embodiments, the extension via (EX_VA) is a hydrogen ion (H + It can be a pathway for the movement of ) through the extended via (EX_VA) hydrogen ions (H + ) may be moved. However, the technical concept of the present invention is not limited thereto.

[0092] A portion of the extended via (EX_VA) may be provided within the insulating pattern (102) of the extended region (R2). For example, as shown in FIG. 7, the bottom surface (EX_VA_BS) of the extended via (EX_VA) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100).

[0093] In some embodiments, a portion of the extension via (EX_VA) may enclose a portion of the cell contact (150). For example, the level of the bottom surface (EX_VA_BS) of the extension via (EX_VA) may differ from the level of the top surface (150US) of the cell contact (150). The height from the rear surface (100b) of the cell substrate (100) to the bottom surface (EX_VA_BS) of the extension via (EX_VA) may be greater than the height from the rear surface (100b) of the cell substrate (100) to the top surface (150US) of the cell contact (150). However, the technical concept of the present invention is not limited thereto.

[0094] In some embodiments, the vertical length of the extension via (EX_VA) in the third direction (Z) may be the same as the vertical length of the input / output via (IO_VA) in the third direction (Z). The extension via (EX_VA) and the input / output via (IO_VA) may be formed in the same process.

[0095] Cell vias (C_VA) may be formed by penetrating the upper insulating film (104) and the second interlayer insulating film (103). Cell vias (C_VA) may be provided on the common source plate (101) of the cell array region (R1). Cell vias (C_VA) do not overlap with the insulating pattern (102) in the third direction (Z). Cell vias (C_VA) overlap with the common source plate (101) in the third direction (Z). In some embodiments, cell vias (C_VA) may not overlap with the cell substrate (100) in the first direction (X) and the second direction (Y). For example, the bottom surface (C_VA_BS) of the cell vias (C_VA) may be placed on the same plane as the rear surface of the common source plate (101), i.e., the rear surface (100b) of the cell substrate (100). However, the technical concept of the present invention is not limited thereto.

[0096] In some embodiments, the vertical length of the cell via (C_VA) in the third direction (Z) may be smaller than the vertical length of the extension via (EX_VA) and the input / output via (IO_VA) in the third direction (Z). Due to the etch selectivity of the common source plate (101) and the insulation pattern (102), the vertical length of the cell via (C_VA) may be smaller than the vertical length of the extension via (EX_VA) and the input / output via (IO_VA).

[0097] The cell via (C_VA) can electrically connect the cell pad (C_PAD) and the common source plate (101) to each other. In some embodiments, the cell via (C_VA) is hydrogen ion (H + It can be a pathway for the movement of ) through the cell via (C_VA) hydrogen ions (H + ) can be moved. However, the technical concept of the present invention is not limited thereto. In addition, in some embodiments, noise of the common source plate (101) can be reduced through the cell via (C_VA).

[0098] The PERI structure (PERI) may include a PERI substrate (200), a lower insulating film (204), a peripheral circuit element (PT), a third interlayer insulating film (240), wiring patterns (260, 275), wiring contacts (255, 265), a second input / output contact (270), and a second input / output pad (295).

[0099] The ferri substrate (200) may include a front surface and a rear surface facing each other. The front surface of the ferri substrate (200) may face the cell structure (CELL). The rear surface of the ferri substrate (200) may face the cell structure (CELL).

[0100] The ferri substrate (200) may include a semiconductor substrate such as, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the ferri substrate (200) may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0101] Peripheral circuit elements (PT) may be formed on the ferry substrate (200). Peripheral circuit elements (PT) may be placed on the front surface of the ferry substrate (200). Peripheral circuit elements (PT) may constitute a peripheral circuit (e.g., 30 in FIG. 1) that controls the operation of a non-volatile memory device. For example, the peripheral circuit elements (PT) may include control logic (e.g., 37 in FIG. 1), a row decoder (e.g., 33 in FIG. 1), and a page buffer (e.g., 35 in FIG. 1).

[0102] Peripheral circuit elements (PTs) may include, for example, transistors, but are not limited thereto. For example, peripheral circuit elements (PTs) may include various active elements such as transistors, as well as various passive elements such as capacitors, resistors, and inductors.

[0103] A lower insulating film (204) may be disposed on the rear surface of the perimeter substrate (200). A second input / output pad (295) may be disposed on the lower insulating film (204). The second input / output pad (295) may be connected to at least one of the peripheral circuit elements (PT) disposed in the perimeter structure (PERI) through a second input / output contact (270). The perimeter substrate (200) and the second input / output pad (295) may be separated by the lower insulating film (204).

[0104] A third interlayer insulating film (240) may be provided on the front surface of the ferri substrate (200). A plurality of wiring patterns (260, 275) and a plurality of wiring contacts (255, 265) may be provided within the third interlayer insulating film (240). The third interlayer insulating film (240) may include an insulating material. For example, the third interlayer insulating film (240) may include at least one of silicon oxide, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0105] A plurality of wiring patterns (260, 275) and a plurality of wiring contacts (255, 265) can be electrically connected to each other. A peripheral circuit element (PT) and bit lines (BL) can be electrically connected through the plurality of wiring patterns (260, 275) and the plurality of wiring contacts (255, 265). The plurality of wiring patterns (260, 275) and the plurality of wiring contacts (255, 265) may include a conductive material. The plurality of wiring patterns (260, 275) and the plurality of wiring contacts (255, 265) may include, for example, tungsten (W) or copper (Cu), but are not limited thereto.

[0106] A non-volatile memory device according to some embodiments may further include a first bonding metal (190) formed on the uppermost metal layer of a cell structure (CELL) and a second bonding metal (290) formed on the uppermost metal layer of a peer structure (PERI).

[0107] The first bonding metal (190) and the second bonding metal (290) can be bonded to each other. Accordingly, the second surface (CELL_b) of the cell structure (CELL) and the third surface (PERI_a) of the peri structure (PERI) can be bonded to each other. If the first bonding metal (190) and the second bonding metal (290) are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method.

[0108] The first bonding metal (190) can be connected to the bit line (BL) through the first bonding contact (185). The second bonding metal (290) can be connected to peripheral circuit elements (PT) through the second bonding contact (285). Through this, the peer structure (PERI) and the cell structure (CELL) can be electrically connected to each other.

[0109] FIGS. 8 to 11 are exemplary drawings for illustrating a non-volatile memory device according to some embodiments. For reference, FIGS. 8 to 11 may be cross-sectional views taken along line AA' of FIG. 3. For convenience of explanation, content that overlaps with that described using FIGS. 1 to 7 is omitted.

[0110] First, referring to FIG. 8, a portion of the common source plate (101) may be provided on the extension area (R2).

[0111] Forming a cell substrate (100) may include first forming a free common source plate (101P in FIG. 21), etching the free common source plate (101P in FIG. 21) to form a trench, and forming an insulating pattern (102) that fills the trench.

[0112] A common source plate (101) can be formed on an extended region (R2) according to the mask used when etching the free common source plate (101P in FIG. 21) to form the trench. At this time, the insulation pattern (102) overlaps the cell contact (150) and the first input / output contact (170) in the third direction (Z). The common source plate (101) on the extended region (R2) does not overlap the cell contact (150) in the third direction (Z).

[0113] Referring to FIG. 9, the cell pad (C_PAD), extension pad (EX_PAD), extension via (EX_VA), and cell via (C_VA) may not be formed.

[0114] Cell vias (C_VA) and cell pads (C_PAD) may not be formed on the common source plate (101) of the cell array region (R1). Extension vias (EX_VA) and extension pads (EX_PAD) may not be formed on the insulating pattern (102) of the extension region (R2).

[0115] Referring to FIG. 10, the cell pad (C_PAD), extension pad (EX_PAD), extension via (EX_VA), and cell via (C_VA) may not be formed.

[0116] Additionally, a common source plate (101) may be provided on the extension region (R2). The insulation pattern (102) on the extension region (R2) is illustrated as having a width that gradually decreases in the first direction (X) as it moves from the rear surface (100b) of the cell substrate (100) toward the front surface (100a) of the cell substrate (100), but is not limited thereto.

[0117] Referring to FIG. 11, a non-volatile memory device according to some embodiments may be a double stack non-volatile memory device.

[0118] For example, the mold structure (MS) may include a lower mold structure (MS1) and an upper mold structure (MS2). The lower mold structure (MS1) may be provided on the front surface (100a) of the cell substrate (100). The upper mold structure (MS2) may be provided on the lower mold structure (MS1). The upper mold structure (MS2) may be interposed between the peri structure (PERI) and the lower mold structure (MS1).

[0119] The lower mold structure (MS1) may be configured by alternately stacking lower gate electrodes (ECL, GSL, WL11~WL1n) and lower mold insulating film (112). The upper mold structure (MS2) may be configured by alternately stacking upper gate electrodes (WL21~WL2n, SSL) and upper mold insulating film (114). The channel structure (CH) may penetrate the upper mold structure (MS2) and the lower mold structure (MS1) on the cell array region (R1) in a third direction (Z). The lower mold insulating film (112) and the upper mold insulating film (114) may each include at least one insulating material, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0120] In some embodiments, the first interlayer insulating film (140) may include a first lower interlayer insulating film (142) and a first upper interlayer insulating film (144). The first lower interlayer insulating film (142) may cover the lower mold structure (MS1). The first upper interlayer insulating film (144) may be provided on the first lower interlayer insulating film (142). The first upper interlayer insulating film (144) may be interposed between the first lower interlayer insulating film (142) and the ferri structure (PERI). The first lower interlayer insulating film (142) and the first upper interlayer insulating film (144) may each include an oxide-based insulating material. The first lower interlayer insulating film (142) and the first upper interlayer insulating film (144) may each comprise, for example, at least one of silicon oxide, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant smaller than that of silicon oxide, but are not limited thereto.

[0121] The cell contact (150) can penetrate the first upper interlayer insulating film (144), the first lower interlayer insulating film (142), and the mold structure (MS) in the extension region (R2). The source contact (160) can penetrate the first upper interlayer insulating film (144) and the first lower interlayer insulating film (142) in the pad region (R3). The first input / output contact (170) can penetrate the first upper interlayer insulating film (144) and the first lower interlayer insulating film (142) in the pad region (R3).

[0122] FIGS. 12 and 13 are exemplary drawings for illustrating a non-volatile memory device according to some embodiments. For reference, FIGS. 12 and 13 may be enlarged cross-sectional views of the Q region of FIG. 4. For convenience of explanation, content that overlaps with that described using FIGS. 1 through 7 is omitted.

[0123] First, referring to FIG. 12, the input / output via (IO_VA) and the first input / output contact (170) can be misaligned in the third direction (Z). The input / output via (IO_VA) and the first input / output contact (170) can be offset in the third direction (Z).

[0124] The extension via (EX_VA) and the cell contact (150) can be misaligned in the third direction (Z). The extension via (EX_VA) and the cell contact (150) can be offset in the third direction (Z).

[0125] In some embodiments, the upper surface (170US) of the first input / output contact (170) may be in contact with the insulation pattern (102). The input / output via (IO_VA) may not be in contact with part of the first input / output contact (170). The upper surface (150US) of the cell contact (150) may be in contact with the insulation pattern (102). The extension via (EX_VA) may not be in contact with part of the cell contact (150).

[0126] Referring to FIG. 13, the upper surface (170US) of the first input / output contact (170) and the lower surface (IO_VA_BS) of the input / output via (IO_VA) can be placed on the same plane.

[0127] The input / output via (IO_VA) may not wrap around the first input / output contact (170). The input / output via (IO_VA) may not overlap with the first input / output contact (170) in the first direction (X).

[0128] The upper surface (150US) of the cell contact (150) and the lower surface (EX_VA_BS) of the extension via (EX_VA) may lie on the same plane. The extension via (EX_VA) may not wrap around the cell contact (150). The extension via (EX_VA) may not overlap with the cell contact (150) in the first direction (X).

[0129] Hereinafter, a method for manufacturing a non-volatile memory device according to some embodiments of the present invention will be described.

[0130] FIGS. 14 to 27 are drawings sequentially illustrating the process of manufacturing a non-volatile memory device having the cross-section of FIG. 4.

[0131] Referring to FIG. 14, a substrate (SUB) is provided. The substrate (SUB) may be a silicon wafer.

[0132] A liner film (LF) may be formed on a substrate (SUB). The liner film (LF) may include titanium nitride (TiN), but is not limited thereto. A free cell substrate (100P) may be formed on the liner film (LF). The free cell substrate (100P) may include a front surface (100Pa) and a rear surface (100Pb) facing each other. The rear surface (100Pb) of the free cell substrate (100P) may face the substrate (SUB). The front surface (100Pa) of the free cell substrate (100P) may face the rear surface (100Pb). The free cell substrate (100P) may include polysilicon.

[0133] On the front surface (100Pa) of a free cell substrate (100P), a mold insulating film (110) and a mold sacrificial film (ILD_SC) may be alternately stacked. The mold insulating film (110) and the mold sacrificial film (ILD_SC) may be stacked in a stepped manner. The mold insulating film (110) may include an oxide-based insulating material. The mold sacrificial film (ILD_SC) may include a material having an etching selectivity ratio with respect to the mold insulating film (110). For example, the mold sacrificial film (ILD_SC) may include a nitride-based insulating material. For example, the mold sacrificial film (ILD_SC) may include silicon nitride (SiN), but is not limited thereto.

[0134] A channel structure (CH) can be formed penetrating the mold insulating film (110) and the mold sacrificial film (ILD_SC). A channel pad (136) can be formed on the channel structure (CH). A first interlayer insulating film (140) covering the channel structure (CH), the channel pad (136), the mold insulating film (110), and the mold sacrificial film (ILD_SC) can be formed.

[0135] A wordline cutting structure (WLC) penetrating the first interlayer insulating film (140), the mold insulating film (110), and the mold sacrificial film (ILD_SC) can be formed.

[0136] Referring to FIG. 15, first, a cell contact (150) may be formed. The cell contact (150) may be formed by penetrating the first interlayer insulating film (140), the mold insulating film (110), and the mold sacrificial film (ILD_SC). A portion of the cell contact (150) may be formed within the pre-cell substrate (100P). The upper surface (150US) of the cell contact (150) may be provided between the front surface (100Pa) and the rear surface (100Pb) of the pre-cell substrate (100P). The upper surface (150US) of the cell contact (150) may face the substrate (SUB).

[0137] A source contact (160) may be formed. The source contact (160) may be formed by penetrating the first interlayer insulating film (140). A portion of the source contact (160) may be formed within the free cell substrate (100P). The upper surface (160US) of the source contact (160) may be provided between the front surface (100Pa) and the rear surface (100Pb) of the free cell substrate (100P). The upper surface (160US) of the source contact (160) may face the substrate (SUB).

[0138] A first input / output contact (170) may be formed. The first input / output contact (170) may be formed by penetrating the first interlayer insulating film (140). A portion of the first input / output contact (170) may be formed within the free cell substrate (100P). The upper surface (170US) of the first input / output contact (170) may be provided between the front surface (100Pa) and the rear surface (100Pb) of the free cell substrate (100P). The upper surface (170US) of the first input / output contact (170) may face the substrate (SUB).

[0139] Next, gate electrodes (ECL, GSL, WL1~WLn, SSL) can be formed. The gate electrodes (ECL, GSL, WL1~WLn, SSL) can be formed through a replacement process. The mold sacrificial layer (ILD_SC) is removed, and the gate electrodes (ECL, GSL, WL1~WLn, SSL) can be formed in the space where the mold sacrificial layer (ILD_SC) was removed.

[0140] Referring to FIG. 16, a bitline contact plug (BLPG), a bitline (BL), a first contact (155), a second contact (165), a third contact (175), a first bonding contact (185), and a first bonding metal (190) may be formed.

[0141] First, a bitline contact plug (BLPG), a first contact (155), a second contact (165), and a third contact (175) may be formed. The bitline contact plug (BLPG) may be connected to a channel pad (136). The first contact (155) may be connected to a cell contact (150). The second contact (165) may be connected to a source contact (160). The third contact (175) may be connected to a first input / output contact (170).

[0142] Next, a bit line (BL) can be formed. The bit line (BL) can be extended in a second direction (Y). The bit line (BL) can be connected to a bit line contact plug (BLPG), a first contact (155), a second contact (165), and a third contact (175).

[0143] Next, a first bonding contact (185) and a first bonding metal (190) can be formed sequentially. The first bonding contact (185) and the first bonding metal (190) can be connected to a bit line (BL). The first bonding metal (190) can define a second surface (CELL_b) of the cell structure.

[0144] Referring to FIG. 17, a PERI structure (PERI) may be provided. The PERI structure (PERI) may be the same as the PERI structure (PERI) described in FIG. 4.

[0145] The peristructure (PERI) includes a third surface (PERI_a) and a fourth surface (PERI_b) facing each other. The second surface (CELL_b) of the cell structure can be bonded to the third surface (PERI_a) of the peristructure (PERI). The first bonding metal (190) and the second bonding metal (290) can be bonded to each other. Through the first bonding metal (190) and the second bonding metal (290), the cell structure (CELL) to be formed later and the peristructure (PERI) can be electrically connected to each other.

[0146] Referring to FIG. 18, the substrate (SUB), the liner film (LF), and the free cell substrate (100P) can be removed.

[0147] The free cell substrate (100P) is removed so that a portion of the first input / output contact (170), a portion of the source contact (160), a portion of the cell contact (150), a portion of the channel structure (CH), and a portion of the wordline cutting structure (WLC) may be exposed.

[0148] Figure 19 is an enlarged cross-sectional view of the R region of Figure 18.

[0149] Referring to FIG. 19, the free cell substrate (100P) can be removed so that a portion of the channel structure (CH) is exposed. A portion of the information storage film (132) of the channel structure (CH) can be exposed.

[0150] FIG. 21 is an enlarged cross-sectional view of the R region of FIG. 20.

[0151] Referring to FIGS. 20 and 21, a portion of the exposed information storage film (132) may be removed. This may expose the semiconductor pattern (130). The upper surface (130US) of the semiconductor pattern (130) and a portion of the sidewall of the semiconductor pattern (130) may be exposed.

[0152] Referring to FIG. 22, a free common source plate (101P) may be formed. The free common source plate (101P) may cover the exposed first input / output contact (170), source contact (160), cell contact (150), channel structure (CH), and wordline cutting structure (WLC). The free common source plate (101P) may be in contact with the exposed semiconductor pattern (130). The free common source plate (101P) may comprise doped polysilicon or metal, but is not limited thereto.

[0153] Referring to FIG. 23, a common source plate (101) can be formed by etching a free common source plate (101P).

[0154] The free common source plate (101P) can be etched to expose a portion of the first input / output contact (170) and the cell contact (150). The common source plate (101) can be connected to the source contact (160) and the channel structure (CH). The common source plate (101) does not overlap the cell contact (150) and the first input / output contact (170) in the third direction (Z).

[0155] Referring to FIG. 24, an insulating pattern (102) may be formed. The insulating pattern (102) may cover the exposed first input / output contact (170) and cell contact (150). The insulating pattern (102) may be formed between the common source plate (101). The common source plate (101) and the insulating pattern (102) may form a cell substrate (100).

[0156] A cell substrate (100) may include a cell array region (R1), an extension region (R2), and a pad region (R3). A common source plate (101) may be disposed on the cell array region (R1). A common source plate (101) may not be disposed on the extension region (R2). An insulating pattern (102) may be disposed on the extension region (R2). A common source plate (101) may be disposed on a part of the pad region (R3). An insulating pattern (102) may be disposed on another part of the pad region (R3).

[0157] The cell substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. The front surface (100a) of the cell substrate (100) may be in contact with a first interlayer insulating film (140) or a mold insulating film (110). The upper surface (170US) of the first input / output contact (170) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100). The upper surface (150US) of the cell contact (150) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100).

[0158] Referring to FIG. 25, a second interlayer insulating film (103) and an upper insulating film (104) may be formed on the rear surface (100b) of the cell substrate (100).

[0159] First, a second interlayer insulating film (103) may be formed on the rear surface (100b) of the cell substrate (100). An upper insulating film (104) may be formed on the second interlayer insulating film (103). The upper surface of the upper insulating film (104) may define the first surface (CELL_a) of the cell structure.

[0160] Referring to FIG. 26, a first trench (t1) can be formed by penetrating the upper insulating film (104) and the second interlayer insulating film (103). Second and third trenches (t2, t3) can be formed by penetrating the upper insulating film (104) and the second interlayer insulating film (103) and etching the cell substrate (100).

[0161] The first trench (t1) may be formed on the cell array region (R1). The first trench (t1) may be a trench for forming cell vias (C_VA). The bottom surface (t1_BS) of the first trench (t1) may be placed coplanar with the rear surface (100b) of the cell substrate (100).

[0162] A second trench (t2) may be formed on an extension region (R2). The second trench (t2) may be a trench for forming an extension via (EX_VA). The bottom surface (t2_BS) of the second trench (t2) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100). The second trench (t2) may expose the top surface (150US) of the cell contact (150). The second trench (t2) may also expose a portion of the sidewall of the cell contact (150).

[0163] A third trench (t3) may be formed on the pad area (R3). The third trench (t3) may be a trench for forming an input / output via (IO_VA). The bottom surface (t3_BS) of the third trench (t3) may be provided between the front surface (100a) and the rear surface (100b) of the cell substrate (100). The third trench (t3) may expose the top surface (170US) of the first input / output contact (170). The third trench (t3) may also expose a portion of the sidewall of the first input / output contact (170).

[0164] In some embodiments, the bottom surface (t2_BS) of the second trench (t2) and the bottom surface (t3_BS) of the third trench (t3) may lie on the same plane. The second trench (t2) and the third trench (t3) may be formed through the same process. In some embodiments, the vertical depth in the third direction (Z) of the second trench (t2) and the third trench (t3) may be greater than the vertical depth in the third direction (Z) of the first trench (t1). Although the first to third trenches (t1, t2, t3) may be formed through the same process, the common source plate (101) and the insulation pattern (102) may have an etch selectivity ratio. As a result, the vertical depth in the third direction (Z) of the second trench (t2) and the third trench (t3) may be greater than the vertical depth in the third direction (Z) of the first trench (t1).

[0165] Referring to FIG. 27, a cell via (C_VA) filling the first trench (t1) may be formed. An extension via (EX_VA) filling the second trench (t2) may be formed. An input / output via (IO_VA) filling the third trench (t3) may be formed.

[0166] Next, a cell pad (C_PAD) connected to a cell via (C_VA) may be formed. An extension pad (EX_PAD) connected to an extension via (EX_VA) may be formed. A first input / output pad (IO_PAD) connected to an input / output via (IO_VA) may be formed.

[0167] Thus, a cell structure can be formed. The cell structure may be identical to the cell structure described in FIG. 4.

[0168] Hereinafter, with reference to FIGS. 1 to 7 and FIGS. 28 to 30, an electronic system including a non-volatile memory device according to exemplary embodiments is described.

[0169] FIG. 28 is an exemplary block diagram illustrating an electronic system according to some embodiments. FIG. 29 is an exemplary perspective view illustrating an electronic system according to some embodiments. FIG. 30 is a schematic cross-sectional view cut along line II of FIG. 29.

[0170] Referring to FIG. 28, an electronic system (1000) according to some embodiments may include a non-volatile memory device (1100) and a controller (1200) electrically connected to the non-volatile memory device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more non-volatile memory devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD) comprising one or more non-volatile memory devices (1100), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device.

[0171] The non-volatile memory device (1100) may be, for example, a NAND flash memory device, or, for example, a non-volatile memory device described above using FIGS. 1 to 7. The non-volatile memory device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F).

[0172] The first structure (1100F) may be a peripheral circuit structure comprising a decoder circuit (1110; e.g., row decoder (33) of FIG. 1), a page buffer (1120; e.g., page buffer (35) of FIG. 1), and a logic circuit (1130; e.g., control logic (37) of FIG. 1).

[0173] The second structure (1100S) may include the common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR) described above using FIG. 2. The cell strings (CSTR) may be connected to the decoder circuit (1110) through a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Additionally, the cell strings (CSTR) may be connected to the page buffer (1120) through the bit lines (BL).

[0174] In some embodiments, the common source line (CSL) and cell string (CSTR) may be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S).

[0175] In some embodiments, bit lines (BL) may be electrically connected to a page buffer (1120) through second connecting wires (1125) extending from a first structure (1100F) to a second structure (1100S).

[0176] A non-volatile memory device (1100) can communicate with a controller (1200) through an input / output pad (1101) that is electrically connected to a logic circuit (1130; e.g., control logic (37) of FIG. 1). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0177] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). In some embodiments, the electronic system (1000) may include a plurality of non-volatile memory devices (1100), and in this case, the controller (1200) may control the plurality of non-volatile memory devices (1100).

[0178] The processor (1210) can control the operation of the entire electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the non-volatile memory device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the non-volatile memory device (1100). Through the NAND interface (1221), control commands for controlling the non-volatile memory device (1100), data to be written to the memory cell transistors (MCT) of the non-volatile memory device (1100), data to be read from the memory cell transistors (MCT) of the non-volatile memory device (1100), etc., may be transmitted. The host interface (1230) may provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the non-volatile memory device (1100) in response to the control command.

[0179] Referring to FIGS. 28 to 30, an electronic system according to some embodiments may include a main board (2001), a main controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003) and DRAM (2004). The semiconductor packages (2003) and DRAM (2004) may be connected to the main controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0180] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In some embodiments, the electronic system (2000) may communicate with the external host according to any one of the interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In some embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a main controller (2002) and a semiconductor package (2003).

[0181] The main controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0182] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the electronic system (2000) includes the DRAM (2004), the main controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0183] A semiconductor package (2003) may include a first semiconductor package (2003a) and a second semiconductor package (2003b) spaced apart from each other. The first semiconductor package (2003a) and the second semiconductor package (2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). The first semiconductor package (2003a) and the second semiconductor package (2003b) may each include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0184] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 28.

[0185] In some embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first semiconductor package (2003a) and the second semiconductor package (2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). In some embodiments, in each of the first semiconductor package (2003a) and the second semiconductor package (2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0186] In some embodiments, the main controller (2002) and the semiconductor chips (2200) may be included in a single package. In some embodiments, the main controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the main controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0187] In some embodiments, the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body (2120), package upper pads (2130) disposed on the upper surface of the package substrate body (2120), lower pads (2125) disposed on the lower surface of the package substrate body (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) may be connected to wiring patterns (2005) of the main board (2001) of the electronic system (2000) through conductive connections (2800) as shown in FIG. 29.

[0188] Referring to FIGS. 29 and FIGS. 30, in an electronic system according to some embodiments, each of the semiconductor chips (2200) may include a non-volatile memory device as described above using FIGS. 1 through 7. For example, each of the semiconductor chips (2200) may include a PERI structure and a cell structure (CELL). For example, the PERI structure may include a PERi substrate (200) and a peripheral circuit element (PT) as described above using FIGS. 3 through 7. Also, for example, the cell structure (CELL) may include a cell substrate (100), a mold structure (MS), a channel structure (CH), a wordline cutting structure (WLC), a bit line (BL), and a cell contact (150) as described above using FIGS. 3 through 7.

[0189] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0190] 100: Cell substrate 101: Common source plate 102: Insulation pattern 103: Second interlayer insulation film 110: Mold insulating film MS: Mold structure 140: 1st interlayer insulating film BL: Bit line CH: Channel structure 150: Cell contact 160: Source contact 170: 1st I / O contact C_VA: Cell via EX_VA: Extended via IO_VA: I / O via C_PAD: Cell pad EX_PAD: Extension pad IO_PAD: Input / Output pad

Claims

Claim 1 A cell substrate comprising a cell array region, an extension region, and a pad region, and having a front and rear surface facing each other, and comprising a common source plate and an insulating pattern; a mold structure comprising a plurality of gate electrodes and a plurality of mold insulating films disposed on the front surface of the cell substrate, stacked sequentially in the cell array region, stacked in a stepped manner in the extension region, and alternately stacked; a channel structure connected to the common source plate by penetrating the mold structure on the cell array region; a cell contact connected to at least one of the plurality of gate electrodes by penetrating the mold structure on the extension region; a first interlayer insulating film disposed on the front surface of the cell substrate and covering the mold structure; a second interlayer insulating film disposed on the rear surface of the cell substrate; an input / output pad provided on the second interlayer insulating film of the pad region; and an input / output contact penetrating the first interlayer insulating film on the pad region. A non-volatile memory device comprising, on the pad region, an input / output via that connects the input / output contact and the input / output pad to each other by etching the second interlayer insulating film and the cell substrate, wherein the common source plate is non-overlapping in a first direction perpendicular to the cell contact and the front surface of the input / output contact and the cell substrate, the insulating pattern surrounds a portion of the input / output via and includes an insulating material, the front surface of the common source plate and the front surface of the insulating pattern are located on the same plane, and the rear surface of the common source plate and the rear surface of the insulating pattern are located on the same plane. Claim 2 A non-volatile memory device according to claim 1, wherein the common source plate is not placed in the extension region. Claim 3 A non-volatile memory device according to claim 1, wherein the upper surface of the cell contact is provided between the front surface of the cell substrate and the rear surface of the cell substrate. Claim 4 A non-volatile memory device according to claim 1, wherein the upper surface of the input / output contact is provided between the front surface of the cell substrate and the rear surface of the cell substrate. Claim 5 A non-volatile memory device according to claim 1, further comprising a cell pad provided on the second interlayer insulating film of the cell array region, and a cell via that penetrates the second interlayer insulating film on the common source plate of the cell array region to connect the common source plate and the cell pad to each other, wherein the bottom surface of the cell via is placed in the same plane as the rear surface of the cell substrate. Claim 6 A cell structure comprising a first surface and a second surface facing each other; and a peristructure bonded to the cell structure and comprising a third surface bonded to the second surface and a fourth surface facing the third surface, wherein the cell structure comprises a cell array region, an extension region, and a pad region, and comprises a front surface and a rear surface facing each other, and comprises a cell substrate including a common source plate and an insulating pattern, wherein the front surface of the cell substrate faces the peristructure; a mold structure disposed on the front surface of the cell substrate and comprising a plurality of gate electrodes that are stacked sequentially in the cell array region and stacked in a stepped manner in the extension region and alternately stacked, and a plurality of mold insulating films; a channel structure penetrating the mold structure on the cell array region and connected to the common source plate; a cell contact penetrating the mold structure on the extension region and connected to at least one of the plurality of gate electrodes; and a first interlayer insulating film disposed on the front surface of the cell substrate and covering the mold structure. An input / output contact penetrating the first interlayer insulating film on the pad region; a second interlayer insulating film disposed on the rear surface of the cell substrate; a cell pad provided on the second interlayer insulating film of the cell array region; an extension pad provided on the second interlayer insulating film of the extension region; an input / output pad provided on the second interlayer insulating film of the pad region; a cell via on a common source plate of the cell array region, penetrating the second interlayer insulating film to connect the common source plate and the cell pad to each other; an extension via on the extension region, etching the second interlayer insulating film and the insulating pattern to connect the cell contact and the extension pad to each other;A non-volatile memory device comprising, on the pad region, an input / output via that connects the input / output contact and the input / output pad to each other by etching the second interlayer insulating film and the insulating pattern, wherein the bottom surface of the extension via and the bottom surface of the input / output via are provided between the front surface of the cell substrate and the rear surface of the cell substrate, and the insulating pattern overlaps in a first direction perpendicular to the cell contact and the input / output contact and the front surface of the cell substrate, surrounds a portion of the input / output via, and includes an insulating material, wherein the common source plate does not overlap with the cell contact and the input / output contact in the first direction, the front surface of the common source plate and the front surface of the insulating pattern are located on the same plane, and the rear surface of the common source plate and the rear surface of the insulating pattern are located on the same plane. Claim 7 A non-volatile memory device according to claim 6, wherein the upper surface of the cell contact is provided between the front surface of the cell substrate and the rear surface of the cell substrate. Claim 8 A non-volatile memory device according to claim 6, wherein the upper surface of the input / output contact is provided between the front surface of the cell substrate and the rear surface of the cell substrate. Claim 9 A main substrate; a non-volatile memory device on the main substrate; and a controller electrically connected to the non-volatile memory device on the main substrate, wherein the non-volatile memory device comprises a cell array region, an extension region, and a pad region, and comprises a cell substrate having a front surface and a rear surface facing each other, and a common source plate and an insulating pattern; a mold structure disposed on the front surface of the cell substrate and having a plurality of gate electrodes and a plurality of mold insulating films that are stacked sequentially in the cell array region and stacked in a stepped manner in the extension region and alternately stacked; a channel structure that penetrates the mold structure on the cell array region and is connected to the common source plate; a cell contact that penetrates the mold structure on the extension region and is connected to at least one of the plurality of gate electrodes; a first interlayer insulating film disposed on the front surface of the cell substrate and covering the mold structure; a second interlayer insulating film disposed on the rear surface of the cell substrate; an input / output pad provided on the second interlayer insulating film of the pad region; and an input / output contact penetrating the first interlayer insulating film on the pad region. An electronic system comprising, on the pad region, an input / output via that connects the input / output contact and the input / output pad to each other by etching the second interlayer insulating film and the cell substrate, wherein the common source plate is non-overlapping in a first direction perpendicular to the cell contact and the front surface of the input / output contact and the cell substrate, the insulating pattern surrounds a portion of the input / output via and includes an insulating material, the front surface of the common source plate and the front surface of the insulating pattern are located on the same plane, and the rear surface of the common source plate and the rear surface of the insulating pattern are located on the same plane. Claim 10 A free cell substrate is provided comprising a front surface and a rear surface facing each other, and a mold structure is formed on the front surface of the free cell substrate in which a plurality of mold insulating films and a plurality of gate electrodes are alternately stacked, an interlayer insulating film is formed covering the mold structure, and a cell contact is formed penetrating the mold structure and connected to at least one of the plurality of gate electrodes, the upper surface of the cell contact is provided between the front surface and the rear surface of the free cell substrate, and an input / output contact is formed penetrating the interlayer insulating film, the upper surface of the input / output contact is provided between the front surface and the rear surface of the free cell substrate, and the free cell substrate is removed to form a cell substrate, wherein the cell substrate comprises a front surface and a rear surface facing each other and comprises a common source plate and an insulating pattern, wherein the front surface of the common source plate and the front surface of the insulating pattern are located on the same plane, and the rear surface of the common source plate and the rear surface of the insulating pattern are located on the same plane, and the common source plate is in a first direction perpendicular to the input / output contact and the cell contact and the front surface of the cell substrate. A method for manufacturing a non-volatile memory device comprising: non-overlapping, wherein the insulating pattern overlaps the input / output contact and the cell contact in the first direction, wherein the insulating pattern includes an insulating material, and wherein the cell substrate is etched to form an input / output via connected to the input / output contact, wherein the bottom surface of the input / output via is provided between the front and rear surfaces of the cell substrate, and wherein the insulating pattern surrounds a portion of the input / output via.

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