Phototransistor, display device and method of the phototransistor

Abstract

A phototransistor according to one embodiment of the present invention includes a gate electrode, a semiconductor layer disposed on the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor layer, a source electrode and a drain electrode, and a porous layer disposed on the source electrode, the semiconductor layer, and the drain electrode. By including a porous layer in which a plurality of holes are defined, the phototransistor can capture external light provided to the phototransistor or increase the amount of external light provided to the semiconductor layer through internal scattering.

Description

Technology Field

[0001] The present invention relates to a phototransistor, an electronic device having the same, and a method for manufacturing a phototransistor, and more specifically, to a phototransistor that senses light, an electronic device having the same, and a method for manufacturing a phototransistor. Background Technology

[0002] A phototransistor is a device designed to convert optical signals into electrical signals; electrons and holes are generated by light irradiated at the junction between the base and collector of the transistor, thereby producing an output current.

[0003] Electronic devices provide various functions that enable organic communication with the user, such as displaying images to provide information or detecting user input. Recent electronic devices also include functions to detect the user's biometric information.

[0004] Biometric information recognition methods include the capacitive method, which detects changes in capacitance formed between electrodes; the optical method, which detects incident light using optical sensors; and the ultrasonic method, which detects vibrations using piezoelectric materials. The problem to be solved

[0005] The object of the present invention is to provide a phototransistor with improved light sensing performance and an electronic device including said phototransistor.

[0006] The objective of the present invention is to provide a method for manufacturing a phototransistor with improved optical sensing performance. means of solving the problem

[0007] A phototransistor according to one embodiment of the present invention comprises a gate electrode, a semiconductor layer disposed on the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the semiconductor layer, and a porous layer disposed on the source electrode, the semiconductor layer and the drain electrode, having a plurality of holes defined therein.

[0008] The above semiconductor layer may include an oxide semiconductor.

[0009] The above porous layer may contain organic material.

[0010] The porous layer comprises a first subporous layer containing an organic material and a second subporous layer disposed on the first subporous layer and containing an inorganic material, and the plurality of holes may include a first subhole formed by penetrating the second subporous layer and a second subhole formed by penetrating the first subporous layer.

[0011] The above phototransistor may further include a protective layer on the porous layer.

[0012] A first portion in which the semiconductor layer, the source electrode, and the drain electrode overlap in a plane and a second portion in which they do not overlap are defined, and the plurality of holes may overlap with the first and second portions.

[0013] The source electrode and the drain electrode may include a transparent conductive material.

[0014] The plurality of holes are spaced apart from each other on a plane, and the sizes of the plurality of holes on the plane may be the same.

[0015] The plurality of holes mentioned above can be formed by penetrating the porous layer.

[0016] An electronic device according to one embodiment of the present invention includes a base layer, a display element layer including a light-emitting element, and a circuit layer disposed between the base layer and the display element layer. The circuit layer includes a pixel driving circuit electrically connected to the light-emitting element and a phototransistor having a light-sensing function. The phototransistor may have a gate electrode, a semiconductor layer disposed on the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the gate insulating layer, and a porous layer disposed on the source electrode, the semiconductor layer, and the drain electrode, having a plurality of holes defined therein.

[0017] The above semiconductor layer may include an oxide semiconductor.

[0018] The above porous layer may contain organic material.

[0019] The porous layer comprises a first subporous layer containing an organic material and a second subporous layer disposed on the first subporous layer and containing an inorganic material, and the plurality of holes may be defined by penetrating the first and second subporous layers.

[0020] An electronic device according to one embodiment of the present invention may further include a protective layer on the porous layer.

[0021] An electronic device comprising a window, a display module disposed below the window, a sensing unit disposed below the display module, and a housing coupled to the window and accommodating the display module and the sensing unit, wherein the sensing unit includes a phototransistor having a light-sensing function, and the phototransistor has a gate electrode, a semiconductor layer disposed on the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the gate insulating layer, and a porous layer disposed on the source electrode, the semiconductor layer, and the drain electrode, having a plurality of holes defined therein.

[0022] The above semiconductor layer may include an oxide semiconductor.

[0023] The above porous layer may contain organic material.

[0024] The porous layer comprises a first subporous layer containing an organic material and a second subporous layer disposed on the first subporous layer and containing an inorganic material, and the plurality of holes may be defined by penetrating the first and second subporous layers.

[0025] A method for manufacturing a phototransistor according to one embodiment of the present invention may include the steps of forming a gate electrode, forming a gate insulating layer on the gate electrode, forming a source electrode, a semiconductor layer, and a drain electrode on the gate insulating layer, forming a porous layer on the source electrode, the semiconductor layer, and the drain electrode, and forming a plurality of holes that expose the semiconductor layer in the porous layer.

[0026] The step of forming the plurality of holes may include the step of forming an organic layer on the source electrode, the semiconductor layer, and the drain electrode; the step of depositing nanoparticles on the organic layer; the step of forming an inorganic layer on the organic layer to fix the nanoparticles to the organic layer; the step of removing the nanoparticles to form a first subporous layer; and the step of patterning the organic layer using the first subporous layer as a mask to form a second subporous layer.

[0027] The thickness of the first subporous layer may be smaller than the diameter of the nanoparticle.

[0028] A method for manufacturing a phototransistor may further include a step of aligning the nanoparticles using a magnetic field after the step of scattering the nanoparticles on the organic layer.

[0029] The method for manufacturing a phototransistor may further include the step of forming a protective layer on the porous layer.

[0030] The step of removing the nanoparticles may include removing all nanoparticles using a polymer roller on a large substrate.

[0031] The step of removing the nanoparticles may include a step of selectively etching and removing the nanoparticles through a dry or wet etching process. Effects of the invention

[0032] According to one embodiment of the present invention, by including a porous layer, the phototransistor can capture external light provided to the phototransistor or increase the amount of external light provided to the semiconductor layer through internal scattering.

[0033] In addition, the light absorption rate of the phototransistor can be controlled by adjusting the size and number of multiple holes provided in the porous layer. Brief explanation of the drawing

[0034] FIG. 1a is a cross-sectional view of a phototransistor according to one embodiment of the present invention. FIG. 1b is a perspective view of the phototransistor shown in FIG. 1a. FIG. 2a is a cross-sectional view of a phototransistor according to one embodiment of the present invention. FIG. 2b is a perspective view of the phototransistor shown in FIG. 2a. FIG. 3a is a cross-sectional view of a phototransistor according to one embodiment of the present invention. FIG. 3b is a perspective view of the phototransistor shown in FIG. 3a. Figure 4a is a graph showing the photoresponse of a comparative phototransistor to red light. FIG. 4b is a graph showing the photoresponse of a phototransistor to red light according to one embodiment of the present invention. Figure 5a is a graph showing the photoresponse of a comparative phototransistor to green light. FIG. 5b is a graph showing the photoresponse of a phototransistor to green light according to one embodiment of the present invention. FIG. 6 is a graph showing the photoresponse to green light in a phototransistor according to one embodiment of the present invention. FIG. 7 is a graph illustrating the continuous photocurrent phenomenon when green light is irradiated onto a phototransistor (PT) according to one embodiment of the present invention. FIG. 8 is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 9 is an exploded perspective view of an electronic device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view of an electronic device according to one embodiment of the present invention. FIG. 11a is a circuit diagram showing a pixel and a sensor provided in a display panel according to one embodiment of the present invention. FIG. 11b is a cross-sectional view of a display panel according to one embodiment of the present invention. FIGS. 12a and 12b are cross-sectional views of a display panel according to an embodiment of the present invention. FIG. 13a is an exploded perspective view of an electronic device according to one embodiment of the present invention. FIG. 13b is a cross-sectional view taken along the cutting line VI-VI' shown in FIG. 13a. FIGS. 14a to 14f are process diagrams illustrating a method for manufacturing a phototransistor according to one embodiment of the present invention. FIG. 15a is a cross-sectional view taken along the cutting line I-I' shown in FIG. 14a. FIG. 15b is a cross-sectional view taken along the cutting line II-II' shown in FIG. 14b. FIG. 15c is a cross-sectional view taken along the cutting line Ⅲ-Ⅲ' shown in FIG. 14c. FIG. 15d is a cross-sectional view taken along the cutting line Ⅳ-Ⅳ' shown in FIG. 14e. FIG. 15e is a cross-sectional view of the phototransistor of FIG. 14f cut along the cutting line V-V'. FIG. 16 is a process diagram showing a method for manufacturing a phototransistor according to one embodiment of the present invention. Specific details for implementing the invention

[0035] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0036] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0037] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content.

[0038] "And / or" includes all one or more combinations that the associated configurations can define.

[0039] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0040] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Additionally, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and are explicitly defined herein unless interpreted in an ideal or overly formal sense.

[0042] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0043] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0045] FIG. 1a is a cross-sectional view of a phototransistor according to one embodiment of the present invention, and FIG. 1b is a perspective view of the phototransistor shown in FIG. 1a.

[0046] Referring to FIGS. 1a and 1b, a phototransistor (PT) according to one embodiment of the present invention may include a substrate (SB), a gate electrode (PTG), a gate insulating layer (GIL), a semiconductor layer (SCL), a source electrode (SE), a drain electrode (DE), and a porous layer (PL).

[0047] The substrate (SB) may provide a base surface on which a gate electrode (PTG) is placed. The substrate (SB) may be a semiconductor substrate (e.g., a silicon substrate, a compound semiconductor substrate). Specifically, the substrate (SB) may be a P++ semiconductor or a silicon dioxide (SiO2) substrate. However, it is not limited thereto, and the substrate (SB) may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0048] A gate electrode (PTG) may be formed on a substrate (SB). The gate electrode (PTG) may be an electrode pattern formed by patterning a conductive material. According to one embodiment of the present invention, the gate electrode (PTG) may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0049] A gate insulating layer (GIL) covering a gate electrode (PTG) is disposed on a substrate (SB). The gate insulating layer (GIL) may include an insulating material. Specifically, the gate insulating layer (GIL) may include silicon oxide or silicon nitride. However, it is not limited thereto, and the gate insulating layer (GIL) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. According to one embodiment of the present invention, the gate insulating layer (GIL) may include silicon dioxide (SiO2).

[0050] A semiconductor layer (SCL) may be disposed on a gate insulating layer (GIL). The semiconductor layer (SCL) may be disposed on the gate insulating layer (GIL) so as to face a gate electrode (PTG). A source electrode (SE) and a drain electrode (DE) may be disposed on the gate insulating layer (GIL) and the semiconductor layer (SCL). The source electrode (SE) and the drain electrode (DE) may be disposed spaced apart from each other on the semiconductor layer (SCL). According to one embodiment of the present invention, the source electrode (SE) may be in contact with one side of the semiconductor layer (SCL), and the drain electrode (DE) may be in contact with the other side of the semiconductor layer (SCL). The source electrode (SE) and the drain electrode (DE) may be formed extending in opposite directions from the semiconductor layer (SCL). Each of the source electrode (SE) and the drain electrode (DE) comprises a metallic material, and for example, the metallic material may be composed of copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), etc., but is not limited thereto.

[0051] According to one embodiment of the present invention, as a portion of the source electrode (SE) and a portion of the drain electrode (DE) are disposed on the semiconductor layer (SCL), the source electrode (SE) and the drain electrode (DE) may partially overlap with the semiconductor layer (SCL) in a planar manner. Accordingly, a first region (A1) in which the semiconductor layer (SCL) overlaps with the source electrode (SE) and the drain electrode (DE), and a second region (A2) in which the semiconductor layer (SCL) does not overlap with the source electrode (SE) and the drain electrode (DE) may be defined in the phototransistor (PT). According to one embodiment of the present invention, the semiconductor layer (SCL) may have a thickness of about 43.8 nm. Alternatively, in a planar manner, the semiconductor layer (SCL) may not overlap with the source electrode (SE) and the drain electrode (DE). In this case, the semiconductor layer (SCL) is placed on the same layer as the source electrode (SE) and the drain electrode (DE), and can be located between the source electrode (SE) and the drain electrode (DE).

[0052] The semiconductor layer (SCL) may be formed of crystalline silicon, amorphous silicon, or an oxide semiconductor. According to one embodiment of the present invention, the semiconductor layer (SCL) may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. The oxide semiconductor may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc. Oxide semiconductors have superior light-sensing characteristics compared to crystalline silicon and amorphous silicon, but they have a large bandgap of 3.0 eV or more, so they cannot absorb light in the visible and infrared regions and can transmit it.

[0053] Referring to FIGS. 1a and 1b, a porous layer (PL) having a plurality of holes (HS) defined therein may be formed on a semiconductor layer (SCL). According to one embodiment of the present invention, the porous layer (PL) may be an organic layer containing an organic material. However, it is not limited thereto, and the porous layer (PL) may be an inorganic layer containing an inorganic material or may have a structure in which an organic layer and an inorganic layer are stacked. As an example of the present invention, the porous layer (PL) may have a thickness of about 20 nm.

[0054] Referring to FIG. 1b, a plurality of holes (HS) may be arranged spaced apart from each other on a plane. For example, as illustrated, they may be arranged spaced apart from each other on a plane at a constant interval. However, they are not limited thereto, and the plurality of holes (HS) may be arranged spaced apart at different intervals. According to one embodiment of the present invention, the plurality of holes (HS) on a plane may have the same size. For example, the size of the plurality of holes (HS) may be 10 nm or more and 1000 nm or less. However, they are not limited thereto, and the plurality of holes (HS) may have different sizes on a plane. According to one embodiment of the present invention, the plurality of holes (HS) may be formed by penetrating the porous layer (PL). However, they are not limited thereto, and the plurality of holes (HS) may be provided in a recessed form from the upper surface of the porous layer (PL).

[0055] According to one embodiment of the present invention, the source electrode (SE) and the drain electrode (DE) may comprise a transparent conductive material. In this case, external light incident on the first region (A1) may pass through the source electrode (SE) and the drain electrode (DE) formed of the transparent conductive material and be incident on the semiconductor layer (SCL). Accordingly, a plurality of holes (HS) may be formed overlappingly in the first region (A1) and the second region (A2) to capture or guide the external light toward the semiconductor layer (SCL). Alternatively, a plurality of holes (HS) may be formed entirely in the porous layer (PL) as well as in the first region (A1) and the second region (A2).

[0056] If the source electrode (SE) and the drain electrode (DE) contain a metallic material, external light cannot pass through the source electrode (SE) and the drain electrode (DE). Therefore, if the source electrode (SE) and the drain electrode (DE) contain a metallic material, external light incident on the first region (A1) cannot pass through the source electrode (SE) and the drain electrode (DE) and thus cannot be incident on the semiconductor layer (SCL). In this case, a plurality of holes (HS) of the porous layer (PL) can be formed only in the second region (A2) where the source electrode (SE) and the drain electrode (DE) and the semiconductor layer (SCL) do not overlap.

[0057] According to one embodiment of the present invention, the porous layer (PL) includes a plurality of holes (HS) so that external light provided to the phototransistor (PT) can be captured or the amount of external light provided to the semiconductor layer (SCL) can be increased through internal scattering. In addition, the light absorption rate of the phototransistor (PT) can be controlled by adjusting the size and number of the plurality of holes (HS) provided in the porous layer (PL).

[0058] FIG. 2a is a cross-sectional view of a phototransistor according to one embodiment of the present invention, and FIG. 2b is a perspective view of the phototransistor shown in FIG. 2a.

[0059] In FIGS. 2a and 2b, compared to FIGS. 1a and 1b, the porous layer (PLa) shown in FIGS. 2a and 2b has a structure composed of a first subporous layer (PSL1) and a second subporous layer (PSL2). Since the structure disposed below the second subporous layer (PSL2) has the same structure as FIGS. 2a and 2b, a detailed description that is redundant is omitted.

[0060] Referring to FIGS. 2a and 2b, the porous layer (PLa) may include a first subporous layer (PSL1) and a second subporous layer (PSL2) having a porous structure. The first subporous layer (PSL1) may be disposed on a source electrode (SE), a drain electrode (DE), and a semiconductor layer (SCL). The second subporous layer (PSL2) may be disposed on the first subporous layer (PSL1). A plurality of holes (HSa) may be formed in the porous layer (PLa) by penetrating the first subporous layer (PSL1) and the second subporous layer (PSL2). The plurality of holes (HSa) may include a plurality of first sub-holes (HSa1) formed by penetrating the second subporous layer (PSL2) and a plurality of second sub-holes (HSa2) formed by penetrating the first subporous layer (PSL1). The first and second sub-holes (HSa1, HSa2) can be aligned with each other.

[0061] Referring to FIG. 2b, a plurality of holes (HSa) may be arranged spaced apart from each other on a plane. For example, as illustrated, they may be arranged spaced apart from each other on a plane at a constant interval. However, they are not limited thereto, and the plurality of holes (HSa) may be arranged spaced apart at different intervals. According to one embodiment of the present invention, the plurality of holes (HSa) on a plane may have the same size. For example, the size of the plurality of holes (HSa) may be 10 nm or more and 1000 nm or less. However, they are not limited thereto, and the plurality of holes (HSa) may have different sizes on a plane. According to one embodiment of the present invention, the plurality of holes (HSa) may be formed by penetrating a porous layer (PLa). However, they are not limited thereto, and the plurality of holes (HSa) may be provided in a recessed form penetrating a first subporous layer (PSL1) and extending from the upper surface of a second subporous layer (PSL2).

[0062] According to one embodiment of the present invention, the first subporous layer (PSL1) may be an organic layer containing an organic material. The first subporous layer (PSL1) may have a thickness of about 20 nm.

[0063] According to one embodiment of the present invention, the second subporous layer (PSL2) may be an inorganic layer comprising an inorganic material. The second subporous layer (PSL2) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The second subporous layer (PSL2) may be a single layer of hafnium oxide, but is not limited thereto. The second subporous layer (PSL2) may have a single-layer or multi-layer structure and may include at least one of the materials described above, but is not limited thereto.

[0064] FIG. 3a is a cross-sectional view of a phototransistor according to one embodiment of the present invention, and FIG. 3b is a perspective view of the phototransistor shown in FIG. 3a.

[0065] FIGS. 3a and 3b illustrate a phototransistor (PT) that includes an additional protective layer (PTL) compared to FIGS. 2a and 2b. Since the configuration excluding the protective layer (PTL) is identical to the configuration shown in FIGS. 2a and 2b, a redundant description is omitted.

[0066] Referring to FIGS. 3a and 3b, a protective layer (PTL) may be formed on a porous layer (PLa). A semiconductor layer (SCL) may be exposed to the outside through a plurality of holes (HSa) formed in the porous layer (PLa) to penetrate the first subporous layer (PSL1) and the second subporous layer (PSL2). The protective layer (PTL) covers the entire porous layer (PLa) to protect the semiconductor layer (SCL) from foreign substances such as moisture, oxygen, and dust particles.

[0067] The protective layer (PTL) may include an inorganic insulating material or an organic insulating material. The protective layer (PTL) may have a single-layer structure. However, it is not limited thereto, and the protective layer (PTL) may have a multi-layer structure. In the case where the protective layer (PTL) has a multi-layer structure, the protective layer (PTL) may have a structure in which the inorganic insulating material and the organic insulating material are stacked. The inorganic insulating material is silicon oxide (SiO₂). x ) or silicon nitride (SiN x It may include ) etc., and organic insulating materials may include benzocyclobutene or photoacrylic, but inorganic insulating materials and organic insulating materials are not particularly limited thereto.

[0068] FIG. 4a is a graph showing the photoresponse to red light of a phototransistor (hereinafter, comparison phototransistor) that does not include a porous layer, and FIG. 4b is a graph showing the photoresponse to red light of a phototransistor (PT) that includes the porous layer (PLa) shown in FIG. 2a. In FIG. 4a and FIG. 4b, the x-axis represents the gate voltage applied to the gate electrode (PTG) (see FIG. 2a) of the comparison phototransistor and the phototransistor (PT), and the y-axis represents the drain current of the comparison phototransistor and the phototransistor (PT). Referring to FIG. 4a, the first graph (GL1) shows the photoresponse of the comparison phototransistor in a dark state where red light is not provided, and the second graph (GL2) is 1 / It shows the photoresponse of a comparative phototransistor when red light is provided at an intensity of . The third graph (GL3) is 5 / It shows the photoresponse of a comparative phototransistor when red light is provided with an intensity of , and the fourth graph (GL4) is 10 / It shows the photoresponse of a comparative phototransistor when red light is provided with an intensity of . Referring to FIG. 4b, the fifth graph (GL5) shows the photoresponse of the phototransistor (PT) in a dark state where red light is not provided, and the sixth graph (GL6) is 1 / It shows the photoresponse of the phototransistor (PT) when red light is provided with an intensity of . Graph 7 (GL7) is 5 / It shows the photoresponse of the phototransistor (PT) when red light is provided with an intensity of , and the 8th graph (GL8) is 10 / It shows the photoresponse of a phototransistor (PT) when red light is provided at an intensity of .

[0069] According to graphs 1 through 4 (GL1, GL2, GL3, GL4), it was found that the comparison phototransistor has the same threshold voltage as the threshold voltage in the dark state even as the intensity of red light increases. In other words, it was found that the threshold voltage of the comparison phototransistor does not change even as the intensity of red light increases. However, according to graphs 5 through 8 (GL5, GL6, GL7, GL8), when the phototransistor (PT) includes a porous layer (PLa), it was found that as the intensity of red light increases, the threshold voltage of the phototransistor (PT) shifts in the negative direction compared to the threshold voltage of the phototransistor (PT) in the dark state. It was also found that the off-current of the phototransistor (PT) increases as the intensity of red light increases.

[0070] Phototransistors using oxide semiconductors possess higher stability and mobility compared to phototransistors containing amorphous silicon. While phototransistors using oxide semiconductors possess high stability and mobility, their characteristics as light-sensing devices are limited because they cannot absorb light in the visible and infrared regions due to their wide bandgap. The phototransistor (PT) according to the present invention can improve the light absorption rate in the visible and infrared regions by including a porous layer (PL) having a plurality of holes (HS) defined on a semiconductor layer (SCL) containing an oxide semiconductor. The phototransistor (PT) can improve the light absorption rate by increasing the amount of light incident on the semiconductor layer (SCL) through the plurality of holes (HS) by capturing external light or scattering it internally. The light absorption rate can be controlled by the size and number of the plurality of holes (HS).

[0071] FIG. 5a is a graph showing the photoresponse of a comparative phototransistor to green light, and FIG. 5b is a graph showing the photoresponse of a phototransistor (PT) containing the porous layer (PLa) shown in FIG. 2a to green light.

[0072] In FIGS. 5A and 5B, the x-axis represents the gate voltage applied to the gate electrode (PTG) of the phototransistor (see FIG. 2A), and the y-axis represents the drain current of the comparison phototransistor and the phototransistor (PT). Referring to FIG. 5A, the first graph (GL1a) shows the photoresponse of the comparison phototransistor in a dark state where no green light is provided, and the second graph (GL2a) is 1 / It shows the photoresponse of a comparative phototransistor when green light is provided with an intensity of . The third graph (GL3a) is 5 / It shows the photoresponse of a comparative phototransistor when green light is provided with an intensity of , and the fourth graph (GL4a) is 10 / It shows the photoresponse of a comparative phototransistor when green light is provided with an intensity of . Referring to FIG. 5b, the fifth graph (GL5a) shows the photoresponse of the phototransistor (PT) in a dark state where green light is not provided, and the sixth graph (GL6a) is 1 / It shows the photoresponse of the phototransistor (PT) when green light is provided with an intensity of . Graph 7 (GL7a) is 5 / It shows the photoresponse of the phototransistor (PT) when green light is provided with an intensity of , and graph 8 (GL8a) is 10 / It shows the photoresponse of a phototransistor (PT) when green light is provided at an intensity of .

[0073] According to graphs 1 through 4 (GL1a, GL2a, GL3a, GL4a), it can be confirmed that the comparative phototransistor shows almost no photoreaction to light irradiation even when the intensity of green light increases. In other words, it was found that the threshold voltage and off-current of the comparative phototransistor hardly change even when the intensity of green light increases. However, according to graphs 5 through 8 (GL5a, GL6a, GL7a, GL8a), when the phototransistor (PT) includes a porous layer (PLa), it was found that as the intensity of green light increases, the threshold voltage of the phototransistor (PT) shifts in the negative direction compared to the threshold voltage of the phototransistor (PT) in the dark state. It was also found that as the intensity of green light increases, the off-current of the phototransistor (PT) also increases.

[0074] FIG. 6 is a graph showing the photoresponse of a phototransistor (PT) to green light according to an embodiment of the present invention. In particular, the graphs shown in FIG. 6 represent the photoresponse of a phototransistor (PT) having a protective layer (PTL) formed on a porous layer (PLa) in which a plurality of holes (HSa) are defined, as shown in FIG. 3a and 3b. In FIG. 6, the x-axis represents the gate voltage applied to the gate electrode (PTG) of the phototransistor (PT) (see FIG. 2a), and the y-axis represents the drain current of the phototransistor (PT). Referring to FIG. 6, the first graph (GL1b) represents the photoresponse of the phototransistor (PT) in a dark state where green light is not provided, and the second graph (GL2b) is 1 / It shows the photoresponse of the phototransistor (PT) when green light is provided with an intensity of . The third graph (GL3b) is 5 / It shows the photoresponse of the phototransistor (PT) when green light is provided with an intensity of , and the fourth graph (GL4b) is 10 / It shows the photoresponse of a phototransistor (PT) when green light is provided at an intensity of .

[0075] When compared to the threshold voltage in the dark state (hereinafter referred to as the dark threshold voltage (approximately 0V)), the intensity of the green light is 1 / When the first green light is applied (hereinafter referred to as the first green light), the threshold voltage of the phototransistor (PT) was found to shift in the negative direction by approximately 25V. When the first green light is supplied, the magnitude of the drain current of the first green light measured at the dark threshold voltage (approximately 0V) was approximately compared to the magnitude of the drain current in the dark state measured at the dark threshold voltage. It can be confirmed that it has increased by a factor of 5. The intensity of the green light is 5 / When the second green light is applied (hereinafter referred to as the second green light), the threshold voltage of the phototransistor (PT) was found to shift in the negative direction by approximately 28 V. When the second green light is supplied, the magnitude of the drain current of the second green light measured at the dark threshold voltage (approximately 0 V) ​​was approximately compared to the magnitude of the drain current in the dark state measured at the dark threshold voltage. It can be confirmed that it has increased by a factor of 10. The intensity of the green light is 10 / When (hereinafter, the third green light), the threshold voltage was found to shift in the negative direction by about 30V.

[0076] When the third green light is supplied, the magnitude of the drain current of the third green light measured at the dark threshold voltage (approximately 0V) is approximately compared to the magnitude of the drain current in the dark state measured at the dark threshold voltage. You can confirm that it has doubled.

[0077] According to one embodiment of the present invention, the porous layer (PLa) may include a plurality of holes (HSa) to capture external light provided to the phototransistor (PT) or increase the amount of external light provided to the semiconductor layer (SCL) through internal scattering. Additionally, the light absorption rate of the phototransistor (PT) may be controlled by adjusting the size and number of the plurality of holes (HSa) provided in the porous layer (PLa). As the porous layer (PLa) includes a plurality of holes (HSa) penetrating the first subporous layer (PSL1) and the second subporous layer (PSL2), the semiconductor layer (SCL) may be exposed to the outside. The protective layer (PTL) covers the entire porous layer (PLa) to protect the semiconductor layer (SCL) from foreign substances such as moisture, oxygen, and dust particles. Accordingly, compared to a structure where the semiconductor layer (SCL) is directly exposed to the outside, the absorption rate of external light by the semiconductor layer (SCL) may decrease because the porous layer (PLa) is hindered from absorbing external light by the protective layer (PTL).

[0078] As explained above, the graph shown in Fig. 6, which shows the photoresponse to green light of a phototransistor (PT) with an added protective layer (PTL), shows a weaker light absorption characteristic than the graph shown in Fig. 5b, which shows the photoresponse to green light of a phototransistor (PT) including a porous layer (PLa). However, when compared to the graph shown in Fig. 5a, which shows the photoresponse to green light of a comparative phototransistor, it can be confirmed that a significant light absorption characteristic can still be secured.

[0079] FIG. 7 is a graph illustrating the continuous photocurrent phenomenon when green light is irradiated onto a phototransistor (PT) according to one embodiment of the present invention.

[0080] Specifically, the graph in FIG. 7 shows a phototransistor (PT) (see FIG. 2a) under the condition that a voltage of -4V is applied to the gate electrode (PTG) (see FIG. 2a) and a voltage of 10.1V is applied to the drain electrode (DE) (see FIG. 2a) for 2500 seconds, with a wavelength of 565nm, a frequency of 0.1Hz, and an intensity of 10 / This is a graph showing the magnitude of the drain current over time when green light is applied.

[0081] In describing the present invention, a high persistent photocurrent (PPC) means that the difference between the current value when light is applied and the current value when light is not applied is small, and a low persistent photocurrent means that the difference between the current value when light is applied and the current value when light is not applied is large.

[0082] Referring to Fig. 7, it can be seen that the waveform of the drain current has a period of 10 seconds because the frequency is 0.1 Hz. As shown in the graph, the minimum drain current (minimum drain current when no light is applied) is approximately 0.5 nA, and the maximum drain current (maximum drain current when light is applied) is approximately 6.3 nA. Accordingly, when green light is applied, the time taken for the drain current to increase from the minimum drain current to approximately 90% of the maximum drain current is approximately 1.92 seconds, and when the application of green light is stopped, the time taken for the drain current to decrease from the maximum drain current to approximately 10% of the maximum drain current is approximately 2.01 seconds. Such a period can be maintained for approximately 2500 seconds, and during this period, the values ​​of the maximum drain current and the minimum drain current can be maintained at a constant level.

[0083] Generally, oxide phototransistors can exhibit a high sustained photocurrent. When the above process is repeated, oxide phototransistors exhibiting a high sustained photocurrent may have inconsistent maximum and minimum drain current values ​​due to residual holes. However, the phototransistor (PT) of the present invention having porous layers (PL, PLa) has superior durability compared to a conventional oxide phototransistor that does not include porous layers (PL, PLa) (the maximum and minimum drain current values ​​can be maintained constant). This improves the operational reliability of the phototransistor (PT).

[0084] FIG. 8 is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 9 is an exploded perspective view of an electronic device according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0085] An electronic device (ED) may be a device that is activated by an electrical signal and displays an image. For example, the electronic device (ED) may be included in large devices such as televisions and outdoor billboards, as well as in small and medium-sized devices such as monitors, mobile phones, tablet computers, navigation systems, and game consoles. Meanwhile, the embodiments of the electronic device (ED) are exemplary and are not limited to any one of them unless they depart from the concept of the present invention. In this embodiment, a mobile phone is illustrated as an example of an electronic device (ED).

[0086] Referring to FIG. 8, the electronic device (ED) may have a rectangular shape having long sides extended in a first direction (DR1) in a plane and short sides extended in a second direction (DR2) intersecting the first direction (DR1). However, it is not limited thereto, and the electronic device (ED) may have various shapes such as a circle or a polygon in a plane.

[0087] An electronic device (ED) of one embodiment may be flexible. “Flexible” means a characteristic of being able to bend, and may include everything from a structure that is fully foldable to a structure that can be bent to the level of several nanometers. For example, a flexible electronic device (ED) may include a curved device or a foldable device. However, it is not limited thereto, and the electronic device (ED) may be rigid.

[0088] An electronic device (ED) can display an image (IM) through a display area (ED-AA). The display area (ED-AA) of the electronic device (ED) may be parallel to a plane defined by a first direction (DR1) and a second direction (DR2). The display area (ED-AA) may display an image (IM) in a third direction (DR3) that intersects substantially perpendicularly with the plane defined by the first direction (DR1) and the second direction (DR2). Meanwhile, although a planar display area (ED-AA) has been illustrated as an example, in one embodiment, the display area (ED-AA) may have a curved shape that is bent from at least one side of the plane.

[0089] Meanwhile, the front (or top) and back (or bottom) surfaces of each component constituting the electronic device (ED) may be opposed to each other in a third direction (DR3), and the normal direction of each of the front and back surfaces may be substantially parallel to the third direction (DR3). The distance between the front and back surfaces defined along the third direction (DR3) may correspond to the thickness of the component (or unit).

[0090] In this specification, “in a plane” may be defined as a state viewed from a third direction (DR3). In this specification, “in a cross-section” may be defined as a state viewed from a first direction (DR1) or a second direction (DR2). Meanwhile, the directions indicated by the first to third directions (DR1, DR3, DR3) are relative concepts and can be converted to other directions.

[0091] The image (IM) provided by the electronic device (ED) of one embodiment may include a still image as well as a dynamic image. In FIG. 8, a clock window and icons are shown as examples of the image (IM). The surface on which the image (IM) is displayed may correspond to the front surface of the electronic device (ED) and may correspond to the front surface of the window (WM).

[0092] An electronic device (ED) according to one embodiment can detect an external input applied from the outside. The external input may include various forms of input provided from outside the electronic device (ED). For example, the external input may include force, pressure, temperature, light, etc. The external input may include not only inputs that come into contact with the electronic device (ED) (e.g., contact by a user's hand or pen), but also inputs applied in close proximity to the electronic device (ED) or adjacent at a predetermined distance (e.g., hovering).

[0093] An electronic device (ED) of one embodiment can detect user input through a display area (ED-AA) defined on the front and respond to the detected input signal. However, the area of ​​the electronic device (ED) that detects external input is not limited to the front of the electronic device (ED), and depending on the design of the provided electronic device (ED), user input applied to the side or back of the electronic device (ED) may also be detected, and is not limited to any one embodiment.

[0094] An electronic device (ED) of one embodiment can detect biometric information, such as a user's fingerprint (FG), which is authorized from the outside. A fingerprint recognition area may be provided in a display area (ED-AA) of the electronic device (ED). The fingerprint recognition area may be provided in the entire area of ​​the display area (ED-AA) or in a part of the display area (ED-AA).

[0095] Referring to FIG. 9, the electronic device (ED) may include a window (WM), a display module (DM), and a housing (HAU). The window (WM) may be combined with the housing (HAU) to form the exterior of the electronic device (ED) and may provide an internal space capable of accommodating the components of the electronic device (ED).

[0096] A window (WM) may be placed on a display module (DM). The window (WM) may have a shape corresponding to the shape of the display module (DM). The window (WM) may cover the entire outer surface of the display module (DM) and protect the display module (DM) from external impacts and scratches.

[0097] The window (WM) may include an optically transparent insulating material. For example, the window (WM) may include a glass substrate or a polymer substrate, and in one embodiment, the window (WM) may include a reinforced glass substrate. The window (WM) may have a single-layer or multi-layer structure. The window (WM) may further include functional layers, such as an anti-fingerprint layer, a phase control layer, and a hard coating layer, disposed on the optically transparent substrate.

[0098] The front surface of the window (WM) may correspond to the display surface of the electronic device (ED). The front surface of the window (WM) may include a transparent area (TA) and a bezel area (BZA).

[0099] The transparent area (TA) of the window (WM) may be an optically transparent area. The window (WM) can transmit an image (IM) provided by the display module (DM) through the transparent area (TA), and the user can see the image (IM). The transparent area (TA) of the window (WM) may correspond to the display area (ED-AA) of the electronic device (ED).

[0100] The bezel area (BZA) of the window (WM) may be provided as an area printed with a material containing a predetermined color. The bezel area (BZA) of the window (WM) may prevent a component of the display module (DM) placed overlapping the bezel area (BZA) from being visible to the outside.

[0101] The bezel region (BZA) may be adjacent to the transparent region (TA). The shape of the transparent region (TA) may substantially be defined by the bezel region (BZA). For example, the bezel region (BZA) may be positioned outside the transparent region (TA) to surround the transparent region (TA). However, this is illustrated as an example, and the bezel region (BZA) may be adjacent to only one side of the transparent region (TA) or may be omitted. Additionally, the bezel region (BZA) may be positioned on a side rather than the front of the electronic device (ED).

[0102] The display module (DM) can be placed between the window (WM) and the housing (HAU). The display module (DM) can display images according to electrical signals and transmit and receive information regarding external inputs. The display module (DM) can be divided into an active area (AA) and a peripheral area (NAA).

[0103] The active area (AA) may be an area that is activated according to an electrical signal. The active area (AA) may be a part that displays an image or detects an external input. According to one embodiment, the active area (AA) of the display module (DM) may correspond to the aforementioned transmission area (TA). Meanwhile, in this specification, “a region / part corresponds to a region / part” means “overlaps with one another” and is not limited to having the same area and / or the same shape.

[0104] The peripheral area (NAA) may be adjacent to the active area (AA). For example, the peripheral area (NAA) may surround the active area (AA). However, it is not limited to this, and the peripheral area (NAA) may be defined in various shapes. The peripheral area (NAA) may be an area where driving circuits or driving wiring for driving the active area (AA), various signal lines providing electrical signals, and pads are placed. The peripheral area (NAA) of the display module (DM) may correspond to the bezel area (BZA) described above. Components of the display module (DM) placed in the peripheral area (NAA) may be prevented from being visible to the outside by the bezel area (BZA).

[0105] The housing (HAU) is positioned below the display module (DM) to accommodate the display module (DM). The housing (HAU) absorbs shocks applied from the outside and protects the display module (DM) by preventing foreign substances / moisture, etc., from penetrating into the display module (DM). In one embodiment, the housing (HAU) may be provided in a form in which a plurality of storage members are combined.

[0106] Meanwhile, the electronic device (ED) may further include an electronic module comprising various functional modules for operating a display module (DM), a power supply module for supplying power required for the electronic device (ED), and a bracket that is combined with the display module (DM) and / or housing (HAU) to divide the internal space of the electronic device (ED).

[0107] Referring to FIG. 10, the display module (DM) may include a display panel (DP), an input sensing layer (ISL), and a reflection adjustment layer (RCL). The display panel (DP) may include a base layer (BL), a circuit layer (DP_CL), a display element layer (DP_ED), and an encapsulation layer (TFE).

[0108] A display panel (DP) according to one embodiment may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel (DP) may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of an inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0109] The base layer (BL) may provide a base surface on which the circuit layer (DP_CL) is placed. The base layer (BL) may include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite material substrate.

[0110] A circuit layer (DP_CL) may be disposed on a base layer (BL). The circuit layer (DP_CL) may include at least one insulating layer, circuit elements, signal lines, and signal pads. The circuit layer (DP_CL) may include a pixel driving circuit included in each pixel for displaying an image and a sensor driving circuit included in each sensor for recognizing external information. As an example, the sensor may be an optical sensor that recognizes biometric information in an optical manner.

[0111] The display element layer (DP_ED) may be disposed on the circuit layer (DP_CL). The display element layer (DP_ED) may include light-emitting elements disposed in overlap with the active region (AA). The light-emitting elements of the display element layer (DP_ED) may be connected to circuit elements of the circuit layer (DP_CL) to form pixels. Each pixel may output light through the active region (AA) in response to a driving signal.

[0112] The encapsulation layer (TFE) can be disposed on the display element layer (DP_ED) to seal the display element layer (DP_ED). The encapsulation layer (TFE) may include a plurality of thin films. The thin films of the encapsulation layer (TFE) may be disposed to improve the optical efficiency of the devices in the display element layer (DP_ED) or to protect the devices.

[0113] The input sensing layer (ISL) may be placed on the display panel (DP). The input sensing layer (ISL) may be placed directly on the display panel (DP). In this specification, the term “directly placed” may be used to describe a process in which a separate adhesive layer or adhesive member is not placed and the layer is formed by a continuous process. For example, the expression “the input sensing layer (ISL) is placed directly on the display panel (DP)” may indicate that, after the display panel (DP) is formed, the input sensing layer (ISL) is formed on the base surface provided by the display panel (DP) through a continuous process without a separate adhesive layer.

[0114] Meanwhile, not limited to this, the input sensing layer (ISL) can be combined with the display panel (DP) through an adhesive layer. The input sensing layer (ISL) can be manufactured through a separate process from the display panel (DP) and then fixed to the upper surface of the display panel (DP) by an adhesive layer.

[0115] The input sensing layer (ISL) can detect an external input applied from the outside and obtain coordinate information of the external input. The input sensing layer (ISL) can be driven in various ways, such as capacitive, resistive, infrared, acoustic, or pressure methods, and is not limited to any one of them. For example, the input sensing layer (ISL) can be driven in a capacitive manner and may include a plurality of sensing electrodes for detecting external input. The input sensing layer (ISL) can provide an input signal corresponding to the external input to a display panel (DP), and the display panel (DP) can generate an image corresponding to the input signal.

[0116] A reflection adjustment layer (RCL) can be placed on an input sensing layer (ISL). The reflection adjustment layer (RCL) can be placed directly on the input sensing layer (ISL). That is, the reflection adjustment layer (RCL) can be formed by applying (or printing) a composition of the reflection adjustment layer (RCL) onto a base surface provided by the input sensing layer (ISL). The reflection adjustment layer (RCL) can reduce the reflectivity caused by external light incident from the outside.

[0117] The electronic device (ED) may further include an adhesive layer (AL) disposed between a display module (DM) and a window (WM). The display module (DM) and the window (WM) may be joined to each other with the adhesive layer (AL) in between. The adhesive layer (AL) may include a transparent adhesive such as an optically clear adhesive film (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive film (PSA). However, the type of adhesive included in the adhesive layer (AL) is not limited to these.

[0118] FIG. 11a is a circuit diagram showing pixels and sensors provided in a display panel according to one embodiment of the present invention, and FIG. 11b is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0119] Referring to FIGS. 11a and 11b, a pixel (Px) includes a light-emitting element (ED) and a pixel driving circuit (PD). The light-emitting element (ED) may be a light-emitting diode. In one example of the present invention, the light-emitting element (ED) may be an organic light-emitting diode comprising an organic light-emitting layer. The pixel driving circuit (PD) is connected to the light-emitting element (ED) and can control a driving current (Ied) supplied to the light-emitting element (ED). In one example of the present invention, the pixel driving circuit (PD) is connected to a first driving voltage line (VL1). The first driving voltage line (VL1) can transmit a first driving voltage (ELVDD) to the pixel driving circuit (PD). Additionally, the pixel driving circuit (PD) may be further connected to first and second initialization voltage lines (VL3, VL4). The first and second initialization voltage lines (VL3, VL4) can each transmit a first initialization voltage (VINT1) and a second initialization voltage (VINT2) to a pixel driving circuit (PD). The anode electrode of the light-emitting element (ED) is connected to the pixel driving circuit (PD), and the cathode electrode can be connected to a second driving voltage line (VL2) that transmits a second driving voltage (ELVSS). The second driving voltage (ELVSS) may have a lower voltage level than the first driving voltage (ELVDD).

[0120] The sensor (Fx) includes a phototransistor (PTa) that performs a light reception function and a sensor driving circuit (SD) connected to the phototransistor (PTa). The phototransistor (PTa) may be an oxide phototransistor containing an oxide as a photoelectric conversion layer. The gate electrode (PTGa) and drain electrode (DEa) of the phototransistor (PTa) are connected to a sensing node connected to the sensor driving circuit (SD), and the source electrode (SEa) of the phototransistor (PTa) may be connected to a second driving voltage line (VL2) that transmits a second driving voltage (ELVSS). Although not illustrated, the configuration of the sensor driving circuit (SD) may be modified.

[0121] Referring to FIG. 11b, the display panel (DP) may include a base layer (BL), a circuit layer (DP_CL), a display element layer (DP_ED), and an encapsulation layer (TFE).

[0122] The base layer (BL) may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylate resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0123] At least one inorganic layer is formed on the upper surface of the base layer (BL). The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multiple inorganic layers may constitute a barrier layer (BRL) and / or a buffer layer (BFL) described later. The barrier layer (BRL) and the buffer layer (BFL) may be optionally disposed.

[0124] The circuit layer (DP_CL) may include a barrier layer (BRL) and / or a buffer layer (BFL). The barrier layer (BRL) prevents foreign substances from entering from the outside. The barrier layer (BRL) may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in multiple numbers, and the silicon oxide layers and silicon nitride layers may be stacked alternately.

[0125] A buffer layer (BFL) may be disposed on a barrier layer (BRL). The buffer layer (BFL) enhances the bonding strength between the base layer (BL) and the semiconductor pattern and / or conductive pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0126] A semiconductor pattern is disposed on a buffer layer (BFL). Hereinafter, the semiconductor pattern directly disposed on the buffer layer (BFL) is defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polysilicon. However, it is not limited thereto, and the first semiconductor pattern may include amorphous silicon.

[0127] FIG. 11b illustrates only a portion of the first semiconductor pattern, and the first semiconductor pattern may be further disposed in other areas of the pixel (Px, see FIG. 11a). The electrical properties of the first semiconductor pattern differ depending on whether it is doped. The first semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant, and an N-type transistor includes a doped region doped with an N-type dopant.

[0128] The doped region has greater conductivity than the non-doped region and substantially functions as an electrode or signal line. The non-doped region substantially corresponds to the active (or channel) of the transistor. In other words, a part of the first semiconductor pattern may be the active of the transistor, another part may be the source or drain of the transistor, and yet another part may be a connected signal line (or connected electrode).

[0129] As shown in FIG. 11b, the first electrode (S1), channel portion (A1), and second electrode (D1) of the first transistor (T1) are formed from the first semiconductor pattern. The first electrode (S1) and the second electrode (D1) of the first transistor (T1) extend in opposite directions from the channel portion (A1).

[0130] A first insulating layer (10) is disposed on a buffer layer (BFL). The first insulating layer (10) covers a first semiconductor pattern. The first insulating layer (10) may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer (10) may be a single-layer silicon oxide layer. The insulating layer of the circuit layer (DP_CL) described below, as well as the first insulating layer (10), may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above.

[0131] A third electrode (G1) of the first transistor (T1) is placed on the first insulating layer (10). The third electrode (G1) may be part of a metal pattern. The third electrode (G1) of the first transistor (T1) overlaps with the channel portion (A1) of the first transistor (T1). In the process of doping the first semiconductor pattern, the third electrode (G1) of the first transistor (T1) may serve as a mask.

[0132] A second insulating layer (20) covering a third electrode (G1) is disposed on the first insulating layer (10). The second insulating layer (20) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. In this embodiment, the second insulating layer (20) may be a single layer of silicon oxide.

[0133] An upper electrode (UE) may be disposed on the second insulating layer (20). The upper electrode (UE) may overlap with the third electrode (G1). The upper electrode (UE) may be a part of a metal pattern or a part of a doped semiconductor pattern. A part of the third electrode (G1) and the upper electrode (UE) overlapping therewith may form a capacitor. In one embodiment of the present invention, the upper electrode (UE) may be omitted.

[0134] A gate electrode (PTGa) of a phototransistor (PTa) may be disposed on the second insulating layer (20). The gate electrode (PTGa) may be part of a metal pattern. According to one embodiment of the present invention, the gate electrode (PTG) may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto. The gate electrode (PTGa) may be formed through the same process as the top electrode (UE).

[0135] In one embodiment of the present invention, the second insulating layer (20) may be replaced with an insulating pattern. An upper electrode (UE) is disposed on the insulating pattern. The upper electrode (UE) and the gate electrode (PTGa) may serve as a mask for forming the insulating pattern from the second insulating layer (20).

[0136] A third insulating layer (30) covering an upper electrode (UE) and a gate electrode (PTGa) is disposed on the second insulating layer (20). In this embodiment, the third insulating layer (30) may be a single layer of silicon oxide. A semiconductor pattern is disposed on the third insulating layer (30). Hereinafter, the semiconductor pattern directly disposed on the third insulating layer (30) is defined as the second semiconductor pattern. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. Oxide semiconductors may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0137] FIG. 11b illustrates only a portion of the second semiconductor pattern, and a third semiconductor pattern may be further disposed in other areas of the pixel, although not illustrated. The third semiconductor pattern may include multiple regions distinguished by whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, reduced region) has greater conductivity than the region where it is not reduced (hereinafter, non-reduced region). The reduced region substantially serves as an electrode or a signal line. The non-reduced region substantially corresponds to the semiconductor layer of the transistor. In other words, a portion of the second semiconductor pattern may be the semiconductor layer of the phototransistor (PTa), and another portion may be the source electrode (SEa) or drain electrode (DEa) of the phototransistor (PTa).

[0138] The circuit layer (DP_CL) may further include elements included in the sensor driving circuit (SD, see FIG. 11a). For convenience of explanation, the sensor driving circuit (SD) is omitted in FIG. 11b.

[0139] The source electrode (SEa), semiconductor layer (SCLa), and drain electrode (DEa) of the phototransistor (PTa) are formed from a second semiconductor pattern. The semiconductor layer (SCLa) may be formed of amorphous silicon or an oxide semiconductor. According to one embodiment of the present invention, the semiconductor layer (SCLa) may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. Oxide semiconductors may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0140] The source electrode (SEa) and the drain electrode (DEa) may be formed spaced apart from each other with the semiconductor layer (SCLa) in between. According to one embodiment of the present invention, the source electrode (SEa) may be positioned to contact one side of the semiconductor layer (SCLa). On the other hand, the drain electrode (DEa) may be positioned to contact the other side of the semiconductor layer (SCLa). Accordingly, the source electrode (SEa) and the drain electrode (DEa) may be formed extending in opposite directions from the semiconductor layer (SCLa). The source electrode (SEa) and the drain electrode (DEa) may be made of a metallic material, for example, copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), etc., but are not limited thereto.

[0141] The fourth insulating layer (40) is arranged to cover the source electrode (SEa), semiconductor layer (SCLa), and drain electrode (DEa) of the phototransistor (PTa). According to one embodiment of the present invention, the fourth insulating layer (40) may have a porous structure including a plurality of holes (HSb) on the source electrode (SEa), semiconductor layer (SCLa), and drain electrode (DEa). The fourth insulating layer (40) may be an organic layer containing an organic material. However, it is not limited thereto, and the fourth insulating layer (40) may be an inorganic layer containing an inorganic material or may have a multilayer structure in which an organic layer and an inorganic layer are stacked. In this way, the fourth insulating layer (40) may correspond to the porous layer (PL, see FIG. 1) shown in FIG. 1a.

[0142] Referring to FIG. 11b, a plurality of holes (HSb) may be arranged spaced apart from each other on a plane. For example, they may be arranged spaced apart from each other at regular intervals on a plane. However, they are not limited thereto, and the plurality of holes (HSb) may be arranged spaced apart at different intervals. According to one embodiment of the present invention, the plurality of holes (HSb) on a plane may have the same size. For example, the size of the plurality of holes (HSb) may be 10 nm or more and 1000 nm or less. However, they are not limited thereto, and the plurality of holes (HSb) may have different sizes on a plane. According to one embodiment of the present invention, the plurality of holes (HSb) may be formed by penetrating the fourth insulating layer (40). However, they are not limited thereto, and the plurality of holes (HSb) may be provided in a recessed form from the upper surface of the fourth insulating layer (40).

[0143] According to one embodiment of the present invention, the fourth insulating layer (40) includes a plurality of holes (HSb) so that external light provided to the phototransistor (PTa) can be captured or the amount of external light provided to the semiconductor layer (SCLa) can be increased through internal scattering. In addition, the light absorption rate of the phototransistor (PTa) can be controlled by adjusting the size and number of the plurality of holes (HSb) provided in the fourth insulating layer (40).

[0144] A fifth insulating layer (50) is disposed on the fourth insulating layer (40). In this embodiment, the fifth insulating layer (50) may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer (50) may include a plurality of silicon oxide layers and silicon nitride layers that are alternately stacked. The fifth insulating layer (50) is a structure that can be omitted.

[0145] At least one additional insulating layer is disposed on the fifth insulating layer (50). As in the present embodiment, a sixth insulating layer (60) and a seventh insulating layer (70) may be disposed on the fifth insulating layer (50). The sixth insulating layer (60) and the seventh insulating layer (70) may be organic layers and may have a single-layer or multi-layer structure. The sixth insulating layer (60) and the seventh insulating layer (70) may be single-layer polyimide resin layers. Not limited thereto, the sixth insulating layer (60) and the seventh insulating layer (70) may include at least one of acrylic resin, methacrylate resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0146] A first connecting electrode (CNE10) may be disposed on the fifth insulating layer (50). The first connecting electrode (CNE10) is connected to a connecting signal line (CSL) through a first contact hole (CH1) penetrating the first to fifth insulating layers (10 to 50), and a second connecting electrode (CNE20) may be connected to the first connecting electrode (CNE10) through a second contact hole (CH2) penetrating the sixth insulating layer (60). In one embodiment of the present invention, at least one of the fifth insulating layer (50) to the seventh insulating layer (70) may be omitted, and one of the first and second connecting electrodes (CNE10, CNE20) may also be omitted.

[0147] A third connecting electrode (CNE11) may be further disposed on the fifth insulating layer (50). The third connecting electrode (CNE11) is connected to the third electrode (STD1) of the reset transistor (ST1) through a third contact hole (CH3) penetrating the fourth and fifth insulating layers (40, 50), and the fourth connecting electrode (CNE21) may be connected to the third connecting electrode (CNE11) through a fourth contact hole (CH4) penetrating the sixth insulating layer (60).

[0148] The display element layer (DP_ED) is disposed on the circuit layer (DP_CL). The display element layer (DP_ED) may include an anode electrode (E_AE) of a light-emitting element (ED, see FIG. 11a). As shown in FIG. 11b, the anode electrode (E_AE) may be connected to a second connecting electrode (CNE20) through a fifth contact hole (CH5) penetrating the seventh insulating layer (70). The sensing anode electrode (O_AE) may be connected to a fourth connecting electrode (CNE21) through a sixth contact hole (CH6) penetrating the seventh insulating layer (70).

[0149] The display element layer (DP_ED) further includes a pixel definition layer (PDL) disposed on the circuit layer (DP_CL). The pixel definition layer (PDL) may include a light-emitting opening (OP1) defined corresponding to a light-emitting element (ED). At least a portion of the anode electrode (E_AE) of the light-emitting element (ED) is exposed. The light-emitting opening (OP1) of the pixel definition layer (PDL) may define a light-emitting region (PXA). For example, pixels (PX, see FIG. 11a) may be arranged in a certain order on a plane of a display panel (DP, see FIG. 10). An area where multiple pixels (PX) are arranged may be defined as a pixel region, and a pixel region may include a light-emitting region (PXA) and a non-light-emitting region (NPXA) adjacent to the light-emitting region (PXA). The non-light-emitting region (NPXA) may surround the light-emitting region (PXA).

[0150] A common layer (CML) is disposed on the pixel definition layer (PDL). The common layer (CML) includes a common cathode electrode (C_CE), a hole control layer (HCL), and an electronic control layer (ECL). The common cathode electrode (C_CE) is commonly connected to the light-emitting element (ED). The common cathode electrode (C_CE) may face the sensing anode electrode (O_AE) and the anode electrode (E_AE). The hole control layer (HCL) and the electronic control layer (ECL) are disposed between the pixel definition layer (PDL) and the common cathode electrode (C_CE). The hole control layer (HCL) may include a hole transport layer and a hole injection layer, and the electronic control layer (ECL) may include an electron transport layer and an electron injection layer.

[0151] An emitting layer (EL) may be disposed corresponding to an emitting aperture (OP1) defined in a pixel definition layer (PDL). Although a patterned emitting layer (EL) is illustrated as an example in this embodiment, the present invention is not limited thereto. A common emitting layer may be disposed in common across a plurality of pixels (PX). In this case, the common emitting layer may generate white light or blue light. The emitting layer (EL) is disposed on a hole control layer (HCL). An electronic control layer (ECL) is disposed on the emitting layer (EL). A common cathode electrode (C_CE) is disposed on the electronic control layer (ECL). The hole control layer (HCL), the electronic control layer (ECL), and the common cathode electrode (C_CE) are disposed in common across a plurality of pixels (PX).

[0152] FIGS. 12a and 12b are cross-sectional views of a display panel according to an embodiment of the present invention. In describing FIGS. 12a and 12b, descriptions that overlap with FIG. 11b are omitted.

[0153] Referring to FIG. 12a, a plurality of holes (HSc) may be formed by penetrating the fifth insulating layer (50a) and the fourth insulating layer (40). The plurality of holes (HSc) may include a plurality of first sub-holes (HSc1) formed by penetrating the fifth insulating layer (50a) and a plurality of second sub-holes (HSc2) formed by penetrating the fourth insulating layer (40). The first and second sub-holes (HSc1, HSc2) may be aligned with each other. As illustrated, a plurality of holes (HSc) may be formed by penetrating the fifth insulating layer (50a) and the fourth insulating layer (40). However, not limited thereto, the first sub-hole (HSc1) may be formed by penetrating the fifth insulating layer (50a), and the second sub-hole (HSc2) may be provided in a recessed form from the upper surface of the fourth insulating layer (40).

[0154] The fifth insulating layer (50a) may be an inorganic layer made of inorganic material. For example, the fifth insulating layer (50a) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The fifth insulating layer (50a) may be a single layer of hafnium oxide, but is not limited thereto. The fifth insulating layer (50a) may have a single-layer or multi-layer structure and may include at least one of the materials described above, but is not limited thereto. Thus, the fourth insulating layer (40) corresponds to the first subporous layer (PSL1, see FIG. 2a) shown in FIG. 2a, and the fifth insulating layer (50a) may correspond to the second subporous layer (PSL2, see FIG. 2a) shown in FIG. 2a.

[0155] Referring to FIG. 12b, compared to FIG. 11b, the fourth insulating layer (40) may be omitted and a separate porous layer (PLb) may be included. Specifically, a porous layer (PLb) with a plurality of holes (HSd) defined therein may be formed on the source electrode (SEa), the semiconductor layer (SCLa), and the drain electrode (DEa). According to one embodiment of the present invention, the porous layer (PLb) may be an organic layer containing an organic material. However, it is not limited thereto, and the porous layer (PLb) may be an inorganic layer containing an inorganic material or may have a structure in which an organic layer and an inorganic layer are stacked. The porous layer (PLb) may be manufactured through a separate process from the fifth insulating layer (50), and then the fifth insulating layer (50) may be disposed on the porous layer (PLb).

[0156] FIG. 13a is an exploded perspective view of an electronic device according to one embodiment of the present invention. FIG. 13b is a cross-sectional view taken along the cutting line VI-VI' shown in FIG. 13a.

[0157] Referring to FIG. 13a, the electronic device (Eda) may include a window (WM), an anti-reflective layer (RP), a display module (DM), a sensing unit (FSU), and a housing (HAU). The display module (DM) may be placed below the window (WM).

[0158] An anti-reflective layer (RP) may be placed below the window (WM). The anti-reflective layer (RP) reduces the reflectivity of external light incident from the upper side of the window (WM). In one embodiment of the present invention, the anti-reflective layer (RP) may be omitted or may be a component included in the display module (DM).

[0159] The sensing unit (FSU) may be placed below the display module (DM). The sensing unit (FSU) may be a layer that detects the user's biometric information. The sensing unit (FSU) may detect the surface of a touch target. The surface may include surface uniformity or surface curvature shape.

[0160] The sensing unit (FSU) may include a sensing area (400-A) and a non-sensing area (400-N). The sensing area (400-A) may be an area that is activated according to an electrical signal. For example, the sensing area (400-A) may be an area that detects bio-information. A driving circuit or driving wiring for driving the sensing area (400-A) may be disposed in the non-sensing area (400-N).

[0161] In one embodiment of the present invention, the sensing area (400-A) may overlap with the entire active area (AA). In this case, fingerprint recognition may be possible across the entire active area (AA). That is, the user's fingerprint can be recognized across the entire area, rather than in a specific area limited to a portion. However, the present invention is not limited thereto. For example, in another embodiment of the present invention, the sensing unit (FSU) may overlap with a portion of the active area (AA).

[0162] The housing (HAU) can accommodate an anti-reflective layer (RP), a display module (DM), and a sensing unit (FSU). The housing (HAU) can be combined with a window (WM) to form the exterior of the electronic device (Eda).

[0163] Although not shown, a battery module or the like that supplies power necessary for the overall operation of the electronic device (EDa) may be placed between the sensing unit (FSU) and the housing (HAU).

[0164] Referring to FIG. 13b, the sensing unit (FSU) may include a sensing base layer (410), a sensor layer (420), and an optical pattern layer (430).

[0165] The sensing base layer (410) may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material is not particularly limited. For example, the sensing base layer (410) may include two layers of polyimide-based resin layers and a barrier layer disposed between the polyimide-based resin layers. The barrier layer may include amorphous silicon and silicon oxide.

[0166] A sensor layer (420) may be disposed on a sensing base layer (410). The sensor layer (420) may be referred to as a bio-information sensing layer. The sensor layer (420) may include a sensing circuit and insulating layers. The sensing circuit may include at least one transistor or one photodiode. According to one embodiment of the present invention, the sensor layer (420) may include a phototransistor (PTb) having a porous layer (PLb) in which a plurality of holes (HSe) are defined. FIG. 13b shows only the phototransistor (PTb) included in the sensor layer (420).

[0167] A barrier layer (421) is disposed on a sensing base layer (410). The barrier layer (421) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The barrier layer (421) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the barrier layer (421) may be a single-layer silicon oxide layer.

[0168] A buffer layer (422) is disposed on the barrier layer (421). The buffer layer (422) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In this embodiment, the buffer layer (422) may be a single-layer silicon oxide layer.

[0169] A gate electrode (PTGa) of a phototransistor (PTb) may be disposed on a buffer layer (422). The gate electrode (PTGa) may be part of a metal pattern. According to one embodiment of the present invention, the gate electrode (PTGa) may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0170] In one embodiment of the present invention, the buffer layer (422) may be replaced with an insulating pattern. The gate electrode (PTGa) may serve as a mask for forming an insulating pattern from the buffer layer (422).

[0171] A first sensing insulating layer (423) covering a gate electrode (PTGa) is disposed on a buffer layer (422). In this embodiment, the first sensing insulating layer (423) may be a single layer of silicon oxide. A semiconductor pattern is disposed on the first sensing insulating layer (423). The semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. Oxide semiconductors may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0172] The source electrode (SEb), semiconductor layer (SCLb), and drain electrode (DEb) of the phototransistor (PTb) are formed from a semiconductor pattern. The semiconductor layer (SCLb) may be formed from amorphous silicon or an oxide semiconductor. According to one embodiment of the present invention, the semiconductor layer (SCLb) may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. Oxide semiconductors may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0173] The source electrode (SEb) and the drain electrode (DEb) may be formed spaced apart from each other with the semiconductor layer (SCLb) in between. According to one embodiment of the present invention, the source electrode (SEb) may be positioned to contact one side of the semiconductor layer (SCLb). On the other hand, the drain electrode (DEb) may be positioned to contact the other side of the semiconductor layer (SCLb). Accordingly, the source electrode (SEb) and the drain electrode (DEb) may be formed extending in opposite directions from the semiconductor layer (SCLb). The source electrode (SEb) and the drain electrode (DEb) may be made of a metallic material, for example, copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), etc., but are not limited thereto.

[0174] A porous layer (PLc) may be disposed on the source electrode (SEb), semiconductor layer (SCLb), and drain electrode (DEb) of a phototransistor (PTb). Specifically, a porous layer (PLc) having a plurality of holes (HSe) defined therein may be formed on the source electrode (SEb), semiconductor layer (SCLb), and drain electrode (DEb). According to one embodiment of the present invention, the porous layer (PLc) may be an organic layer containing an organic material. However, it is not limited thereto, and the porous layer (PLc) may be an inorganic layer containing an inorganic material or may have a structure in which an organic layer and an inorganic layer are stacked. The porous layer (PLc) may be manufactured through a separate process from the second sensing insulating layer (424), after which the second sensing insulating layer (424) may be disposed on the porous layer (PLb).

[0175] The second sensing insulating layer (424) is positioned to cover the porous layer (PLc). According to one embodiment of the present invention, the second sensing insulating layer (424) may have a porous structure comprising a plurality of holes (HSe) on the source electrode (SEb), semiconductor layer (SCLb), and drain electrode (DEb) when the porous layer (PLc) is omitted. The second sensing insulating layer (424) may be an organic layer containing an organic material. However, it is not limited thereto, and the second sensing insulating layer (424) may be an inorganic layer containing an inorganic material or may have a multilayer structure in which an organic layer and an inorganic layer are stacked. According to one embodiment of the present invention, the porous layer (PLc) corresponds to the first subporous layer (PSL1, see FIG. 2a) shown in FIG. 2a, and the second sensing insulating layer (424) may correspond to the second subporous layer (PSL2, see FIG. 2a) shown in FIG. 2a.

[0176] Referring to FIG. 13b, a plurality of holes (HSe) may be arranged spaced apart from each other on a plane. For example, they may be arranged spaced apart from each other at regular intervals on a plane. However, they are not limited thereto, and the plurality of holes (HSe) may be arranged spaced apart at different intervals. According to one embodiment of the present invention, the plurality of holes (HSe) on a plane may have the same size. For example, the size of the plurality of holes (HSb) may be 10 nm or more and 1000 nm or less. However, they are not limited thereto, and the plurality of holes (HSb) may have different sizes on a plane. According to one embodiment of the present invention, the plurality of holes (HSb) may be formed by penetrating the second sensing insulating layer (424). However, they are not limited thereto, and the plurality of holes (HSb) may be provided in a recessed form from the upper surface of the second sensing insulating layer (424).

[0177] According to one embodiment of the present invention, the porous layer (PLc) includes a plurality of holes (HSe), thereby capturing external light provided to the phototransistor (PTb) or increasing the amount of external light provided to the semiconductor layer (SCLb) through internal scattering. Additionally, the light absorption rate of the phototransistor (PTb) can be controlled by adjusting the size and number of the plurality of holes (HSe) provided in the porous layer (PLc).

[0178] A third sensing insulating layer (425) is disposed on the second sensing insulating layer (424). In this embodiment, the third sensing insulating layer (425) may include a silicon oxide layer and a silicon nitride layer. The third sensing insulating layer (425) may include a plurality of silicon oxide layers and silicon nitride layers that are alternately stacked. The third sensing insulating layer (425) is a structure that can be omitted.

[0179] The optical pattern layer (430) can be placed directly on the sensor layer (420). For example, the optical pattern layer (430) and the sensor layer (420) can be formed through a continuous process. The optical pattern layer (430) can filter light incident on the sensor (420). For example, the angle of incidence of light that can pass through the optical pattern layer (430) can be controlled by the optical pattern layer (430). For example, the angle of incidence can be limited to a predetermined angle or less. As the angle of incidence is limited, the accuracy of fingerprint recognition can be improved.

[0180] FIGS. 14a to 14f are process diagrams illustrating a method for manufacturing a phototransistor according to one embodiment of the present invention, and FIGS. 15a to 15e are cross-sectional views of the process diagrams of FIGS. 14a to 14f. FIG. 16 is a process diagram illustrating a method for removing nanoparticles according to one embodiment in the step of manufacturing a phototransistor.

[0181] Referring to FIG. 14a, a gate electrode (PTG) is formed on a substrate (SB). A metal layer can be formed through a deposition process, and then the metal layer can be patterned through a photolithography process and an etching process. Next, at least one gate insulating layer (GIL) covering the gate electrode (PTG) is formed. Fluorine gas may be used in the etching process for forming the gate electrode (PTG). After the etching process, fluorine residue may exist on the gate insulating layer (GIL) or around the gate electrode (PTG). The gate insulating layer (GIL) may function as a barrier layer to prevent the diffusion of such fluorine residue.

[0182] Next, a semiconductor layer (SCL) is formed. After forming the semiconductor layer (SCL) through a sputtering process, the semiconductor layer (SCL) can be patterned through a photolithography process and an etching process. According to one embodiment of the present invention, the semiconductor layer (SCL) may be formed from crystalline silicon, amorphous silicon, or an oxide semiconductor. A source electrode (SE) and a drain electrode (DE) may be formed extending in opposite directions from the semiconductor layer (SCL). The source electrode (SE) and the drain electrode (DE) may be made of a metallic material, for example, copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), etc. Next, an organic layer (OL) may be formed on the semiconductor layer (SCL). The organic layer (OL) can be arranged to cover the semiconductor layer (SCL), source electrode (SE), and drain electrode (DE). FIG. 14a is a process diagram showing the step of scattering nanoparticles (NP) on the organic layer (OL), and FIG. 15a is a cross-sectional view cut along the cutting line I-I' shown in FIG. 14a.

[0183] Referring to FIGS. 14a and 15a, nanoparticles (NP) can be dispersed on an organic layer (OL) formed on a semiconductor layer (SCL), a source electrode (SE), and a drain electrode (DE). In this process, the nanoparticles (NP) can be randomly placed on the organic layer (OL) and may not be fixed on the organic layer (OL). Therefore, referring to FIG. 15a, the distance between multiple nanoparticles (NP) may not be constant.

[0184] FIG. 14b is a process diagram showing the step of aligning nanoparticles (NP) using a magnetic field, and FIG. 15b is a cross-sectional view cut along the cutting line II-II' shown in FIG. 14b.

[0185] Referring to FIGS. 14a and 15b, nanoparticles (NP) dispersed on an organic layer (OL) can be arranged in a specific shape by a magnetic field on the underside of a substrate (SB). According to one embodiment of the present invention, since the nanoparticles (NP) include a metallic material, they can be magnetic, and when the nanoparticles (NP) are placed in a space where a constant magnetic field is formed, the nanoparticles (NP) can be rearranged in the direction in which the magnetic field is formed. As illustrated, the nanoparticles (NP) can be spaced apart from each other at a constant interval. However, they are not limited thereto, and the distance between the nanoparticles (NP) may not be constant depending on the strength of the magnetic field and the direction in which it is formed.

[0186] FIG. 14c is a process diagram showing the step of placing an inorganic layer (IL) on an organic layer (OL), and FIG. 14d is a process diagram showing the step of removing nanoparticles (NP). FIG. 15c is a cross-sectional view taken along the cutting line Ⅲ-Ⅲ' shown in FIG. 14c.

[0187] Referring to FIGS. 14c and 15c, an inorganic layer (IL) can be formed on an organic layer (OL) through a coating or deposition process. The inorganic layer (IL) can be formed to fill the space where nanoparticles (NP) are not placed. In one example of the present invention, the thickness of the inorganic layer (IL) may be smaller than the diameter of the nanoparticles (NP). Specifically, the inorganic layer (IL) may have a thickness of 51.2 nm, and the diameter of the nanoparticles (NP) may have a thickness of 155 nm. The nanoparticles (NP) can be fixed to the upper surface of the organic layer (OL) by the inorganic layer (IL).

[0188] Referring to FIG. 14d, nanoparticles (NP) can be removed using a tape (TP) having an adhesive layer formed on one side. Specifically, the adhesive layer of the tape (TP) can be brought into contact with nanoparticles (NP) protruding above the upper surface of the inorganic layer (IL), and then the tape (TP) can be separated to selectively remove only the nanoparticles (NP). By adjusting the size of the tape (TP), all nanoparticles (NP) can be removed in a single separation process, but this is not limited thereto. That is, all nanoparticles (NP) can be removed through two or more separation processes. The method of removing nanoparticles (NP) is not limited to using a tape; alternatively, a method of selectively etching and removing nanoparticles (NP) through a dry or wet etching process can be used.

[0189] Referring to FIG. 16, when manufacturing multiple phototransistors in multiple cell regions of a large substrate (LSB), a polymer roller (PR) is placed on the large substrate (LSB) to remove nanoparticles (NP) scattered in multiple cell regions in a single process. Specifically, by rotating the polymer roller (PR) and moving it in a second direction (DR2), nanoparticles (NP) scattered in multiple cell regions can be removed in a single process, thereby simplifying the nanoparticle (NP) removal process.

[0190] FIG. 14e is a process diagram showing the step of patterning the organic layer, and FIG. 15d is a cross-sectional view cut along the cutting line Ⅳ-Ⅳ' shown in FIG. 14e.

[0191] When nanoparticles (NP) placed on the organic layer (OL) are removed, a second subporous layer (PSL2) can be formed on the organic layer (OL) in which a plurality of first subholes (HSe) are defined at the locations where the nanoparticles (NP) were placed.

[0192] Referring to FIG. 15d, a plurality of first sub-holes (HSe) can be formed to be identical to the shape of the underlying structure of the nanoparticles (NP). Thus, as in FIG. 14e, the plurality of first sub-holes (HSe) can be defined as having a hemispherical shape. However, this is not limited thereto, and the shape of the plurality of first sub-holes (HSe) can be varied depending on the way the nanoparticles (NP) are removed.

[0193] Referring to FIG. 14e and FIG. 15d, an ashing process using O2 plasma can be performed using a plasma device (OPE) placed on the second subporous layer (PSL2). The plasma device (OPE) is a device capable of performing dry etching, and a sealed processing space is created within a vacuum chamber, a semiconductor wafer is placed on the high-frequency side electrode, and a process can be carried out in which a gas for generating plasma is supplied from the gas supply electrode side provided opposite the high-frequency side electrode. Patterning using O2 gas is also called ashing and is one of the methods for removing organic matter.

[0194] The organic layer (OL) can be patterned through an ashing process using O2 plasma. At this time, the second subporous layer (PSL2) can serve as a mask used to pattern the organic layer (OL) during the ashing process. The second subporous layer (PSL2) requires resistance to withstand exposure to the ashing process using O2 plasma. The second subporous layer (PSL2) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The second subporous layer (PSL2) may be a single layer of hafnium oxide, but is not limited thereto. The second subporous layer (PSL2) may have a single-layer or multi-layer structure and may include at least one of the materials described above, but is not limited thereto.

[0195] FIG. 14f is a process diagram illustrating a phototransistor having a plurality of holes formed in an organic layer, and FIG. 14e is a cross-sectional view of the phototransistor of FIG. 14f cut along V-V'.

[0196] An organic layer (OL, see FIG. 14e) is patterned by O2 plasma to form a first subporous layer (PSL1) below a second subporous layer (PSL2). The first subporous layer (PSL1) may include a plurality of second subholes (HSf) formed by penetrating the organic layer (OL). Thus, a porous layer (PLa) comprising the first subporous layer (PSL1) and the second subporous layer (PSL2) can be formed.

[0197] Although not shown, a protective layer (PTL) (see FIG. 3a and 3b) may be further formed on the porous layer (PLa). To protect the semiconductor layer (SCL) from foreign substances such as moisture, oxygen, and dust particles, the protective layer (PTL) may be positioned to cover the entire porous layer (PLa).

[0198] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0199] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0200] PTG: Gate electrode SCL: Semiconductor layer GIL: Gate insulation layer SE: Source electrode DE: Drain electrode PL: Porous layer HS: Multiple holes PT: Phototransistor PTL: Protection layer DP_ED: Display layer DP_CL: Circuit layer NP: Nanoparticle LSB: Large Substrate PR: Polymer Roller

Claims

Claim 1 A phototransistor comprising: a gate electrode; a semiconductor layer disposed on the gate electrode; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode and a drain electrode disposed spaced apart from each other on the semiconductor layer; and a porous layer disposed on the source electrode, the semiconductor layer and the drain electrode, wherein a plurality of holes are defined therein, the plurality of holes exposing the upper surfaces of the source electrode and the drain electrode. Claim 2 In claim 1, the semiconductor layer comprises a phototransistor including an oxide semiconductor. Claim 3 In claim 1, the porous layer comprises an organic material in a phototransistor. Claim 4 The phototransistor according to claim 1, wherein the porous layer comprises a first subporous layer comprising an organic material; and a second subporous layer disposed on the first subporous layer and comprising an inorganic material, and the plurality of holes comprises a first subhole formed by penetrating the second subporous layer; and a second subhole formed by penetrating the first subporous layer. Claim 5 A phototransistor according to claim 1, further comprising a protective layer disposed on the porous layer. Claim 6 In claim 1, a first portion in which the semiconductor layer, the source electrode, and the drain electrode overlap in a plane and a second portion in which they do not overlap are defined, and the plurality of holes are phototransistors that overlap with the first and second portions. Claim 7 In claim 6, the source electrode and the drain electrode are a phototransistor comprising a transparent conductive material. Claim 8 In claim 1, the plurality of holes are spaced apart from each other in a plane and the sizes of the plurality of holes in the plane are the same for the phototransistor. Claim 9 In claim 1, the plurality of holes are phototransistors formed by penetrating the porous layer. Claim 10 An electronic device comprising: a base layer; a display element layer including a light-emitting element; and a circuit layer disposed between the base layer and the display element layer, wherein the circuit layer includes a pixel driving circuit electrically connected to the light-emitting element and a phototransistor having a light-sensing function, and wherein the phototransistor comprises: a gate electrode; a semiconductor layer disposed on the gate electrode; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode and a drain electrode disposed spaced apart from each other on the gate insulating layer; and a porous layer disposed on the source electrode, the semiconductor layer and the drain electrode, and having a plurality of holes defined therein, wherein the plurality of holes expose the upper surface of the source electrode and the drain electrode. Claim 11 In claim 10, the semiconductor layer comprises an oxide semiconductor in an electronic device. Claim 12 In claim 10, the porous layer comprises an organic material in an electronic device. Claim 13 An electronic device according to claim 10, wherein the porous layer comprises a first subporous layer comprising an organic material; and a second subporous layer disposed on the first subporous layer and comprising an inorganic material, wherein the plurality of holes are defined by penetrating the first and second subporous layers. Claim 14 An electronic device according to claim 13, further comprising a protective layer disposed on the porous layer. Claim 15 An electronic device comprising: a window; a display module disposed below the window; a sensing unit disposed below the display module; and a housing coupled to the window and accommodating the display module and the sensing unit, wherein the sensing unit includes a phototransistor having a light-sensing function, and the phototransistor includes: a gate electrode; a semiconductor layer disposed on the gate electrode; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode and a drain electrode disposed spaced apart from each other on the gate insulating layer; and a porous layer disposed on the source electrode, the semiconductor layer and the drain electrode, having a plurality of holes defined therein, wherein the plurality of holes expose the upper surface of the source electrode and the drain electrode. Claim 16 In claim 15, the semiconductor layer comprises an oxide semiconductor in an electronic device. Claim 17 In claim 15, the porous layer comprises an organic material in an electronic device. Claim 18 An electronic device according to claim 15, wherein the porous layer comprises a first subporous layer comprising an organic material; and a second subporous layer disposed on the first subporous layer and comprising an inorganic material, wherein the plurality of holes are defined by penetrating the first and second subporous layers. Claim 19 A method for manufacturing a phototransistor comprising: a step of forming a gate electrode; a step of forming a gate insulating layer on the gate electrode; a step of forming a source electrode, a semiconductor layer, and a drain electrode on the gate insulating layer; a step of forming an organic layer on the source electrode, the semiconductor layer, and the drain electrode; a step of scattering nanoparticles on the organic layer; and a step of forming a porous layer having a plurality of holes formed therein, wherein the organic layer in the region where the nanoparticles are disposed is selectively removed to expose the semiconductor layer to the organic layer. Claim 20 A method for manufacturing a phototransistor according to claim 19, wherein the step of forming a porous layer having a plurality of holes that expose the semiconductor layer to the organic layer by selectively removing the organic layer in the region where the nanoparticles are disposed comprises: a step of forming an inorganic layer on the organic layer where the nanoparticles are dispersed to fix the nanoparticles to the organic layer; a step of removing the nanoparticles to form a first subporous layer; and a step of patterning the organic layer using the first subporous layer as a mask to form a second subporous layer. Claim 21 A method for manufacturing a phototransistor according to claim 20, wherein the thickness of the first subporous layer is smaller than the diameter of the nanoparticle. Claim 22 A method for manufacturing a phototransistor according to claim 21, wherein the step of forming the plurality of holes further comprises the step of aligning the nanoparticles using a magnetic field after the step of scattering the nanoparticles on the organic layer. Claim 23 A method for manufacturing a phototransistor according to claim 21, further comprising the step of forming a protective layer on the porous layer. Claim 24 A method for manufacturing a phototransistor according to claim 21, wherein the step of removing the nanoparticles comprises removing all nanoparticles using a polymer roller on a large substrate. Claim 25 A method for manufacturing a phototransistor according to claim 21, wherein the step of removing the nanoparticles comprises the step of selectively etching and removing the nanoparticles through a dry or wet etching process.

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