Display device

Abstract

The display device includes a display panel and an input sensor. The display panel includes an encapsulated organic layer disposed inside a first line pattern. The organic pattern includes, on a plane, a first portion disposed outside the first line pattern and a second portion disposed inside the first line pattern and overlapping the encapsulated organic layer. The organic pattern supports a signal line of the input sensor.

Description

Technology Field

[0001] The present invention relates to a display device, and more specifically, to a display device including an input sensor. Background Technology

[0002] The objective of the present invention is to provide a display device in which the area of ​​the non-displayed image region is reduced. The problem to be solved

[0003] The objective of the present invention is to provide a display device in which the area of ​​the non-displayed image region is reduced. means of solving the problem

[0004] A display device according to the present invention comprises a display panel including a display area and a peripheral area disposed outside the display area, a sensing electrode disposed on the display panel and superimposing the display area, a signal line disposed on the display panel and superimposing the peripheral area and connected to the sensing electrode, and an organic pattern disposed on the display panel and superimposing the signal line. The display panel comprises a pixel superimposed on the display area, a first line pattern superimposed on the peripheral area, a first encapsulating inorganic layer disposed on the display area and the peripheral area and superimposing the first line pattern and the pixel, an encapsulating organic layer disposed on the first encapsulating inorganic layer and the inner side of the first line pattern, and a second encapsulating inorganic layer disposed on the encapsulating organic layer, superimposing the display area and the peripheral area, and contacting the first encapsulating inorganic layer within the peripheral area. The above organic pattern includes, on a plane, a first portion disposed outside the first line pattern and a second portion disposed inside the first line pattern and overlapping the encapsulated organic layer.

[0005] On a plane, the area of ​​the second part may be smaller than the area of ​​the first part.

[0006] The average thickness of the first part above may be greater than the average thickness of the second part above.

[0007] The above display panel may further include a second line pattern disposed outside the first line pattern on a flat surface.

[0008] Within the above surrounding area, the thickness of the area adjacent to the display area of ​​the bag organic layer may be greater than the thickness of the area far from the display area of ​​the bag organic layer.

[0009] The first line pattern is extended in a first direction, and the signal line includes a first line portion extended in the first direction and a second line portion extended from the first line portion and intersecting with the first direction, and the second line portion may overlap with the second portion.

[0010] On a flat plane, the first line portion can be placed on the outside of the bag organic layer.

[0011] The first line pattern is extended in a first direction, and the first part is extended in the first direction, and the first part may include a plurality of curved surface patterns arranged along the first direction, each providing a convex curved surface.

[0012] The above second part is provided in plurality, and the plurality of second parts may be spaced apart and arranged within the first direction.

[0013] The first line pattern is extended in a first direction, and the first part is extended in the first direction, and a plurality of valley regions can be defined in the first part, each extending in a second direction that is spaced apart along the first direction and intersects the first direction.

[0014] The above organic pattern may further include dyes or pigments.

[0015] The above organic pattern can come into contact with the above second encapsulated inorganic layer.

[0016] It may further include a first inorganic layer disposed on the second encapsulated inorganic layer and a second inorganic layer disposed on the first inorganic layer. The organic pattern may be disposed between the first inorganic layer and the second inorganic layer.

[0017] It may further include a first inorganic layer disposed on the second inorganic layer and a second inorganic layer disposed on the first inorganic layer. The signal line may include a line of a first layer disposed between the first inorganic layer and the second inorganic layer, and a line of a second layer disposed on the second inorganic layer and connected to the line of the first layer through a contact hole penetrating the second inorganic layer.

[0018] The above display area may include a first display area, a second display area disposed outside the first display area on a plane, and a third display area disposed outside the second display area. The pixel may include a first pixel comprising a first light-emitting element disposed in the first display area and a first pixel circuit electrically connected to the first light-emitting element and disposed in the first display area, a second pixel comprising a second light-emitting element disposed in the second display area and a second pixel circuit electrically connected to the second light-emitting element and disposed in the second display area, and a third pixel comprising a third light-emitting element disposed in the third display area and a third pixel circuit electrically connected to the third light-emitting element and disposed in the second display area.

[0019] The above display panel may further include a scan driving circuit that provides a scan signal to the first pixel, the second pixel, and the third pixel. The scan driving circuit may be superimposed on the third display area. The third light-emitting element may be superimposed on the scan driving circuit.

[0020] The first line pattern is extended in a first direction, and a plurality of third light-emitting elements are provided, and the second portion may be positioned between two adjacent third light-emitting elements spaced apart within the first direction among the plurality of third light-emitting elements.

[0021] The resolution of the first display area may be greater than the resolution of the second display area or the resolution of the third display area.

[0022] The light emission area of ​​the first color of the second light-emitting element may be larger than the light emission area of ​​the first color of the first light-emitting element.

[0023] A display device according to one embodiment of the present invention may include a display panel comprising a display area and a peripheral area disposed outside the display area, a sensing electrode disposed on the display panel and superimposing the display area, a signal line disposed on the display panel and superimposing the peripheral area and connected to the sensing electrode, and an organic pattern disposed on the display panel and supporting the signal line. The display panel may include a light-emitting element superimposed on the display area, a first encapsulating inorganic layer disposed on the display area and the peripheral area and superimposing the light-emitting element, an encapsulating organic layer disposed on the first encapsulating inorganic layer and providing an inclined surface, and a second encapsulating inorganic layer disposed on the encapsulating organic layer and in contact with the first encapsulating inorganic layer within the peripheral area. The organic pattern may include a first portion that does not superimpose the encapsulating organic layer and a second portion that superimposes the inclined surface of the encapsulating organic layer. Effects of the invention

[0024] As described above, the signal line of the input sensor is positioned outside the first line pattern, thereby reducing the area between the first line pattern and the display area. Consequently, the area of ​​the non-display area of ​​the display device can be reduced.

[0025] Tensile stress can be relieved by the organic pattern including curved patterns that provide a convex curved surface.

[0026] By including dyes or pigments, the organic pattern can function as a light-blocking pattern. Structures beneath the organic pattern are not visible to the user. Brief explanation of the drawing

[0027] FIG. 1a is a perspective view of a display device according to one embodiment of the present invention. FIG. 1b is a cross-sectional view of a display device corresponding to I-I' of FIG. 1a. FIG. 1c is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 2 is a plan view of a display panel according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 4 is a cross-sectional view of an input sensor according to one embodiment of the present invention. FIG. 5a is a plan view of an input sensor according to one embodiment of the present invention. FIG. 5b is a cross-sectional view of a display module corresponding to II-II' of FIG. 5a. FIG. 5c is a partial perspective view illustrating an organic pattern and a signal line. FIG. 5d is a cross-sectional view of a display module according to one embodiment of the present invention. FIGS. 6a to 6c are partial perspective views of an organic pattern according to one embodiment of the present invention. FIG. 7a is a plan view of a display panel according to one embodiment of the present invention. Fig. 7b is a plan view of a portion of Fig. 7a enlarged. FIG. 7c is a cross-sectional view corresponding to III-III' in FIG. 7b. FIG. 7d is a partial perspective view showing an organic pattern and a signal line. FIGS. 7e to 7g are plan views illustrating a part of an input sensor that overlaps a part of the display panel shown in FIG. 7b. Specific details for implementing the invention

[0028] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0029] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0030] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0031] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0032] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0034] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0036] FIG. 1a is a perspective view of a display device (DD) according to an embodiment of the present invention. FIG. 1b is a cross-sectional view of the display device (DD) corresponding to I-I' in FIG. 1a. FIG. 1c is a cross-sectional view of a display module (DM) according to an embodiment of the present invention.

[0037] Referring to FIGS. 1a and 1b, a display device (DD) according to one embodiment of the present invention may include a display module (DM), a roller (ROL), a holder (HD), and a housing (HS). The display device (DD) may further include additional components depending on the application.

[0038] FIGS. 1a and 1b illustrate a display device (DD) in a state where a display module (DM) is housed in a housing (HS) (hereinafter, a first state). In the first state, a display device in which a part of the display module (DM) is exposed from the housing (HS) is illustrated as an example, but is not limited thereto. In the first state, the display module (DM) can be fully inserted into the housing (HS).

[0039] In a fully unfolded state (hereinafter referred to as the second state), the display module (DM) exposed from the housing (HS) may provide a flat display surface (DD-IS). The display surface (DD-IS) may be parallel to the plane defined by the first directional axis (DR1) and the second directional axis (DR2). A bezel area adjacent to the display surface (DD-IS) is defined on the front of the display module (DM). The bezel area may be an area where an image is not displayed. The normal direction of the display surface (DD-IS), that is, the thickness direction of the display module (DM), is indicated by the third directional axis (DR3). The front (or top) and back (or bottom) surfaces of each member are distinguished based on the third directional axis (DR3).

[0040] Referring to FIG. 1c, the display module (DM) may include a display panel (DP), an input sensor (ISL), an anti-reflective layer (ARL), and a window (WIN). The display panel (DP) may be a configuration that substantially generates an image. The display panel (DP) may be a light-emitting display panel, for example, the display panel (DP) may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro LED display panel, or a nano LED display panel.

[0041] The input sensor (ISL) can be placed on the display panel (DP). The input sensor (ISL) can be placed directly on the display panel (DP) through a continuous process. Here, "directly placed" may mean that no third component is placed between the input sensor (ISL) and the display panel (DP). That is, an adhesive layer may not be placed between the input sensor (ISL) and the display panel (DP).

[0042] The anti-reflection layer (ARL) can be placed directly on the input sensor (ISL). The anti-reflection layer (ARL) can reduce the reflectivity of external light incident from outside the display device (DD). The anti-reflection layer (ARL) can be formed on the input sensor (ISL) through a continuous process. The anti-reflection layer (ARL) may include color filters. The color filters may have a predetermined arrangement. For example, the color filters may be arranged considering the light emission colors of the pixels included in the display panel (DP). Additionally, the anti-reflection layer (ARL) may further include a black matrix adjacent to the color filters.

[0043] In one embodiment of the present invention, the anti-reflection layer (ARL) may include a polarizer and a retarder. At this time, an adhesive layer may be disposed between the anti-reflection layer (ARL) and the input sensor (ISL).

[0044] The window (WIN) may be placed directly on the anti-reflective layer (ARL) or bonded via an adhesive layer. The window (WIN) may be formed by coating a synthetic resin or by attaching a synthetic resin film. The window (WIN) may include thin-film glass. The window (WIN) may further include a bezel pattern defining a bezel area. The bezel pattern may be a light-blocking pattern that obscures a structure on the underside.

[0046] FIG. 2 is a plan view of a display panel (DP) according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a display panel (DP) according to one embodiment of the present invention.

[0047] As illustrated in FIG. 2, the display panel (DP) includes a display area (DP-DA) and an adjacent peripheral area (DP-NDA) on a plane. In this embodiment, the peripheral area (DP-NDA) may be defined along the border of the display area (DP-DA). The peripheral area (DP-NDA) may correspond to the bezel area of ​​the display device and may be a non-display area where an image is not displayed.

[0048] A display panel (DP) may include a scan driving circuit (GDC), a plurality of signal lines (SGL), and a plurality of pixels (PX). The plurality of pixels (PX) are arranged in a display area (DP-DA). Each of the pixels (PX) includes a light-emitting element and a pixel circuit (or pixel driving circuit) connected thereto.

[0049] The scan driving circuit (GDC) generates multiple scan signals and sequentially outputs the multiple scan signals to multiple scan lines (GL) described below. The scan driving circuit (GDC) may further output another control signal to the driving circuit of the pixels (PX). The scan driving circuit (GDC) may include multiple thin-film transistors formed through the same process as the pixel circuit, such as the LTPS (Low Temperature Polycrystalline Silicon) process or the LTPO (Low Temperature Polycrystalline Oxide) process.

[0050] A plurality of signal lines (SGL) include scan lines (GL), data lines (DL), power lines (PL), and control signal lines (CSL). Each of the scan lines (GL) is connected to a corresponding pixel (PX) among a plurality of pixels (PX), and each of the data lines (DL) is connected to a corresponding pixel (PX) among a plurality of pixels (PX). The power line (PL) is connected to a plurality of pixels (PX). The control signal line (CSL) can provide control signals to the scan driving circuit (GDC).

[0051] The display panel (DP) includes signal pads (DP-PD) connected to the ends of signal lines (SGL). The area within the peripheral area (DP-NDA) where the signal pads (DP-PD) are located can be defined as the pad area (NDA-PD). A data driving circuit connected to the signal pads (DP-PD) may be installed in the display panel (DP).

[0052] The display panel (DP) may include line patterns (DMP1, DMP2). The line patterns (DMP1, DMP2) prevent liquid organic material from overflowing during the inkjet process of the display panel (DP) (hereinafter referred to as a dam function). Two line patterns (DMP1, DMP2) are illustrated as examples.

[0053] Two line patterns (DMP1, DMP2) are placed in the surrounding area (DP-NDA) and surround the display area (DP-DA). Closed-line shaped line patterns (DMP1, DMP2) are illustrated as examples but are not limited thereto. Each of the line patterns (DMP1, DMP2) may include a portion placed on one side and a portion placed on the other side of the display area (DP-DA) within the second direction (DR2). The line patterns (DMP1, DMP2) may include a portion parallel to the pad area (NDA-PD).

[0054] A crack detection pattern (CRD) is positioned outside the line patterns (DMP1, DMP2). Crack detection patterns (CRD) positioned on both sides of the display area (DP-DA) are illustrated as an example. In one embodiment of the present invention, the crack detection patterns (CRD) may be omitted.

[0055] FIG. 3 illustrates a partial cross-section of a display panel (DP) corresponding to a display area (DP-DA). The display panel (DP) may include a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE) sequentially stacked on a base layer (BL).

[0056] The circuit element layer (DP-CL) includes at least one insulating layer and a circuit element. The circuit element includes a signal line, a pixel circuit, etc. The circuit element layer (DP-CL) can be formed through a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and a process of patterning an insulating layer, a semiconductor layer, and a conductive layer by photolithography.

[0057] The buffer layer (BFL) may include a plurality of stacked inorganic layers. A semiconductor pattern is disposed on the buffer layer (BFL). The buffer layer (BFL) enhances the bonding strength between the base layer (BL) and the semiconductor pattern.

[0058] The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. FIG. 3 illustrates only some semiconductor patterns, and on a plane, the semiconductor pattern may be arranged according to a specific rule across pixels (PX, see FIG. 2).

[0059] The electrical properties of a semiconductor pattern differ depending on whether it is doped. The semiconductor pattern may include a first region (A1) with low doping concentration and conductivity and a second region (S1, D1) with relatively high doping concentration and conductivity. One second region (S1) may be placed on one side of the first region (A1), and another second region (D1) may be placed on the other side of the first region (A1). The second regions (S1, D1) may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant. The first region (A1) may be a non-doped region or may be doped at a lower concentration compared to the second regions (S1, D1).

[0060] The second region (S1, D1) may substantially function as an electrode or a signal transmission region. One second region (S1) may correspond to the source of the transistor, and one second region (D1) may be the drain. FIG. 3 illustrates a portion of a signal transmission region (SCL) formed from a semiconductor pattern. Although not separately illustrated, the signal transmission region (SCL) may be connected to the drain of the transistor (TR-P) on a plane. The pixel circuit may include a plurality of transistors and at least one capacitor. FIG. 3 illustrates one transistor (TR-P) as an exemplary configuration of the pixel circuit, but the pixel circuit is not limited thereto.

[0061] A first insulating layer (10) is disposed on a buffer layer (BFL). The first insulating layer (10) overlaps a plurality of pixels (PX, see FIG. 2) in common and covers a semiconductor pattern. The first insulating layer (10) can be disposed in a display area (DP-DA) and a peripheral area (DP-NDA, see FIG. 2).

[0062] The first insulating layer (10) may be an inorganic layer and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of silicon oxide, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, titanium oxide, and hafnium oxide. In addition to the first insulating layer (10), the inorganic layer of the circuit element layer (DP-CL) described below may include any one of the materials listed above.

[0063] A gate (G1) is disposed on the first insulating layer (10). The gate (G1) may include a multilayer metal layer. The gate (G1) overlaps the first region (A1). In the process of doping a semiconductor pattern, the gate (G1) is like a mask.

[0064] A second insulating layer (20) covering a gate (G1) is disposed on the first insulating layer (10). The second insulating layer (20) overlaps the pixels (PX, see FIG. 2) in common. An upper electrode (UE) may be disposed on the second insulating layer (20). The upper electrode (UE) may overlap with the gate (G1). The upper electrode (UE) may include a multilayer metal layer. In one embodiment of the present invention, the upper electrode (UE) may be omitted.

[0065] A third insulating layer (30) covering an upper electrode (UE) is disposed on the second insulating layer (20). A first connecting electrode (CNE1) may be disposed on the third insulating layer (30). The first connecting electrode (CNE1) may be connected to a signal transmission area (SCL) through a contact hole (CNT-1) penetrating the first to third insulating layers (10 to 30). The second insulating layer (20) and the third insulating layer (30) may be inorganic layers.

[0066] A fourth insulating layer (40) is disposed on the third insulating layer (30). A fifth insulating layer (50) is disposed on the fourth insulating layer (40). The fourth insulating layer (40) and the fifth insulating layer (50) may be organic layers. A second connecting electrode (CNE2) may be disposed on the fourth insulating layer (40). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a contact hole (CNT-2) penetrating the fourth insulating layer (40). The connection relationship between the signal transmission area (SCL) and the first electrode (AE) through the first connecting electrode (CNE1) and the second connecting electrode (CNE2) is merely exemplary, and the connection relationship between the pixel circuit and the light-emitting element is not particularly limited.

[0067] A light-emitting element (OLED) is disposed on the fifth insulating layer (50). A first electrode (AE, or anode) is disposed on the fifth insulating layer (50). The first electrode (AE) is connected to a second connecting electrode (CNE2) through a contact hole (CNT-3) penetrating the fifth insulating layer (50). An opening (OP) is defined in the pixel defining film (PDL). The opening (OP) of the pixel defining film (PDL) exposes at least a portion of the first electrode (AE). The pixel defining film (PDL) may be an organic layer.

[0068] As illustrated in FIG. 3, the display area (DP-DA) may include a light-emitting area (PXA) and a non-light-emitting area (NPXA) adjacent to the light-emitting area (PXA). The non-light-emitting area (NPXA) may surround the light-emitting area (PXA). In this embodiment, the light-emitting area (PXA) is defined to correspond to a portion of the first electrode (AE) exposed by the opening (OP).

[0069] A hole control layer (HCL) can be placed in common in the emitting region (PXA) and the non-emitting region (NPXA). The hole control layer (HCL) includes a hole transport layer and may further include a hole injection layer. An emitting layer (EML) is placed on the hole control layer (HCL). The emitting layer (EML) can be placed in the region corresponding to the aperture (OP). That is, the emitting layer (EML) can be formed separately on each of the pixels (PX, see FIG. 2).

[0070] An electronic control layer (ECL) is disposed on an emitting layer (EML). The electronic control layer (ECL) includes an electron transport layer and may further include an electron injection layer. The hole control layer (HCL) and the electronic control layer (ECL) can be formed commonly across a plurality of pixels using an open mask. A second electrode (CE, or cathode) is disposed on the electronic control layer (ECL). The second electrode (CE) has a single shape and is disposed commonly across a plurality of pixels (PX, see FIG. 2). As shown in FIG. 3, a thin film encapsulation layer (TFE) is disposed on the second electrode (CE).

[0071] The thin film encapsulation layer (TFE) may include a first inorganic layer (IOL1, or the first encapsulation inorganic layer), an organic layer (OL, or the encapsulation organic layer), and a second inorganic layer (IOL2, or the second encapsulation inorganic layer). The first inorganic layer (IOL1) and the second inorganic layer (IOL2) protect the display device layer (DP-OLED) from moisture / oxygen, and the organic layer (OL) protects the display device layer (DP-OLED) from foreign substances such as dust particles.

[0073] FIG. 4 is a cross-sectional view of an input sensor (ISL) according to an embodiment of the present invention. The input sensor (ISL) acquires coordinate information of an external input. The input sensor (ISL) may have a multilayer structure. The input sensor (ISL) may include a single layer or a multilayer conductive layer. The input sensor (ISL) may include a single layer or a multilayer insulating layer. The input sensor (ISL) may detect an external input, for example, by a capacitive method. In the present invention, the operation method of the input sensor (ISL) is not particularly limited, and in an embodiment of the present invention, the input sensor (ISL) may detect an external input by an electromagnetic induction method or a pressure sensing method.

[0074] As illustrated in FIG. 4, the input sensor (ISL) may include a first insulating layer (IS-IL1), a first conductive pattern layer (IS-CL1), a second insulating layer (IS-IL2), a second conductive pattern layer (IS-CL2), and a third insulating layer (IS-IL3). Each of the first insulating layer (IS-IL1) and the second insulating layer (IS-IL2) may include at least one inorganic layer. The first insulating layer (IS-IL1) may be placed directly on a thin film encapsulation layer (TFE). In one embodiment of the present invention, the first insulating layer (IS-IL1) and / or the third insulating layer (IS-IL3) may be omitted.

[0075] Each of the first insulating layer (IS-IL1) and the second insulating layer (IS-IL2) may comprise at least one of silicon oxide, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, titanium oxide, and hafnium oxide. The third insulating layer (IS-IL3) may comprise at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin. In one embodiment, the third insulating layer (IS-IL3) is not limited to an organic layer, and the third insulating layer (IS-IL3) may comprise an inorganic layer or be an adhesive layer.

[0076] Each of the first conductive pattern layer (IS-CL1) and the second conductive pattern layer (IS-CL2) may include a plurality of conductive patterns. The conductive patterns may have a single-layer structure or a multilayer structure stacked along the third directional axis (DR3). The conductive pattern of the multilayer structure may include at least two of transparent conductive layers and metal layers. The conductive pattern of the multilayer structure may include metal layers containing different metals. The transparent conductive layer may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), PEDOT, metal nanowires, and graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and alloys thereof. Each of the first conductive pattern layer (IS-CL1) and the second conductive pattern layer (IS-CL2) includes a plurality of conductive patterns.

[0078] FIG. 5a is a plan view of an input sensor (ISL) according to an embodiment of the present invention. FIG. 5b is a cross-sectional view of a display module (DM) corresponding to II-II' in FIG. 5a. FIG. 5c is a partial perspective view showing an organic pattern (ORP) and a signal line (SL2).

[0079] As illustrated in FIG. 5a, the input sensor (ISL) includes a sensing electrode and a signal line connected thereto. In this embodiment, the sensing electrode may include first electrodes (E1-1 to E1-5) and second electrodes (E2-1 to E2-4) that are insulated from each other. The first electrodes (E1-1 to E1-5) and the second electrodes (E2-1 to E2-4) are positioned within a display area (DP-DA).

[0080] The signal lines include first signal lines (SL1) connected to first electrodes (E1-1 to E1-5) and second signal lines (SL2) connected to second electrodes (E2-1 to E2-4). The first signal lines (SL1) and the second signal lines (SL2) overlap in the peripheral area (DP-NDA). One of the first signal lines (SL1) and the second signal lines (SL2) transmits a transmission signal to the corresponding electrodes to detect an external input from an external circuit, and the other transmits a change in capacitance between the first electrodes (E1-1 to E1-5) and the second electrodes (E2-1 to E2-4) to the external circuit as a reception signal.

[0081] The first signal lines (SL1) connected to one side of the corresponding first electrode and the first signal lines (SL1) connected to the other side of the corresponding first electrode are arranged with the display area (DP-DA) in between. By dispersing the first signal lines (SL1) to both sides of the display area (DP-DA), the area of ​​the surrounding area (DP-NDA) can be reduced. In this embodiment, the first signal line (SL1) is shown connected only to one end of the first electrodes (E1-1 to E1-5), but it is not limited thereto. In one embodiment of the present invention, signal lines may be connected to both ends of the first electrodes (E1-1 to E1-5).

[0082] Each of the first signal lines (SL1) and the second signal lines (SL2) may include a line of the first layer and a line of the second layer disposed on different layers. The line of the first layer may be formed from the first conductive pattern layer (IS-CL1) of FIG. 4, and the line of the second layer may be formed from the second conductive pattern layer (IS-CL2). FIG. 5a illustrates, by way of example, a contact hole (TH-O) connecting the line of the first layer and the line of the second layer. The contact hole (TH-O) may penetrate the second insulating layer (IS-IL2, see FIG. 4).

[0083] Each of the first electrodes (E1-1 to E1-5) and the second electrodes (E2-1 to E2-4) may have a mesh shape in which a plurality of openings are defined. Each of the first electrodes (E1-1 to E1-5) and the second electrodes (E2-1 to E2-4) may include conductive lines defining a plurality of openings. The plurality of openings are defined to correspond to the light-emitting region (PXA, see FIG. 3) of the display panel (DP). The second electrodes (E2-1 to E2-4) intersect insulatedly with the first electrodes (E1-1 to E1-5). Either of the first electrodes (E1-1 to E1-5) and the second electrodes (E2-1 to E2-4) may have a single shape. In this embodiment, the first electrodes (E1-1 to E1-5) having a single shape are exemplified. The first electrodes (E1-1 to E1-5) may include sensing portions (SP1) and intermediate portions (CP1).

[0084] Each of the second electrodes (E2-1 to E2-4) may include sensing patterns (SP2) and bridge patterns (CP2, or connection patterns). Two adjacent sensing patterns (SP2) may be connected by two bridge patterns (CP2), but the number of bridge patterns is not limited. The bridge patterns (CP2) may be formed by patterning the first conductive pattern layer (IS-CL1) shown in FIG. 4, and a plurality of first electrodes (E1-1 to E1-5) and sensing patterns (SP2) may be formed by patterning the second conductive pattern layer (IS-CL2).

[0085] In order to show the relative positions of the line patterns (DMP1, DMP2) and the crack detection pattern (CRD) with respect to the input sensor (ISL), the line patterns (DMP1, DMP2) and the crack detection pattern (CRD) are shown in FIG. 5a.

[0087] Referring to FIG. 5b, a cross-section corresponding to II-II' in FIG. 5a is shown. The cross-section of the display panel (DP) corresponding to the display area (DP-DA) is described with reference to FIG. 4, so a detailed description is omitted. The light-emitting element (OLED) in FIG. 4 is shown briefly compared to the light-emitting element (OLED) in FIG. 3. A sensing portion (SP1) is disposed on a thin film encapsulation layer (TFE) within the display area (DP-DA). The sensing portion (SP1) is disposed between the second insulating layer (IS-IL2) and the third insulating layer (IS-IL3).

[0088] A voltage line (VL) is placed on the peripheral area (DP-NDA). The voltage line (VL) may be placed on the second insulating layer (20) of the display panel (DP). The voltage line (VL) may receive a low power supply voltage. The low power supply voltage is applied to the second electrode (CE). A connecting electrode (VL-E) is placed on the voltage line (VL), and the connecting electrode (VL-E) is connected to the second electrode (CE). The connecting electrode (VL-E) may be placed on the third insulating layer (30) of the display panel (DP).

[0089] A first line pattern (DMP1) is positioned to overlap with a voltage line (VL). The first line pattern (DMP1) can come into contact with a connecting electrode (VL-E). The first line pattern (DMP1) has a dam function in an inkjet process for forming an encapsulated organic layer (OL). A second line pattern (DMP2) is positioned outside the first line pattern (DMP1), and the second line pattern (DMP2) has the same function as the first line pattern (DMP1) and assists the first line pattern (DMP1).

[0090] The first line pattern (DMP1) includes a first layer (I1), a second layer (I2), and a third layer (I3). The first layer (I1) may be formed of the same material as the fourth insulating layer (40), the second layer (I2) may be formed of the same material as the fifth insulating layer (50), and the third layer (I3) may be formed of the same material as the pixel defining film (PDL). The second line pattern (DMP2) may further include a layer containing the same material as the third insulating layer (30) relative to the second line pattern (DMP2).

[0091] The first encapsulating inorganic layer (IOL1) and the second encapsulating inorganic layer (IOL2) overlap with the first line pattern (DMP1) and the second line pattern (DMP2), and are in contact on the outside of the first line pattern (DMP1). The first encapsulating inorganic layer (IOL1) and the second encapsulating inorganic layer (IOL2) can seal the encapsulating organic layer (OL). Additionally, the first encapsulating inorganic layer (IOL1) is in contact with the second insulating layer (20), which is an inorganic layer, and the second line pattern (DMP2) on the outside. The first encapsulating inorganic layer (IOL1) and the second insulating layer (20) can seal the organic layer between them.

[0092] A crack detection pattern (CRD) is disposed on the outside of the first insulating layer (10) and the second insulating layer (20). The crack detection pattern (CRD) may include a first layer containing the same material as the first insulating layer (10) and a second layer containing the same material as the second insulating layer (20). A crack detection pattern (CRD) containing inorganic material can detect cracks that occur and then expand at the edge of the display panel (DP).

[0093] A scan driving circuit (GDC) is placed between the voltage line (VL) and the display area (DP-DA). A transistor (TR-D) and a signal line (VL-int), which are components of the scan driving circuit (GDC), are illustrated as examples. The scan driving circuit (GDC) includes a plurality of stage circuits, each of which generates a scan signal, and the stage circuit includes a plurality of transistors. Figure 5b illustrates a single transistor (TR-D) as an example.

[0094] The transistor (TR-D) of the scan driving circuit (GDC) can be formed through the same process as the transistor (TR-P) of the pixel circuit. The transistor (TR-D) of the scan driving circuit (GDC) can have the same stacked structure as the transistor (TR-P) of the pixel circuit. The signal line (VL-int) can receive a clock signal or a bias voltage.

[0095] According to the present embodiment, an organic pattern (ORP) overlapping the surrounding area (DP-NDA) is disposed on a thin film encapsulation layer (TFE). Since the liquid organic material forming the encapsulation organic layer (OL) is provided uniformly within the display area (DP-DA), the encapsulation organic layer (OL) can provide a relatively flat upper surface within the display area (DP-DA). As the liquid organic material spreads outward, an inclined surface is naturally formed in the area adjacent to the first line pattern (DMP1). The liquid organic material hardens to form an encapsulation organic layer (OL) having an inclined surface. In other words, the thickness of the area of ​​the encapsulation organic layer (OL) adjacent to the display area (DP-DA) within the surrounding area (DP-NDA) is greater than the thickness of the area placed far from the display area (DP-DA).

[0096] Since the encapsulating organic layer (OL) is not placed on the outer side of the first line pattern (DMP1), a step (or curvature) is formed between the peripheral area (DP-NDA) and the display area (DP-DA). The organic pattern (ORP) eliminates the step formed between the peripheral area (DP-NDA) and the display area (DP-DA).

[0097] Referring to FIGS. 5a and 5b, the first signal line (SL1) can be superimposed on the line patterns (DMP1, DMP2). The organic pattern (ORP) provides a flat upper surface and can support the first signal line (SL1) in the area where the line patterns (DMP1, DMP2) are formed. FIG. 5b exemplarily illustrates a first signal line (SL1) comprising a first layer line (SL1-1) and a second layer line (SL1-2) connected by a contact hole (TH-O).

[0098] FIG. 5c is illustrated in a simplified manner compared to FIG. 5b, and the second encapsulation inorganic layer (IOL2) and the insulating layers (IS-IL1, IS-IL2, IS-IL3) of the input sensor (ISL) are not illustrated. Additionally, the first signal line (SL1) is illustrated as a single layer. The circuit element layer (DP-CL) and the display element layer (DP-OLED) are illustrated in a simplified manner.

[0099] Referring to FIGS. 5b and 5c, the organic pattern (ORP) may include a first part (ORP1) positioned outside the first line pattern (DMP1) and a second part (ORP2) positioned inside the first line pattern (DMP1) and overlapping with the encapsulated organic layer (OL). The part of the organic pattern (ORP) overlapping with the first line pattern (DMP1) may be defined as part of the first part (ORP1) or part of the second part (ORP2), and may be ignored as it has a relatively small area.

[0100] In this embodiment, the organic pattern (ORP) can come into contact with the second inorganic layer (IOL2). The organic pattern (ORP) can be formed immediately after the second inorganic layer (IOL2) is formed.

[0101] In a planar view, the first part (ORP1) has a larger area than the second part (ORP2). This is because the first part (ORP1) is placed in the area where the first signal line (SL1) is placed and the area where it is not, whereas the second part (ORP2) is placed centered on the area where the first signal line (SL1) is placed. Since the second part (ORP2) corresponds to a bridge supporting the first signal line (SL1), it is sufficient to secure the area supporting the first signal line (SL1).

[0102] By patterning the second part (ORP2) and making it discontinuous within the first direction (DR1), the tensile force exerted on the organic pattern (ORP) can be reduced even when tensile force is generated in the rolled state of the display module (DM), as illustrated in FIGS. 1a and 1b. Such an organic pattern (ORP) can be applied not only to a rollable display device but also to a foldable display device in which tensile force is generated.

[0103] Since the first part (ORP1) is placed in an area where the encapsulating organic layer (OL) is relatively thick compared to the first encapsulating inorganic layer (IOL1) and the second encapsulating inorganic layer (IOL2), the first part (ORP1) has a relatively larger thickness than the second part (ORP2). The thicknesses of the first part (ORP1) and the second part (ORP2) can be compared as average values.

[0104] An organic pattern (ORP) is placed between the surrounding area (DP-NDA) and the display area (DP-DA) to prevent a height difference from occurring in the layer where the first signal line (SL1) is placed. Due to the organic pattern (ORP), the first signal line (SL1) can be extended parallel to the sensing electrode from the sensing electrode (the sensing portion (SP1) in FIG. 5c). As a result, the gap between the second electrode (CE) and the first signal line (SL1) does not narrow even in the sloped area of ​​the encapsulated organic layer (OL). The coupling between the second electrode (CE) and the first signal line (SL1) can be maintained constant regardless of the shape of the encapsulated organic layer (OL).

[0105] The organic pattern (ORP) includes a negative-type photosensitive organic material, and its shape and thickness can be controlled according to the result of masking. A portion of the sufficiently exposed organic layer exists as a first portion (ORP1), and a portion of the organic layer whose exposure amount is controlled by the slit area of ​​the halftone mask exists as a second portion (ORP2). A portion of the unexposed organic layer is removed. A positive-type photosensitive organic material can be exposed in a manner opposite to that of a negative-type photosensitive organic material to form an organic pattern.

[0106] The first signal line (SL1) may include a first line portion (SL10) extended in a first direction (DR1) and a second line portion (SL20) extended from the first line portion (SL10) in a second direction (DR2). The first line portion (SL10) may be supported by a first portion (ORP1), and the second line portion (SL20) may be supported by a second portion (ORP2). Since the second portion (ORP2) has a smaller thickness compared to the first line portion (SL10), it can provide a substantially flat support surface with the first portion (ORP1) even when overlapping with the encapsulated organic layer (OL).

[0107] The first line portion (SL10) is positioned on the outside of the encapsulated organic layer (OL). The first signal line (SL1) shown in FIG. 5b corresponds to the position of the first line portion (SL10). The first line portion (SL10) may not overlap with the second electrode (CE). The coupling between the second electrode (CE) and the first signal line (SL1) may be reduced.

[0108] Referring to FIG. 5d, the first insulating layer (IS-IL1) of the input sensor (ISL) may have a multilayer structure. The first insulating layer (IS-IL1) may include a first inorganic layer (IS-IL11) and a second inorganic layer (IS-IL12) on the first inorganic layer (IS-IL11). Each of the first inorganic layer (IS-IL11) and the second inorganic layer (IS-IL12) may include at least one of silicon oxide, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, titanium oxide, and hafnium oxide. An organic pattern (ORP) may be disposed between the first inorganic layer (IS-IL11) and the second inorganic layer (IS-IL12).

[0109] Although not separately illustrated, in one embodiment of the present invention, an organic pattern (ORP) is positioned below the line (SL1-1) of the first layer in FIG. 5b, and the organic pattern (ORP) may contact the line (SL1-1) of the first layer and support the line (SL1-1) of the first layer. At this time, the stacked structure of the first insulating layer (IS-IL1) may be single layer or multi-layer.

[0111] FIGS. 6a to 6c are partial perspective views of an organic pattern (ORP) according to an embodiment of the present invention. Hereinafter, a detailed description of the same configuration as described with reference to FIGS. 5a to 5d is omitted.

[0112] Referring to FIGS. 6a through 6c, the first portion (ORP1) may include curved surface patterns (CSP) arranged along the first direction (DR1). Each of the curved surface patterns may provide a convex curve. The curved surface patterns can reduce the tensile force exerted on the organic pattern (ORP) even when tensile force is applied while the display module (DM) is rolled, as illustrated in FIGS. 1a and 1b. These curved surface patterns (CSP) can be applied not only to rollable displays but also to foldable displays where tensile force is applied.

[0113] As illustrated in FIG. 6a, the curved surface pattern (CSP) can provide a curved surface of a semi-cylindrical shape. The organic pattern (ORP) illustrated in FIG. 6a may be described as having defined valley regions (VA). Although one valley region (VA) is illustrated exemplarily in FIG. 6a, multiple valley regions (VA) may be arranged along a first direction (DR1). The valley region (VA) extends into a second direction (DR2) that intersects the first direction (DR1).

[0114] As illustrated in FIG. 6b, the curved surface pattern (CSP) can provide a curved surface in the shape of a half sphere. As illustrated in FIG. 6c, the second part (ORP2) can provide a convex curved surface instead of a flat surface. The second part (ORP2) can have a half cone shape.

[0115] As illustrated in FIGS. 6a to 6c, the organic pattern (ORP) may include a dye or a pigment. An organic pattern (ORP) having a predetermined color can prevent a structure placed below the organic pattern (ORP) from being visible to the outside.

[0117] FIG. 7a is a plan view of a display panel (DP) according to an embodiment of the present invention. FIG. 7b is an enlarged plan view of a part (AA) of FIG. 7a. FIG. 7c is a cross-sectional view corresponding to III-III' of FIG. 7b. FIG. 7d is a partial perspective view showing an organic pattern (ORP) and a signal line (SL1). FIG. 7e to 7g are plan views showing a part of an input sensor (ISL) superimposed on a part (AA) of the display panel (DP) shown in FIG. 7b.

[0118] Referring to FIG. 7a, the scan driving circuit (GDC) is placed overlapping the display area (DP-DA). Accordingly, the area for the scan driving circuit (GDC) in the peripheral area (DP-NDA) is unnecessary, and the area of ​​the peripheral area (DP-NDA) can be reduced.

[0119] Referring to FIG. 7b, the display area (DP-DA) includes a first display area (AA1), a second display area (AA2) outside the first display area (AA1), and a third display area (AA3) outside the second display area (AA2). A peripheral area (DP-NDA) is positioned outside the third display area (AA3).

[0120] A first pixel (PX1) is placed in a first display area (AA1), and a second pixel (PX2) is placed in a second display area (AA2). A third pixel (PX3) is placed in the second display area (AA2) and the third display area (AA3). Each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be provided in multiple numbers. Each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include a red pixel, a green pixel, and a blue pixel, and may further include a white pixel.

[0121] The first pixel (PX1) includes a first light-emitting element (OLED1) placed in the first display area (AA1) and a first pixel circuit (PC1) electrically connected to the first light-emitting element (OLED1) and placed in the first display area (AA1). The second pixel (PX2) includes a second light-emitting element (OLED2) placed in the second display area (AA2) and a second pixel circuit (PC2) electrically connected to the second light-emitting element (OLED2) and placed in the second display area (AA2). The third pixel (PX3) includes a third light-emitting element (OLED3) placed in the third display area (AA3) and a third pixel circuit (PC3) electrically connected to the third light-emitting element (OLED3) and placed in the second display area (AA2).

[0122] Each of the first light-emitting element (OLED1), the second light-emitting element (OLED2), and the third light-emitting element (OLED3) may be identical to the light-emitting element (OLED) shown in FIG. 3, and each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include the transistor (TR-P) shown in FIG. 3. In FIG. 7b, a first electrode (AE) having a substantially rhombus shape is exemplarily illustrated to represent the first light-emitting element (OLED1), the second light-emitting element (OLED2), and the third light-emitting element (OLED3).

[0123] A scan driving circuit (GDC) formed through the same process as the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) is disposed in the third display area (AA3). Accordingly, the third pixel circuit (PC3) cannot be disposed in the third display area (AA3), and the third pixel circuit (PC3) is disposed in the second display area (AA2).

[0124] Since the second pixel circuit (PC2) and the third pixel circuit (PC3) must be placed in the second display area (AA2), the second display area (AA2) has a lower resolution compared to the first display area (AA1). In other words, the second display area (AA2) has fewer pixels placed within a reference area than the first display area (AA1). The third display area (AA3) also has a lower resolution than the first display area (AA1). The resolutions of the second display area (AA2) and the third display area (AA3) can be substantially the same.

[0125] In order to prevent a decrease in brightness due to low resolution in the second display area (AA2) and the third display area (AA3), the second light-emitting element (OLED2) and the third light-emitting element (OLED3) have a relatively large light-emitting area. When the first color light-emitting area of ​​the second light-emitting element (OLED2) and the third light-emitting element (OLED3), e.g., a red light-emitting area, a green light-emitting area, or a blue light-emitting area, has a first area, the first color light-emitting area of ​​the first light-emitting element (OLED1) may have a second area that is smaller than the first area.

[0126] Since the first electrode (AE) of the third light-emitting element (OLED3) is positioned at a location spaced apart from the third pixel circuit (PC3), that is, at a location overlapping the scan driving circuit (GDC), the third pixel (PX3) may further include a connecting wire (TWL) for connecting the third light-emitting element (OLED3) and the third pixel circuit (PC3). The connecting wire (TWL) electrically connects the third light-emitting element (OLED3) placed in the third display area (AA3) and the third pixel circuit (PC3) placed in the second display area (AA2). The connecting wire (TWL) may include various materials such as metal, transparent conductive oxide, and conductive polymer, and is not limited to any one of them.

[0127] Referring to FIG. 7c, a first light-emitting element (OLED1), a second light-emitting element (OLED2), and a third light-emitting element (OLED3) are illustrated as examples. The connection relationship between the third light-emitting element (OLED3) and the transistor (TR-P3) of the third circuit (PC3) is illustrated as examples. A first connection electrode (CNE10) may be connected to the source or drain of the transistor (TR-P3) of the third circuit (PC3), a second connection electrode (CNE20) may be connected to the first connection electrode (CNE10), and a connection wire (TWL) may be connected to the second connection electrode (CNE20). The first electrode of the first light-emitting element (OLED1) may be connected to the connection wire (TWL). The third light-emitting element (OLED3) may be superimposed on the transistor (TR-D) of the scan driving circuit (GDC).

[0128] Referring to FIGS. 7c and 7d, a portion of the encapsulation organic layer (OL) overlapping the third display area (AA3) may provide an inclined surface. A second portion (ORP2) of the organic pattern (ORP) may overlap the surrounding area (DP-NDA) and the third display area (AA3). Referring to FIG. 7d, the second portion (ORP2) of the organic pattern (ORP) may be placed in the area between the third light-emitting elements (OLED3) spaced apart within the first direction (DR1). By not overlapping the third light-emitting elements (OLED3), the second portion (ORP2) of the organic pattern (ORP) may reduce interference with the source light generated from the third light-emitting elements (OLED3).

[0129] Referring to FIG. 7e, the second line portion (SL20) may be placed in the area between the third light-emitting elements (OLED3) spaced apart within the first direction (DR1). Additionally, the second line portion (SL20) may be placed in the area between the second light-emitting elements (OLED2) spaced apart within the first direction (DR1). By not overlapping the third light-emitting elements (OLED3) and the second light-emitting elements (OLED2), the second line portion (SL20) can reduce interference with the source light generated from the third light-emitting elements (OLED3) and the second light-emitting elements (OLED2).

[0130] Referring to FIG. 7e, the sensing portion (SP1) may overlap with the first display area (AA1). In the sensing portion (SP1), a plurality of first openings (MH1) corresponding to the first light-emitting elements (OLED1) are defined. Each of the plurality of first openings (MH1) may have an area larger than the opening (OP, see FIG. 3) corresponding to the first light-emitting element (OLED1). The sensing portion (SP1) may include conductive lines extending in a first diagonal direction (CDR1) and a second diagonal direction (CDR2) that intersect the first direction (DR1) and the second direction (DR2).

[0131] Referring to FIG. 7f, the sensing portion (SP1) may further overlap with the second display area (AA1). In the sensing portion (SP1), a plurality of second openings (MH2) corresponding to the second light-emitting elements (OLED2) are defined. Each of the plurality of second openings (MH2) may have a larger area than the opening (OP, see FIG. 3) corresponding to the second light-emitting element (OLED2). The second opening (MH2) may have a larger area than the first opening (MH1).

[0132] Referring to FIG. 7g, the sensing portion (SP1) may further overlap with the third display area (AA3). In the sensing portion (SP1), a plurality of third openings (MH3) corresponding to the third light-emitting elements (OLED3) are defined. Each of the plurality of third openings (MH3) may have an area larger than the opening (OP, see FIG. 3) corresponding to the third light-emitting element (OLED3). The third opening (MH3) may have substantially the same area as the third opening (MH3).

[0134] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0135] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0136] Display panel DP Display area DP-DA Surrounding Area DP-NDA Sensing electrode E1 Signal line SL1 Organic Pattern ORP Pixel PX 1st Line Pattern DMP1 1st bag inorganic layer IOL1 Bag organic layer OL 2nd bag inorganic layer IOL2 Part 1 of the organic pattern ORP1 Part 2 of the organic pattern ORP2 2nd Line Pattern DMP2 Line 1 section SL10 Line 2 section SL20 Curved patterns CSP Valley Areas VA 1st Weapon Layer IS-IL11 2nd Weapon Layer IS-IL12 Line SL1-1 on the 1st floor Line SL1-2 on the 2nd floor First display area, second display area, third display area AA1, AA2, AA3 Pixel 1, Pixel 2, Pixel 3 PX1, PX2, PX3 1st pixel circuit, 2nd pixel circuit, 3rd pixel circuit PC1, PC2, PC3 1st to 3rd light-emitting elements OLED1 to OLED3 Scan driving circuit GDC

Claims

Claim 1 A display panel comprising a display area and a peripheral area disposed outside the display area; a sensing electrode disposed on the display panel and superimposing the display area; a signal line disposed on the display panel, superimposing the peripheral area and connected to the sensing electrode; and an organic pattern disposed on the display panel and superimposing the signal line, wherein the display panel comprises: a pixel superimposing the display area; a first line pattern superimposing the peripheral area; a first encapsulating inorganic layer disposed on the display area and the peripheral area and superimposing the first line pattern and the pixel; an encapsulating organic layer disposed on the first encapsulating inorganic layer and disposed inside the first line pattern; and a second encapsulating inorganic layer disposed on the encapsulating organic layer, superimposing the display area and the peripheral area, and contacting the first encapsulating inorganic layer within the peripheral area, wherein the organic pattern comprises, on a plane, a first portion disposed outside the first line pattern; A display device comprising a first line pattern and a second portion disposed inside the first line pattern and overlapping the encapsulated organic layer, wherein the first line pattern extends in a first direction, and the signal line includes a first line portion extending in the first direction and a second line portion extending from the first line portion and intersecting the first direction, and the second line portion overlapping the second portion. Claim 2 A display device according to claim 1, wherein the area of ​​the second part on a plane is smaller than the area of ​​the first part. Claim 3 A display device according to claim 1, wherein the average thickness of the first part is greater than the average thickness of the second part. Claim 4 A display device according to claim 1, wherein the display panel further comprises a second line pattern disposed outside the first line pattern on a flat surface. Claim 5 A display device according to claim 1, wherein the thickness of the region adjacent to the display region of the bagged organic layer within the surrounding region is greater than the thickness of the region far from the display region of the bagged organic layer. Claim 6 delete Claim 7 In claim 1, the first line portion on the plane is a display device disposed on the outer side of the bag organic layer. Claim 8 A display device according to claim 1, wherein the first line pattern extends in a first direction, the first portion extends in the first direction, and the first portion is arranged along the first direction and each comprises a plurality of curved surface patterns that provide a convex curved surface. Claim 9 In claim 8, the second part is provided in plurality, and the plurality of second parts are spaced apart and arranged within the first direction. Claim 10 A display device according to claim 1, wherein the first line pattern extends in a first direction, the first part extends in the first direction, and the first part has a plurality of valley regions defined therein that are spaced apart along the first direction and each extends in a second direction that intersects the first direction. Claim 11 In claim 1, the organic pattern is a display device further comprising a dye or pigment. Claim 12 In claim 1, the organic pattern is a display device in contact with the second encapsulated inorganic layer. Claim 13 In claim 1, the device further comprises a first inorganic layer disposed on the second encapsulated inorganic layer; and a second inorganic layer disposed on the first inorganic layer, wherein the organic pattern is a display device disposed between the first inorganic layer and the second inorganic layer. Claim 14 A display device according to claim 1, further comprising: a first inorganic layer disposed on the second encapsulated inorganic layer; and a second inorganic layer disposed on the first inorganic layer, wherein the signal line comprises a line of the first layer disposed between the first inorganic layer and the second inorganic layer, and a line of the second layer disposed on the second inorganic layer and connected to the line of the first layer through a contact hole penetrating the second inorganic layer. Claim 15 A display device according to claim 1, wherein the display area comprises a first display area, a second display area disposed outside the first display area on a plane, and a third display area disposed outside the second display area, and the pixel comprises: a first pixel comprising a first light-emitting element disposed in the first display area and a first pixel circuit electrically connected to the first light-emitting element and disposed in the first display area; a second pixel comprising a second light-emitting element disposed in the second display area and a second pixel circuit electrically connected to the second light-emitting element and disposed in the second display area; and a third pixel comprising a third light-emitting element disposed in the third display area and a third pixel circuit electrically connected to the third light-emitting element and disposed in the second display area. Claim 16 In claim 15, the display panel further comprises a scan driving circuit that provides a scan signal to the first pixel, the second pixel, and the third pixel, the scan driving circuit is superimposed on the third display area, and the third light-emitting element is superimposed on the scan driving circuit. Claim 17 A display device according to claim 15, wherein the first line pattern extends in a first direction, the third light-emitting element is provided in plurality, and the second portion is disposed between two adjacent third light-emitting elements spaced apart within the first direction among the plurality of third light-emitting elements. Claim 18 In claim 15, a display device in which the resolution of the first display area is greater than the resolution of the second display area or the resolution of the third display area. Claim 19 In claim 18, a display device in which the light-emitting area of ​​the first color of the second light-emitting element is larger than the light-emitting area of ​​the first color of the first light-emitting element. Claim 20 A display panel comprising a display area and a peripheral area disposed outside the display area; a sensing electrode disposed on the display panel and overlapping the display area; a signal line disposed on the display panel, overlapping the peripheral area and connected to the sensing electrode; and an organic pattern disposed on the display panel and supporting the signal line, wherein the display panel comprises: a light-emitting element overlapping the display area; a first line pattern overlapping at least partially over the peripheral area; a first encapsulation inorganic layer disposed on the display area and the peripheral area and overlapping the light-emitting element; an encapsulation organic layer disposed on the first encapsulation inorganic layer and providing an inclined surface; and a second encapsulation inorganic layer disposed on the encapsulation organic layer and in contact with the first encapsulation inorganic layer within the peripheral area, wherein the organic pattern comprises a first portion that does not overlap the encapsulation organic layer; A display device comprising a second portion that overlaps the inclined surface of the above-mentioned bag organic layer, wherein the first line pattern extends in a first direction, and the signal line includes a first line portion extended in the first direction and a second line portion extended from the first line portion and intersecting the first direction, and the second line portion overlaps the second portion.

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