An energy-efficient neural rendering computing-in-memory processor for mobile device

Abstract

An energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention comprises: a plurality of PIM-based renderers designed to reduce memory access, a PIM group composed of a plurality of PIM cores (PIMC) that store embeddings of a predetermined size decomposed by axis in the PIM (Processing-In-Memory) and output rendering results per sample; a global memory that stores and manages a plurality of block embeddings of a predetermined size constituting the 3D space; a pre / post processor unit that derives sample coordinates and performs volume rendering; an upper-level RISC controller that controls access to the global memory (GMEM); and a ray-unit dynamic block reuse (RDBR) and a dynamic block allocator that manages it; thereby having the effect of reducing energy consumption caused by large-scale memory access.

Description

Technology Field

[0001] The present invention relates to an energy-efficient neural rendering in-memory computing processor for a mobile device, comprising a quantization algorithm that supports energy-efficient rendering operations in a mobile device and can reduce memory access energy, and a processor that supports this algorithm and further reduces memory access energy by utilizing the locality of input data during rendering. Background Technology

[0003] With the growth of the metaverse, the demand to realistically render 3D scenes on mobile devices has increased rapidly. Existing ray tracing methods had limitations, requiring a lot of manual work and taking a long time.

[0004] Recently, Neural Radiance Field (NeRF) has emerged as a promising solution that enables 3D scene modeling and convenient rendering. To render with NeRF, prior modeling of an object is required. Modeling is performed using photographs of the object taken from various angles and the coordinates of the camera used during shooting.

[0005] NeRF repeats four main steps to render 3D objects and generate a 2D image view. First, a single ray is projected from the camera onto each pixel of the 2D image to be rendered. Second, samples are extracted along each ray path to calculate the spatial coordinate values ​​of each sample. Third, Density and Color Mapping (DCM) is performed on each sample. At this stage, density and color values ​​for any sample can be obtained by performing interpolation on the density and color embeddings obtained by decomposing the 3D space during the prior modeling phase. Finally, the final rendered image is completed by taking a weighted sum of the final color values ​​of each pixel using the density and color of each sample.

[0006] There are several technical challenges that need to be addressed to realize the above-mentioned NeRF-based 3D scene rendering in a mobile environment. In particular, large-scale memory access occurring during the DCM process is pointed out as a problem. DCM decomposes 3D space into x, y, and z axes to store 1D embedding vectors for each axis, and estimates the density and color values ​​of a sample by performing interpolation and aggregation based on the sample's spatial coordinates using these vectors. The total capacity of the embedding vectors used in this process reaches approximately 180 KB, which causes a significant amount of energy to be consumed through memory access.

[0007] In particular, interpolation operations account for more than 89% of the energy in the entire rendering process, and 74.6% of that is attributable to memory access. This is because memory access occurs frequently due to the low data reusability during the sampling process.

[0008] To implement energy-efficient rendering using NeRF on mobile devices, it is essential to reduce energy consumption caused by such memory access. When rendering at 30fps on current GPU platforms, more than 10W of power is consumed; this leads to excessive consumption on mobile devices with limited battery capacity, which constrains the practical implementation of NeRF.

[0009] Existing technologies have proposed various approaches to optimize memory access, but they are primarily designed for fixed hardware, which presents a problem in that they are difficult to apply to the dynamic conditions of mobile environments. Prior art literature

[0010] Korean Patent Publication No. 10-2749978 (December 30, 2024) The problem to be solved

[0011] To overcome the aforementioned limitations and solve the problem, the present invention aims to provide an energy-efficient neural rendering memory-in-computing processor for a mobile device that uses an explicit NeRF method, which is the lightest possible for use in a mobile device, to decompose the 3D space where an object exists into multiple pairs of vector embeddings, thereby enabling subsequent rendering of the object with a small amount of memory, and to restore density and color values ​​for arbitrary spatial coordinates during rendering by decomposing the 3D space into embeddings corresponding to density and color, respectively.

[0012] In addition, to overcome the aforementioned limitations and solve the problem, the present invention aims to provide an energy-efficient neural rendering memory-in-computing processor for mobile devices that minimizes battery consumption and enables real-time 3D scene rendering in mobile devices by reducing large-scale memory access occurring during the DCM process of neural radiative fields.

[0013] Furthermore, in order to overcome the aforementioned limitations and solve the problem, the present invention aims to provide an energy-efficient neural rendering in-memory computing processor for mobile devices that can efficiently reduce energy consumption by devising a method to reuse data during the DCM process of a neural radioactive field and applying optimization techniques to reduce the number of memory accesses.

[0014] Furthermore, to overcome the aforementioned limitations and solve the problems, the present invention aims to provide an energy-efficient neural rendering memory-in-memory computing processor for mobile devices that can improve the overall system throughput and increase energy efficiency by reducing the number of global memory accesses through block-unit mapping of spatial encoding to solve the large-scale memory access problem occurring in the rendering method, thereby reducing overall rendering energy, and, unlike existing methods that required individual memory access for every sample during the rendering process, applying a ray-unit Dynamic Block Reuse (DBR) method to maximize the opportunity to reuse data within the same block, and enhancing the data reusability of Processing-In-Memory (PIM) through the Dynamic Block Reuse method. means of solving the problem

[0016] To achieve the above-mentioned objective, the energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by comprising: a PIM group composed of a plurality of PIM cores (PIMCs) that are configured to reduce memory access, store embeddings of a predetermined size decomposed by axis in the PIM (Processing-In-Memory), and output rendering results per sample; a global memory that stores and manages a plurality of block embeddings of a predetermined size constituting the 3D space; a pre / post processor unit that derives sample coordinates and performs volume rendering; an upper RISC controller that controls access to the global memory (GMEM); and a ray-unit dynamic block reuse (RDBR) and a dynamic block allocator that manages the same.

[0017] To achieve the above-mentioned objective, the PIM-based renderer of an energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by performing axis-wise interpolation operations with a single memory access and processing weights through bitwise complement quantization (BCQ).

[0018] To achieve the above-mentioned objective, the PIM-based renderer of an energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by maintaining the loss of accuracy within a predetermined range through bit-unit complementary quantization, which converts 16-bit coordinate values ​​used as interpolation weights into 2-bit bit-unit complementary quantized weights.

[0019] To achieve the above-mentioned objective, the PIM-based renderer of an energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by performing in-memory interpolation operations with only a single memory access to reduce precharge energy, thereby reducing memory access energy and rendering energy per sample.

[0020] To achieve the above-mentioned objective, the pre- and post-processing unit of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention is characterized by reducing energy consumption through Space Encoding Block-wise Mapping (SEBM), which configures the 3D space into a plurality of blocks of a predetermined size, loads the entire block embedding from the Global Memory (GMEM) and assigns it to a single PIM group, and allows the embedding to be reused by samples occupying the space once it is loaded.

[0021] To achieve the above-mentioned purpose, the spatial encoding block unit mapping of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention is characterized by transmitting each block to a PIM core (PIMC) during the block mapping process and managing the processing order of sample data by utilizing a Ray ID FIFO.

[0022] To achieve the above-mentioned objective, a dynamic block allocator (DBA) of an energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by analyzing the required blocks to identify a new block ID (NBID) required in the next patch and a block ID (UBID) that will not be reused in the current patch.

[0023] To achieve the above-mentioned objective, the dynamic block allocator (DBA) of an energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by transmitting samples to the corresponding PIM group without changing the block allocation map in the case of a block ID to be reused in the current patch, and overwriting the embedding of the block ID to be reused (UBID) with the embedding of the block ID to be reused (UBID) in the case of a block ID not to be reused (UBID).

[0024] To achieve the above-mentioned objective, the dynamic block allocator (DBA) of an energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention is characterized by increasing throughput by preloading the next patch to fill an idle PIM group. Effects of the invention

[0026] The energy-efficient in-memory computing processor for a mobile device according to the present invention divides 3D spatial data into blocks and maximizes data reusability by utilizing spatial locality, thereby having the effect of reducing energy consumption caused by large-scale memory access.

[0027] In addition, the energy-efficient neural rendering memory-in-computer processor for a mobile device according to the present invention utilizes bitwise complement quantization to reduce memory access energy during interpolation operations, and has the effect of performing efficient operations with only a single memory access through an 8T SRAM-PIM structure.

[0028] In addition, the energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention includes a structure that efficiently manages sample data and increases throughput through a ray-unit dynamic block reuse method, thereby reducing energy consumption and improving throughput, which has the effect of enabling real-time 3D neural rendering in a mobile environment.

[0029] As a result, the energy-efficient neural rendering in-memory computing processor for a mobile device according to the present invention has the effect of effectively minimizing large-scale memory access energy by effectively utilizing the spatial locality of samples in neural rendering through a 3D mobile neural radiative field (NeRF) PIM processor. Brief explanation of the drawing

[0031] FIG. 1 is a diagram illustrating that the problem to be solved by an energy-efficient neural rendering memory-in-computation processor for a mobile device according to the present invention is an internal memory access problem related to data density / color mapping. FIG. 2 is a diagram illustrating the overall architecture of an energy-efficient in-memory computing processor for a mobile device according to the present invention. Figure 3 is a diagram illustrating a method to reduce the energy consumption of a DCM through the PBR structure of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention. FIG. 4 is a diagram illustrating the spatial encoding block unit mapping of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention. FIG. 5 is a diagram illustrating the ray-unit dynamic block reuse of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention. FIG. 6 is a diagram illustrating the actual chip and performance of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention. Specific details for implementing the invention

[0032] Terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, and should be interpreted in a meaning and concept consistent with the technical spirit of the invention, based on the principle that the inventor can appropriately define the concept of the terms to best describe his invention.

[0033] Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely one preferred embodiment of the present invention and do not represent all of the technical ideas of the present invention; thus, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0034] An energy-efficient in-memory computing processor for a mobile device according to the present invention will be described in more detail below with reference to the attached drawings.

[0035] First, the processing of the Neural Radiance Field (NeRF) is briefly explained with reference to Fig. 1.

[0036] The processing of the above Neural Radiance Field (NeRF) is carried out in such a way that the accelerator processor generates and samples rays on a pixel-by-pixel basis, the accelerator preprocessor calculates and maps 3D coordinates based on the sample location, the accelerator computation core calculates the density and color of the sample, and the accelerator postprocessor generates the final image through volume rendering.

[0037] The present invention aims to overcome the problem of excessive energy consumption for internal memory access related to data density / color mapping during the processing of the Neural Radiance Field (NeRF) described above through an energy-efficient neural rendering memory-in-computing processor for a mobile device.

[0039] FIG. 2 is a structural diagram of an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention.

[0040] As illustrated in FIG. 2a, an energy-efficient neural rendering memory-in-computing processor for a mobile device according to the present invention comprises a plurality of PIM groups (PIMG<Processing-In-Memory Group> It includes :100), 256KB global memory (200), a pre / post processor unit (Pre / Post Processor Unit:300) that derives sample coordinates and performs volume rendering, a top RISC controller (Top RISC Controller:400), and a dynamic block allocator (Dynamic Block Allocator:500).

[0041] The above PIM group (PIMG)<Processing-In-Memory Group> :100) consists of a PIM core (PIMC:110) that stores and processes embeddings decomposed by axis and peripheral logic, and the entire system is designed for efficient data flow and energy saving.

[0042] The above PIM group (PIMG)<rocessing-In-Memory Group> :100) consists of three PIM cores (PIMC:110), 3KB of input / output memory (120), and a Ray ID FIFO (130) for identifying the order of queried samples, as shown in FIG. 2b.

[0043] The above PIM core (110) stores embeddings of size 32, decomposed by axes (x, y, z) as shown in FIG. 2c, in an 8T SRAM-based PIM, and is composed of a plurality of PIM-based renderers (111) including aggregation circuits including peripheral logic to output rendering results per sample.

[0044] Referring to FIG. 3, the structure and operation of the PIM-based renderer (111) for reducing memory access energy will be explained.

[0045] Figure 3 illustrates in detail how data is mapped and operations are performed within memory, thereby reducing pre-charge energy by 25% compared to conventional methods and demonstrating high energy efficiency and throughput.

[0046] The above PIM-based renderer (111) utilizes an 8T SRAM-PIM structure to perform axis-wise interpolation operations with a single memory access and efficiently processes weights through bitwise complement quantization (BCQ).

[0047] That is, the PIM-based renderer (111) utilizes bitwise complement quantization (BCQ) and an 8T SRAM-PIM structure to reduce energy consumption of density and color mapping (DCM).

[0048] The above PIM-based renderer (111) takes two embeddings to perform interpolation operations and performs a weighted sum of them.

[0049] The above PIM-based renderer (111) minimizes the energy of memory-intensive interpolation operations through two-stage optimization using PIM.

[0050] First, the PIM-based renderer (111) reduces energy consumption while maintaining accuracy loss within 0.6dB through bit-unit complementary quantization, which converts 16-bit coordinate values ​​used as interpolation weights into 2-bit bit-unit complementary quantized weights.

[0051] Second, the above PIM-based renderer (111) utilizes the characteristics of bit-level complementary quantization (BCQ) with an 8T SRAM-PIM structure to perform in-memory interpolation operations with only a single memory access.

[0052] At this time, in the above 8T SRAM-PIM structure, the embeddings to be interpolated are placed in the same column.

[0053] As shown in FIG. 3, each cell of the above 8T SRAM-PIM structure is configured in a form in which a computing word line (CWL), a computing bit line (CBL), and two PMOS transistors are added to the existing 6T structure.

[0054] When the above PIM-based renderer (111) performs interpolation, it precharges only the bitline (BL), and the most significant bit (MSB) and least significant bit (LSB) of the weight are supplied to the computing wordline (CWL) and wordline (WL), respectively. Since the computing wordline (CWL) and wordline (WL) of adjacent rows are activated complementarily, 2-bit quantized weights are calculated simultaneously, and the multiplication result is reflected in the computing bitline (CBL) and bitline (BL).

[0055] This allows interpolation operations to be performed with only a single memory access, thereby reducing precharge energy by 25%. The above PIM-based renderer (PBR:111) reduces memory access energy by 49.5% and rendering energy per sample by 59.9%.

[0056] In addition, the PIM core (PIMC:110) reduces overall rendering energy through block-wise processing of a Space Encoding Block-wise Mapping (SEBM) structure as shown in FIG. 4. The motivation for the SEBM is derived from the spatial locality of the samples.

[0057] Since adjacent rays are projected into a continuous space, samples are clustered intensively in a specific space. To utilize this characteristic, the Space Encoding Block-wise Mapping (SEBM) organizes the 3D space into multiple blocks of size 32×32×32, as illustrated in FIG. 4a. Instead of repeatedly moving a single embedding, the SEBM loads the entire block of embeddings from the global memory (GMEM:200) and assigns them to a single PIM group (100). Once the embeddings are loaded, they can be reused by the samples occupying that space.

[0058] That is, the SEBM significantly reduces energy consumption by dividing the 3D space into blocks of size 32×32×32 and assigning the embedding data of each block to the PIM group (100).

[0059] The SEBM transmits each block to the PIM core (PIMC:110) during the block mapping process and efficiently manages the processing order of sample data by utilizing components such as the Ray ID FIFO (130). The SEBM significantly reduces the number of global memory (GMEM:200) accesses, thereby inducing the effect of reducing overall rendering energy.

[0060] The operation flow of the SEBM above is explained with reference to Fig. 4b.

[0061] The above pre- and post-processing unit (300) finds all samples in an 8×8 input ray patch and assigns a block ID according to the coordinates of the samples.

[0062] Samples sharing the same block ID must be calculated in the same PIM group (100) regardless of the projected ray.

[0063] The above pre- and post-processing unit (300) assigns samples to the Ray ID FIFO (130) of the above PIM group (100) to support sample relocation.

[0064] At this time, the PIM group (100) performs rendering per sample in a streaming manner.

[0065] The SEBM according to the present invention reduces the total rendering energy by 98.6% for global memory (GMEM:200) access and 67.8% for neural radiation field (NeRF) synthetic datasets.

[0066] Meanwhile, FIG. 5 shows a Ray-wise Dynamic Block Reuse (RDBR) structure proposed in the present invention and a dynamic block allocator (DBA:500) that manages it, wherein the RDBR utilizes block similarity between patches to further improve the reusability of embeddings within the PIM group (100).

[0067] RDBR: Reconfigurable Dynamic Block Replacement

[0068] RDBR: Ray-wise Dynamic Block Reuse

[0069] The above ray-unit dynamic block reuse (RDBR) increases energy efficiency by reusing block data through the use of block similarity between patches, and based on spatial locality, 75.6% of the blocks in the current ray patch can be reused in the next patch.

[0070] Thanks to spatial locality, 75.6% of the blocks in the current ray patch can be reused in the next patch. To properly manage block replacement, the above RDBR integrates the above dynamic block allocator (DBA:500) together with the block allocation map.

[0071] The above dynamic block allocator (DBA:500) analyzes the required blocks and determines (identifies) the new block IDs (NBID) required in the next patch and the block IDs (UBID) that will not be reused in the current patch.

[0072] For block IDs to be reused in the current patch, the dynamic block allocator (DBA:500) sends the sample to the corresponding PIM group (100) without changing the block allocation map.

[0073] On the other hand, for a block ID that will not be reused (UBID), the dynamic block allocator (DBA:500) overwrites the embedding of the block ID that will not be reused (UBID) with the embedding of the newly required block ID (NBID).

[0074] Additionally, the dynamic block allocator (DBA:500) preloads the next patch to fill the idle PIM group (100) and increase throughput.

[0075] That is, the dynamic block allocator (DBA:500) minimizes idle time of the PIM group (100) and increases throughput through a parallel bank access method.

[0076] The above RDBR reduces global memory (200) access by 97.8% and improves throughput by 4.4 times.

[0077] Figure 6 shows the chip design and benchmark results of an energy-efficient neural rendering memory-in-computation processor for a mobile device according to the present invention.

[0078] FIG. 6 clearly shows the arrangement of the eight above-mentioned PIM groups (100), global memory (200), pre- and post-processing unit (300), and upper RISC controller (400).

[0079] Each PIM group (100) is designed for independent and parallel processing of data and provides efficient energy consumption and high throughput.

[0080] It is manufactured using a 28nm CMOS process and occupies a die area of ​​5.1mm² (3.23mm x 1.57mm), including an on-chip SRAM (72KB PIM) of 360KB (including the on-chip SRAM-PIM, which is expressed as having 72KB PIM among the total 360KB SRAM memory). The processor operates at a maximum operating frequency of 200MHz with a supply voltage of 1.0V, supports 8-bit fixed-point data processing, consumes a total power of 129.8mW, and requires an average rendering energy of 6.6nJ per pixel.

[0082] Benchmark results on the Neural Radiance Field (NeRF) synthetic dataset shown in Fig. 6 show that a view rendered at an average speed of 30.7 FPS provides photorealistic results compared to the actual scene.

[0083] The measurement results show rendering performance on various datasets.

[0084] The pixel signal-to-noise ratio (PSNR) was 30.3 dB on the Lego dataset and 23.9 dB on the Materials dataset. Rendering speeds were 26.1 FPS on the Lego dataset and 28.1 FPS on the Chair dataset, demonstrating high frame rates. With an average energy consumption of 4.2 mJ / frame, real-time rendering was implemented, showing significantly lower energy efficiency compared to existing GPUs that consume excessive energy and are unsuitable for mobile devices.

[0085] The graph at the bottom right of the diagram summarizes that it demonstrates significantly superior performance in terms of energy and throughput compared to existing systems. On average, energy consumption per frame decreased by 93.5%, and throughput per frame increased 4.2 times compared to existing systems.

[0086] In conclusion, the present invention proposes a 3D mobile NeRF PIM processor that minimizes large-scale memory access energy in neural rendering by effectively utilizing the spatial locality of samples.

[0087] Although the technical concept of the present invention has been described above together with the accompanying drawings, this is merely an illustrative explanation of preferred embodiments of the present invention and is not intended to limit the invention. Furthermore, it is evident that anyone with ordinary knowledge in the technical field to which the present invention pertains can make various modifications and imitations within the scope of the technical concept of the present invention without departing from its scope. Explanation of the symbols

[0088] 100 : PIM Group (PIMG)<Processing-In-Memory Group> ) 110 : PIM Core (PIMC), 120: I / O memory 130 : Ray ID FIFO 200 : Global Memory 300 : Pre / Post Processor Unit 400 : Top RISC Controller 500 : Dynamic Block Allocator

Claims

Claim 1 An energy-efficient neural rendering in-memory computing processor for a mobile device, which generates and samples a 3D space in which a sample exists by generating rays in pixel units, maps 3D coordinates based on the sample location, calculates the density and color of the sample, and generates a final image through volume rendering, comprising: a PIM group composed of a plurality of PIM-based renderers designed to reduce memory access, which stores embeddings of a predetermined size decomposed by the axis of the 3D space in the PIM (Processing-In-Memory) and outputs rendering results per sample; a global memory that stores and manages a plurality of block embeddings of a predetermined size constituting the 3D space and selectively provides data to the PIM group; a pre / post-processor unit that derives sample coordinates and performs volume rendering; a high-level RISC controller that controls access to the global memory (GMEM); and a ray-unit dynamic block reuse (RDBR) and a dynamic block allocator that manages it; characterized by comprising: an energy-efficient neural rendering in-memory computing processor for a mobile device. Claim 2 An energy-efficient neural rendering in-memory computing processor for mobile devices, characterized in that, in claim 1, the PIM-based renderer performs axis-wise interpolation operations with a single memory access and processes weights through Bitwise Complement Quantization (BCQ). Claim 3 An energy-efficient neural rendering in-memory computing processor for a mobile device, wherein the PIM-based renderer maintains accuracy loss within a predetermined range through bit-unit complementary quantization that converts 16-bit coordinate values ​​used as interpolation weights into 2-bit bit-unit complementary quantized weights. Claim 4 An energy-efficient neural rendering in-memory computing processor for a mobile device, characterized in that, in claim 3, the PIM-based renderer performs in-memory interpolation operations with only a single memory access to reduce precharge energy, thereby reducing memory access energy and rendering energy per sample. Claim 5 An energy-efficient neural rendering memory-in-computing processor for a mobile device, characterized in that, in claim 1, the pre- and post-processing unit reduces energy consumption through Space Encoding Block-wise Mapping (SEBM), wherein the pre- and post-processing unit configures the 3D space into a plurality of blocks of a predetermined size, loads the entire block embedding from the Global Memory (GMEM) and assigns it to a single PIM group, and when the embedding is loaded, it can be reused by samples occupying the space. Claim 6 An energy-efficient neural rendering in-memory computing processor for a mobile device, characterized in that, in claim 5, the spatial encoding block unit mapping transmits each block to a PIM core (PIMC) during the block mapping process and manages the processing order of sample data using a Ray ID FIFO. Claim 7 An energy-efficient neural rendering in-memory computing processor for a mobile device, wherein, in claim 1, the dynamic block allocator (DBA) analyzes the required blocks to identify a new block ID (NBID) required in the next patch and a block ID (UBID) that will not be reused in the current patch. Claim 8 An energy-efficient neural rendering in-memory computing processor for a mobile device, characterized in that, in claim 7, the dynamic block allocator (DBA) transmits samples to the corresponding PIM group without changing the block allocation map in the case of a block ID to be reused in the current patch, and in the case of a block ID not to be reused (UBID), overwrites the embedding of the block ID not to be reused (UBID) with the embedding of the newly required block ID (NBID). Claim 9 An energy-efficient neural rendering in-memory computing processor for a mobile device, wherein, in claim 7, the dynamic block allocator (DBA) preloads the next patch to fill idle PIM groups to increase throughput.

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