Vertical stacked microdisplay panel and manufacturing method thereof

Abstract

The present invention relates to a vertically stacked microdisplay panel, comprising: a back wafer having a plurality of CMOS electrode pads aligned on its upper surface; a plurality of LED stacks each having at least one light-emitting part and each being aligned on the plurality of CMOS electrode pads; and a common electrode formed on the plurality of LED stacks. When the LED stacks include the plurality of light-emitting parts, the plurality of light-emitting parts are bonded through a bonding layer and stacked in a vertical direction. The LED stacks are characterized by emitting only a specific color when the plurality of light-emitting parts are bonded through the bonding layer, such that light generated from the lower light-emitting parts is blocked by the bonding layer. According to the present invention, a vertically stacked tandem structure can be formed by conventional metal bonding.

Description

Technology Field

[0001] The present invention relates to a vertically stacked microdisplay panel and a method for manufacturing the same, and more specifically, to a vertically stacked LEDoS microdisplay panel and a method for manufacturing the same in which an alignment process between an LED stack and a CMOS electrode pad is unnecessary by using an engineering monolithic epitaxy wafer method. Background Technology

[0002] The types of implementation for the recently trending Metaverse are classified into four forms: VR (virtual reality), AR (augmented reality), MR (mixed reality), and XR (extended reality). Among these, the future Metaverse ecosystem is expected to develop around XR, a reality that integrates VR, AR, and MR. To effectively implement this, devices (such as smart glasses and head-mounted displays) containing microdisplays with a diagonal length of less than one inch as core components are required, along with software for next-generation computing platforms capable of providing innovative user experiences. In particular, the development of high-performance microdisplay panel technology is absolutely necessary to provide XR users with the greatest sense of immersion, visibility, and convenience while minimizing dizziness.

[0003] As illustrated in FIG. 1, the conventional microdisplay panel (10) is a technology that combines a Si CMOS semiconductor wafer process with a high-resolution, high-brightness ultra-small display process. The conventional microdisplay panel (10) may have a structure in which a Si CMOS wafer (11) having a crystal plane of 4" or larger (100) equipped with a plurality of CMOS electrode pads (12), a microLED electrode pad (14), and a transparent wafer (13) having a plurality of microLED chips (15) are bonded through a conductive bond (16). Meanwhile, the types of microdisplay panels expected to be applied to XR devices include liquid crystal (LC) based LCoS (LC on Si), OLED (organic light-emitting diode) based OLEDoS (OLED on Si), and ultra-small microLED based LEDoS (LED on Si) having a pixel size of less than 5㎛. In the case of VR with a low pixel density display, development and mass production are centered on LCoS and OLEDoS.

[0004] However, with the advancement of metaverse implementation technology, there is an increasing need for lightweight AR, MR, and XR devices equipped with high pixel density microdisplay panels. In response to this need, there is an urgent need to develop LEDoS technology, which is attracting attention as a theoretically ideal solution based on the superiority of inorganic properties, but a microdisplay panel platform for this has not yet been established.

[0005] When applied to XR devices, microLED-based LEDoS with pixel sizes of less than 5㎛ offers the advantages of excellent power-to-performance ratio and short response speed. Additionally, it has a long lifespan due to its inorganic composition and allows for efficient power usage, which helps mitigate heat and enables long battery life. In particular, since XR devices have a very short distance between the display and the eyes, even a slight delay in image conversion can easily cause discomfort such as dizziness. Therefore, LEDoS, which has a nanosecond response speed, is considered the most suitable for XR devices compared to LCoS and OLEDoS, which have microsecond response speeds.

[0006] Furthermore, it is assessed that the biggest reason LEDoS is attracting attention in AR, MR, and XR devices, unlike VR, is due to its brightness and luminous efficiency. Given the nature of smart glasses that can be worn regardless of location, high brightness is an essential condition to ensure normal operation even in outdoor environments such as sunlight. Theoretically, microLEDs support brightness levels of tens to millions of nits, and since microLEDs are inorganic rather than organic, they also have the advantage of high luminous efficiency.

[0007] However, despite the aforementioned advantages, the biggest reason why ultra-small microLED-based LEDoS with pixel sizes of less than 5㎛ has not established itself as a key component of XR devices is the difficulty of mass production. In other words, since LEDoS requires fixing millions of ultra-small microLEDs onto a Si CMOS wafer, the process difficulty is high and the yield is very low, leading to increased manufacturing costs and high component prices. This is reflected in the end consumer price, resulting in high-priced XR devices, making it difficult to meet market demand.

[0008] Meanwhile, as illustrated in Fig. 2, the development of LEDoS with microLED light sources of group 3-5 compounds (GaN, GaP, etc.) has been carried out through traditional approaches such as ① monolithic integration of a wafer (or unit die) composed of a microLED array on a wafer, or ② hybridization between wafers (or unit dies) on a wafer or blue, green, or red light source wafer (or unit die) on which a microLED array is fabricated.

[0009] One of the biggest obstacles to the development of LEDoS using blue, green, and red microLED light sources composed of Group 3-5 compounds to date is the difficulty in securing solutions for pixels smaller than 5㎛. Recently, however, pixels at the 5㎛ level have been successfully demonstrated using monolithic integration technology, and some prototypes developed based on hybridization technology have achieved pixels at the 10㎛ level by fabricating them using sapphire flip chips. Additionally, it has been proven that it is possible to reduce pixels to the 5㎛ level in the same way by using microtube wiring in hybridization technology. However, both monolithic integration technology and hybridization technology are impractical solutions that face significant difficulties in mass production in terms of quality and yield, making mass production difficult.

[0010] The aforementioned monolithic integration technology and hybridization technology share a common characteristic in that a front plane wafer composed of a group 3-5 compound microLED array and a Si CMOS back plane wafer composed of numerous IC electrode pad arrays are designed and fabricated separately and then assembled. In either method, however, microLED arrays fabricated at the unit die-level or wafer-level on the Si CMOS wafer must be ultra-finely aligned. Consequently, this alignment is limited by the precision of process-related equipment, which has a significant impact on pixel and pixel pitch limitations, and makes mass production difficult. Accordingly, to manufacture LEDoS equipped with high-resolution, high-brightness, and high-speed driving blue, green, and red microLED light sources featuring pixels smaller than 5㎛ and pitches smaller than 3㎛, a new alternative solution is required to avoid the aforementioned ultra-fine alignment constraints.

[0011] Accordingly, although several impressive demonstrations with 6㎛ pixels have recently been released using engineering monolithic epitaxy wafers manufactured through a low-temperature metal bonding process between a Si CMOS wafer and a microLED array wafer, mass production is considered impossible due to low quality and yield issues caused by the low-temperature metal bonding and the use of small-diameter wafers of 6 inches or less. Above all, when fabricating ultra-fine pixels of less than 3㎛ for microdisplays using conventional engineering monolithic epitaxy wafers with metal bonding, even greater difficulties are faced during patterning etching.

[0012] As another example, a new engineering monolithic epitaxy wafer approach has recently been proposed that has achieved significant success in solving the problem of limiting the brightness and resolution of LEDoS using group 3-5 compound microLED light sources, while also providing mass production and low-cost manufacturing solutions through the use of 12-inch large-diameter Si CMOS wafers.

[0013] As illustrated in Fig. 3, specifically, the process using an engineering monolithic epitaxy wafer is carried out through the following four steps: ① First, using an LED epitaxy wafer, LED epitaxy cut to a predetermined size (e.g., 4 mm × 6 mm) is aligned and bonded at the unit die level onto a 12-inch large-diameter Si blanket wafer. Subsequently, the growth wafer and buffer layer of the LED epitaxy are removed and planarized, leaving only an LED active layer of a predetermined thickness (e.g., approximately 1.5 μm) on the large-diameter Si blanket wafer, thereby completing the LED fab process in the form of a pixel chip. ② Next, the Si blanket wafer with the completed pixel chip is bonded to a 12-inch CMOS IC Si wafer at the wafer level through multilayer metal bonding. ③ Next, the Si blanket wafer is removed. ④ Next, the residual process is finally performed on the CMOS IC Si wafer for the microLED array functioning as a pixel.

[0014] However, in step ①, when bonding the LED epitaxy unit die onto the Si blanket wafer, there is a limitation in that position alignment must be performed on a CMOS IC Si wafer of the same size to bond it, and in step ②, when bonding with a multilayer metal containing low-melting point metals (Sn, In), the ejection phenomenon of the low-melting point metal components overflowing occurs relatively easily, resulting in a short circuit defect that electrically connects between microLED subpixel arrays within the panel or with neighboring CMOS IC electrode pad arrays. Furthermore, in step ②, due to the optically opaque nature of the Si blanket wafer and the multilayer metal bonding layer, it is difficult to perform ultra-fine alignment wafer bonding between the Si blanket wafer (i.e., front plane wafer) and the CMOS IC Si wafer, which leads to defects. Here, ultra-fine alignment means aligning a microLED array, which is a plurality (hundreds to tens of millions) of ultra-small pixel chips provided on a Si blanket wafer, with a CMOS IC electrode pad array provided on a CMOS IC Si wafer in a 1:1 matching ratio.

[0015] In other words, the engineering monolithic epitaxy wafer approach presented in the aforementioned technologies is evaluated as providing a solution that brings us one step closer to realizing ultra-small microLED-based LEDoS with pixel sizes of less than 5㎛, but there are quality and yield issues caused by the use of metal (low temperature, multilayer) in wafer bonding, and it is very difficult to fabricate high-resolution microdisplays with ultra-fine pixels of less than 3㎛, and there are also problems related to some alignment processes, so a new alternative is needed.

[0016] In addition, in the vertically stacked tandem structure of conventional microdisplays, a color filter is still applied to achieve full color, so there are disadvantages in terms of color quality, process complexity, and productivity. Prior art literature

[0017] Republic of Korea Published Patent Application No. 10-2018-0009116 The problem to be solved

[0018] The objective of the present invention is to solve the aforementioned conventional problems by using an engineering monolithic epitaxy wafer method, thereby eliminating the need for an alignment process between the LED stack and the CMOS electrode pads, and simultaneously enabling general metal bonding, to provide a vertically stacked LEDoS microdisplay panel and a method for manufacturing the same. means of solving the problem

[0019] The above objective is achieved by a vertically stacked microdisplay panel according to the present invention, comprising: a back wafer having a plurality of CMOS electrode pads aligned on its upper surface; a plurality of LED stacks each having at least one light-emitting part and each being aligned on the plurality of CMOS electrode pads; and a common electrode formed on the plurality of LED stacks, wherein when the LED stacks include the plurality of light-emitting parts, the plurality of light-emitting parts are bonded through a bonding layer and stacked in a vertical direction, and when the plurality of light-emitting parts are bonded through the bonding layer, the LED stacks emit only a specific color by blocking light generated from the lower light-emitting parts by the bonding layer.

[0020] In addition, the bonding layer may be formed of an opaque conductive material.

[0021] Additionally, the plurality of LED laminates may include a first LED laminate for emitting only a first color, a second LED laminate for emitting only a second color, and a third LED laminate for emitting only a third color.

[0022] In addition, the common electrode may be an anode or a cathode.

[0023] The above objective is achieved by a method for manufacturing a vertically stacked microdisplay panel according to the present invention, comprising: a preparation step of preparing a plurality of front wafers including a support wafer and a light-emitting part, a temporary wafer, and a back wafer having a plurality of CMOS electrode pads aligned on the upper surface; a stacking step of stacking a plurality of light-emitting parts vertically on a temporary wafer by repeating the process of bonding the front wafer onto the temporary wafer through a bonding layer and then removing the support wafer; a bonding step of bonding the stacked plurality of light-emitting parts to the back wafer and then removing the temporary wafer to stack a plurality of light-emitting parts on the back wafer; an etching step of etching the stacked plurality of light-emitting parts to separate them into preset units so that a plurality of LED stacks are each aligned on a plurality of CMOS electrode pads; a removal step of selectively removing the light-emitting part of each LED stack; and a forming step of forming a common electrode on a plurality of LED stacks, wherein the LED stack emits only a specific color when the plurality of light-emitting parts are bonded through the bonding layer, such that light generated from the lower light-emitting part is blocked by the bonding layer.

[0024] In addition, the bonding layer may be formed of an opaque conductive material.

[0025] Additionally, the plurality of LED laminates may include a first LED laminate for emitting only a first color, a second LED laminate for emitting only a second color, and a third LED laminate for emitting only a third color.

[0026] In addition, the common electrode may be an anode or a cathode. Effects of the invention

[0027] According to the present invention, even though a vertically stacked tandem structure is adopted, a color filter becomes unnecessary, so the color quality of the microdisplay can be significantly improved, and process complexity and productivity can be significantly improved.

[0028] In addition, according to the present invention, unlike conventional monolithic integration methods or hybrid methods that have alignment issues, an engineering monolithic epitaxy wafer is first fabricated, and then a stack on the engineering monolithic epitaxy wafer is etched to separate it into preset units, thereby allowing a plurality of LED stacks to be aligned on a plurality of CMOS electrode pads. This enables the use of not only small-diameter wafers of 6 inches or less, but also large-diameter wafers of 8 inches or more, thereby having the effect of significantly increasing the product yield.

[0029] In addition, according to the present invention, a vertically stacked tandem structure can be formed by conventional metal bonding.

[0030] In addition, according to the present invention, since the stacking order of the light-emitting parts is not limited, there is an effect of being able to adjust the red light-emitting part, which has the lowest light-emitting efficiency, to the top layer.

[0031] Meanwhile, the effects of the present invention are not limited to those mentioned above, and various effects may be included within the scope obvious to a person skilled in the art from the contents described below. Brief explanation of the drawing

[0032] FIG. 1 illustrates the structure of a conventional microdisplay panel, and FIG. 2 illustrates a conventional LEDoS development approach, and FIG. 3 illustrates an approach using a conventional engineering monolithic epitaxy wafer, and FIG. 4 is a flowchart of a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, and FIG. 5 illustrates the process of preparing a front wafer in a p-side up shape in a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, and FIG. 6 illustrates the process of preparing an n-side up front wafer in a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, and FIG. 7 illustrates the process of preparing a back wafer in a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, and FIGS. 8 and 9 illustrate the process of manufacturing a vertically stacked microdisplay panel according to a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, and FIG. 10 illustrates a vertically stacked microdisplay panel according to one embodiment of the present invention. Specific details for implementing the invention

[0033] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings.

[0034] In addition, when describing embodiments of the present invention, if it is determined that a detailed description of related known configurations or functions would hinder understanding of the embodiments of the present invention, such detailed description is omitted.

[0035] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by such terms.

[0037] Now, with reference to the attached drawings, a method (S100) for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention will be described in detail.

[0038] FIG. 4 is a flowchart of a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, FIG. 5 illustrates the process of preparing a front wafer in a p-side up shape in a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, FIG. 6 illustrates the process of preparing a front wafer in an n-side up shape in a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, FIG. 7 illustrates the process of preparing a back wafer in a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention, and FIG. 8 and FIG. 9 illustrate the process of manufacturing a vertically stacked microdisplay panel according to a method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention.

[0039] As illustrated in FIGS. 4 to 9, a method (S100) for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention includes a preparation step (S110), a stacking step (S120), a bonding step (S130), an etching step (S140), a removal step (S150), and a forming step (S160).

[0040] The preparation step (S110) is a step of preparing a plurality of front wafers (110), temporary wafers (T), and back wafers (140).

[0041] A plurality of front wafers (110) are each intended to emit different colors. The plurality of front wafers (110) may include a first front wafer (111) for emitting a first color, a second front wafer (112) for emitting a second color different from the first color, and a third front wafer (113) for emitting a third color different from the first and second colors. Meanwhile, the first color, the second color, and the third color may be, for example, red, green, and blue, respectively, but are not limited thereto, and various other colors may be included.

[0042] Here, the first front wafer (111) includes a support wafer (S) and a first light-emitting part (121) disposed on top of the support wafer (S), the second front wafer (112) includes a support wafer (S) and a second light-emitting part (122) disposed on top of the support wafer (S), and the third front wafer (113) includes a support wafer (S) and a third light-emitting part (123) disposed on top of the support wafer (S).

[0043] The light-emitting part (120) generates light and can emit blue light, green light, or red light. In the present invention, when the light-emitting part (120) emits blue light or green light, binary, ternary, or quaternary compounds such as InN, InGaN, GaN, AlGaN, AlN, and AlGaInN, which are group 3 (Al, Ga, In) nitride semiconductors among group 3-5 compound semiconductors, can be placed in appropriate positions and order on the initial growth wafer (G) and grown by epitaxy.

[0044] In particular, to emit blue or green light, a high-quality InGaN group 3 nitride semiconductor with a high In composition must be preferentially formed on top of a group 3 nitride semiconductor composed of GaN, AlGaN, AlN, and AlGaInN, but is not limited thereto.

[0045] In addition, when the light-emitting part (120) in the present invention emits red light, binary, ternary, and quaternary compounds such as InP, InGaP, GaP, AlInP, AlGaP, AlP, and AlGaInP, which are group 3 (Al, Ga, In) phosphide semiconductors among group 3-5 compound semiconductors, can be arranged in appropriate positions and order on the initial growth wafer (G) and grown by epitaxy. Furthermore, in order to further improve the value of display panel products and the development of equipment and process technologies in recent years, when emitting red light, in addition to group 3 phosphide semiconductors, a high-quality group 3 nitride semiconductor of InGaN having a high In composition of 30% or more can be preferentially formed on top of a group 3 nitride semiconductor composed of GaN, AlGaN, AlN, and AlGaInN.

[0046] In particular, to emit red light, a high-quality Group 3 phosphide semiconductor of InGaP with a high In composition must be preferentially formed on top of a Group 3 phosphide semiconductor composed of GaP, AlInP, AlGaP, AlP, and AlGaInP, but is not limited thereto, and the following description is based on a Group 3 nitride semiconductor.

[0047] Each light-emitting part (120) more specifically includes a first semiconductor region (1201) (e.g., a p-type semiconductor region), an active region (1203) (e.g., multi quantum wells, MQWs), and a second semiconductor region (1202) (e.g., an n-type semiconductor region), and may have a structure in which the second semiconductor region (1202), the active region (1203), and the first semiconductor region (1201) are epitaxially grown in sequence on a growth wafer (G), and may have a thickness of approximately 5.0 to 8.0 μm overall by including multiple layers of group 3 nitride, but is not limited thereto.

[0048] Each of these first semiconductor region (1201), active region (1203), and second semiconductor region (1202) may be composed of a single layer or multiple layers, and although not illustrated, prior to epitaxially growing the light-emitting part (120) on the growth wafer (G), necessary layers such as a buffer layer may be added to improve the quality of the epitaxially grown light-emitting part (120). For example, the buffer layer may be composed of a compliant layer (CL) consisting of a nucleation layer (NL) and an un-doped semiconductor region to relieve stress and improve thin film quality, and may have a thickness of typically around 4.0 μm. Additionally, when removing the growth wafer (G) using a laser lift-off (LLO) technique, a sacrificial layer (SL) may be provided between the nucleation layer and the un-doped semiconductor region, and a seed layer may function as a sacrificial layer.

[0049] The second semiconductor region (1202) has second conductivity and is formed on the growth wafer (G). This second semiconductor region (1202) may have a thickness of 2.0 to 3.5 μm.

[0050] The active region (1203) generates light by utilizing the recombination of electrons and holes and is formed on the second semiconductor region (1202). This active region (1203) can have a thickness of several tens of nanometers in a multilayer.

[0051] The first semiconductor region (1201) has a first conductivity (p-type) and is formed on the active region (1203). This first semiconductor region (1201) can have a thickness of several tens of nanometers to several micrometers in a multilayer structure, and the surface can have gallium polarity (Ga-polarity).

[0052] That is, the active region (1203) is interposed between the first semiconductor region (1201) and the second semiconductor region (1202), so that light can be generated when holes in the first semiconductor region (1201), which is a p-type semiconductor region, and electrons in the second semiconductor region (1202), which is an n-type semiconductor region, recombine in the active region (1203).

[0053] Additionally, during the process of preparing the front wafer (110), an ohmic contact electrode (124) having optical transparency and electrical conductivity, which is ohmic contacted and electrically connected to the light-emitting part (120), may be formed on at least one of the upper or lower surfaces of the light-emitting part (120), and this will be described later.

[0054] The support wafer (S) supports the light-emitting part (120) (first light-emitting part (121), second light-emitting part (122) or third light-emitting part (123)) placed on the top, and if the first growth wafer (G) is not removed, the growth wafer (G) may be the support wafer (S), and may be a separate wafer bonded to remove the first growth wafer (G).

[0055] FIG. 5 illustrates the process of preparing a front wafer (110) in a p-side up shape in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0056] As illustrated in FIG. 5, the process of preparing the first front wafer (111) in a p-side up form is as follows.

[0057] In the case of a first front wafer (111) for emitting red light, a second semiconductor region (1202), an active region (1203), and a first semiconductor region (1201) are epitaxially grown in sequence on a GaAs growth wafer (G), and then a p-type ohmic contact electrode (124) having transparent conductivity is formed on the upper surface of the first semiconductor region (1201), and then a front wafer (110) in a p-side up form is prepared by forming the ohmic contact electrode (124). At this time, the growth wafer (G) acts as a support wafer (S), and may have a structure in which the support wafer (S), the light-emitting part (120), and the ohmic contact electrode (124) are stacked in sequence.

[0058] In addition, the process of preparing a second front wafer (112) or a third front wafer (113) in a p-side up form is as follows.

[0059] In the case of a second front wafer (112) for emitting green light or a third front wafer (113) for emitting blue light, a second semiconductor region (1202), an active region (1203), and a first semiconductor region (1201) are epitaxially grown in sequence on a sapphire (α-phase Al2O3) growth wafer (G), and then a p-side up front wafer (110) is prepared by forming a p-type ohmic contact electrode (124) with transparent conductivity on the upper surface of the first semiconductor region (1201). At this time, the growth wafer (G) acts as a support wafer (S), and may have a structure in which the support wafer (S), the light-emitting part (120), and the ohmic contact electrode (124) are stacked in sequence.

[0060] Meanwhile, for green light and blue light, a blue light or green light emitting part (120) may be formed on Si having a crystal plane (111) instead of a sapphire (α-phase Al2O3) growth wafer (G), and the Si growth wafer (G) may be separated and removed by mechanical polishing or chemical lift-off (CLO).

[0061] FIG. 6 illustrates the process of preparing an n-side up front wafer (110) in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0062] As illustrated in FIG. 6, the process of preparing the first front wafer (111) in an n-side up form is as follows.

[0063] In the case of a first front wafer (111) for emitting red light, a second semiconductor region (1202), an active region (1203), and a first semiconductor region (1201) are epitaxially grown in sequence on a GaAs growth wafer (G), and then a support wafer (S) and the first semiconductor region (1201) are bonded through a temporary bonding layer (B). Afterward, the growth wafer (G) is separated from the light-emitting part (120) using a chemical lift-off (CLO) technique, and the second semiconductor region (1202) is etched to reduce the thickness of the second semiconductor region (1202). Then, an n-side up front wafer (110) is prepared by forming an n-type ohmic contact electrode (124) with transparent conductivity on the surface of the second semiconductor region (1202) with reduced thickness. At this time, the support wafer (S) may be formed of a Si material having a crystal plane (111), (110), or (100), but is not limited thereto, and may have a structure in which the support wafer (S), temporary bonding layer (B), light-emitting part (120), and ohmic contact electrode (124) are stacked in order.

[0064] In addition, the process of preparing the second front wafer (112) or the third front wafer (113) in an n-side up form is as follows.

[0065] In the case of a second front wafer (112) for emitting green light or a third front wafer (113) for emitting blue light, a second semiconductor region (1202), an active region (1203), and a first semiconductor region (1201) are epitaxially grown in sequence on a sapphire (α-phase Al2O3) growth wafer (G), and then a support wafer (S) and the first semiconductor region (1201) are bonded through a temporary bonding layer (B). Afterward, the growth wafer (G) is separated from the light-emitting part (120) using a laser lift-off (LLO) technique, and the second semiconductor region (1202) is etched to reduce the thickness of the second semiconductor region (1202). Then, an n-side up front wafer (110) is prepared by forming an n-type ohmic contact electrode (124) with transparent conductivity on the surface of the second semiconductor region (1202) with reduced thickness. At this time, the support wafer (S) may be formed of a Si material having a crystal plane (111), (110), or (100), but is not limited thereto, and may have a structure in which the support wafer (S), temporary bonding layer (B), light-emitting part (120), and ohmic contact electrode (124) are stacked in order.

[0066] Furthermore, in the present invention, the growth wafer (G), support wafer (S), and / or temporary wafer (T) materials may each be either silicon (Si) or sapphire, but the choice of material may be determined according to the wafer bonding method.

[0067] For example, when surface activated bonding is performed at room temperature after a surface activation process, wafers of different materials such as silicon (Si) or sapphire may be selected regardless of the coefficient of thermal expansion, but when bonding between a growth wafer (G), a support wafer (S), a temporary wafer (T), and a back wafer (140), the bonding is performed at a temperature of 50°C or higher, or when annealing is performed at a temperature of 50°C or higher without removing one side of the wafer while the wafers are bonded, wafers of the same material must be selected.

[0068] Meanwhile, in the manufacturing process of the front wafer (110) described above, before the ohmic contact electrode (124) is formed on the surface of the first semiconductor region (1201) or the surface of the second semiconductor region (1202), the surface of the first semiconductor region (1201) may be exposed (in the form of a p-side up) or the surface of the second semiconductor region (1202) may be exposed (in the form of an n-side up), so that the respective surfaces may have smooth surfaces, the surfaces may be polished through mechanical polishing (MP) or chemical-mechanical polishing (CMP) to be smoothly flattened.

[0069] Additionally, the ohmic contact electrode (124) of the front wafer (110) is formed of a transparent conductive material. When the ohmic contact electrode (124) is formed to be in contact with a first semiconductor region (1201) which is a p-type semiconductor, the ohmic contact electrode (124) material may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the ohmic contact electrode (124) is formed to be in contact with a second semiconductor region (1202) which is an n-type semiconductor, the ohmic contact electrode (124) material may include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. Furthermore, since the surface roughness of the second semiconductor region (1202) having nitrogen polarity (N-polarity) is much greater than that of the first semiconductor region (1201) having gallium polarity (Ga-polarity), it is desirable to introduce a chemical-mechanical polishing (CMP) process to polish and flatten the surface of the second semiconductor region (1202) before forming the ohmic contact electrode (124) having transparent conductivity.

[0070] Additionally, the surface of the ohmic contact electrode (124) formed on the front wafer (110) can also be polished through mechanical polishing (MP) or chemical-mechanical polishing (CMP) to be smooth and flattened.

[0071] Meanwhile, when manufacturing a vertically stacked microdisplay panel (100) equipped with a positive common electrode, the third front wafer (113) may have a p-side up shape, the second front wafer (112) may have a p-side up shape, and the first front wafer (111) may have a p-side up shape; however, when manufacturing a vertically stacked microdisplay panel (100) equipped with a negative common electrode, the third front wafer (113) may have an n-side up shape, the second front wafer (112) may have an n-side up shape, and the first front wafer (111) may have an n-side up shape. However, it goes without saying that the shape of each front wafer (110) may vary depending on the stacking order of the light-emitting part (120).

[0072] The back wafer (140) is an active driving IC driven by an active matrix (AM) method, and refers to a CMOS wafer having a plurality of CMOS electrode pads (141) arranged in an array on its upper surface as shown in FIG. 8. A passivation layer may be formed on the upper surface of the back wafer (140) so that the upper surface of the plurality of CMOS electrode pads (141) is not exposed, and a portion of the passivation layer may be etched so that the plurality of CMOS electrode pads (141) are exposed when the front wafer (110) is bonded.

[0073] Here, the back wafer (140) can be provided as a Si wafer having a crystal plane (100), and can be provided as an 8-inch or 12-inch Si wafer according to a standard CMOS IC process, but considering that the usual LED wafer (front wafer (110)) for bonding is 4 inches or 6 inches, the size of the back wafer is not particularly limited.

[0074] The stacking step (S120) is a step of stacking a plurality of light-emitting parts (120) and a bonding layer (170) in a vertical direction on a temporary wafer (T) by repeatedly bonding a front wafer (110) with its upper and lower reversed orientation onto a temporary wafer (T) through a bonding layer (170) so that the light-emitting part (120) of the front wafer (110) faces the temporary wafer (T), i.e., so that the light-emitting part (120) of the front wafer (110) and the temporary wafer (T) face each other, and then removing the support wafer (S).

[0075] At this time, a separation layer (C) may be formed on the temporary wafer (T) and separated by being sacrificed when the temporary wafer (T) is removed in the bonding step (S130) described later. This separation layer (C) may be composed of oxides or nitrides such as ITO, GaN, InGaN, AlGaN, InAlN, GaOx, GaON, ZnO, InGaZnO, InZnO, or InGaO, but is not limited thereto.

[0076] In addition, if the supporting wafer (S) of the front wafer (110) is a Si wafer having a crystal plane (111), (110), or (100), and the temporary wafer (T) is also a Si wafer having a crystal plane (100), there is no difference in the coefficient of thermal expansion during bonding, which contributes to the quality stabilization of the vertically stacked microdisplay panel.

[0077] However, as described above, depending on the wafer bonding method, the supporting wafer (S) and / or temporary wafer (T) materials may be either silicon (Si) or sapphire, respectively. In the case of surface activated bonding at room temperature after a surface activation process, wafers of different materials, such as silicon (Si) or sapphire, may be selected regardless of the coefficient of thermal expansion.

[0078] Here, the bonding layer (170) may be formed from an opaque conductive material. Specifically, any metal bonding such as AuSn, NiSn, or AuIn may be used, and it may also be made of a single material such as Au-Au or Pt-Pt. The bonding layer (170) is preferably thinner and may be composed of a single layer or multiple layers; if composed of multiple layers, a reflective metal may be formed on the ohmic contact electrode (124).

[0079] Meanwhile, the bonding layer (170) may be composed of a single layer or multiple layers. In the case of multiple layers, the lower layer may have absorbent properties to block light generated from below, and the upper layer may have reflective properties to reflect light generated from above; for example, Ag / Ni may be applicable. Furthermore, the bonding layer (170) may include an etching mask layer for isolation during the etching step described later.

[0080] As illustrated in FIGS. 8 and 9, specifically in the stacking step (S120), to form, for example, a positive common electrode (160) structure, a third front wafer (113) in a p-side up form that emits blue light is bonded through a bonding layer (170) onto a temporary wafer (T) (or a separation layer (C) on the temporary wafer (T)), and then the support wafer (S) of the third front wafer (113) is removed using a laser lift-off or the like. Afterward, the second semiconductor region (1202) of the third light-emitting part (123) exposed by removing the support wafer (S) is etched to reduce its thickness.

[0081] Next, a second front wafer (112) in a p-side up shape that emits green light is bonded through a bonding layer (170), and then the support wafer (S) of the second front wafer (112) is removed using a laser lift-off or the like. Afterward, the second semiconductor region (1202) of the second light-emitting part (122) exposed as a result of removing the support wafer (S) is etched to reduce its thickness.

[0082] Next, a first front wafer (111) in a p-side up shape that emits red light is bonded through a bonding layer (170), and then the support wafer (S) of the first front wafer (111) is removed using a laser lift-off or the like. Afterward, the second semiconductor region (1202) of the first light-emitting part (121) exposed by removing the support wafer (S) is etched to reduce its thickness, and then a first bonding layer (131) is formed on the surface of the second semiconductor region (1202) to form a stacked structure.

[0083] Here, the first bonding layer (131) and the second bonding layer (132) described later may be formed from a material capable of eutectic bonding such as AuSn at a CMOS heat resistance temperature or lower, or a material capable of solid liquid intermetallic bonding such as NiSn, AuIn, CuSn, or AgIn, but are not limited thereto. Furthermore, single material (metal) bonding is also possible, and the thinner the thickness of the first bonding layer (131) and the second bonding layer (132), the more desirable it is.

[0084] Next, heat treatment at a high temperature can be optionally performed to improve the bonding strength of the stacked structure. That is, in the present invention, after stacking all RGB light sources on a support wafer (S), heat treatment at a high temperature is performed to secure bonding strength between the RGB epitaxies, and then the RGB stacked structure can be bonded to the CMOS Si back wafer (140) at once.

[0085] Through this, a temporary wafer (T), a separation layer (C), a bonding layer (170), an ohmic contact electrode (124), a third light-emitting part (123), a bonding layer (170), an ohmic contact electrode (124), a second light-emitting part (122), a bonding layer (170), an ohmic contact electrode (124), a first light-emitting part (121), and a first bonding layer (131) can be stacked in a vertical direction, and the stacked body can be selectively heat-treated at a high temperature, thereby ensuring strong bonding strength between RGB epitaxies.

[0086] However, the present invention is not limited to this stacking order, and various combinations are possible, such as stacking the third light-emitting part (123), the second light-emitting part (122), and the first light-emitting part (121) in the same manner in a vertical direction, or stacking in the order of the second light-emitting part (123), the first light-emitting part (121), and the third light-emitting part (123).

[0087] The bonding step (S130) is a step of bonding a temporary wafer (T), in which a plurality of light-emitting parts (120) and a bonding layer (170) are stacked in a vertical direction, with a back wafer (140), and then removing the temporary wafer (T).

[0088] At this time, the bonding in the bonding step (S130) may be achieved through an opaque conductive metal bonding, such as a eutectic bonding between a first bonding layer (131) formed on a temporary wafer (T) and a second bonding layer (132) formed on a back wafer (140), but is not limited thereto.

[0089] Additionally, after the temporary wafer (T) and the back wafer (140) are bonded, heat treatment of the bonding layer (130) can be selectively performed at a temperature that does not damage the CMOS circuit of the back wafer (140), and the removal of the temporary wafer (T) can be performed using mechanical polishing (MP) and chemical lift-off (CLO) techniques. Meanwhile, if a sapphire temporary wafer (T) is used as the temporary wafer (T), the temporary wafer (T) can be removed using a laser lift-off (LLO) technique.

[0090] Accordingly, when using a first front wafer (111) in a p-side-up shape, a second front wafer (112) in a p-side-up shape, and a third front wafer (113) in a p-side-up shape, a first light-emitting part (121) emitting red light, a second light-emitting part (122) emitting green light, and a third light-emitting part (123) emitting blue light can be sequentially stacked in a p-side-up shape on a back wafer (140). However, the stacking order of the light-emitting parts (120) is not limited.

[0091] Additionally, when using a first front wafer (111) in an n-side-up shape, a second front wafer (112) in an n-side-up shape, and a third front wafer (113) in an n-side-up shape, a first light-emitting part (121) emitting red light, a second light-emitting part (122) emitting green light, and a third light-emitting part (123) emitting blue light may be sequentially stacked in an n-side-up shape on a back wafer (140). However, the stacking order of the light-emitting parts (120) is not limited.

[0092] The etching step (S140) is a step in which a plurality of LED stacks (L) are each placed and aligned on a plurality of CMOS electrode pads (141) by etching a plurality of stacked light-emitting parts (120), ohmic contact electrodes (124), bonding layers (170), a first bonding layer (131), and a second bonding layer (132) to separate them into preset units.

[0093] That is, the etching step (S140) etches a plurality of light-emitting parts (120), ohmic contact electrodes (124), bonding layers (170), first bonding layers (131), and second bonding layers (132) in a vertical direction until the surface of the back wafer (140) or an adjacent area (e.g., a passivation layer) is exposed so that they are arranged in an array, that is, so that a plurality of LED stacks (L) are aligned on top of the aligned CMOS electrode pads (141). Here, the already set unit refers to a pixel or sub-pixel unit and may refer to the width (diameter) of the plurality of LED stacks (L).

[0094] After undergoing the etching step (S140) described above, each LED stack (L) placed on the CMOS electrode pad (141) may have a structure in which a second bonding layer (132), a first bonding layer (131), a first layer, a bonding layer (170), a second layer, a bonding layer (170), a third layer, and a bonding layer (170) are stacked. Here, the first layer may be a first light-emitting part (121) with an ohmic contact electrode (124) formed on its upper surface, the second layer may be a second light-emitting part (122) with an ohmic contact electrode (124) formed on its upper surface, and the third layer may be a third light-emitting part (123) with an ohmic contact electrode (124) formed on its upper surface, but as described above, the stacking order of the light-emitting part (120) may vary, and it is obvious that a plurality of layers of four or more layers may be provided.

[0095] The removal step (S150) is a step of selectively removing the light-emitting part of each LED stack (L).

[0096] In the present invention, a plurality of LED stacks (L) may include a first LED stack (L1), a second LED stack (L2), and a third LED stack (L3). Specifically, in the removal step (S150), the third layer of the second LED stack (L2) and the first LED stack (L1), and the bonding layer (170) on top of the third layer are removed first, then the second layer of the first LED stack (L1) and the bonding layer (170) on top of the second layer are removed, and then the bonding layers (170) exposed on top of each LED stack (L) are removed to expose the ohmic contact electrode (124).

[0097] That is, in the present invention, the second LED stack (L2) has a smaller number of layers than the third LED stack (L3), and the first LED stack (L1) has a smaller number of layers than the second LED stack (L2). For example, the first LED stack (L1) includes only the first layer, and the second LED stack (L2) includes the first layer and the second layer, and a bonding layer (170) is disposed between the first layer and the second layer. Additionally, the third LED stack (L3) includes the first layer, the second layer, and the third layer, and a bonding layer (170) is disposed between each layer.

[0098] Accordingly, each LED stack (L) emits only a specific color by blocking the light generated from the lower light-emitting part (120) by the bonding layer (170). Specifically, the first LED stack (L1) emits the color of the light-emitting part (120) of the first layer, and the second LED stack (L2) emits the color of the light-emitting part (120) of the second layer, and the color of the light-emitting part (120) of the first layer is blocked by the bonding layer (170). Additionally, the third LED stack (L3) emits the color of the light-emitting part (120) of the third layer, and the color of the light-emitting part (120) of the first layer and the color of the light-emitting part (120) of the second layer are each blocked by the bonding layer (170).

[0099] The forming step (S160) is a step of forming a mold portion (150) that fills between a plurality of aligned LED stacks (L), and then forming a common electrode (160) on the plurality of LED stacks (L). At this time, if the light-emitting portions (120) are in a p-side up shape, the common electrode (160) can be formed as an anode, and if the light-emitting portions (120) are in an n-side up shape, the common electrode (160) can be formed as a cathode.

[0100] At this time, preferably, prior to forming the mold portion (150) that fills between the aligned plurality of LED stacks (L), a passivation process may be performed, which is a process of wrapping the sides of all light-emitting portions (120) with an optically transparent and electrically insulating material (e.g., SiO2, SiNx, Al2O3).

[0101] More specifically, in the forming step (S160), a mold portion (150) is formed between and on top of a plurality of aligned LED stacks (L), and after etching the mold portion (150) so that the upper ohmic contact electrode (124) of the plurality of LED stacks (L) is exposed, a common electrode (160) is formed to be connected to the upper portion of the plurality of LED stacks (L) to complete a vertical stacked LEDoS structure, wherein the common electrode (160) may be formed of a material having transparent conductivity similar to the ohmic contact electrode (124), and when the common electrode (160) is an anode, the common electrode (160) material may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO, and when the common electrode (160) is a cathode, the common electrode (160) material may include TiN, It may include CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0102] Additionally, the surface of the common electrode (160) can also be polished through mechanical polishing (MP) or chemical-mechanical polishing (CMP) to be smooth and flattened.

[0103] Furthermore, although not shown, a protection layer made of transparent organic material may be additionally formed to protect the common electrode (160) from the atmospheric environment.

[0105] From now on, a vertical stacked microdisplay panel (100) according to one embodiment of the present invention will be described in detail with reference to the attached drawings.

[0106] FIG. 10 illustrates a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0107] As illustrated in FIG. 10, a vertically stacked microdisplay panel (100) according to one embodiment of the present invention comprises a back wafer (140), a plurality of LED stacks (L), a mold part (150), and a common electrode (160).

[0108] In the following, some details that overlap with the method (S100) for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention will be omitted from the description.

[0109] The back wafer (140) is an active driving IC driven by an active matrix (AM) method, and refers to a CMOS wafer having a plurality of CMOS electrode pads (141) arranged in an array on its upper surface. A passivation layer may be formed on the upper surface of the back wafer (140), and a portion of the passivation layer may be etched so that the plurality of CMOS electrode pads (141) are exposed when the front wafer (110) is bonded.

[0110] A plurality of LED stacks (L) each include at least one light-emitting part (120) having an ohmic contact electrode (124) on its upper surface, and are each aligned on a plurality of CMOS electrode pads (141).

[0111] In the present invention, a plurality of LED stacks (L) may include a first LED stack (L1), a second LED stack (L2), and a third LED stack (L3). The second LED stack (L2) has a smaller number of layers than the third LED stack (L3), and the first LED stack (L1) has a smaller number of layers than the second LED stack (L2). For example, the first LED stack (L1) includes only a first layer, and the second LED stack (L2) includes a first layer and a second layer, with a bonding layer (170) disposed between the first layer and the second layer. Additionally, the third LED stack (L3) includes a first layer, a second layer, and a third layer, with a bonding layer (170) disposed between each layer.

[0112] Here, the first layer may be a first light-emitting part (121) with an ohmic contact electrode (124) formed on its upper surface, the second layer may be a second light-emitting part (122) with an ohmic contact electrode (124) formed on its upper surface, and the third layer may be a third light-emitting part (123) with an ohmic contact electrode (124) formed on its upper surface, but as described above, the stacking order of the light-emitting part (120) may vary.

[0113] Accordingly, each LED stack (L) emits only a specific color by blocking the light generated from the lower light-emitting part (120) by the bonding layer (170). Specifically, the first LED stack (L1) emits the color of the light-emitting part (120) of the first layer, and the second LED stack (L2) emits the color of the light-emitting part (120) of the second layer, and the color of the light-emitting part (120) of the first layer is blocked by the bonding layer (170). In addition, the third LED stack (L3) emits the color of the light-emitting part (120) of the third layer, and the color of the light-emitting part (120) of the first layer and the color of the light-emitting part (120) of the second layer are each blocked by the bonding layer (170).

[0114] The mold portion (150) supports a vertical stacked LEDoS structure and is formed to fill the space between a plurality of aligned LED stacks (L).

[0115] In the present invention, the light-emitting portions (120) of the LED laminate (L) may be laminated in a p-side up or n-side up configuration, and accordingly, the common electrode (160) may be provided as an anode or a cathode and formed on a plurality of LED laminates (L) in which a mold portion (150) is formed. Here, when the common electrode (160) is an anode, the material of the common electrode (160) may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO, and when the common electrode (160) is a cathode, the material of the common electrode (160) may include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0117] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate.

[0118] Furthermore, terms such as "include," "compose," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; therefore, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0119] Furthermore, the above description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention.

[0120] Accordingly, the embodiments disclosed in this invention are intended to illustrate, not limit, the technical concept of the invention, and the scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of this invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of this invention. Explanation of the symbols

[0121] 10: Conventional microdisplay panel 11: Si CMOS wafer 12: CMOS electrode pad 13: Transparent wafer 14: microLED electrode pad 15 : microLED chip 16: Conductive junction S100: Method for manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention S110: Preparation stage S120: Stacking step S130: Bonding step S140: Etching step S150: Removal step S160: Formation stage 100: A vertically stacked microdisplay panel according to one embodiment of the present invention 110: Front wafer S: Support wafer 120 : Light-emitting part 111: 1st front wafer 121 : First light-emitting part 112: 2nd front wafer 122 : Second light-emitting part 113: 3rd front wafer 123 : 3rd light-emitting part L : LED laminate L1: 1st LED laminate L2: 2nd LED laminate L3: 3rd LED laminate 1201: 1st semiconductor region 1202: Second semiconductor region 1203 : Active area 124 : Ohmic contact electrode G: Growth wafer B: Temporary bonding layer 131 : First bonding layer 132 : Second bonding layer 140: Back wafer 141 : CMOS electrode pad 150 : Mold part 160 : Common electrode 170 : Bonding layer

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 A method for manufacturing a vertically stacked microdisplay panel comprising: a preparation step of preparing a plurality of front wafers including a support wafer and a light-emitting part, a temporary wafer, and a back wafer having a plurality of CMOS electrode pads aligned on the upper surface; a stacking step of stacking a plurality of light-emitting parts vertically on a temporary wafer by repeating the process of bonding the front wafer onto the temporary wafer through a bonding layer and then removing the support wafer; a bonding step of bonding the stacked plurality of light-emitting parts to the back wafer and then removing the temporary wafer to stack a plurality of light-emitting parts on the back wafer; an etching step of etching the stacked plurality of light-emitting parts to separate them into preset units so that a plurality of LED stacks are each aligned on a plurality of CMOS electrode pads; a removal step of selectively removing the light-emitting part of each LED stack; and a forming step of forming a common electrode on a plurality of LED stacks, wherein the LED stacks emit only a specific color when the plurality of light-emitting parts are bonded through the bonding layer, such that light generated from the lower light-emitting part is blocked by the bonding layer. Claim 6 A method for manufacturing a vertically stacked microdisplay panel according to claim 5, wherein the bonding layer is formed of an opaque conductive material. Claim 7 A method for manufacturing a vertically stacked microdisplay panel according to claim 6, wherein the plurality of LED stacks comprises a first LED stack for emitting only a first color, a second LED stack for emitting only a second color, and a third LED stack for emitting only a third color. Claim 8 A method for manufacturing a vertically stacked microdisplay panel according to claim 5, wherein the common electrode is an anode or a cathode.

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