Apparatus including three terminal insensing memory device and method for operating the same

Abstract

A device including a three-terminal sensing memory element and a method of operating the device including a three-terminal sensing memory element are disclosed. An apparatus including a three-terminal sensing memory element comprises a three-terminal sensing memory element and a control circuit for controlling a signal applied to each terminal of the three-terminal sensing memory element, wherein the three-terminal sensing memory element comprises upper electrodes including a source electrode corresponding to a first terminal among the three terminals and a drain electrode corresponding to a second terminal among the three terminals, a lower electrode including a gate electrode corresponding to a third terminal among the three terminals, and a thin film layer located between the upper electrodes and the lower electrode and forming a conductive filament, wherein the three-terminal sensing memory element generates a photoexcitation current in response to light incident on the three-terminal sensing memory element, and when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect formed between the gate electrode and the source electrode and the drain electrode is opposite to the source-drain current change caused by the conductive filament, and the control circuit, by adjusting the voltage applied to the gate electrode, controls the current flowing through the conductive filament and between the source electrode and the drain electrode The source-drain current flowing through the formed channel is controlled, and the source-drain current may include the photoexcitation current.

Description

Technology Field

[0001] The present disclosure relates to an apparatus including a three-terminal sensing memory element and a method of operating the apparatus including a three-terminal sensing memory element. Background Technology

[0003] Neuromorphic devices can be semiconductor devices capable of performing computational and memory functions by mimicking the structure and operation of the nervous system. Optoelectronic synapse devices can be neuromorphic devices that generate electrical output using light stimulation as input. The electrical conductivity of optoelectronic synapse devices can change depending on optical properties such as light intensity, wavelength, and period. These properties can enable neurological operations such as learning, forgetting, long-term memory, and short-term memory.

[0004] A conductive filament (CF) can represent a path for current formed by ion movement or the accumulation of oxygen vacancies within an insulating layer. A semiconductor device can be in a high-resistance or low-resistance state depending on the resistance of the conductive filament.

[0006] An apparatus including a three-terminal sensing memory element according to one embodiment includes a control circuit that controls a signal applied to each terminal of the three-terminal sensing memory element and the three-terminal sensing memory element, wherein the three-terminal sensing memory element includes upper electrodes including a source electrode corresponding to a first terminal among the three terminals and a drain electrode corresponding to a second terminal among the three terminals, a lower electrode including a gate electrode corresponding to a third terminal among the three terminals, and a thin film layer located between the upper electrodes and the lower electrode and forming a conductive filament (CF), wherein the three-terminal sensing memory element generates a photoexcitation current in response to light incident on the three-terminal sensing memory element, and when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect (FE) formed between the gate electrode, the source electrode, and the drain electrode is the source-drain current change caused by the conductive filament and The control circuit controls the current flowing through the conductive filament and the source-drain current flowing through the channel formed between the source electrode and the drain electrode by adjusting the voltage applied to the gate electrode, and the source-drain current may include the photoexcitation current.

[0007] The above three-terminal sensing memory device may further include a semiconductor layer interposed between the upper electrodes and the thin film layer.

[0008] The above device changes the resistance of the conductive filament or the carrier concentration in the channel due to the electric field effect by adjusting the voltage applied to the gate electrode, and at least one of the magnitude and rate of change of the source-drain current can be determined according to the resistance of the conductive filament or the carrier concentration.

[0009] The above device controls the decay rate of the photo-excitation current by adjusting the voltage applied to the gate electrode, and when the same gate voltage is applied to the gate electrode, the decay rate of the photo-excitation current caused by the electric field effect may be opposite to the decay rate of the photo-excitation current caused by the conductive filament.

[0010] The above three-terminal sensing memory device performs the operation of a logic gate according to the polarity of the voltage applied to the gate electrode, and the logic gate can take the magnitude of the voltage applied to the gate electrode and the presence or absence of the incident light as inputs.

[0011] The above three-terminal sensing memory device can operate as an AND gate or an OR gate depending on the voltage applied to the gate electrode by utilizing the fact that when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect is opposite to the source-drain current change caused by the conductive filament.

[0012] A method of operation of an apparatus including a three-terminal sensing memory element and a control circuit according to one embodiment includes applying a voltage to a gate electrode to form a channel through which electrons flow between the source electrode of the three-terminal sensing memory element and the drain electrode of the three-terminal sensing memory element, and measuring a source-drain current flowing in the channel, wherein the source-drain current includes a photoexcitation current generated by light incident on the three-terminal sensing memory element, and when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect formed between the gate electrode, the source electrode, and the drain electrode is opposite to the source-drain current change caused by the conductive filament, and the operation of applying a voltage to the gate electrode may include controlling the current flowing in the conductive filament and the source-drain current flowing in the channel formed between the source electrode and the drain electrode by adjusting the voltage applied to the gate electrode.

[0013] The above three-terminal sensing memory device may further include a semiconductor layer interposed between the upper electrodes, including the source electrode and the drain electrode, and the thin film layer.

[0014] The operation of applying a voltage to the gate electrode may include controlling the resistance of the conductive filament or the carrier concentration in the channel according to the electric field effect by adjusting the voltage applied to the gate electrode, and controlling at least one of the magnitude and rate of change of the source-drain current.

[0015] The operation of controlling the rate of change of the source-drain current includes controlling the decay rate of the photo-excitation current by adjusting the voltage applied to the gate electrode, and when the same gate voltage is applied to the gate electrode, the decay rate of the photo-excitation current caused by the electric field effect may be opposite to the decay rate of the photo-excitation current caused by the conductive filament.

[0016] The above operation method further includes an operation of performing the operation of a logic gate according to the polarity of the voltage applied to the gate electrode, and the logic gate may take the magnitude of the voltage applied to the gate electrode and the presence or absence of the incident light as inputs.

[0017] The operation of the logic gate may include an operation of operating as an AND gate or an OR gate depending on the voltage applied to the gate electrode, utilizing the fact that when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect is opposite to the source-drain current change caused by the conductive filament. Brief explanation of the drawing

[0019] FIG. 1 is a block diagram for explaining the configurations of a device including a three-terminal sensing memory element according to one embodiment. FIG. 2a is a diagram illustrating the case where a positive voltage is applied to the gate electrode of a three-terminal sensing memory device having a conductive filament formed thereon according to one embodiment. FIG. 2b is a diagram illustrating the case where a negative voltage is applied to the gate electrode of a three-terminal sensing memory device having a conductive filament formed thereon according to one embodiment. FIG. 2c is a diagram illustrating the case where a positive voltage is applied to the gate electrode of a three-terminal sensing memory device in an electric field effect state according to one embodiment. FIG. 2d is a diagram illustrating the case where a negative voltage is applied to the gate electrode of a three-terminal sensing memory device in an electric field effect state according to one embodiment. FIG. 3a is a diagram illustrating a graph showing the generation and decay rates of photoexcitation current according to the voltage applied to the gate electrode in a conductive filament state of high resistance and low resistance according to one embodiment. FIG. 3b is a diagram illustrating a graph showing the generation and decay rates of photoexcitation current according to the voltage applied to the gate electrode in an electric field effect state according to one embodiment. FIG. 3c is a diagram illustrating the process of performing image inversion using a conductive filament in a high resistance state and a low resistance state, in a device including a three-terminal sensing memory element according to one embodiment. FIG. 3d is a diagram illustrating the process of a device including a three-terminal sensing memory element according to one embodiment performing image inversion using an electric field effect. FIG. 4a is a diagram for explaining a graph showing the input and output of a three-terminal sensing memory device that performs logic gate operations using a conductive filament in a high-resistance state and a low-resistance state according to one embodiment. FIG. 4b is a diagram illustrating a graph showing the input and output of a three-terminal sensing memory device that performs logic gate operations using an electric field effect according to one embodiment. FIG. 5 is a flowchart for explaining the operation method of a device including a three-terminal sensing memory element according to one embodiment. Specific details for implementing the invention

[0020] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments.

[0021] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0022] When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or joined to that other component, or that there may be other components in between.

[0023] Singular expressions include plural expressions unless the context clearly indicates otherwise. In this document, phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B, or C” may each include any one of the items listed together with the corresponding phrase, or all possible combinations thereof. In this specification, terms such as “comprising” or “having” are intended to designate the existence of the described feature, number, step, action, component, part, or combination thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0024] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0025] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are given the same reference numeral regardless of the drawing number, and redundant descriptions thereof will be omitted.

[0027] FIG. 1 is a block diagram for explaining the configurations of a device including a three-terminal sensing memory element according to one embodiment.

[0028] Referring to FIG. 1, the device (100) may include a three-terminal sensing memory element (110) (e.g., the three-terminal sensing memory element (200) of FIG. 2a, the three-terminal sensing memory element (200) of FIG. 2b, the three-terminal sensing memory element (200) of FIG. 2c, the three-terminal sensing memory element (200) of FIG. 2d)) and a control circuit (120) that controls a signal applied to each terminal of the three-terminal sensing memory element (110). A three-terminal sensing memory element (110) comprises upper electrodes including a source electrode corresponding to a first terminal among the three terminals (e.g., source electrode (210) of FIG. 2A, source electrode (210) of FIG. 2B, source electrode (210) of FIG. 2C, source electrode (210) of FIG. 2D) and a drain electrode corresponding to a second terminal among the three terminals (e.g., drain electrode (220) of FIG. 2A, drain electrode (220) of FIG. 2B, drain electrode (220) of FIG. 2C, drain electrode (220) of FIG. 2D), a lower electrode including a gate electrode corresponding to a third terminal among the three terminals (e.g., gate electrode (230) of FIG. 2A, gate electrode (230) of FIG. 2B, gate electrode (230) of FIG. 2C, gate electrode (230) of FIG. 2D), and a thin film layer (e.g., FIG. 10) located between the upper electrodes and the lower electrode and forming a conductive filament. It may include a thin film layer (240) of FIG. 2a, a thin film layer (240) of FIG. 2b, and a thin film layer (240) of FIG. 2d that forms an electric field effect. The control circuit (120) can control the current flowing through the conductive filament and the current flowing through the channel formed between the source electrode and the drain electrode by adjusting the voltage applied to the gate electrode. The three-terminal sensing memory device (110) and the control circuit (120) may be integrated into a single chip or separated and disposed on different substrates.

[0029] In one embodiment, the source electrode, drain electrode, and gate electrode may each comprise, for example, at least one of platinum (Pt), silver (Ag), aluminum (Al), iridium (Ir), gold (Au), ruthenium (Ru), tungsten (W), titanium (Ti), nickel (Ni), hafnium (Hf), iridium oxide (IrO2), ruthenium oxide (RuO2), titanium nitride (TiN), or tantalum nitride (TaN), but are not limited to these examples. The source electrode, drain electrode, and gate electrode may each be the same material or different materials.

[0030] In one embodiment, the thin film layer may comprise at least one of a metal oxide, a metal nitride, and a semiconductor oxide. The metal oxide may comprise, for example, at least one of Ga2O3, ZnO, Al2O3, CaO, CdO, Co3O5, CoO2, CuO2, MoO3, WO3, MnO2, RuO2, TiO2, SnO2, Nb2O5, NiO, CrO2, Fe3O4, ZrO2, HfO2, or V2O5, but is not limited to these examples. The metal nitride may comprise, for example, at least one of GaN, InN, AlN, Ti2N, Ti3N2, Ti4N3, Zr2N, V2N, or Cr2N, but is not limited to these examples. The semiconductor oxide may comprise, for example, SiO2, but is not limited to these examples. The thin film layer may be doped with n-type or p-type.

[0031] In one embodiment, the thin film layer may be positioned on a substrate (e.g., substrate (250) of FIG. 2a, substrate (250) of FIG. 2b, substrate (250) of FIG. 2c, substrate (250) of FIG. 2d). The substrate may be a conductive substrate on which a gate electrode is formed and a carrier can be supplied. The substrate may be, for example, a silicon substrate, a semiconductor substrate (e.g., germanium), or an SOI (silicon on insulator) substrate, but is not limited to these examples.

[0032] In one embodiment, the three-terminal sensing memory device (110) may further include a semiconductor layer interposed between the upper electrodes and the thin film layer. The semiconductor layer may be used as a source-drain channel layer capable of generating a photocurrent by photostimulation. To form the semiconductor layer, other materials may be used among the materials of the thin film layer mentioned above, excluding the material used in the thin film layer. The semiconductor layer may include, for example, at least one of carbon nanotubes (CNT), graphene, reduced graphene oxide (RGO), In2O3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), ZTO (zinc tin oxide), TiO2 (titanium oxide), ITO (indium tin oxide), HfIZO (hafnium indium zinc oxide), and SnO2 (tin oxide), but is not limited to these examples. The semiconductor layer may be doped as n-type or p-type.

[0033] In one embodiment, the three-terminal sensing memory device (110) can increase the source-drain current by supplying carriers from the gate electrode to the thin film layer through a conductive filament formed in the thin film layer in response to the application of a negative voltage to the gate electrode when a semiconductor layer made of an n-type semiconductor is present. The three-terminal sensing memory device (110) can decrease the source-drain current by moving carriers from the thin film layer to the gate electrode through a conductive filament formed in the thin film layer in response to the application of a positive voltage to the gate electrode.

[0034] In one embodiment, the three-terminal sensing memory device (110) can increase the source-drain current by supplying carriers from the gate electrode to the thin film layer through a conductive filament formed in the thin film layer in response to the application of a positive voltage to the gate electrode when a semiconductor layer made of a p-type semiconductor is present. The three-terminal sensing memory device (110) can decrease the source-drain current by moving carriers from the thin film layer to the gate electrode through a conductive filament formed in the thin film layer in response to the application of a negative voltage to the gate electrode.

[0035] In one embodiment, the three-terminal sensing memory element (110) may be a single element or an array (e.g., a matrix) composed of multiple elements. When the three-terminal sensing memory element (110) is configured as an array, the gate electrode of an individual element may be selectively connected to a word line, and the source electrode and drain electrode may be selectively connected to a bit line. When the three-terminal sensing memory element (110) is configured as an array, image inversion can be performed using the relative magnitude relationship of current values ​​measured at different elements (pixels). The three-terminal sensing memory element (110) can perform the operation of a logic gate through comparison with a threshold value. The description of the image inversion and logic gate operation of the three-terminal sensing memory element is explained in detail below with reference to FIGS. 3c to 4b.

[0036] In one embodiment, a conductive filament can be formed and destroyed in the thin film layer by applying voltage between the upper electrode layer (e.g., source electrode, drain electrode) and the lower electrode layer (e.g., gate electrode) of the thin film layer. The conductive filament may be in a low resistance state (LRS) after the set process or in a high resistance state (HRS) after the reset process. The set process may be a process in which a conductive filament is created by applying voltage between the upper electrode layer and the lower electrode layer. Conversely, the reset process may be a process in which a conductive filament is destroyed by applying voltage between the upper electrode layer and the lower electrode layer. The three-terminal sensing memory device (110) may be switched to a high resistance state and a low resistance state through the set process and the reset process. The current flowing through the channel formed between the source electrode and the drain electrode may be determined according to the resistance state of the conductive filament.

[0037] A three-terminal sensing memory element (110) can generate a photoexcitation current (current induced by light) in response to light incident from the outside. The current flowing through the channel may include the photoexcitation current. The generated photoexcitation current may be output through a channel formed between a source electrode and a drain electrode. The light may be provided by an external light source or by a light source module (not shown) inside the device (100).

[0038] In one embodiment, the source-drain current change caused by the electric field effect may be opposite to the source-drain current change caused by the conductive filament. For example, when the applied gate voltage is positive, electrons in the channel between the source electrode and the drain electrode accumulate due to the electric field effect, which may increase conductivity. The source-drain current may increase. Conversely, when the applied gate voltage is positive, electrons move out of the channel through the conductive filament, which may decrease the source-drain current.

[0039] As another example, when the applied gate voltage is negative, electrons in the channel may be depleted due to the electric field effect, and conductivity may decrease. The source-drain current may decrease. Conversely, when the applied gate voltage is negative, electrons may move into the channel through the conductive filament, and the source-drain current may increase. Even when the same gate voltage is applied, the electric field effect and the conductive filament can cause current changes with opposite characteristics. By utilizing these differences in characteristics, the three-terminal sensing memory device (110) can implement operations such as image inversion or logic gate switching within a single device.

[0040] In one embodiment, the control circuit (120) may be a circuit that generates, adjusts, and / or measures a signal applied to each terminal of the three-terminal sensing memory element (110). The control circuit (120) may include a bias that sets the magnitude and polarity of the voltage (Vgs) and source-drain voltage (Vds) applied to the gate electrode, and a driver that controls the magnitude, pulse width, pulse period, and / or number of pulses of the voltage to apply the bias. The control circuit (120) may include a sensing circuit. The sensing circuit may include a current sensing amplifier for measuring the source-drain current flowing through the channel, a resistor / current-voltage converter, and / or an A / D converter. The control circuit may further include a timing controller, a memory buffer, a communication interface, and / or a power supply circuit as needed.

[0041] In one embodiment, the control circuit (120) can determine the resistance state of the conductive filament in the thin film layer, the channel charge concentration, the magnitude and rate of change (e.g., decay (forgetting) rate) of the current flowing through the channel by adjusting the voltage applied to the gate electrode. For example, when a set voltage greater than a certain voltage is applied to the source electrode and the gate electrode, the conductive filament is in a low-resistance state, and when a positive voltage is applied to the gate, the number of carriers present in the channel decreases, and the source-drain current may decrease. The photoexcitation current may have a small initial value and decay at a rapid rate. Conversely, when a negative voltage is applied to the gate electrode after forming a low-resistance filament by applying a set voltage to the source and gate electrodes, the number of carriers present in the channel increases, and the source-drain current may increase. The photoexcitation current may have a relatively large initial value and decay at a slow rate. The control circuit (120) can control the magnitude and decay rate of the current within a single device by controlling the polarity and magnitude of the voltage applied to the gate electrode and the state of the conductive filament. Using these characteristics, the device (100) can perform operations such as image inversion or logic gate inversion.

[0042] In one embodiment, the control circuit (120) may apply a gate voltage and a source-drain voltage according to a set sequence to cause the three-terminal sensing memory device (110) to generate a photo-excitation current. The three-terminal sensing memory device (110) may generate a photo-excitation current in response to the presence, intensity, and pulse conditions of incident light. The light incident on the three-terminal sensing memory device (110) may have a wavelength of, for example, the ultraviolet band, the infrared band, or the visible light band.

[0044] FIG. 2a is a diagram illustrating the case where a positive voltage is applied to the gate electrode of a three-terminal sensing memory device having a conductive filament formed thereon according to one embodiment. FIG. 2b is a diagram illustrating the case where a negative voltage is applied to the gate electrode of a three-terminal sensing memory device having a conductive filament formed thereon according to one embodiment.

[0045] Referring to FIGS. 2a and 2b, a three-terminal sensing memory element (200) (e.g., the three-terminal sensing memory element (110) of FIG. 1) may include a source electrode (210), a drain electrode (220), a gate electrode (230), a thin film layer (240), and a substrate (250). V illustrated in FIGS. 2a and 2b O represents an oxygen vacancy, and e can represent an electron. The arrows shown in FIGS. 2a and 2b can schematically represent the movement path of a carrier (e.g., an electron).

[0046] In one embodiment, a conductive filament may be formed inside the thin film layer (240) by a voltage applied between the source electrode (210) and the gate electrode (230). The resistance of the conductive filament may be varied by adjusting the voltage applied to the gate electrode (230). The magnitude and rate of change of the source-drain current may be determined according to the resistance of the conductive filament.

[0047] For example, when a positive voltage is applied to the gate electrode (230) (Fig. 2a), a vertical electric field may be formed inside the thin film layer (240). Due to the vertical electric field, oxygen ions (O 2-() moves toward the gate electrode, and in response, oxygen vacancies (Vo) can move toward the channel. This forms a conductive filament, so that a portion of the thin film layer between the source and the gate can exhibit low resistance characteristics. Alternatively, through a reset process of the conductive filament formed between the source electrode (210) and the gate electrode (230), the continuity may be weakened or partially broken, causing the resistance of the conductive filament to increase and become a high resistance state. When a positive voltage is applied to the gate electrode (230), carriers escape to the gate, and the current flowing through the channel between the source electrode (210) and the drain electrode (220) may decrease. The decay rate of electrons in the channel through the high-resistance conductive filament may be smaller than that of the low-resistance conductive filament. When light is incident on a three-terminal sensing memory device (200), photoexcited electrons generated by the incident light cannot move effectively and rapidly recombine in traps or interface states within the thin film layer (240), so that the photoexcitation current has a small initial size and can decay rapidly over time. This characteristic can rapidly erase specific patterns during memory operation or induce the decay of existing signals during image inversion operation.

[0048] In another example, when a negative voltage is applied to the gate electrode (230) (Fig. 2b), electrons are supplied to the source-drain channel through the low-resistance and high-resistance conductive filaments formed within the thin film layer (240), and the current flowing in the channel between the source electrode (210) and the drain electrode (220) (e.g., source-drain current) can be increased. The rate of change of current in the source-drain channel can be determined by controlling the conductive filaments within the thin film layer (240) to low resistance and high resistance. Since the low-resistance conductive filament can supply electrons from the gate to the source-drain channel more easily than the high-resistance conductive filament, the source-drain channel current of the low-resistance conductive filament can be increased more significantly. When light is incident on the three-terminal sensing memory device (200), photo-excited electrons generated by the incident light travel along the conductive filaments, so the photo-excitation current has a large initial magnitude and can decay slowly over time. These characteristics can maintain specific patterns for a long time during memory operations or amplify specific signals during image inversion operations.

[0049] The structure and material of the three-terminal sensing memory device (200) according to the present disclosure are not limited to the structure shown in a specific embodiment. For example, an example in which a gate electrode (230) is disposed on the upper surface of a substrate (250) has been shown, but this is merely an example and is not limited thereto. Also, the materials of the source electrode (210), drain electrode (220), gate electrode (230), and thin film layer (240) are not limited to a specific embodiment. For example, the source electrode (210) and drain electrode (220) may be formed of a metal such as platinum (Pt), gold (Au), silver (Ag), or copper (Cu), or an alloy thereof. The thin film layer (240) may be formed of various insulating or semiconductor materials, and various materials capable of forming a conductive filament may be used. The three-terminal sensing memory device (200) according to the present disclosure is not limited to a specific combination of materials and may be implemented in a modified example including various electrode materials and thin film materials.

[0051] FIG. 2c is a diagram illustrating the case where a positive voltage is applied to the gate electrode of a three-terminal sensing memory device in an electric field effect state according to one embodiment. FIG. 2d is a diagram illustrating the case where a negative voltage is applied to the gate electrode of a three-terminal sensing memory device in an electric field effect state according to one embodiment.

[0052] Referring to FIGS. 2c and 2d, a three-terminal sensing memory device (200) (e.g., the three-terminal sensing memory device (110) of FIG. 1) may include a source electrode (210), a drain electrode (220), a gate electrode (230), a thin film layer (240), and a substrate (250). e shown in FIGS. 2c and 2d may represent an electron. The arrows shown in FIGS. 2c and 2d may schematically represent the movement path of a carrier (e.g., an electron).

[0053] In one embodiment, an electric field may be formed inside the thin film layer (240) by a voltage applied to the gate electrode (230). By adjusting the voltage applied to the gate electrode (230), the concentration of carriers in the source-drain channel may be varied. The magnitude and rate of change of the source-drain current may be determined according to the carrier concentration in the source-drain channel.

[0054] For example, when a positive voltage is applied to the gate electrode (Fig. 2c), a vertical electric field is formed between the thin film layer (240) and the gate electrode (230), allowing electrons in the source-drain channel region to move according to the electric field. Due to this electric field effect, electrons accumulate in the source-drain channel, which can increase the electron concentration. The source-drain current may increase. Conversely, when a negative voltage is applied to the gate electrode (Fig. 2d), electrons in the source-drain channel are depleted, which can decrease the electron concentration. The source-drain current may decrease.

[0055] In one embodiment, when light is incident on a three-terminal sensing memory device (200), the decay rate of the photoexcitation current may vary due to the electric field effect. When a positive voltage is applied to the gate electrode, the number of electrons in the source-drain channel increases, and the decay rate of the photoexcitation current may decrease. The forget time may increase. When a negative voltage is applied to the gate electrode, the number of electrons in the source-drain channel decreases, and the decay rate of the photoexcitation current may increase. The forget time may decrease. These characteristics can be utilized to control the forget rate of the three-terminal sensing memory device (200) or to implement logic inversion and image inversion operations.

[0056] The structure and material of the three-terminal sensing memory device (200) according to the present disclosure are not limited to the structure shown in a specific embodiment. For example, an example in which a gate electrode (230) is disposed on the upper surface of a substrate (250) has been shown, but this is merely an example and is not limited thereto. Also, the materials of the source electrode (210), drain electrode (220), gate electrode (230), and thin film layer (240) are not limited to a specific embodiment. For example, the source electrode (210) and drain electrode (220) may be formed of a metal such as platinum (Pt), gold (Au), silver (Ag), or copper (Cu), or an alloy thereof. The thin film layer (240) may be formed of various insulating or semiconductor materials, and various materials capable of forming a conductive filament may be used. The three-terminal sensing memory device (200) according to the present disclosure is not limited to a specific combination of materials and may be implemented in a modified example including various electrode materials and thin film materials.

[0058] FIG. 3a is a diagram illustrating a graph showing the generation and decay rates of photoexcitation current according to the voltage applied to the gate electrode in a conductive filament state of high resistance and low resistance according to one embodiment.

[0059] In one embodiment, a three-terminal sensing memory device (e.g., the three-terminal sensing memory device (110) of FIG. 1, the three-terminal sensing memory device (200) of FIG. 2a, the three-terminal sensing memory device (200) of FIG. 2b)) can generate a photoexcitation current in response to incident light. The three-terminal sensing memory device can control the decay rate of the photoexcitation current according to the voltage applied to the gate electrode (e.g., the gate electrode (230) of FIG. 2a, the gate electrode (230) of FIG. 2b).

[0060] In one embodiment, a three-terminal sensing memory device may gradually increase the photoexcitation current (e.g., excitatory post-synaptic current; EPSC) during the learning process by stimulating a light pulse. When a light pulse is applied for a certain period of time or longer, the EPSC may exceed a learning threshold and reach a stable learning state. Subsequently, a forgetting process may proceed when the light is blocked. The EPSC may gradually decrease over time. The decay rate (forgetting rate) of the EPSC may vary depending on the voltage applied to the gate electrode. For example, if a positive voltage is applied to the gate electrode, the EPSC may decrease rapidly and fall below the forgetting threshold within a short period of time. Conversely, if a negative voltage is applied to the gate electrode, the EPSC may decrease slowly and maintain a value close to the initial learning state for a long period of time.

[0061] In one embodiment, the conductive filament of the three-terminal sensing memory device may be in a high resistance state or a low resistance state. The resistance of the conductive filament may vary through set and reset processes depending on the source-gate voltage. The decay rate of the photoexcitation current (EPSC) during the forgetting process may vary depending on the resistance state of the conductive filament.

[0062] For example, if the source-gate voltage is negative and the conductive filament is in a high-resistance state, the source-drain channel is relatively depleted. Consequently, when photostimulation ends, not only are stored charges rapidly emitted or recombinated, but the photoexcitation current in the source-drain channel can decrease more rapidly because the number of carriers supplied from the gate through the high-resistance conductive filament channel is lower than that through the low-resistance conductive filament channel. In the high-resistance state, the decay rate may increase. Conversely, in the low-resistance state, carriers accumulate in the source-drain channel, allowing charges generated by photoexcitation (e.g., photoexcited electrons) to be retained through the channel for a longer period. Furthermore, because carriers are supplied more easily from the gate through the low-resistance conductive filament channel than through the high-resistance conductive filament channel, the photoexcitation current in the source-drain channel can be maintained for a longer duration. When the conductive filament channel is in a low-resistance state, the decay rate of the photoexcitation current formed in the source-drain channel decreases, which can extend the forget time.

[0063] As another example, when the source-gate voltage is positive and the conductive filament is in a low-resistance state, carriers present in the source-drain channel can move through the conductive filament, thereby reducing the carrier concentration within the channel. In the case of a low-resistance conductive filament, the speed of carrier movement through the filament can be faster than in the case of a high-resistance conductive filament. Since the decay rate of the source-drain current is slower in the high-resistance state than in the low-resistance state, the forget time may be longer in the high-resistance state.

[0064] As illustrated in FIG. 3a, the graph in FIG. 3a may be a graph showing that learning is performed by increasing EPSC by applying light stimulation (e.g., UV pulse stimulation (265 nm, width 0.5 s, duty cycle 50%) 100 times) to a 3-terminal sensing memory device (e.g., Pt / Ga2O3 / Pt photoelectric synapse device, Ag / CNT / SiO2 / Si device), and that after the light is applied, the EPSC value is attenuated to 70% of the maximum reached EPSC value. When forgetting was performed with the voltage applied to the gate fixed at 0 mV in a high resistance state, the 1st, 2nd, and 3rd forgetting times increased to 72 s, 77 s, and 105 s, respectively, and when forgetting was performed with the voltage applied to the gate at 3 mV, 0 mV, and -3 mV, the times increased to 52 s, 87 s, and 110 s. In the low-resistance state, when forgetting was performed with the voltage applied to the gate fixed at 0mV, the 1st, 2nd, and 3rd forgetting times increased to 72s, 79s, and 110s, respectively, and when forgetting was performed with the voltage applied to the gate at 3mV, 0mV, and -3mV, they increased to 43s, 88s, and 151s, respectively. In both the high-resistance and low-resistance states, the forgetting time may increase when a negative voltage is applied to the gate electrode. At the same negative gate voltage, the forgetting time in the low-resistance state may increase compared to the high-resistance state.

[0066] FIG. 3b is a diagram illustrating a graph showing the generation and decay rates of photoexcitation current according to the voltage applied to the gate electrode in an electric field effect state according to one embodiment. The three-terminal sensing memory device according to this embodiment can utilize the electric field effect without forming a conductive filament in the thin film layer.

[0067] In one embodiment, the decay rate of the photoexcitation current (EPSC) during the forgetting process of the three-terminal sensing memory device (110) of FIG. 2c of a three-terminal sensing memory device utilizing an electric field effect (e.g., the three-terminal sensing memory device (110) of FIG. 1, the three-terminal sensing memory device (200) of FIG. 2c, and the three-terminal sensing memory device (200) of FIG. 2d) may vary depending on the voltage applied to the gate electrode. For example, when a positive voltage is applied to the gate electrode, the electron concentration in the source-drain channel increases, so the photoexcitation current may be maintained for a long time. The decay rate of the photoexcitation current may decrease. Conversely, when a negative voltage is applied to the gate electrode, the electron concentration in the source-drain channel decreases, so the photoexcitation current may decrease rapidly.

[0068] As illustrated in FIG. 3b, the graph in FIG. 3b may represent a graph showing that learning is performed by increasing EPSC through the application of optical stimulation to a 3-terminal sensing memory device, and that after the light is applied, the EPSC value decays to 70% of the maximum reached EPSC value. When forgetting was performed with the voltage applied to the gate fixed at 0mV, the 1st, 2nd, and 3rd forgetting times increased to 26s, 27s, and 29s, respectively; however, despite the 1st, 2nd, and 3rd learning processes, when forgetting was performed with the voltage applied to the gate at 3mV, 0mV, and -3mV at each forgetting stage, the times decreased to 31s, 28s, and 26s. In terms of electric field effects, when a positive voltage was applied to the gate, the forgetting time increased compared to the 0mV reference. When a negative voltage was applied to the gate, the forgetting time decreased. A 3-terminal sensing memory device can maintain a learning state for a longer period when a positive voltage is applied to the gate electrode due to the electric field effect.

[0069] In one embodiment, the decay rate of the photoexcitation current caused by the electric field effect may be opposite to the decay rate of the photoexcitation current caused by the conductive filament. The three-terminal sensing memory device according to the present embodiment can control the retention time and forgetting rate of the learned signal according to the polarity and magnitude of the voltage applied to the gate electrode even under the same optical stimulation conditions. By utilizing this, the device (e.g., device (100) of FIG. 1) can implement memory enhancement and suppression by utilizing the opposite electric field effect and the characteristics of the conductive filament within a single device.

[0071] FIG. 3c is a diagram illustrating the process of performing image inversion using a conductive filament in a high resistance state and a low resistance state, in a device including a three-terminal sensing memory element according to one embodiment.

[0072] Referring to FIG. 3c, images learned from nine three-terminal sensing memory elements (e.g., the three-terminal sensing memory element (110) of FIG. 1, the three-terminal sensing memory element (200) of FIG. 2a, and the three-terminal sensing memory element (200) of FIG. 2b) can be forgotten over time. Each cell of the array (e.g., each grid in FIG. 3b) can correspond to an individual element. EPSC values ​​during the learning / forgetting process can be expressed as brightness. The darker the color, the higher the EPSC value.

[0073] In one embodiment, a three-terminal sensing memory device can perform learning when a light pulse is applied. A predetermined voltage (e.g., -3mV, 0mV, 3mV) may be applied to the gate electrode. During learning, the EPSC value may increase due to the applied light pulse. When learning is finished, the light may be blocked to initiate forgetting. The decay (forgetting) rate of the EPSC may vary depending on the polarity and magnitude of the voltage applied to the gate electrode. Over time, the relationship between relative current magnitudes may change due to the difference in decay rates between devices.

[0074] For example, as illustrated in FIG. 3c, a first-order learning process can be performed by applying a gate bias of +3 mV to some cells and 0 mV to others. Cells to which +3 mV is applied may decay rapidly, causing the color to fade quickly. Cells to which 0 mV is applied decay slowly, resulting in a darker color than cells to which +3 mV is applied. A second-order learning process can be performed by applying 0 mV to all cells under the same light pulse conditions. Since all cells decay gradually at a similar rate, a uniform decrease in brightness may occur over time. A third-order learning process can be performed by applying a gate bias of -3 mV to some cells and 0 mV to others. After blocking the light, cells to which -3 mV is applied decay slowly, allowing them to maintain a dark brightness for a longer period. After learning and forgetting are finished, the cells in the T-shaped region remain relatively darker as positive and negative voltages of the gate are applied, and the brightness of each cell can be inverted.

[0075] In one embodiment, when a negative voltage is applied to the gate electrode, the low-resistance state allows for the maintenance of a deeper brightness for a longer period because the decay rate of the EPSC after photostimulation is slower than in the high-resistance state. Even when undergoing learning and forgetting processes under the same conditions, the low-resistance state may exhibit a greater contrast in brightness changes than the high-resistance state. For example, in the low-resistance state, certain cells maintain a relatively high current for a long time, while other cells gradually decrease their current and display faint brightness; consequently, the contrast between cells may increase. Conversely, in the high-resistance state, the overall decay proceeds rapidly, so the difference in current between cells may decrease. The contrast may also appear relatively smaller. A 3-terminal sensing memory device in the low-resistance state can maintain a clear pattern or highlight specific areas during image learning and memory processes.

[0076] In one embodiment, a three-terminal sensing memory device can implement image inversion by utilizing different decay rates based on differences in the polarity and magnitude of the applied gate voltage. For example, immediately after learning, a specific region (e.g., the cell in the T-shaped region of FIG. 3c) appears relatively dark, but during forgetting, the cell to which +3 mV is applied fades quickly, while the cell to which -3 mV is applied maintains a high EPSC value for a longer period. As the dark background region becomes relatively lighter over time, and conversely, the T-shaped region that was light during learning becomes darker, the T-shaped image may appear in an inverted form relative to the background.

[0078] FIG. 3d is a diagram illustrating the process of an image inversion using an electric field effect in a device including a three-terminal sensing memory element according to one embodiment. The three-terminal sensing memory element according to this embodiment (e.g., the three-terminal sensing memory element (110) of FIG. 1, the three-terminal sensing memory element (200) of FIG. 2c, and the three-terminal sensing memory element (200) of FIG. 2d)) can utilize an electric field effect without forming a conductive filament in a thin film layer.

[0079] In one embodiment, the decay (forgetting) rate of the EPSC may vary depending on the polarity and magnitude of the voltage applied to the gate electrode. Over time, the relationship between relative current magnitudes may change due to the difference in decay rates between the devices. For example, as shown in FIG. 3d, a first-order learning process may be performed by applying a gate bias of +3 mV to some cells and 0 mV to the rest. Cells to which +3 mV is applied may decay slowly and have a darker color than other cells. Cells to which 0 mV is applied decay relatively quickly and may have a lighter color than cells to which +3 mV is applied. A second-order learning process may be performed by applying 0 mV to all cells and using the same light pulse conditions. Since all cells decay gradually at a similar rate, a uniform decrease in brightness may appear over time. A third-order learning process may be performed by applying a gate bias of -3 mV to some cells and 0 mV to the rest. After blocking light, cells to which -3 mV is applied may decay rapidly, causing the brightness to decrease quickly. After learning and forgetting are finished, as positive and negative voltages are applied to the gate, cells in the T-shaped region may remain relatively fainter, and the brightness of each cell may be inverted.

[0080] In one embodiment, a three-terminal sensing memory device can implement image inversion by utilizing different decay rates based on differences in the polarity and magnitude of the applied gate voltage. The three-terminal sensing memory device can utilize the electric field effect and the conductive filament to cause opposite decay rates of photoexcitation current when the same gate voltage is applied. For example, when the voltage applied to the gate electrode is positive, the electric field effect can be used to reduce the decay rate of a specific cell, allowing it to maintain a deep color for a longer period, while the conductive filament can be used to increase the decay rate of another cell, thereby reducing the contrast.

[0082] FIG. 4a is a diagram for explaining a graph showing the input and output of a three-terminal sensing memory device that performs logic gate operations using a conductive filament in a high-resistance state and a low-resistance state according to one embodiment.

[0083] In one embodiment, a three-terminal sensing memory device (e.g., the three-terminal sensing memory device (110) of FIG. 1, the three-terminal sensing memory device (200) of FIG. 2a, the three-terminal sensing memory device (200) of FIG. 2b)) can perform the operation of a logic gate according to the polarity of the voltage applied to the gate electrode (e.g., the gate electrode (230) of FIG. 2a, the gate electrode (230) of FIG. 2b) using a conductive filament. The logic gate can take the magnitude of the voltage applied to the gate electrode and the presence or absence of incident light as inputs.

[0084] The graph shown in FIG. 4a can represent the source-drain current of a three-terminal sensing memory device when input 1 is the voltage applied to the gate electrode (±10, ±100mV) and input 2 is the presence or absence of incident light (ON / OFF). The three-terminal sensing memory device can output 1 if the source-drain current value exceeds 100pA, and 0 if it is lower. When the voltage applied to the gate electrode is positive, the source-drain current may be greater than the threshold current (e.g., 100pA) when the magnitude of the applied voltage is 100mV and light is incident. When the voltage applied to the gate electrode is positive, the three-terminal sensing memory device using a conductive filament can operate as an AND gate. When the voltage applied to the gate electrode is negative, the source-drain current may be greater than the threshold current, except in the case where the magnitude of the applied voltage is 10mV and light is not incident. When the voltage applied to the gate electrode is negative, a 3-terminal sensing memory device using a conductive filament can operate as an OR gate. The 3-terminal sensing memory device can perform the operation of different logic gates by switching the polarity of the voltage applied to the gate. The 3-terminal sensing memory device can adjust sensitivity and safety by controlling the current magnitude and noise margin according to the resistance state (e.g., HRS, LRS). The 3-terminal sensing memory device can perform different logic operations on a single device.

[0086] FIG. 4b is a diagram illustrating a graph showing the input and output of a three-terminal sensing memory device that performs logic gate operations using an electric field effect according to one embodiment. The three-terminal sensing memory device according to this embodiment can utilize an electric field effect without forming a conductive filament in the thin film layer.

[0087] In one embodiment, a three-terminal sensing memory device (e.g., the three-terminal sensing memory device (110) of FIG. 1, the three-terminal sensing memory device (200) of FIG. 2c, the three-terminal sensing memory device (200) of FIG. 2d)) can perform the operation of a logic gate according to the polarity of the voltage applied to the gate electrode (e.g., the gate electrode (230) of FIG. 2c, the gate electrode (230) of FIG. 2d) using an electric field effect. The logic gate can take the magnitude of the voltage applied to the gate electrode and the presence or absence of incident light as inputs.

[0088] The graph shown in FIG. 4b can represent the source-drain current of a three-terminal sensing memory device utilizing the electric field effect when input 1 is the voltage applied to the gate electrode (±10, ±100mV) and input 2 is the presence or absence of incident light (ON / OFF). The three-terminal sensing memory device can output 1 if the source-drain current value exceeds 100pA, and output 0 if it is lower. When the voltage applied to the gate electrode is a positive voltage, the source-drain current may be smaller than the threshold current (e.g., 100pA) when the magnitude of the applied voltage is 10mV and no light is incident. When the voltage applied to the gate electrode is a positive voltage, the three-terminal sensing memory device utilizing the electric field effect can operate as an OR gate. When the voltage applied to the gate electrode is negative, the magnitude of the applied voltage is 100mV, and except for the case where light is incident, the source-drain current may be smaller than the threshold current. When the voltage applied to the gate electrode is negative, a 3-terminal sensing memory device utilizing the electric field effect can operate as an AND gate. The 3-terminal sensing memory device can perform the operation of different logic gates by switching the polarity of the voltage applied to the gate.

[0089] In one embodiment, a three-terminal sensing memory device can operate as an AND gate or an OR gate depending on the voltage applied to the gate electrode by utilizing the fact that when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect is opposite to the source-drain current change caused by the conductive filament. Different logic operations can be performed in a single three-terminal sensing memory device. The three-terminal sensing memory device can switch logic gates according to the polarity of the applied gate voltage.

[0091] FIG. 5 is a flowchart for explaining the operation method of a device including a three-terminal sensing memory element according to one embodiment.

[0092] Operations of a device (e.g., device (100) of FIG. 1) comprising a three-terminal sensing memory element (e.g., three-terminal sensing memory element (110) of FIG. 1, three-terminal sensing memory element (200) of FIG. 2a, three-terminal sensing memory element (200) of FIG. 2b, three-terminal sensing memory element (200) of FIG. 2c, three-terminal sensing memory element (200) of FIG. 2d)) can be performed by a control circuit (e.g., control circuit (120) of FIG. 1). The order of the illustrated operations may be changed, and multiple operations may be performed sequentially or simultaneously.

[0093] In operation (510), the device may apply a voltage to a gate electrode (e.g., gate electrode (230) in Fig. 2a, gate electrode (230) in Fig. 2b, gate electrode (230) in Fig. 2c, gate electrode (230) in Fig. 2d) so that a channel for electron flow is formed between the source electrode of the three-terminal sensing memory element (e.g., source electrode (210) in Fig. 2a, source electrode (210) in Fig. 2b, source electrode (210) in Fig. 2c, source electrode (210) in Fig. 2d) and the drain electrode of the three-terminal sensing memory element (e.g., drain electrode (220) in Fig. 2a, drain electrode (220) in Fig. 2b, drain electrode (220) in Fig. 2d). The voltage applied to the gate electrode may be applied as any waveform, such as, for example, DC, pulse, pulse train, ramp, stair-step, or PWM, but is not limited to these examples. The waveform of the applied voltage may vary depending on the purpose (e.g., learning, forgetting). The control circuit may adjust at least one of the voltage magnitude, pulse width, period, duty cycle, number of pulses, or delay time. The control circuit may determine the voltage applied to the gate electrode for the purpose, such as controlling the resistance of the conductive filament or controlling the current flowing through the channel.

[0094] In one embodiment, the device can control the degree of formation of conductive filaments within a thin film layer (e.g., thin film layer (240) in FIG. 2a, thin film layer (240) in FIG. 2b) and the carrier concentration of the source-drain channel by controlling the polarity and magnitude of the applied source-gate or drain-gate voltage. The device can control the magnitude and decay rate of the source-drain current. For example, if the voltage applied to the gate electrode is positive, current decay proceeds rapidly, and the learned signal may be quickly extinguished. Conversely, if a negative voltage is applied to the gate electrode, the signal may be maintained for a longer period. These characteristics allow for the control of learning / forgetting characteristics within a single device and enable the implementation of image inversion or logic gate inversion.

[0095] In operation (520), the device can control the resistance of the conductive filament or the carrier concentration in the channel due to electric field effects by adjusting the voltage applied to the gate electrode. The device can redistribute oxygen vacancies within the thin film layer and change the resistance of the conductive filament by adjusting the polarity, magnitude, pulse width, and / or number of pulses of the voltage applied to the gate electrode. For example, if a voltage greater than the set voltage is applied to the source-gate electrode, the conductive filament may be switched to a low-resistance state. Conversely, if a voltage greater than the reset voltage is applied to the source-gate electrode, the conductive filament may be switched to a low-resistance state. Additionally, the device may increase the carrier concentration in the source-drain channel when a positive voltage is applied to the gate electrode due to electric field effects, and decrease the carrier concentration in the source-drain channel when a negative voltage is applied to the gate electrode.

[0096] In one embodiment, the resistance of the conductive filament or the channel carrier concentration due to the electric field effect can determine the current flowing in the source-drain channel and the rate of current decay. For example, when the conductive filament is in a low-resistance state, the magnitude of the current flowing in the source-drain channel increases under a negative gate voltage, and the rate of current decay may decrease. When a positive voltage is applied to the gate electrode due to the electric field effect, carriers accumulate in the source-drain channel, increasing the source-drain current and slowing down the decay rate. When a negative voltage is applied to the gate electrode, carriers are depleted in the source-drain channel, causing the current to decrease and the decay rate to increase. Controlling the resistance of the conductive filament or the carrier concentration within the source-drain channel can be performed independently for each three-terminal sensing memory device in the array. Image inversion and logic gate inversion can be implemented by adjusting the relative retention time between the three-terminal sensing memory devices.

[0097] In operation (530), the device can control at least one of the magnitude and rate of change of the source-drain current. The device can control the current flowing through the channel and the rate of change of the current (e.g., decay (forgetting) rate) by combining the voltage applied to the electrode, the source-drain voltage, and the optical stimulation. For example, when a positive voltage is applied to the gate electrode of a three-terminal sensing memory device with a conductive filament formed thereon, the source-drain channel is depleted, and the current flowing through the channel may decrease. The current flowing through the channel may decay rapidly after the optical stimulation ends. Conversely, when a negative voltage is applied to the gate electrode of a three-terminal sensing memory device with a conductive filament formed thereon, the source-drain channel is accumulated, and the current flowing through the channel may increase. The current flowing through the source-drain channel may decay slowly even after the optical stimulation ends, maintaining a high value for a long time. Even when learning is performed under the same optical stimulation conditions, the forgetting rate may vary depending on the polarity and magnitude of the voltage applied to the gate electrode. By utilizing these characteristics, the device can perform control of the retention time of a learned signal, image inversion, and / or logic gate operations at the single element or array level.

[0098] In operation (540), the device can measure the source-drain current flowing through the channel. The source-drain current may include a photoexcitation current generated by light incident on a three-terminal sensing memory element. The measured current may be compared to a predetermined threshold value and output as a digital signal (e.g., logic gate output), or used as an analog signal (e.g., brightness of an image) depending on its relative magnitude. Since the magnitude and decay rate of the source-drain current depend on the polarity and magnitude of the gate voltage, different outputs may appear even under the same light stimulation conditions.

[0099] In one embodiment, the device may output a digital signal by comparing the current flowing through the source-drain channel with a predetermined threshold value. For example, if there is no optical stimulation or the voltage applied to the gate electrode is low, the current flowing through the channel may be below the threshold value, a logic value of '0' may be output. Conversely, if there is optical stimulation and the voltage applied to the gate electrode is high, the current flowing through the channel may be above the threshold value, a logic value of '1' may be output. The device may perform a logic gate operation by comparing the magnitude of the current flowing through the source-drain channel with the threshold value.

[0100] In one embodiment, the device may output the relative magnitude of the current flowing through the source-drain channel as an analog signal. For example, by comparing the current values ​​measured at each of the plurality of cells included in the array, a component with a large current may be represented as a darker contrast (bright pixel), and a component with a small current may be represented as a lighter contrast (dark pixel). The device may form a continuous image proportional to the magnitude of the current. The device may implement visual changes such as the maintenance, gradual decay, or inversion of an image pattern by utilizing the difference in the decay rate of the current over time.

[0102] The embodiments described above may be implemented as hardware components, software components, and / or combinations of hardware and software components. For example, the devices, methods, and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0103] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or command the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, or computer storage medium or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0104] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

[0105] Although the embodiments have been described above with reference to the limited drawings, those skilled in the art can apply various technical modifications and variations based thereon. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0106] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 An apparatus comprising a three-terminal sensing memory element, the apparatus comprises: the three-terminal sensing memory element; and a control circuit for controlling a signal applied to each terminal of the three-terminal sensing memory element, wherein the three-terminal sensing memory element comprises: upper electrodes including a source electrode corresponding to a first terminal among the three terminals and a drain electrode corresponding to a second terminal among the three terminals; a lower electrode including a gate electrode corresponding to a third terminal among the three terminals; and a thin film layer located between the upper electrodes and the lower electrode and forming a conductive filament (CF), wherein the three-terminal sensing memory element generates a photoexcitation current in response to light incident on the three-terminal sensing memory element, and when the same gate voltage is applied to the gate electrode, an electric field effect formed between the gate electrode, the source electrode, and the drain electrode;The source-drain current change caused by FE) is opposite to the source-drain current change caused by the conductive filament, and when the same gate voltage is applied to the gate electrode, the decay rate of the photo-excitation current caused by the electric field effect is opposite to the decay rate of the photo-excitation current caused by the conductive filament, and the control circuit controls the resistance of the conductive filament or the carrier concentration in the channel formed between the source electrode and the drain electrode according to the electric field effect by adjusting the voltage applied to the gate electrode, and controls the current flowing through the conductive filament and the source-drain current flowing in the channel formed between the source electrode and the drain electrode by adjusting the voltage applied to the gate electrode - at least one of the magnitude and rate of change of the source-drain current is determined according to the resistance of the conductive filament or the carrier concentration -, controls the decay rate of the photo-excitation current by adjusting the voltage applied to the gate electrode, and the source-drain The current is a device including the above photo-excitation current.; Claim 2 In claim 1, the three-terminal sensing memory element further comprises a semiconductor layer interposed between the upper electrodes and the thin film layer. Claim 3 delete Claim 4 delete Claim 5 In claim 1, the three-terminal sensing memory element performs the operation of a logic gate according to the polarity of the voltage applied to the gate electrode, and the logic gate takes as input the magnitude of the voltage applied to the gate electrode and the presence or absence of the incident light. Claim 6 In claim 5, the three-terminal sensing memory element operates as an AND gate or an OR gate depending on the voltage applied to the gate electrode by utilizing the fact that when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect is opposite to the source-drain current change caused by the conductive filament. Claim 7 A method of operation of a device comprising a three-terminal sensing memory element and a control circuit, comprising: applying a voltage to a gate electrode such that a channel for electron flow is formed between the source electrode of the three-terminal sensing memory element and the drain electrode of the three-terminal sensing memory element; The method includes an operation of measuring a source-drain current flowing in the channel, wherein the source-drain current includes a photo-excitation current generated by light incident on the three-terminal sensing memory device, wherein when the same gate voltage is applied to the gate electrode, the source electrode and the drain electrode change caused by the electric field effect is opposite to the source-drain current change caused by the conductive filament, wherein when the same gate voltage is applied to the gate electrode, the decay rate of the photo-excitation current caused by the electric field effect is opposite to the decay rate of the photo-excitation current caused by the conductive filament, and the operation of applying a voltage to the gate electrode is an operation of controlling the resistance of the conductive filament or the carrier concentration in the channel according to the electric field effect by adjusting the voltage applied to the gate electrode; A method of operation comprising controlling at least one of the magnitude and rate of change of a current flowing in a conductive filament and a source-drain current flowing in a channel formed between the source electrode and the drain electrode by adjusting a voltage applied to the gate electrode, wherein the operation of controlling the rate of change of the source-drain current includes controlling the decay rate of the photoexcitation current by adjusting a voltage applied to the gate electrode. Claim 8 In claim 7, the method of operation further comprises a semiconductor layer interposed between the upper electrodes, including the source electrode and the drain electrode, and the thin film layer, wherein the three-terminal sensing memory element further comprises the source electrode and the drain electrode. Claim 9 delete Claim 10 delete Claim 11 In claim 7, the method of operation further includes an operation of performing a logic gate operation according to the polarity of the voltage applied to the gate electrode, wherein the logic gate takes as input the magnitude of the voltage applied to the gate electrode and the presence or absence of the incident light. Claim 12 In claim 11, the operation of performing the operation of the logic gate comprises an operation of operating as an AND gate or an OR gate depending on the voltage applied to the gate electrode by utilizing the fact that when the same gate voltage is applied to the gate electrode, the source-drain current change caused by the electric field effect is opposite to the source-drain current change caused by the conductive filament.

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