Memory and its control method, electronic device

Abstract

The present invention provides a memory and a method for controlling the same, and an electronic device, wherein in a first chip of the memory, each local bit line is coupled to a common bit line on one side through a respective bit line selector, and each local bit line is coupled to a common bit line on the other side through a respective precharge switch; the bit line selector is for receiving a subword line driving signal and, based on the subword line driving signal, selectively connecting a common bit line connected to a connected local bit line; and the precharge switch is for receiving a subword line driving complementary signal and, based on the subword line driving complementary signal, selectively connecting a common bit line connected to a connected local bit line.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims priority to a Chinese patent application filed with the Chinese Intellectual Property Office on December 29, 2023, with application number 202311869141.2 and application title "Memory and method for controlling the same, electronic device," the entire contents of which are incorporated by reference into this application.

[0003] The present invention relates to the field of semiconductors, and in particular to memory and a method for controlling the same, and electronic devices. Background Technology

[0004] As semiconductor technology advances, semiconductor memory is widely applied in electronic devices. Dynamic Random Access Memory (DRAM) is a type of volatile memory, and due to its fast access speed, it is frequently used as cache memory.

[0005] Dynamic random access memory mainly consists of two parts: a peripheral circuit and a storage array (core). To further improve storage density, three-dimensional DRAM (3D DRAM) installs the peripheral circuit and the storage array (core) on two separate chips, and performs the connection by bonding the two chips. At the same time, as the three-dimensional structure of the storage array becomes more complex, additional control logic is required. The problem to be solved

[0006] Embodiments of the present invention provide a memory and a method for controlling the memory and an electronic device. means of solving the problem

[0007] The technical solution of the present invention is implemented as follows.

[0008] In a first aspect, the present invention provides a memory, wherein the memory comprises a first chip, the first chip comprises a plurality of storage array tiles, each of the storage array tiles comprises a plurality of local bit lines and a plurality of common bit lines, wherein the local bit lines extend along a first direction and the common bit lines extend along a second direction, and the common bit lines are each present on both sides along the first direction of the local bit lines; and the first direction and the second direction intersect each other;

[0009] Each of the above local bit lines is coupled to the above common bit line on one side via each bit line selector, and each of the above local bit lines is coupled to the above common bit line on the other side via each precharge switch;

[0010] The bit line selector is configured to receive a subword line driving signal and, based on the subword line driving signal, selectively connect a common bit line connected to a connected local bit line;

[0011] The above precharge switch is configured to receive a subword line driving complement signal and, based on the subword line driving complement signal, selectively connect a common bit line connected to a connected local bit line; wherein, the subword line driving signal and the subword line driving complement signal are both generated by decoding a row address signal among the command address signals received by the memory.

[0012] In some embodiments, each of the storage array tiles comprises a plurality of sub-array tiles arranged sequentially along a second direction, each of the sub-array tiles comprises a plurality of storage regions stacked sequentially along a third direction, each of the storage regions comprises two storage layer groups arranged along a first direction; each of the storage layer groups has a plurality of local bit lines installed, a first common bit line installed on the outer side of each storage layer group, far from another storage layer group of the same storage region, and a second common bit line installed on the inner side of each storage layer group, close to another storage layer group of the same storage region.

[0013] For each of the above storage layer groups, each of the above local bit lines is coupled to the second common bit line through each of the bit line selectors, and each of the above local bit lines is coupled to the first common bit line through each of the above precharge switches.

[0014] In some embodiments, each of the storage array tiles comprises a plurality of sub-array tiles arranged sequentially along a second direction, each of the sub-array tiles comprises a plurality of storage regions stacked sequentially along a third direction, each of the storage regions comprises two storage layer groups arranged along a first direction; each of the storage layer groups has a plurality of local bit lines installed, a first common bit line installed on the outer side of each storage layer group, far from another storage layer group of the same storage region, and a second common bit line installed on the inner side of each storage layer group, close to another storage layer group of the same storage region.

[0015] For the same sub-array tiles mentioned above, assign numbers to the storage area along the third direction;

[0016] In the case of the above storage area with an odd number, each of the above local bit lines is coupled to the first common bit line through each of the above bit line selectors, and each of the above local bit lines is coupled to the second common bit line through each of the above precharge switches;

[0017] For the storage area with an even number, each of the above local bit lines is coupled to the second common bit line through each of the bit line selectors, and each of the above local bit lines is coupled to the first common bit line through each of the above precharge switches.

[0018] In some embodiments, the storage array tile further comprises a plurality of local word lines, each of the local word lines penetrating a plurality of storage layer groups stacked along a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction;

[0019] A plurality of the local word lines aligned along the first direction passing through the same storage layer group form a single sub-word line group;

[0020] One of the above-mentioned local bit lines has a corresponding relationship with one of the above-mentioned subword line groups, and a storage unit is formed at the intersection of each of the above-mentioned local word lines corresponding to the local bit line;

[0021] All local word lines in the same subword line group share the same subword line driving signal and the same subword line driving complementary signal, and the bit line selector of the local bit line receives the subword line driving signal of the corresponding subword line group, and the precharge switch of the local bit line receives the subword line driving complementary signal of the corresponding subword line group.

[0022] In some embodiments, each of the storage array tiles further includes a plurality of common word lines extended along a second direction;

[0023] In each of the above sub-array tiles, local word lines are sequentially assigned independent numbers, and local word lines with the same number in different above sub-array tiles are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal.

[0024] In some embodiments, in the storage array tile, the common word lines are sequentially numbered along a first direction, and N common word lines that are consecutive numbers form a main word line group;

[0025] The above memory includes a decoding unit and a plurality of subword line driving units, where N is a positive integer;

[0026] The decoding unit is configured to decode the row address signal to generate a main word line driving signal, a sub-word line driving signal, and a sub-word line driving complementary signal for each of the common word lines;

[0027] The sub-word line driving unit is coupled to one of the common word lines and is configured to receive a corresponding main word line driving signal, a corresponding sub-word line driving signal, and a corresponding sub-word line driving complementary signal, and to turn on or off the coupled common word line based on these;

[0028] Here, the two storage layer groups of each storage area are sequentially referred to as the first storage layer group and the second storage layer group along the first direction, the main word line driving signal is for selecting one main word line group in both the first storage layer group and the second storage layer group, and the sub word line driving signal and the sub word line driving complementary signal are for selecting one common word line in the main word line group selected in the first storage layer group, or for selecting one common word line in the main word line group selected in the second storage layer group.

[0029] In some embodiments, the sub-word line driving unit includes a first switching tube, a second switching tube, and a third switching tube;

[0030] The control terminals of the first switching tube and the second switching tube both receive the main word line driving signal, the first terminal of the first switching tube receives the sub word line driving signal, the second terminal of the first switching tube, the first terminal of the second switching tube, and the first terminal of the third switching tube are all connected to the common word line, the second terminal of the second switching tube and the second terminal of the third switching tube are all connected to the power supply terminal, and the control terminal of the third switching tube receives the sub word line driving complementary signal.

[0031] In some embodiments, the memory further comprises a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip;

[0032] The second chip above includes a detection magnification area;

[0033] In the first chip above, a step contact structure is installed between two adjacent storage layer groups along the first direction, and the common bit line directly connected to the bit line selector is coupled to the detection enlargement area through the step contact structure.

[0034] In a second aspect, an embodiment of the present invention provides a method for controlling a memory, wherein a first chip in the memory comprises a plurality of storage array tiles, each of the storage array tiles comprises a plurality of local bit lines and a plurality of common bit lines, each of the local bit lines is coupled to a common bit line on one side via a bit line selector, and each of the local bit lines is coupled to a common bit line on the other side via a respective precharge switch;

[0035] The above memory control method is,

[0036] A step of receiving a command address signal and decoding a row address signal among the command address signals to generate a plurality of main word line driving signals, a plurality of sub-word line driving signals, and a plurality of sub-word line driving complementary signals;

[0037] A step of controlling whether the corresponding bit line selector connects to a common bit line connected to a local bit line based on each of the above subword line driving signals; and

[0038] Based on each of the above subword line driving complementary signals, the step of controlling whether the corresponding precharge switch connects to the common bit line connected to the local bit line connected thereto is included.

[0039] In some embodiments, each of the storage array tiles comprises a plurality of sub-array tiles arranged sequentially along a second direction, each of the sub-array tiles comprises a plurality of storage regions stacked sequentially along a third direction, and each of the storage regions comprises two storage layer groups arranged along a first direction; each of the storage layer groups has a plurality of local bit lines installed, and each of the storage layer groups has a common bit line installed on each side along the first direction;

[0040] The above storage array tile further includes a plurality of local word lines, each of which penetrates a plurality of storage layer groups stacked along a third direction; a plurality of the local word lines aligned along a first direction passing through the same storage layer group form a single sub-word line group, and all local word lines in the same sub-word line group share the same sub-word line driving signal and the same sub-word line driving complementary signal; one of the local bit lines has a corresponding relationship with one of the sub-word line groups, and a single storage unit is formed at the intersection of each local word line corresponding to the local bit line;

[0041] Each of the above subword line groups has a subword line driving signal and a subword line driving complementary signal; the control method of the memory is,

[0042] A step of transmitting a subword line driving signal of the above subword line group to a bit line selector of the corresponding local bit line; and

[0043] The method further includes the step of transmitting the subword line driving complement signal of the above subword line group to the precharge switch of the corresponding local bit line.

[0044] In some embodiments, local word lines in each of the sub-array tiles are sequentially assigned independent numbers, and local word lines with the same number in different sub-array tiles are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal; in the storage array tile, the common word lines are assigned numbers along a first direction, and N common word lines with consecutive numbers form a main word line group;

[0045] Each of the above storage regions has two storage layer groups sequentially referred to as the first storage layer group and the second storage layer group along a first direction; and the control method of the memory is,

[0046] A step of selecting one main word line group from both the first storage layer group and the second storage layer group based on the main word line driving signal;

[0047] A step of selecting one common word line from the main word line group selected in the first storage layer group or the main word line group selected in the second storage layer group, based on the sub-word line driving signal and the sub-word line driving complementary signal; and

[0048] It further includes the step of turning on the selected common word line and executing the operation indicated by the command address signal.

[0049] In a third aspect, an embodiment of the present invention provides an electronic device, said electronic device includes a memory of the first aspect. Effects of the invention

[0050] Embodiments of the present invention provide a memory, a method for controlling the same, and an electronic device. By controlling the operating state of a local bit line precharge switch and a bit line selector using a subword line driving signal and a subword line driving complementary signal generated by decoding a row address signal, although the three-dimensional memory additionally introduces a precharge switch and a bit line selector, there is no need to additionally introduce control information and unnecessary decoding logic, thereby improving control efficiency and reducing redundant elements. Brief explanation of the drawing

[0051] Figures 1a / 1b are example diagrams of the structure of a storage array tile of the first chip. Figure 2 is an example of a cross-sectional structure of a storage array tile. Figure 3 is an example of a cross-sectional structure of a different storage array tile. FIG. 4 is an example diagram 1 of the structure of a sub-array tile provided in an embodiment of the present invention. FIG. 5 is an example diagram of a stacking structure of memory provided in an embodiment of the present invention. FIG. 6 is an example diagram 2 of the structure of a sub-array tile provided in an embodiment of the present invention. FIG. 7 is an example diagram of the structure of another storage array tile provided in an embodiment of the present invention. FIGS. 8a / 8b is an example of a cross-sectional structure of a storage array tile provided in an embodiment of the present invention. FIG. 9 is an example diagram of the circuit structure of the first chip provided in an embodiment of the present invention. FIG. 10 is an example diagram of the structure of a subword line driving unit provided in an embodiment of the present invention. FIG. 11 is a flowchart illustrating a control method provided in an embodiment of the present invention. Specific details for implementing the invention

[0052] To make the purpose, technical solution, and advantages of the present invention more clear, the technical solution of the present invention is described in further detail below by combining the drawings and embodiments. The described embodiments should not be construed as a limitation to the present invention, and all other embodiments obtained by a person skilled in the art without creative labor fall within the scope of the claims of the present invention.

[0053] In the description below, "some embodiments" are referred to and describe a subset of all possible embodiments, but it can be understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with one another without contradiction.

[0054] If descriptions such as "First / Second" appear in the application file, the following description is added. In the following description, the terms "First / Second / Third" mentioned are merely for distinguishing similar objects and do not represent a specific order of objects. It is understood that, where permissible, "First / Second / Third" may be interchanged with a specified order or sequence, so that the embodiments of the invention described herein may be implemented in an order other than that shown or described herein.

[0055] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as generally understood by a person skilled in the art of the embodiments of this invention. The terms used in this invention are intended only to explain the purpose of the embodiments of this application and are not intended to limit the embodiments of this invention.

[0056] Noun interpretation:

[0057] WL(WordLine): Word Line;

[0058] BL(BitLine): Bit Line:

[0059] CMOS (Complementary Metal Oxide Semiconductor): Complementary metal oxide semiconductor;

[0060] TSV (Through Silicon Via): Silicon through-via;

[0061] Mat(Memory Array Tile): Storage array tile.

[0062] Before introducing embodiments of the present invention, if we first define three directions describing a three-dimensional structure that can be used on a plane mentioned in the embodiments below, taking Cartesian coordinates as an example, the three directions may include a first direction, a second direction, and a third direction.

[0063] A semiconductor chip may include a top surface located on the front and a bottom surface located on the rear opposite to the front; when the flatness of the top surface and the bottom surface is ignored, a direction in which the top surface and the bottom surface of the semiconductor chip intersect (e.g., vertically) is defined as a third direction; at the same time, the extension direction of a local bit line in the semiconductor chip is defined as a first direction, and the extension direction of a local word line in the semiconductor chip is defined as a second direction, and the first direction and the second direction are mutually at odds.

[0064] In the case of 3D DRAM, a first chip and a second chip are stacked along a third direction, and a storage array (Core) is distributed in the first chip, while a peripheral control area (Periphery), a sensing magnification area, etc. are distributed in the second chip. In the case of the first chip, the storage array (Core) includes a large number of storage units, and these storage units are also partitioned into multiple storage array tiles (Mat) to perform control and management more effectively.

[0065] Referring to FIG. 1a, an example diagram of the structure of a storage array tile (11) of a first chip is illustrated. As shown in FIG. 1a, each storage array tile (11) includes a plurality of sub-array tiles Sub Mat0, Sub Mat1, Sub Mat2...... arranged sequentially along a second direction, and each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, and each storage region includes two storage layer groups arranged along a first direction, each referred to as the first storage layer group and the second storage layer group, and a staircase structure (14) is installed between the first storage layer group and the second storage layer group. Referring to FIG. 1b, the locations of a local bit line Local BL, a common bit line Common BL, a local word line Local WL, and a common word line Common WL are illustrated in FIG. 1b. As illustrated in FIG. 1b, local word lines penetrate a plurality of storage layer groups along a third direction, and at each sub-array tile, local word lines with the same number are coupled to the same common word line along a second direction, and the common word line extends along the second direction; at the same time, each storage layer group includes a plurality of local bit lines extended along a first direction, and one common bit line is installed on each left and right side of each storage layer group.

[0066] Referring to FIGS. 2 and FIGS. 3, both are cross-sectional examples along the third direction of a storage array tile, and both illustrate that the storage array tile includes 20 sub-array tiles (Sub Mat0, Sub Mat1......Sub Mat19). As shown in FIG. 2, a first common bit line is installed on the outer side of each storage layer group (referring to the side far from another storage layer group in the same storage area), and a second common bit line is installed on the inner side of each storage layer group (close to another storage layer group in the same storage area). Referring to FIG. 3, all local bit lines of the storage layer group are connected to the first common bit line through a precharge switch Eq, and all local bit lines of the storage layer group are connected to the second common bit line through a bit line selector Se, and at the same time, a step contact structure is installed between the first storage layer group and the second storage layer group, and each second common bit line is coupled to a detection amplifier in the detection expansion area through the step contact structure.

[0067] For example, when reading data, a specific common word line is opened to turn on multiple groups of target storage units, and each group of target storage units is aligned along a third direction, and at the same time, the bit line selector Se of the local bit line connected to each group of target storage units is connected, and at this time, each target storage unit is connected to its respective corresponding second common bit line, so that the second common bit line of one group aligned along the third direction shares charge with each target storage unit and undergoes detection amplification, and after undergoing detection amplification, is placed at a high potential or a low potential (determined by the data stored in the target storage unit); and at the same time, the bit line selector Se of the unselected local bit line is disconnected and the precharge switch Eq is opened, and all first common bit lines are charged to the precharge potential, so that all unselected local bit lines are placed at the precharge potential. Here, the precharge potential can be an intermediate potential, and the intermediate potential can be half of the storage array power supply voltage (Vblh), i.e., intermediate potential = 1 / 2Vblh.

[0068] In summary, for a 3D DRAM, local bit lines of the same storage layer group share one first common bit line and one second common bit line, and since the bit line selector Se selects whether to access the second common bit line and the precharge switch Eq selects whether to access the first common bit line, additional control logic for the bit line selector Se / precharge switch Eq must be designed.

[0069] Each embodiment of the present invention is described below by combining the drawings.

[0070] In one embodiment of the present invention, a memory is provided, the memory includes a first chip, and the first chip includes a plurality of storage array tiles (11). Referring to FIG. 4, an exemplary diagram of the local structure of the storage array tile (11) provided in the embodiment of the present invention is illustrated, specifically an exemplary diagram of the remaining part after omitting the step contact structure of one sub-array tile (e.g., Sub Mat0, Sub Mat1, etc.). As illustrated in FIG. 4, each storage array tile includes a plurality of local bit lines and a plurality of common bit lines (e.g., a first common bit line (12) and a second common bit line (13) in FIG. 4), the local bit lines extend along a first direction, and the common bit lines extend along a second direction, and there is one common bit line on each side along the first direction of the local bit lines; the first direction and the second direction intersect each other;

[0071] Each local bit line is coupled to a common bit line on one side via a respective bit line selector Se, and each local bit line is coupled to a common bit line on the other side via a respective precharge switch Eq;

[0072] The bit line selector Se is the subword line drive signal Phdec It is configured to receive (i is a positive integer) and, based thereon, selectively connect a connected local bit line and a connected common bit line;

[0073] The precharge switch Eq is the subword line drive complementary signal PhdecN It is configured to receive (where i is a positive integer) and, based on this, selectively connect the connected local bit line and the connected common bit line.

[0074] Here, the subword line driving signal Phdec and subword line driving complementary signal PhdecN All of these are generated by decoding the row address signal among the command address signals received by the memory. Generally, the subword line drive complement signal PhdecN is a subword line driving signal Phdec It is obtained by reverse processing. At the same time, in some embodiments, the subword line driving complementary signal PhdecN is a subword line driving signal Phdec It can be obtained through inverse processing and delay processing, and the subword line driving signal Phdec and subword line driving complementary signal PhdecN It is not a completely strict reversed state.

[0075] It should be understood that the row address signal is intended to indicate the word line information selected (i.e., turned on) in this operation; that is, the embodiment of the present invention controls the operating state of the local bit line precharge switch Eq and bit line selector Se by multiplexing the word line information, and the specific principle can be referred to in the following explanation. Therefore, in the case of a three-dimensional memory, although the precharge switch Eq and bit line selector Se are additionally introduced, there is no need to additionally introduce control information and unnecessary decoding logic, thereby improving control efficiency and reducing redundant elements.

[0076] It needs to be explained that while FIG. 4 illustrates that each storage layer group includes four local bit lines, this does not constitute a relevant limitation.

[0077] Referring to FIGS. 1a and 1b, each storage array tile includes a plurality of sub-array tiles Sub Mat0, Sub Mat1, Sub Mat2...... arranged sequentially along a second direction, and each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction. FIGS. 1a and 1b illustrate examples where each sub-array tile includes five storage regions, but the number of storage regions may be greater. Each storage region includes a first storage layer group and a second storage layer group arranged along a first direction.

[0078] In some embodiments, as shown in FIG. 4, each storage layer group has a plurality of local bit lines installed, and a first common bit line (12) is installed on the outer side of each storage layer group, far from other storage layer groups in the same storage area, and a second common bit line (13) is installed on the inner side of each storage layer group, close to other storage layer groups in the same storage area.

[0079] For each storage layer group, each local bit line is coupled to a second common bit line via each bit line selector Se, and each local bit line is coupled to a first common bit line (12) via each precharge switch Eq.

[0080] In some embodiments, the memory further comprises a second chip, the first chip and the second chip are stacked along a third direction, the first chip is bonded to the second chip; and the second chip includes a sensing magnification area;

[0081] In the first chip, a step contact structure is installed between two adjacent storage layer groups along the first direction, and a common bit line directly connected to the bit line selector Se is coupled to a detection expansion area through the step contact structure.

[0082] It must be understood that the first chip is connected to the second chip via bonding, and bonding connection refers to the implementation of an electrical connection between two chips through a hybrid bonding structure (also referred to as bonding pillars). Hybrid bonding is a process of establishing permanent bonds between heterogeneous or homogeneous chips. "Hybrid" refers to the formation of dielectric-dielectric and metal-metal bonds between two surfaces, possessing the following advantages: (1) the advantage of shorter interconnection distances, where there is no need to connect with wires or traverse the entire CMOS layer via TSVs, and interconnection can be achieved simply by connecting to the copper contacts at the back end; and (2) the advantage of higher interconnection density, where the area of ​​the copper contacts is very small, and compared to tin balls with a diameter of 100 micrometers and TSVs, the spacing of the copper contacts in the hybrid bonding process is less than 10 micrometers, thus undoubtedly enabling higher interconnection density. (3) The advantage of lower costs is undoubtedly that, while performing interconnections of each chip individually requires more time, wafer bonding enables large-area and high-density interconnections, and contributes dramatically to the improvement of production capacity. Naturally, production costs can also be reduced.

[0083] It should be explained that the sensing expansion area includes a plurality of sense amplifiers (Sa), also referred to as sensing amplifiers, and senses and amplifies the electrical signal of a common bit line connected to a selected storage unit, thereby finally causing the potential of the common bit line to reach a low potential or a high potential, thereby achieving the purpose of reading data from or writing data from a selected storage unit.

[0084] Here, the 3D DRAM mostly adopts a method of vertically stacking multiple storage units (i.e., multiple storage layer groups) to form a storage structure, and in order to ensure that the sensing amplifier is connected to the common bit line among each storage layer group, a 3D staircase contact structure must be formed, and the different steps of the staircase contact structure are electrically isolated, and one step is connected to a common bit line (connected to the bit line connector Se), so that the common bit line is connected to the sensing amplifier Sa of the sensing amplifier area, thereby implementing sensing amplification processing.

[0085] In this way, all local bit lines in each storage layer group are coupled to a second common bit line (13) installed in an intermediate part belonging to the storage area via a bit line selector Se, and a step contact structure is further installed in the intermediate part of the storage area, that is, all second common bit lines (13) of each storage layer group can be connected to a detection amplifier in the detection expansion area facing outward through a step contact structure installed in the intermediate part of the storage area.

[0086] In some other embodiments, referring to FIG. 6, for the same sub-array tile, storage areas are numbered along a third direction, storage area 0, storage area 1, storage area 2, storage area 3, storage area 4;

[0087] For storage areas 1 and 3 with odd numbers, each local bit line is coupled to the first common bit line (12) through each bit line selector Se, and each local bit line is coupled to the second common bit line (13) through each precharge switch Eq; for storage areas 0, 2, and 4 with even numbers, each local bit line is coupled to the second common bit line (13) through each bit line selector Se, and each local bit line is coupled to the first common bit line (12) through each precharge switch Eq.

[0088] That is, the first common bit line (12) of two adjacent storage layer groups is adjacent in the third direction, and the second common bit line (13) of two adjacent storage layer groups is adjacent in the third direction, but neither one first common bit line (12) nor one second common bit line (13) is adjacent in the third direction, and at the same time, in the case of odd-numbered storage areas 1 and 3, the local bit line is connected to the first common bit line (12) through the bit line selector Se and connected to the second common bit line (13) through the precharge switch Eq; in the case of even-numbered storage areas 0, 2, and 4, the local bit line is connected to the second common bit line (13) through the bit line selector Se and connected to the first common bit line (12) through the precharge switch Eq. Accordingly, in the case of a selected group of storage layers during the detection amplification process, in two adjacent first common bit lines (12), one first common bit line (12) is inevitably in a detection amplification state (whether it is in a high potential or low potential after the detection amplification state ends is determined by a specific data value), and the other first common bit line (12) is in a precharge potential; in two adjacent second common bit lines (13), one second common bit line (13) is inevitably in a detection amplification state (whether it is in a high potential or low potential after the detection amplification state ends is determined by a specific data value), and the other second common bit line is in a precharge potential, and low potential < precharge potential < high potential. However, since the two adjacent common bit lines along the third direction do not simultaneously perform detection amplification processing, the two adjacent common bit lines along the third direction are not simultaneously in a detection amplification state, so the coupling case of the two adjacent common bit lines is clearly weakened and the detection amplification margin is improved.

[0089] Of course, regardless of how the positions of the precharge switch Eq and the bit line selector Se change, the received control signal does not change, and the sub-word line drive complementary signal PhdecN generated by multiplexing the row address signal still remains. and subword line driving signal Phdec You just need to control it.

[0090] Additionally, referring to FIG. 7, the step contact structure is positioned at the middle of each storage area and at the outer side of each storage area, respectively. In the case of even-numbered storage areas 0, 2, and 4, the local bit line is connected to the inner second common bit line (13) and coupled to the sensing amplifier via the inner step contact structure; in the case of odd-numbered storage areas 1 and 3, the local bit line is connected to the outer first common bit line (12) and coupled to the sensing amplifier via the outer step contact structure.

[0091] In some embodiments, referring to FIG. 1b, the storage array tile further comprises a plurality of local word lines, each local word line penetrates a plurality of storage layer groups stacked along a third direction, and a storage unit is formed at the intersection of each local word line corresponding to a local bit line, and it should be noted that the local bit line and the local word line are not directly connected. For example, the storage unit has a 1T1C structure and includes one transistor and one capacitor, the gate of the transistor is connected to the local word line, and the source and drain of the transistor are connected to the local bit line and the capacitor, respectively; the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0092] Referring to FIG. 8a, the control logic of local word lines and local bit lines is illustrated by taking a cross-section along the third direction of the sub-array tile Sub Mat0 as an example. As shown in FIG. 8a, a plurality of local word lines aligned along the first direction passing through the same storage layer group form a single sub-word line group. All local word lines within the same sub-word line group share the same sub-word line driving signal and the same sub-word line driving complementary signal.

[0093] For example, for the first storage layer group, local word line WL <0> , WL <4> ......WL <1592> , WL <1596> ... forms a single subword line group, and the subword line group is Phdec <0> PhdecN <0> Sharing; Local Word Line WL <1> , WL <5> ......WL <1593> , WL <1597> ... forms a single subword line group, and the subword line group is Phdec <1> PhdecN <1> Sharing; Local Word Line WL <2> , WL <6> ......WL <1594> , WL <1598> ... forms a single subword line group, and the subword line group is Phdec <2> and PhdecN <2> Sharing; Local Word Line WL <3> , WL <7> ......WL <1595> , WL <1599> forms a single subword line group, and said subword line group Phdec <3> PhdecN <3> Share.

[0094] For the second storage layer group, local word line WL <1600> , WL <1604> ......WL <3192> , WL <3196> ... forms a single subword line group, and the subword line group is Phdec <4> and PhdecN <4> Sharing; Local Word Line WL <1601> , WL <1605> ......WL <3193> , WL <3197> ... forms a single subword line group, and the subword line group is Phdec <5> and PhdecN <5> Sharing; Local Word Line WL <1602> , WL <1606> ......WL <3194> , WL <3198> ... forms a single subword line group, and the subword line group is Phdec <6> PhdecN <6> Sharing; Local Word Line WL <1603> , WL <1607> ......WL <3195> , WL <3199> forms a single subword line group, and said subword line group Phdec <7> PhdecN <7> Share.

[0095] One local bit line has a correspondence with one group of subword lines, and the local bit line forms a storage unit at the intersection of each corresponding local word line; for example, local bit line BL0 and local word line WL <0> , WL <4> ......WL <1592> , WL <1596> ... corresponds to, local bit line BL0 and local word line WL <0> A single storage unit exists at the intersection of, and local bit lines BL0 and WL <4> A single storage unit exists at the intersection of......local bit lines Bl0 and WL <1596> There is one storage unit at the intersection of.

[0096] The bit line selector Se of the local bit line receives the subword line drive signal of the corresponding subword line group, and the precharge switch Eq of the local bit line receives the subword line drive complementary signal of the corresponding subword line group. For example, the control signal Sel of the bit line selector Se of the local bit line BL0 <0> =Phdec <0> And, the control signal Eq of the precharge switch Eq of the local bit line BL0 <0> =PhdecN <0> am.

[0097] In some embodiments, as illustrated in FIG. 8b, each storage array tile further includes a plurality of common word lines (Common WL) extended along a second direction; sequentially assigning independent numbers to local word lines in each sub-array tile, and local word lines with the same number in different sub-array tiles are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal.

[0098] That is, the local word line WL among each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19 <0> , WL <4> ......WL <1596> All are subword line driving signals Phdec <0> and subword line driving complementary signal PHdecN <0> Share.

[0099] Specifically, the local word line WL among each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19 <0> is connected to the common word line Common WL0, and the local word line WL among each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19 <4> is connected to the common word line Common WL4......and the local word line WL among each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19 <1596> It is connected to the common word line Common WL1596, but the common word lines Common WL0, Common WL4......, Common WL1596 are sub-word line drive signals Phdec <0> PhdecN and subword line driving complementary signal <0> Sharing;

[0100] Simultaneously, the bit line selector Se of the first local bit line BL0 in each storage area among each sub-array tile is the sub-word line drive signal Phdec <0> Upon receiving, the precharge switch Eq of the local bit line BL0 in each storage area among each sub-array tile is the sub-word line drive signal PhdecN <0> Receives.

[0101] In some embodiments, as illustrated in FIG. 8b, common word lines are sequentially numbered along a first direction in a storage array tile, and N common word lines with consecutive numbers form a main word line group, where N=4 is illustrated as an example in FIG. 8b, i.e., WL <0> ~ WL <3> This is a single main word line group, and WL <4> ~ WL <7> This is a single main word line group.

[0102] Referring to FIG. 9, the memory includes a decoding unit (21) and a plurality of subword line driving units (22), where N is a positive integer;

[0103] The decoding unit (21) is configured to decode the row address signal to generate the main word line driving signal, namely GrDec<399: 0>, the sub-word line driving signal Phdec<7: 0>, and the sub-word line driving complementary signal PhdecN<7: 0> of each common word line.

[0104] A sub-word line driving unit (22) is coupled to one common word line and is configured to receive a corresponding main word line driving signal, a corresponding sub-word line driving signal, and a corresponding sub-word line driving complementary signal, and to turn on or off the coupled common word line based on these signals;

[0105] Here, the main word line driving signal is for selecting one main word line group from both the first storage layer group and the second storage layer group, and the sub word line driving signal and the sub word line driving complementary signal are for selecting one common word line from the main word line group selected in the first storage layer group or selecting one common word line from the main word line group selected in the second storage layer group.

[0106] For example, the main word line drive signal GrDec <0> =0 and, GrDec <1> ~ GrDec <399> =1 (indicates selection when the main word line drive signal is at a low level, and indicates no selection when the main word line drive signal is at a high level), sub word line drive signal Phdec <0> =1, Phdec <1> ~ Phdec <7> =0 and, subword line driving complementary signal PhdecN <0> =0, PhdecN <1> ~ PhdecN <7> If =1, Common Word Line Common WL <0> This is selected, that is, the WL among each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19. <0> All are selected (turned on); simultaneously, for each storage area of ​​each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19 (since FIG. 8b is a cross-sectional example, it is merely an example of one storage area among each sub-array tile Sub Mat0, Sub Mat1......Sub Mat19), here the bit line selector Se of local bit line BL0 is connected (control signal Sel <0> = Phdec <0> =1) and the precharge switch Eq is disconnected, (control signal Eq <0> = PhdecN <0> =0), the bit line selector Se of local bit lines BL1~BL4 is disconnected, and the precharge switch Eq is connected.In this way, Common Word Line Common WL <0> This is turned on, and BL0 is connected to an adjacent common bit line through the bit line selector Se, and since the common bit line is coupled to a sense amplifier via a step contact structure, each WL <0> The storage unit formed by the intersection of and BL0 (via BL0 and bit line selector Se) shares charge with the corresponding common bit line, and the potential of the common bit line implements amplification under the action of a sensing amplifier, while simultaneously; WL <1> ~ WL <4> is not turned on, and in the case of BL1~BL4, it is connected to an adjacent common bit line through a precharge switch Eq, and the common bit line is controlled to a precharge potential, and the precharge potential may be an intermediate potential 1 / 2Vblh, where Vblh is the power potential of the storage array (or sensing amplifier).

[0107] In some embodiments, referring to FIG. 10, the subword line driving unit (22) includes a first switching tube (301), a second switching tube (302), and a third switching tube (303);

[0108] The control terminals of the first switching tube (301) and the second switching tube (302) both receive the main word line driving signal Grdec, the first terminal of the first switching tube (301) receives the sub-word line driving signal Phdec, the second terminal of the first switching tube (301), the first terminal of the second switching tube (302), and the first terminal of the third switching tube (303) are all connected to the common word line Common WL, the second terminal of the second switching tube (302) and the second terminal of the third switching tube (303) are all connected to the power supply terminal, and the control terminal of the third switching tube (303) receives the sub-word line driving complementary signal PhdecN.

[0109] What needs to be explained is that the power supply unit may be a grounded unit, the first switching tube (301) is P-type doped, and the second switching tube (302) and the third switching tube (303) are both N-type doped.

[0110] In this way, in such cases, if Grdec=0, it is explained that the main word line group existing in the common word line is selected and the first switching tube (301) is turned on, and if Phdec=1, the common word line is selected, and since the common word line Common WL is at a high level (i.e., selected / off), the transistors of the interconnected storage units are turned on; in other cases, if Grdec=0 and Phdec=0, it is explained that although the main word line group existing in the common word line is selected, the common word line is not selected and the common word line Common WL is at a low level, so the transistors of the interconnected storage units are not turned on; in yet another case, if Grdec=1, it is explained that the entire main word line group existing in the common word line is not selected, the first switching tube (301) is not turned on, and since the common word line Common WL is at a low level, the transistors of the interconnected storage units are not turned on.

[0111] Additionally, the third switching tube (303) is intended to quickly turn off the corresponding common word line after it has been selected from the common word line and the corresponding operation has been completed.

[0112] In summary, an embodiment of the present invention provides a three-dimensional stereoscopic memory, said three-dimensional stereoscopic memory comprising a first chip and a second chip, wherein the first chip and the second chip are stacked and arranged along a third direction, and the two are connected through a hybrid bonding method. The first chip is primarily intended for fabricating a storage array (Core), and specifically, is also partitioned into a plurality of storage array tiles (Mat) to perform better control and management; the second chip is primarily intended for fabricating a peripheral control area (Periphery) and a sensing expansion area, etc. In the first chip, each storage array tile comprises a plurality of sub-array tiles arranged sequentially along a second direction, and each sub-array tile comprises a plurality of storage areas stacked sequentially along a third direction, and each storage area comprises two storage layer groups arranged along a first direction; Each storage layer group includes a plurality of local bit lines, and a common bit line is installed on each side along the first direction of each storage layer group, and each local bit line is coupled to a common bit line on one side through a respective bit line selector, and each local bit line is coupled to a common bit line on the other side through a respective precharge switch; the bit line selector operates based on a sub-word line driving signal, and the precharge switch operates based on a sub-word line driving complementary signal. In this way, the embodiment of the present invention controls the operating state of the precharge switch Eq and the bit line selector Se of the local bit line by multiplexing word line information, so that although the three-dimensional memory additionally introduces the precharge switch Eq and the bit line selector Se, there is no need to additionally introduce control information and unnecessary decoding logic, thereby improving control efficiency and reducing redundant elements.

[0113] In another embodiment of the present invention, with reference to FIG. 11, an embodiment of the present invention illustrates a flowchart of a control method for a memory. The control method is applied to the memory described above, and with reference to FIG. 1a, the memory includes a first chip and a second chip stacked along a first direction, the first chip includes a plurality of storage array tiles, each storage array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction; each storage layer group includes a plurality of local bit lines, and a common bit line is installed on each side along the first direction of each storage layer group, each local bit line is coupled to a common bit line on one side through a respective bit line selector, and each local bit line is coupled to a common bit line on the other side through a respective precharge switch.

[0114] As illustrated in FIG. 11, the control method is,

[0115] Step S501 of receiving a command address signal and decoding a row address signal among the command address signals to generate a plurality of main word line driving signals, a plurality of sub-word line driving signals and a plurality of sub-word line driving complementary signals;

[0116] Step S502 of controlling whether a corresponding bit line selector connects to a common bit line connected to a local bit line based on each subword line driving signal; and

[0117] Based on each subword line driving complement signal, it includes step S503 of controlling whether the corresponding precharge switch connects to the common bit line connected to the local bit line.

[0118] In some embodiments, referring to FIG. 8b, the storage array tile further comprises a plurality of local word lines, each local word line penetrating a plurality of storage layer groups stacked along a third direction; a plurality of local word lines aligned along a first direction passing through the same storage layer group form a single sub-word line group, and all local word lines in the same sub-word line group share the same sub-word line driving signal and the same sub-word line driving complementary signal; a single local bit line has a corresponding relationship with a single sub-word line group, and a single storage unit is formed at the intersection of each local word line corresponding to the local bit line;

[0119] Each subword line group has a subword line driving signal and a subword line driving complementary signal; the control method of the memory is,

[0120] A step of transmitting a subword line driving signal of a subword line group to a bit line selector of a corresponding local bit line; and

[0121] It further includes the step of transmitting the subword line driving complement signal of the subword line group to the precharge switch of the corresponding local bit line.

[0122] In some embodiments, local word lines in each sub-array tile are sequentially assigned independent numbers, and local word lines with the same number in different sub-array tiles are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal; in a storage array tile, common word lines are assigned numbers along a first direction, and N common word lines with consecutive numbers form a main word line group;

[0123] Each of the above storage regions has two storage layer groups sequentially referred to as the first storage layer group and the second storage layer group along the first direction; and the memory control method is,

[0124] A step of selecting one main word line group from both the first storage layer group and the second storage layer group based on a main word line driving signal;

[0125] A step of selecting one common word line from a main word line group selected in a first storage layer group or a main word line group selected in a second storage layer group based on a subword line driving signal and a subword line driving complementary signal; and

[0126] It further includes the step of turning on the selected common word line and executing the operation indicated by the command address signal.

[0127] In this way, the embodiment of the present invention controls the operating state of the precharge switch Eq and bit line selector Se of the local bit line by multiplexing word line information, so that although the three-dimensional memory additionally introduces the precharge switch Eq and bit line selector Se, there is no need to additionally introduce control information and unnecessary decoding logic, thereby improving control efficiency and reducing redundant elements.

[0128] In another embodiment of the present invention, an electronic device is further provided, said electronic device includes a memory as illustrated in FIG. 4, said memory includes a first chip and a second chip stacked along a third direction, and the first chip and the second chip are bonded together.

[0129] Referring to FIG. 1a, in the first chip, each storage array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction; each storage layer group includes a plurality of local bit lines, and a common bit line is installed on each side along the first direction of each storage layer group, each local bit line is coupled to a common bit line on one side through a respective bit line selector, and each local bit line is coupled to a common bit line on the other side through a respective precharge switch; referring to FIG. 4, the bit line selector operates based on a sub-word line driving signal, and the precharge switch operates based on a sub-word line driving complementary signal. In this way, the embodiment of the present invention controls the operating state of the precharge switch Eq and bit line selector Se of the local bit line by multiplexing word line information, so that although the three-dimensional memory additionally introduces the precharge switch Eq and bit line selector Se, there is no need to additionally introduce control information and unnecessary decoding logic, thereby improving control efficiency and reducing redundant elements.

[0130] It must be explained that, in this specification, the term “include” or variations thereof means including a process, method, article, or apparatus of one series element by including a non-exclusive inclusion, and also including other elements not explicitly listed, or further including intrinsic elements of such process, method, article, or apparatus. Unless further limitations are given, an element defined by the phrase “include one......” does not exclude the existence of other identical elements in the process, method, article, or apparatus including said element.

[0131] The numbers of the embodiments of the present invention above are for illustrative purposes only and do not indicate superiority or inferiority of the embodiments. Methods mentioned in some method embodiments provided in the present invention may be arbitrarily combined to obtain new method embodiments if they do not conflict. Features mentioned in some product embodiments provided in the present invention may be arbitrarily combined to obtain new product embodiments if they do not conflict. Features mentioned in some method or device embodiments provided in the present invention may be arbitrarily combined to obtain new method embodiments or device embodiments if they do not conflict.

[0132] The above description is merely a specific embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. A person skilled in the art to which the present invention pertains will readily understand that any change or substitution within the technical scope disclosed in the present invention must fall within the scope of protection of the present invention. Accordingly, the scope of protection of the present invention must be based on the scope of protection of the patent claims.

Claims

Claim 1 As a memory, the memory comprises a first chip, the first chip comprises a plurality of storage array tiles, each of the storage array tiles comprises a plurality of local bit lines and a plurality of common bit lines, the local bit lines extend along a first direction, the common bit lines extend along a second direction, and each of the common bit lines exists on each side along the first direction of the local bit lines; the first direction intersects the second direction; each of the local bit lines is coupled to the common bit line on one side via a respective bit line selector (Se), and each of the local bit lines is coupled to the common bit line on the other side via a respective precharge switch (Eq); The bit line selector (Se) is configured to receive a sub-word line driving signal and, based on the sub-word line driving signal, selectively connect a common bit line connected to a connected local bit line; the precharge switch (Eq) is configured to receive a sub-word line driving complementary signal and, based on the sub-word line driving complementary signal, selectively connect a common bit line connected to a connected local bit line; and the memory is characterized in that both the sub-word line driving signal and the sub-word line driving complementary signal are generated by decoding a row address signal among the command address signals received by the memory. Claim 2 A memory according to claim 1, wherein each of the storage array tiles comprises a plurality of sub-array tiles arranged sequentially along a second direction, each of the sub-array tiles comprises a plurality of storage regions stacked sequentially along a third direction, each of the storage regions comprises two storage layer groups arranged along a first direction; each of the storage layer groups has a plurality of local bit lines installed, a first common bit line installed on the outer side of each storage layer group, far from another storage layer group of the same storage region, and a second common bit line installed on the inner side of each storage layer group, close to another storage layer group of the same storage region; and for each of the storage layer groups, each of the local bit lines is coupled to the second common bit line through each of the bit line selectors, and each of the local bit lines is coupled to the first common bit line through each of the precharge switches. Claim 3 In claim 1, each of the above storage array tiles comprises a plurality of sub-array tiles arranged sequentially along a second direction, each of the above sub-array tiles comprises a plurality of storage regions stacked sequentially along a third direction, and each of the above storage regions comprises two storage layer groups arranged along a first direction; A memory characterized by the fact that each storage layer group has a plurality of local bit lines installed therein, a first common bit line is installed on the outer side of each storage layer group, far from other storage layer groups in the same storage area, and a second common bit line is installed on the inner side of each storage layer group, close to other storage layer groups in the same storage area; in the case of the same sub-array tile, the storage area is numbered along a third direction; in the case of the storage area with an odd number, each local bit line is coupled to the first common bit line through each bit line selector, and each local bit line is coupled to the second common bit line through each precharge switch; in the case of the storage area with an even number, each local bit line is coupled to the second common bit line through each bit line selector, and each local bit line is coupled to the first common bit line through each precharge switch. Claim 4 A memory according to claim 2, wherein the storage array tile further comprises a plurality of local word lines, each of which penetrates a plurality of storage layer groups stacked along a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction; a plurality of which local word lines aligned along the first direction passing through the same storage layer group form a single sub-word line group; a single local bit line has a corresponding relationship with a single sub-word line group, and a single storage unit is formed at the intersection of each local word line corresponding to the local bit line; all local word lines in the same sub-word line group share the same sub-word line driving signal and the same sub-word line driving complementary signal, the bit line selector of the local bit line receives the sub-word line driving signal of the corresponding sub-word line group, and the precharge switch of the local bit line receives the sub-word line driving complementary signal of the corresponding sub-word line group. Claim 5 A memory according to claim 4, wherein each of the above storage array tiles further comprises a plurality of common word lines extended along a second direction; sequentially assigning independent numbers to local word lines in each of the above sub-array tiles, and local word lines with the same number in different above sub-array tiles are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal. Claim 6 In claim 5, in the storage array tile, the common word lines are sequentially numbered along a first direction, and N common word lines that are consecutive numbers form a main word line group; the memory includes a decoding unit (21) and a plurality of sub-word line driving units (22), where N is a positive integer; the decoding unit (21) is configured to decode the row address signal to generate a main word line driving signal, a sub-word line driving signal, and a sub-word line driving complementary signal for each common word line; the sub-word line driving unit (22) is coupled to one common word line and receives a corresponding main word line driving signal, a corresponding sub-word line driving signal and a corresponding sub-word line driving complementary signal, and is configured to turn the coupled common word line on or off based on the corresponding sub-word line driving signal and the corresponding sub-word line driving complementary signal; and two of each of the storage area A memory characterized in that a storage layer group is sequentially referred to as a first storage layer group and a second storage layer group along a first direction, the main word line driving signal is for selecting one main word line group in both the first storage layer group and the second storage layer group, and the sub word line driving signal and the sub word line driving complementary signal are for selecting one common word line in the main word line group selected in the first storage layer group, or for selecting one common word line in the main word line group selected in the second storage layer group. Claim 7 In claim 6, the sub-word line driving unit (22) comprises a first switching tube (301), a second switching tube (302), and a third switching tube (303); the control terminals of the first switching tube and the second switching tube both receive the main word line driving signal, the first terminal of the first switching tube receives the sub-word line driving signal, the second terminal of the first switching tube, the first terminal of the second switching tube, and the first terminal of the third switching tube are all connected to the common word line, the second terminal of the second switching tube and the second terminal of the third switching tube are all connected to the power supply terminal, and the control terminal of the third switching tube receives the sub-word line driving complementary signal. Claim 8 In claim 7, the memory further comprises a second chip, wherein the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip; the second chip comprises a sensing magnification area; and in the first chip, a step contact structure is installed between two adjacent storage layer groups along a first direction, and the common bit line directly connected to the bit line selector is coupled to the sensing magnification area through the step contact structure. Claim 9 A method for controlling a memory, wherein a first chip in the memory comprises a plurality of storage array tiles, each of the storage array tiles comprises a plurality of local bit lines and a plurality of common bit lines, each of the local bit lines is coupled to a common bit line on one side through a bit line selector, and each of the local bit lines is coupled to a common bit line on the other side through a respective precharge switch; the method for controlling a memory comprises the steps of: receiving a command address signal and decoding a row address signal among the command address signals to generate a plurality of main word line driving signals, a plurality of sub-word line driving signals, and a plurality of sub-word line driving complementary signals; controlling whether a corresponding bit line selector connects to a common bit line connected to a local bit line based on each of the sub-word line driving signals; and controlling whether a corresponding precharge switch connects to a common bit line connected to a local bit line based on each of the sub-word line driving complementary signals. Claim 10 In claim 9, each of the above storage array tiles comprises a plurality of sub-array tiles arranged sequentially along a second direction, each of the above sub-array tiles comprises a plurality of storage regions stacked sequentially along a third direction, each of the above storage regions comprises two storage layer groups arranged along a first direction; each of the above storage layer groups has a plurality of the above local bit lines installed, and one of the above common bit lines is installed on each side along the first direction of each of the above storage layer groups; the storage array tile further comprises a plurality of local word lines, each of the above local word lines penetrates a plurality of storage layer groups stacked along a third direction; a plurality of the above local word lines aligned along the first direction passing through the same above storage layer groups form a single sub-word line group, and all local word lines in the same sub-word line group share the same sub-word line driving signal and the same sub-word line driving complementary signal; One of the above-mentioned local bit lines has a corresponding relationship with one of the above-mentioned subword line groups, and a storage unit is formed at the intersection of each of the above-mentioned local word lines corresponding to the local bit line; each of the above-mentioned subword line groups has a subword line driving signal and a subword line driving complementary signal; and the method of controlling the memory further comprises the steps of: transmitting the subword line driving signal of the subword line group to a bit line selector of the corresponding local bit line; and transmitting the subword line driving complementary signal of the subword line group to a precharge switch of the corresponding local bit line. Claim 11 In claim 10, local word lines in each of the above sub-array tiles are sequentially assigned independent numbers, and local word lines with the same number in different of the above sub-array tiles are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal; in the storage array tiles, the common word lines are assigned numbers along a first direction, and N of the common word lines with consecutive numbers form a main word line group; and two storage layer groups in each of the above storage regions are sequentially referred to as the first storage layer group and the second storage layer group along the first direction; and the control method of the memory comprises the step of selecting one main word line group in both the first storage layer group and the second storage layer group based on the main word line driving signal. A method for controlling a memory, further comprising: a step of selecting one common word line from a main word line group selected in a first storage layer group or a main word line group selected in a second storage layer group based on the sub-word line driving signal and the sub-word line driving complementary signal; and a step of turning on the selected common word line and executing an operation indicated by the command address signal. Claim 12 An electronic device, wherein the electronic device comprises a memory according to any one of claims 1 to 8.

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