Integrated circuit and method for data storage

Abstract

The IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus that provides a primary CS signal via a primary chip select (CS) line connected to the primary memory die. The secondary memory die is coupled to a secondary CS line that transmits a secondary CS signal provided by the bus and the primary memory die, excluding the primary CS line. The primary memory die is configured to receive a command via the bus while the primary CS signal is active, execute the command within the primary memory die in response to identifying that the command is directed to the primary memory die, and execute the command by causing the secondary memory die to transmit the primary CS signal to the secondary CS signal via the secondary CS line in response to identifying that the command is directed to the secondary memory die.

Description

Technology Field

[65535] The embodiments described herein generally relate to securing data storage, and in particular to methods and systems for secure storage within a multi-die package. Background Technology Various systems store data in a storage device comprising a plurality of stacked memory dies within a common package. The use of stacked memory dies within a common package is known in the art. For example, as described in U.S. Patent 9,245,590, any number of Serial Peripheral Interface (SPI) flash memory dies may be stacked and packaged to realize any one or a combination of various capabilities, such as low per-bit cost, high-density storage, code shadowing for RAM, and fast random access for "execute in place" applications, while preserving the advantages of the SPI interface. During device manufacturing, each stacked die is assigned a unique identifier or "Die ID" relative to the other stacked dies within the package. During normal operations, unique die IDs are used by the Die Select command to enable one of the stacked dies to respond to subsequent commands on the SPI interface, while disabling other stacked dies within the package from responding to subsequent commands, except for certain "Universal" commands including the Die Select command. Concurrent operations by the stacked dies are supported.As another example, U.S. Patent 11,194,726 describes methods, systems, and devices for stacked memory dies and combined access operations. A device may include a plurality of memory dies. One die may be configured as a master, and another die may be configured as a slave. The master may communicate with a host device. The slave may be coupled to the master. A device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled to the host device and configured to output a set of data in response to a read command. The first die supplies a first subset of data and obtains a second subset of data from the second die. means of solving the problem One embodiment described herein provides an integrated circuit (IC) comprising a primary memory die and a secondary memory die. The primary memory die is coupled to a bus that provides a primary chip select (CS) signal through a primary CS (Chip Select) line connected to the primary memory die. The secondary memory die is coupled to a secondary CS line that transmits a secondary CS signal provided by the bus and the primary memory die, excluding the primary CS line. The primary memory die is configured to receive a command via the bus while the primary CS signal is active, execute the command within the primary memory die in response to identifying that the command is destined to the primary memory die, and execute the command by causing the secondary memory die to transfer the primary CS signal to the secondary CS signal on the secondary CS line in response to identifying that the command is destined to the secondary memory die.In some embodiments, the primary memory die includes a local memory selectable by a local valid signal conveyed on a local valid line, and the primary memory die is configured to execute the command by (i) transmitting the primary CS signal as the local valid signal on the local valid line, and (ii) deactivating the secondary CS signal provided to the secondary memory die. In other embodiments, the IC includes another secondary die coupled to another secondary CS line that conveys another secondary CS signal provided by the bus and the primary memory die, excluding the primary CS line, and the primary die is configured to cause the other secondary die to execute the command by (i) transmitting the primary CS signal on the other secondary CS line as the other secondary CS signal, (ii) deactivating the secondary CS signal provided to the secondary die, and (iii) deactivating the local effective signal provided to the local memory of the primary die. In other embodiments, the primary memory die and the secondary memory die are each first and second different memory types, and are each selected from a list including at least (i) NAND flash memory type and (ii) NOR flash memory type. In one embodiment, the primary memory die and the secondary memory die each support first and second different access protocols, and the primary memory die is configured to present the second access protocol of the secondary memory die to a host coupled to the bus.In another embodiment, the primary memory die is configured to execute one or more commands received subsequently to the die-selection command in response to receiving a die-selection command specifying a selected memory die between the primary memory die and the secondary memory die. In yet another embodiment, the primary memory die and the secondary memory die are mapped to different address subranges of a common address space, and the primary memory die is configured to identify an address parameter within the received command and to execute the received command by the primary memory die or the secondary memory die depending on the address range to which the address parameter belongs. In some embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the secondary CS signal to block access to the secondary memory die for all incoming commands. In other embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the secondary CS signal to allow access to the secondary memory die for a partial subset of the instructions supported by the secondary memory die.In other embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the secondary CS signal to allow full access to the secondary memory die for all commands supported by the secondary memory die, while selectively executing only commands that change the access mode. In one embodiment, the primary memory die is configured to locally store the boot code of a host coupled to the bus and to manage secure access to the stored boot code. In another embodiment, the primary memory die is configured to serve as a Root of Trust (RoT) of an underlying system including the IC to secure storage operations directed toward the secondary memory die. According to the embodiment described herein, a method for storing data is additionally provided, wherein the primary memory die is coupled to a bus that provides a primary chip select (CS) signal through a primary CS line connected to the primary memory die, and the secondary memory die is coupled to a secondary CS line that conveys a secondary CS signal provided by the bus and the primary memory die, excluding the primary CS line, within an integrated circuit (IC). This method further provides receiving a command through the bus by the primary memory die while the primary CS signal is active.In response to identifying that the above command is directed to the primary memory die, the command is executed within the primary memory die, and in response to identifying that the above command is directed to the secondary memory die, the secondary memory die is made to execute the command by transmitting the primary CS signal to the secondary CS signal on the secondary CS line. These embodiments and other embodiments will be fully understood from the following detailed description of the embodiments considered together with the following drawings. Brief explanation of the drawing FIG. 1 is a block diagram schematically showing a computer system including a plurality of memory dies stacked in a common package according to one embodiment described herein, FIG. 2 is a flowchart schematically showing a method for executing an instruction in a multi-die storage device according to one embodiment described herein, and FIG. 3 is a timing diagram schematically showing signals generated during the execution of a read instruction in a multi-die storage device according to one embodiment described herein. Specific details for implementing the invention The embodiments described herein provide improved methods and systems for managing secure access to multiple memory dies stacked within a common package. In the disclosed embodiments, one memory die controls access to other memory dies by controlling their respective CS inputs. The disclosed embodiments are applicable to different types of memory dies, each having different instruction sets and / or supporting different access protocols. In various systems, a host is coupled to a storage device containing multiple memory dies via a bus. The bus typically includes opcodes, addresses, one or more Input / Output (IO) lines for conveying data, and a CS signal that is activated during a command. Each memory die has a CS input that selects the memory die to execute a corresponding command when activated. A memory die can complete the execution of a supported command if the CS input is activated during the entire command, and will typically abandon the command execution if the CS input is deactivated before the execution is completed. Memory dies typically ignore unsupported instructions, even if their CS input is enabled during the entire instruction set. Various architectures can be used to access individual memory dies within a package. For example, all bus signals, including the bus CS signal, can be coupled in parallel to all memory dies. This type of technology is provided by Winbond under the name SpiStack® and is implemented within Winbond's W25M product family.When a command is transmitted via the bus, all memory dies initially receive the command, and each memory die independently decides whether to execute or abandon the command. This parallel bus approach is not suitable for mixing different types of memory dies within a package, as it typically requires that memory dies have the same memory type and share common rules for determining whether to execute or abandon the command. As another approach, the host bus can be coupled to a mediating controller that terminates the host bus and generates separate bus signals, each containing a CS signal, to the different memory dies. The host can communicate with each memory die only indirectly through the controller. Because the controller handles multiple entire buses for each memory die, this approach is highly complex and costly. In the disclosed embodiments, the bus is coupled in parallel to multiple memory dies, except for a CS signal connected to only one of the memory dies referred to herein as the "primary memory die." The primary memory die controls access to other memory dies, also referred to as "secondary dies" here, by providing a separate CS signal to each of the secondary dies. Consider an integrated circuit (IC) comprising a primary memory die and one or more secondary memory dies. The primary memory die is coupled to a bus that provides a primary chip select (CS) signal via a primary chip select (CS) line connected only to the primary memory die.Secondary memory dies are coupled to each secondary CS line that conveys each secondary CS signal provided by the bus and the primary memory die, excluding the primary CS line. While the primary CS signal is active, the primary memory die receives a command via the bus and executes the command within the primary memory die in response to identifying that the command is directed to the primary memory die. Otherwise, in response to identifying that the command is directed to the secondary memory die, the primary memory die causes the given secondary memory die to execute the command by transmitting the primary CS signal to the secondary CS signal on the secondary CS line of the given secondary memory die. In the following description, for clarity, some embodiments described below refer to a package comprising a primary memory die and a single secondary die. However, the disclosed techniques may be similarly applied to packages comprising a plurality of secondary memory dies. In some embodiments, the primary memory die comprises a local memory selectable by a local "valid signal" conveyed on a local "valid line," and the primary memory die executes a command by (i) transmitting a primary CS signal as a local valid signal on the local valid line and (ii) deactivating a secondary CS signal provided to a secondary memory die. In other embodiments, the IC comprises a bus excluding the primary CS line and another secondary die coupled to another secondary CS line conveying another secondary CS signal provided by the primary memory die.In these embodiments, the primary die causes the other secondary die to execute a command by (i) transmitting the primary CS signal onto another secondary CS line as another secondary CS signal, (ii) deactivating the secondary CS signal provided to the secondary die, and (iii) deactivating the local effective signal provided to the primary die's local memory. In the disclosed architecture, at least some of the memory dies among the primary memory die and the secondary memory die(s) are each different memory types, each selected from a list including at least (i) NAND flash memory type and (ii) NOR flash memory type. In one embodiment, the primary memory die and the secondary memory die each support first and second different access protocols, wherein the primary memory die presents the second access protocol of the secondary memory die to a host coupled to the bus. The primary memory die receives the command (or one or more subsequent) using any suitable method based, for example, on a dedicated die-selection command or address information included in the command. A target memory die for executing commands can be selected. In some embodiments, the primary die may operate in one of three access modes: “Standalone” mode, “Restricted-Access” mode, and “Full-Access” mode. In Standalone mode, the primary memory die controls secondary CS signal(s) to block access to the secondary memory die(s) for all incoming commands.In restricted-access mode, the primary memory die controls secondary CS signal(s) to allow access to the secondary memory die(s) for a partial subset of each instruction supported by the secondary memory die(s). In full-access mode, the primary memory die controls secondary CS signal(s) to allow full access to the secondary memory die(s) for all instructions supported by the secondary memory die(s), while only instructions that change the access mode are selectively executed (by the primary memory die). The disclosed architecture can be used, for example, for secure booting. In such an embodiment, the primary memory die locally stores the boot code of a host coupled to a bus and manages secure access to the stored boot code when, for example, storing, updating, and uploading the boot code. In one embodiment, the primary memory die contributes as a trusted root (RoT) of an underlying system including an IC to secure storage operations directed toward the secondary memory dies. For example, the primary memory die may provide write protection and various cryptographic services, such as encryption and data authentication, to the secondary memory dies. In the disclosed techniques, the primary memory die controls access to the secondary memory dies by controlling their respective CS inputs. The disclosed architecture and related embodiments provide low complexity, low power consumption, and fast access to the secondary memory dies.Furthermore, memory dies of different storage technologies are supported, such as mixing Flash NOR die(s) and Flash NAND die(s) within the same package. Since the primary die is managed based on the command die selection, the memory dies do not need to adhere to common rules and / or cooperate with each other to select the target die, which leads to a simplified and flexible implementation. System DescriptionFIG. 1 is a block diagram schematically illustrating a computer system (20) comprising a plurality of memory dies stacked within a common package according to one embodiment described herein. The computer system (20) includes a host (24) coupled to an integrated circuit (IC) (28) implementing a storage device in an example of the present invention via a bus (32) (also referred to as a link or interface). The bus (32) includes a plurality (e.g., a number 'n') of input / output (IO) lines, a clock line designated as "CLK", and a chip select (CS) line designated as "CS-0". The bus (32) may include, for example, a serial peripheral interface (SPI). Alternatively, other suitable bus types, such as extended SPI, expanded SPI (xSPI), and I2C (Inter-Integrated Circuit bus), may be used. In a computer system (20), the host (24) typically communicates commands with the storage device (28) via the bus (32). Communication may include sending an opcode, sending an address, and sending and / or receiving data. The computer system (20) may be used in various applications such as, for example, Internet of Things (IoT) devices, automotive applications, PC / server BIOS (Basic Input-output System), industrial controllers, etc. The storage device (28) includes a memory die (40) designated as "DIE-0" which includes local memory (42) and CS logic (46).Here, the memory die (40) is referred to as the "primary memory die" or simply the "primary die" for brevity. The storage device (28) further includes one or more memory dies (50), each containing memory (54). The memory dies (50) are designated as "die-m" ("DIE-m"), where 'm' represents an integer greater than 0. The memory dies (50) are referred to here as "secondary memory dies" or simply the "secondary dies" for brevity. The primary die and each secondary die have a CS input that, when activated, selects the corresponding memory die. Selecting a memory die means obtaining access to the internal memory of that memory die. Although the storage device (28) in FIG. 1 includes two secondary dies denoted as die-1 and die-2, in alternative embodiments, the storage device may include a single secondary die or two or more secondary dies. In the architecture of FIG. 1, the CLK line and IO line of the bus (32) connect the host (24) and the primary and secondary dies in parallel, respectively. In contrast, the CS-0 line of the bus (32), also referred to as the "primary CS line," connects the CS inputs of the host and the primary die, but not the CS inputs of the secondary dies. The memory selection line, also referred to as the "effective line," connects the CS logic and local memory (42). The CS lines, denoted as "CS-1" and "CS-2," also referred to as the "secondary CS lines," connect the CS logic and CS inputs of the respective secondary dies. The aforementioned architecture allows the CS logic (46) to control access to its local memory (42) and secondary dies (50) and their memories (54).In the following description, the CS signal conveyed on the primary CS line is also referred to as the "primary CS signal," the CS signal carried on the secondary CS line is also referred to as the "secondary CS signal," and the memory select signal conveyed on the effective line is also referred to as the "effective signal." As described below, the CS logic controls the effective signal for accessing the local memory (42) of the primary die and controls the secondary CS signals for accessing the secondary dies. The local memory (42) of the primary die (40) and the memories (54) of the secondary dies (50) may include any suitable type of memory. In an example of the present invention, the local memory (42) of die-0 includes a NOR flash device, whereas the memories (54) of die-1 and die-2 include NAND flash devices. However, in other embodiments, any other suitable combination of memory types may also be used. For example, the local memory (42) of the primary die and the memories (54) of all secondary dies may be of the same memory type. As another example, two (or more) of the memories (54) of the secondary dies may each have different memory types. The memory types primarily used in the context of the invention are NOR dies or NAND dies, but this is not mandatory, and other suitable memory types (volatile or non-volatile) may also be used.When the host (24) transmits a command over the bus, the primary die controls the valid signal and secondary signals so that the command is initially received by the primary die and all secondary dies while the primary CS signal (transmitted from the CS-0 line) is active. As the command proceeds (e.g., after receiving opicode parameters), the CS logic determines the target die to which the command is directed and controls the valid signal and secondary CS signals so that the command is executed by the target die and abandoned by all other memory dies. Methods for determining the target die will be described in detail below. Execution of commands within a multi-die storage deviceFIG. 2 is a flowchart schematically illustrating a method for executing a command within a multi-die storage device according to one embodiment described herein. The method will be described as being executed by the primary die (die-0) of the storage device (28) in FIG. 1. The method of FIG. 2 may be applied, for example, when all memory dies within the storage device support the same set of commands and command formats. The method begins in a command reception step (100), in which die-0 receives a command from a host (24) via a bus (32). The command is conveyed over the bus IO lines using a bus CLK signal. Furthermore, it is assumed that the primary CS signal conveyed over the primary CS line (CS-0) is activated during the command. In response to the primary CS signal, the CS logic (46) of die-0 initially selects the local memory (42) and all secondary dies (50) (die-1 and die-2 in this example). To this end, the CS logic transmits the primary CS signal as an effective signal on the internal effective line, and transmits the primary CS signal as secondary CS signals on the secondary CS lines of the secondary dies. As a result, the local memory (42) of die-0 and the memories (54) of the secondary dies receive at least the opicode parameters of the instruction, and thus each of the primary die and each of the secondary dies is ready to execute the instruction when selected as the target die. In the die selection step (104), the CS logic of die-0 determines the target die to which the instruction is directed. For example, die-0 may determine the target die based on information conveyed within the opicode parameters and / or address parameters of the current or previous instruction (if available). When die-0 is selected as the target die in step (104), the method proceeds to the primary die execution step (108).Otherwise, Die-1 or Die-2 is the target die, and the method proceeds to the secondary die execution step (112). In step (108), Die-0 executes the command by means of CS logic by (i) transmitting the (active) primary CS signal as an effective signal onto the local effective line of local memory (42) and (ii) deactivating the secondary CS signals of all secondary dies (Die-1 and Die-2 in this example). Since the secondary dies are deselected, the secondary dies abandon the execution of the command. In step (112), Die-0 causes the target die (Die-1 or Die-2 in this example) to execute the command by means of CS logic by (i) transmitting the primary CS signal as a secondary CS signal onto the secondary CS line of the target die, (ii) deactivating the secondary CS signals of the other secondary dies, and (iii) deactivating the local effective signal of Die-0. Deactivating the valid signal or secondary CS signal can be performed using any suitable method, such as using a logical OR gate when the signal is low-active or using a logical AND gate when the signal is high-active. Following each step (108) and step (112), the method loops back to step (100) to receive a subsequent command. The method of FIG. 2 is provided as an example, and other suitable methods may also be used. For example, if the command includes only opicode commands, such as configuration commands, the primary die can control the valid signal and secondary CS signals to allow multiple memory dies to execute commands in parallel with each other. FIG. 3 is a timing diagram schematically showing various signals generated during the execution of a read command in a multi-die storage device according to the embodiment described herein.A timing diagram will be described, for example, for a system (e.g., system (20)) in which a host (24) executes a read command using the method of FIG. 2. In an example of the present invention, the bus (32) includes an SPI having an IO0 line for transmitting commands to a storage device (28) and an IO1 line for receiving data from the storage device. As illustrated in the drawing, the command has an 8-bit opcode parameter (150) transmitted starting with the most significant bit (MSb) and ending with the least significant bit (LSb). Following the opcode parameter is a 32-bit address parameter (154) transmitted starting with the highest address bit (A31) and ending with the lowest address bit (A0). In response to the read command, the storage device reads byte-0… from the target die The byte-m data is transmitted back to the host via the IO1 line. The primary CS signal (158) is transmitted from the host via the primary CS line (CS-0) of the bus that is activated during the command. In the example of FIG. 3, the primary CS signal is activated just before the MSb of the opicode begins (e.g., in this example, a change from a high level to a low level) and remains active until the memory device completes the transmission of the m-th data byte via the IO1 line. In the example of FIG. 3, it is assumed that Die-0 determines the target die in a time instance (162) based on some of the upper address bits of the address parameter. The timing diagram depicts the effective signals and secondary CS signals in the cases where (i) the target die is Die-0 (170), which is the primary die, and (ii) the target die is Die-2 (174), which is the secondary die.When the primary CS signal (158) is activated, the CS logic initially transmits the primary CS signal as an effective signal on the effective line of die-0 and transmits it as secondary signals on the secondary CS lines of die-1 and die-2. This allows all memory dies to receive at least some of the opicode parameters and address parameters. If die-0 is the target die, the CS logic continues to transmit the primary CS signal as an effective signal on the effective line. Furthermore, the CS logic causes die-1 and die-2 to abandon the command by deactivating the secondary CS signals of the secondary dies. (For example) If die-2 is the target die, the CS logic causes die-2 to execute the command by transmitting the primary CS signal as a secondary signal on the secondary CS line of die-2. Die-0 also causes Die-1 and Die-0 to abandon the command by deactivating the secondary CS signal of Die-1 and the active signal of Die-0, respectively. The timing diagram shown in FIG. 3 and described above is cited as an example. Other suitable timing diagrams may be used as alternative examples. For example, in some embodiments, the bus-width operating mode may be Quad or Octal, and additional IO lines may be added accordingly. In this case, multiple bits of the command will be transmitted during each clock cycle. Although FIG. 3 shows 32-bit address parameters, other address lengths, such as 24-bit addresses, may also be used. As another example, although the timing diagram in FIG. 3 depicts low-active CS signals, high-active CS signals may also be used in alternative embodiments. How to determine the target dieAs soon as the primary die receives a command from the storage device (28), it determines which of the memory dies within the storage device will execute the command (e.g., using CS logic (46)). The memory die selected to execute the given command is referred to herein as the "target die" for the given command. The target die may be either the primary die or the secondary dies. Generally, a sequence of commands may contain commands directed to the same memory die or to two or more different memory dies. In the disclosed embodiments, the primary die (40) (die-0) handles the selection of a single target die for each command. The primary die may determine the target die for a given command in various ways, as described below. In one embodiment, each memory die is pre-assigned a respective die identifier, and the primary die selects the target die in response to receiving a dedicated die-selection command that specifies the identifier of the target die. The dedicated command may specify the die identifier, for example, within an opcode parameter or within a separate parameter following the opcode parameter. A die-select command is processed by the primary die but is ignored by the secondary dies because it is not part of the instruction set supported by the secondary dies. In one embodiment, in response to a die-select command, the primary die controls the valid signal and secondary CS signals so that subsequent instructions are executed by the target die (typically without other dies). The primary die continues to monitor subsequently received instructions even if the target die is a secondary die, and as soon as it receives another die-select command, it re-selects the target die accordingly. Some instructions, such as read, program, and erase commands, contain address parameters. For these instructions, the primary die can determine the target die based on the address parameters.In this method, the primary die and secondary dies are mapped to a common address space divided into multiple address sub-ranges, where each memory die is mapped to a respective address sub-range of the address space. In some embodiments, upon receiving an instruction having an address parameter, the primary die determines the target die based on at least a portion of the address parameter, for example, the MS byte (Most Significant byte) of the address, by identifying the address sub-range to which the address parameter belongs. Address-based target die selection as described above is applicable to storage devices where all memory dies share the same set of instructions and instruction formats, but is not limited thereto. As described in FIG. 1 above, the storage device may include memory dies of various memory types that comply with different sets of instructions, different instruction formats, and / or different access protocols, for example, when mixing NOR and NAND flash devices within the same storage device. In such embodiments, a host accessing the target dies needs to use instructions from the set of instructions supported by each target die. Alternatively or additionally, the primary die may present to the host an access protocol used by a secondary die having a memory type different from the memory type of the primary die. This allows the host to communicate with all memory dies using a common access protocol. For example, consider performing a read operation on a storage device (28) where the primary die is a NOR flash device and the secondary dies are NAND flash devices. A read (or write) command for a NOR flash device typically conveys full address parameters (e.g., a 24-bit or 32-bit memory address) for direct access.In contrast, read operations applied to a NAND flash device are typically indirect and involve one or more "page-read" commands following a "page-load" command. Within the target NAND device, the page-load command loads a page from memory into a local read buffer (not shown) of the target NAND device. The page may contain several kilobytes (Kbytes) of data (e.g., 4 kilobytes or any other suitable size). The page-read command reads data from the read buffer loaded by the preceding page-load command. The page-load command typically conveys only the most significant bits (16 most significant bits) of the address parameters (e.g., A31…A16), whereas the page-read command typically conveys only the lower significant bits (16 low significant bits) of the address parameters (e.g., A15…A0). In an example of the present invention, the primary die is such that the address portion conveyed by the page-load command falls within the lower range assigned to the given target die. At that time, a given target die is selected. Page-load commands are typically executed by all secondary NAND dies. After determining the NAND target die, the primary die controls the valid signal and secondary CS signals to ensure that subsequent page-read commands are executed only by the target NAND die and are abandoned by the primary die and other secondary dies. Furthermore, the primary die monitors subsequent commands received via the bus, and as soon as a subsequent page-load command is detected, it re-selects the target die based on the address parameters conveyed in that subsequent page-load command. Additional Considerations and FeaturesAdditional implementation considerations and features will be described below. When two or more memory dies have different storage sizes, various address mappings may be used. For example, consider a storage device comprising a 128-megabit primary NOR die and one or more 1-gigabit secondary NAND dies. This architecture is applicable, for example, to store relatively small boot code within the NOR device and to extend the overall storage space using the secondary NAND dies. In one such embodiment, the primary die may be mapped to an address subrange beyond the address subranges allocated to the secondary NAND dies. For example, in the case of a single 1 Gigabit secondary NAND die, the NAND die is mapped to the address subrange 0000_0000h-07FF_FFFFh, and the 128 Megabit primary NOR die is mapped to the address range 0800_0000h-08FF_FFFFh. In another embodiment, the address subrange assigned to the primary NOR die overlaps with the address range assigned to the secondary NAND dies. For example, the 128 Megabit primary NOR die is mapped to the address subrange given by 0000_0000h-00FF_FFFFh, and the single 1 Gigabit secondary NAND die is mapped to the address subrange given by 0100_0000h-07FF_FFFFh. In this case, the lower 128 megabit addresses of the secondary die are inaccessible. In some embodiments, the primary die (NOR) presents the access protocol of the secondary dies (NAND) to the host.To this end, the primary die (NOR) implements page-load and page-read commands for the NAND dies, enabling a host with a NAND flash controller to access the primary die (NOR) and secondary dies (NAND) using the same command set and format (at least for read operations). In these embodiments, the local memory of the primary die (NOR) appears to the host as a NAND device, and thus software running on the host can access memories within the storage device while accessing a monolithic (single die) NAND flash memory device. In some embodiments, before accessing either the NAND format or any of the secondary NAND dies, the host is required to load a suitable driver designed to access NAND memories from the storage device, for example. Certain commands may be too short to allow sufficient time for the primary die to determine the target die based on address parameters. For example, in xSPI octal Dual Transfer Rate (DTR) bus mode (also referred to as "8d-8d-8d" mode—meaning that command, address, and data transfers are 8-bit wide DTRs), a block erase command of an issued NAND device requires one clock cycle for the op-code, followed by an additional clock cycle for the address. In this case, before the primary die determines the target die based on the address parameter, the secondary dies may undesirably execute the erase command (in response to the op-code and address parameter).In some embodiments, to avoid such erroneous command execution, the primary die restricts the use of the address-based target selection method to selected commands (e.g., read operations only) and blocks commands that could lead to erroneous execution (e.g., erase operations and program operations). Unlike erase and program commands, in a read command, the die continues to process the command after receiving the address, prepares a response, and then begins to transmit the response back to the host, leaving sufficient time for the command to be terminated by dies other than the target die. In some embodiments, commands that modify the contents stored in the storage device, such as program and erase commands, are preceded by a write-enable command. The primary die monitors commands received via the bus, and as soon as it detects a write-enable command (or other qualifying conditions) while the target die is one of the secondary dies, the primary die blocks further access to the secondary dies, for example, by resetting the next system or relying on a predefined flow implemented within the primary die. Thus, the primary die blocks any series of commands starting with a write-enable command followed by a program or erase command, which implies that the secondary dies are inherently write-protected. Therefore, the primary die manages write protection for the secondary dies even if it does not support inherent write protection mechanisms. In some embodiments, the primary die supports security features that can be used to provide write protection (and other security features) for the secondary dies even if the secondary dies do not support inherent security features.For example, the primary die may execute security commands protected by, for example, signatures, passwords, and / or other user authentication mechanisms to obtain access to secondary dies. In some embodiments, the primary die supports selectable access modes from a number of predefined modes. In an exemplary embodiment, the primary die supports a threefold access mode including (i) a "standalone" mode, (ii) a restricted-access mode, and (iii) a full-access mode. In one embodiment, the primary die (40) switches among the access modes by control of the host (24). In standalone mode, the primary die allows access only to local memory and blocks access to any secondary dies. This mode is useful, for example, in a system where the host boots from the primary die (e.g., a NOR flash device). In standalone mode, the primary die selects itself as the target die for all incoming commands, so there is no need to determine the target die on the fly. After the boot process is complete, the primary die may be switched to restricted-access mode, which allows the primary die (e.g., NOR) to access secondary dies (e.g., NANDs) for specific commands containing address parameters (e.g., read access). In restricted-access mode, the primary die can present the access protocols of the secondary dies to the host as described above. In full-access mode, the primary die allows access to secondary dies for all supported commands. This mode can be used to program, erase, and / or configure the secondary dies. In full-access mode, the primary die monitors received commands and responds only to save commands that change the access mode to restricted-access mode or standalone mode.In some embodiments, the standalone mode serves as the default access mode after a reset. In such embodiments, in response to a reset event, the primary die automatically begins to operate in standalone mode, allowing the host to boot from the primary die (e.g., NOR). For example, at a suitable time after booting is complete, the host is loaded from storage device firmware (FW) code containing drivers for accessing the NAND dies and switches to restricted-access or full-access mode. In other embodiments, the restricted-access mode or full-access mode may serve as the default mode after a reset. In this case, after a reset, the primary die begins to operate in the restricted-access mode or full-access mode. Such embodiments are useful, for example, when the host boots from secondary dies rather than the primary die. In an exemplary embodiment, the primary die includes a secure device stacked within the same package as one or more secondary dies. In such embodiments, the primary die serves as the Root of Trust (RoT) of the system. The storage device may rely on the secure functions of the primary die to store, protect, and update the boot code stored within the primary die. The embodiments described above are given by way of example, and other suitable embodiments may also be used. For example, although some of the embodiments refer to a storage device comprising a NOR primary die and one or more NAND secondary dies, this architecture is not mandatory, and in other embodiments, other suitable combinations of NOR, NAND, and / or other memory types may be used.Configurations of a computer system (20), including components such as a host (24), a storage device (28) and a primary die (40), local memory (42) and CS logic (46), and secondary dies (50) and memories (54), are exemplary configurations illustrated purely for conceptual clarity. Any other suitable computer, host, and memory die configurations may be used in alternative embodiments. Different sub-units of the storage device (28) may be implemented using software, hardware, or a combination of hardware and software elements, using suitable hardware such as one or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs). The storage device (28) may include one or more general-purpose processors, which are programmed in software to perform the functions described herein. Software may be downloaded to processor(s) in electronic form, for example, via a network or from a host, or alternatively or additionally, provided and / or stored on non-transitory tangible media such as magnetic, optical, or electronic memory. It will be understood that the foregoing embodiments are cited by way of example and that the following claims are not limited to those specifically shown and described herein. Rather, the scope includes combinations and sub-combinations of the various features described herein, as well as variations and modifications thereof that may come to mind to a person skilled in the art upon reading the foregoing description and are not disclosed in the prior art.The documents incorporated by reference in this patent application shall be considered as part of the application, except to the extent of any terms defined in such incorporated documents in a manner that conflicts with the definitions made expressly or implied in this description, and only the definitions in this description shall be considered.

Claims

Claim 1 In an integrated circuit (IC), the primary memory die is coupled to a bus that provides a primary chip select signal through a primary chip select (CS) line connected to the primary memory die—the bus comprises input / output lines, a clock line, and the primary chip select line, and the bus excluding the primary chip select line comprises the input / output lines and the clock line—; and includes a secondary memory die coupled to a secondary chip select line that transmits a secondary chip select signal provided by the primary memory die, and a secondary memory die directly coupled to the bus excluding the primary chip select line; the primary memory die is configured to receive a command via the bus while the primary chip select signal is active, execute the command within the primary memory die in response to identifying that the command is directed to the primary memory die, and transmit the primary chip select signal to the secondary chip select signal on the secondary chip select line in response to identifying that the command is directed to the secondary memory die, thereby causing the secondary memory die to execute the command; the primary memory die is configured to locally store the boot code of a host coupled to the bus and manage secure access to the stored boot code, or the primary memory die is configured to secure storage operations to the secondary memory die, the base system including the integrated circuit (IC) An integrated circuit (IC) configured to operate as a trusted root (RoT). Claim 2 An integrated circuit (IC) according to claim 1, wherein the primary memory die comprises a local memory selectable by a local effective signal transmitted on a local effective line, and the primary memory die is configured to execute the command by (i) transmitting the primary chip select signal as the local effective signal on the local effective line, and (ii) deactivating the secondary chip select signal provided to the secondary memory die. Claim 3 In paragraph 2, the integrated circuit (IC) comprises another secondary memory die coupled to another secondary chip select line that transmits another secondary chip select signal provided by the primary memory die, and another secondary memory die coupled to the bus excluding the primary chip select line, wherein the primary memory die is configured to cause the other secondary memory die to execute the command by (i) transmitting the primary chip select signal on the other secondary chip select line as the other secondary chip select signal, (ii) deactivating the secondary chip select signal provided to the secondary memory die, and (iii) deactivating the local effective signal provided to the local memory of the primary memory die. Claim 4 In claim 1, the primary memory die and the secondary memory die are each first and second different memory types, and are each selected from a list including at least (i) NAND flash memory type and (ii) NOR flash memory type, an integrated circuit (IC). Claim 5 An integrated circuit (IC) according to claim 1, wherein the primary memory die supports a first access protocol and the secondary memory die supports a second access protocol, the first access protocol is different from the second access protocol, and the primary memory die is configured to provide the second access protocol of the secondary memory die to a host coupled to the bus. Claim 6 An integrated circuit (IC) according to claim 1, wherein the primary memory die is configured to execute one or more commands received subsequently to the die-select command in response to receiving a die-select command specifying a memory die selected between the primary memory die and the secondary memory die. Claim 7 An integrated circuit (IC) according to claim 1, wherein the primary memory die and the secondary memory die are each mapped to different address subranges of a common address space, and the primary memory die is configured to identify an address parameter within the received instruction and to execute the received instruction by the primary memory die or the secondary memory die depending on the address subrange to which the address parameter belongs. Claim 8 delete Claim 9 An integrated circuit (IC) according to claim 1, wherein the primary memory die is configured to operate according to an access mode in which the primary memory die controls the secondary chip select signal to allow access to the secondary memory die for a subset of instructions supported by the secondary memory die. Claim 10 An integrated circuit (IC) according to claim 1, wherein the primary memory die is configured to operate according to an access mode in which the primary memory die controls the secondary chip select signal to allow full access to the secondary memory die for all instructions supported by the secondary memory die while selectively executing instructions that change the access mode. Claim 11 delete Claim 12 delete Claim 13 A method for storing data comprises: a primary memory die coupled to a bus that provides a primary chip select signal through a primary chip select (CS) line connected to a primary memory die, wherein the bus comprises input / output lines, a clock line, and the primary chip select line, and the bus excluding the primary chip select line comprises the input / output lines and the clock line; and a secondary memory die coupled to a secondary chip select line that transmits a secondary chip select signal provided by the primary memory die, and directly coupled to the bus excluding the primary chip select line; wherein, in the integrated circuit (IC), while the primary chip select signal is active, the method comprises receiving a command through the bus by the primary memory die; and executing the command within the primary memory die in response to identifying that the command is directed to the primary memory die. A method comprising the step of causing the secondary memory die to execute the command by transmitting the primary chip select signal to the secondary chip select signal in response to identifying that the command is directed to the secondary memory die, and the method comprises the step of locally storing the boot code of a host coupled to the bus; and the step of managing secure access to the stored boot code, or the method comprises the step of operating as a trusted root (RoT) of an underlying system including the integrated circuit (IC) to secure storage operations to the secondary memory die. Claim 14 In claim 13, the primary memory die comprises a local memory selectable by a local effective signal transmitted over a local effective line, and the step of executing the command within the primary memory die comprises: (i) transmitting the primary chip select signal as the local effective signal over the local effective line, and (ii) deactivating the secondary chip select signal provided to the secondary memory die to execute the command. Claim 15 In claim 14, the integrated circuit (IC) comprises another secondary memory die coupled to another secondary chip select line that transmits another secondary chip select signal provided by the primary memory die and coupled to the bus excluding the primary chip select line, and the method comprises the steps of: (i) transmitting the primary chip select signal on the other secondary chip select line as the other secondary chip select signal; (ii) deactivating the secondary chip select signal provided to the secondary memory die; and (iii) deactivating the local effective signal provided to the local memory of the primary memory die, thereby causing the other secondary memory die to execute the command. Claim 16 In claim 13, the primary memory die and the secondary memory die are each first and second different memory types, respectively selected from a list including at least (i) NAND flash memory type and (ii) NOR flash memory type. Claim 17 In claim 13, the primary memory die supports a first access protocol, the secondary memory die supports a second access protocol, the first access protocol is different from the second access protocol, and the method comprises the step of providing the second access protocol of the secondary memory die to a host coupled to the bus by the primary memory die. Claim 18 A method according to claim 13, comprising the step of, in response to receiving a die-selection command specifying a selected memory die between the primary memory die and the secondary memory die, causing the selected memory die to execute one or more commands received subsequently to the die-selection command. Claim 19 A method according to claim 13, wherein the primary memory die and the secondary memory die are each mapped to different address subranges of a common address space, and the method comprises the steps of: identifying an address parameter within the received command; and executing the received command by the primary memory die or the secondary memory die depending on the address subrange to which the address parameter belongs. Claim 20 delete Claim 21 A method according to claim 13, comprising the step of the primary memory die operating according to an access mode that controls the secondary chip select signal to allow access to the secondary memory die for a subset of instructions supported by the secondary memory die. Claim 22 A method according to claim 13, comprising the step of the primary memory die operating according to an access mode that controls the secondary chip select signal to allow full access to the secondary memory die for all commands supported by the secondary memory die while selectively executing commands that change the access mode. Claim 23 delete Claim 24 delete

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