Image sensor

Abstract

An image sensor is provided. The image sensor comprises: a substrate having a first photoelectric conversion element disposed therein and a first surface and a second surface opposite to the first surface defined therein; a pixel separation pattern extending from the first surface of the substrate into the interior of the substrate, surrounding the first photoelectric conversion element, and defining a first pixel area on the substrate; a first vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel area and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel area and disposed directly adjacent to the first vertical gate structure, and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; and a floating diffusion region disposed at the edge of the first pixel area in the interior of the substrate, disposed between the first portion of the first vertical gate structure and the first portion of the second vertical gate structure, wherein the upper surface is formed coplanar with the first surface of the substrate, wherein the closer the first portion of the first vertical gate structure is to the floating diffusion region, the more the first portion of the first vertical gate structure The width in the horizontal direction is reduced overall, the first part of the first vertical gate structure includes a first side wall facing the first part of the second vertical gate structure, the first part of the second vertical gate structure includes a second side wall facing the first part of the first vertical gate structure, and the gap between the first side wall and the second side wall decreases as it becomes closer to the floating diffusion area.

Description

Technology Field

[0001] The present invention relates to an image sensor. Background Technology

[0002] An image sensing device is one of the semiconductor devices that converts optical information into electrical signals. Such image sensing devices may include Charge Coupled Device (CCD) image sensing devices and Complementary Metal-Oxide Semiconductor (CMOS) image sensing devices.

[0003] A CMOS type image sensor may be abbreviated as CIS (CMOS image sensor). A CIS may have multiple pixels arranged in two dimensions. Each pixel may include, for example, a photodiode (PD). The photodiode can convert incident light into an electrical signal.

[0004] Recently, with the development of the computer and telecommunications industries, the demand for image sensing devices with improved performance and miniaturization has been increasing in various fields, including digital cameras, camcorders, smartphones, gaming devices, security cameras, medical micro cameras, and robots. Accordingly, research is being conducted on highly scaled, high-density semiconductor devices within image sensing devices, and the patterns of these semiconductor devices can have fine widths and be spaced at fine pitches. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide an image sensor that improves the transmission characteristics of a vertical gate structure by arranging the vertical gate structure such that two vertical gate structures are placed in one unit pixel, and the spacing between the two vertical gate structures decreases as they become adjacent to a floating diffusion region in one unit pixel.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] Some embodiments of an image sensor according to the technical concept of the present invention for solving the above problem include: a substrate having a first photoelectric conversion element disposed therein and a first surface and a second surface opposite to the first surface defined therein; a pixel separation pattern extending from the first surface of the substrate into the interior of the substrate, surrounding the first photoelectric conversion element, and defining a first pixel region in the substrate; a first vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region, disposed directly adjacent to the first vertical gate structure, and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; and a floating diffusion region disposed at the edge of the first pixel region in the interior of the substrate, disposed between the first portion of the first vertical gate structure and the first portion of the second vertical gate structure, wherein the upper surface is formed coplanar with the first surface of the substrate. As it gets closer to the floating diffusion region, the horizontal width of the first part of the first vertical gate structure decreases overall, the first part of the first vertical gate structure includes a first side wall facing the first part of the second vertical gate structure, the first part of the second vertical gate structure includes a second side wall facing the first part of the first vertical gate structure, and as it gets closer to the floating diffusion region, the gap between the first side wall and the second side wall decreases.

[0008] Some other embodiments of an image sensor according to the technical concept of the present invention for solving the above problem include: a substrate having first and second photoelectric conversion elements disposed therein and a first surface and a second surface opposite to the first surface defined therein; a pixel separation pattern extending from a first surface of the substrate into the interior of the substrate, surrounding each of the first and second photoelectric conversion elements, and defining each of a first pixel area where the first photoelectric conversion element is disposed on the substrate and a second pixel area where the second photoelectric conversion element is disposed therein; a first vertical gate structure extending from a first surface of the substrate into the interior of the substrate in the first pixel area and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from a first surface of the substrate into the interior of the substrate in the first pixel area and disposed in direct adjacent to the first vertical gate structure and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; and a first portion extending from a first surface of the substrate into the interior of the substrate in the second pixel area and disposed inside the substrate and A third vertical gate structure comprising a second portion disposed on a first surface of a substrate; a fourth vertical gate structure comprising a first portion disposed on the first surface of a substrate and a second portion disposed on the first surface of a substrate, extending from the first surface of the substrate into the interior of the substrate in a second pixel area and disposed directly adjacent to the third vertical gate structure; a floating diffusion area disposed at the edge of each of the first and second pixel areas in the interior of the substrate, disposed between the first portion of the first vertical gate structure and the first portion of the second vertical gate structure and between the first portion of the third vertical gate structure and the first portion of the fourth vertical gate structure, wherein the upper surface is formed coplanar with the first surface of the substrate, the first portion of the first vertical gate structure comprises a first sidewall facing the first portion of the second vertical gate structure.The first part of the second vertical gate structure includes a second side wall facing the first part of the first vertical gate structure, and the distance between the first side wall and the second side wall decreases as it approaches the floating diffusion region.

[0009] Some other embodiments of an image sensor according to the technical concept of the present invention for solving the above problem include: a substrate having a first photoelectric conversion element disposed therein and a first surface and a second surface opposite to the first surface defined therein; a pixel separation pattern extending from the first surface of the substrate into the interior of the substrate, surrounding the first photoelectric conversion element, and defining a first pixel region on the substrate; a first vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region, disposed directly adjacent to the first vertical gate structure, and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; and a vertical structure disposed at the edge of the first pixel region inside the substrate and disposed between the first portion of the first vertical gate structure and the first portion of the second vertical gate structure, wherein the upper surface is formed coplanar with the first surface of the substrate and vertically with respect to the pixel separation pattern. It includes a floating diffusion region that overlaps in the direction, wherein the planar shape of each of the first part of the first vertical gate structure and the first part of the second vertical gate structure has a triangular shape, the angle between two side walls of the first part of the first vertical gate structure adjacent to the floating diffusion region is greater than or equal to 30 degrees and less than 45 degrees, the angle between two side walls of the first part of the second vertical gate structure adjacent to the floating diffusion region is greater than or equal to 30 degrees and less than 45 degrees, the first part of the first vertical gate structure includes a first side wall facing the first part of the second vertical gate structure, the first part of the second vertical gate structure includes a second side wall facing the first part of the first vertical gate structure, and the distance between the first side wall and the second side wall decreases as it gets closer to the floating diffusion region.

[0010] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is an exemplary block diagram for illustrating an image sensor according to some embodiments of the present invention. FIG. 2 is a schematic plan view for illustrating an image sensor according to some embodiments of the present invention. Figure 3 is a cross-sectional view taken along the AA' and BB' lines of Figure 2. Figure 4 is a cross-sectional view taken along the AA' and CC' lines of Figure 2. Figure 5 is a cross-sectional view taken along the AA' and DD' lines of Figure 2. FIGS. 6 and 7 are plan views illustrating a vertical gate structure of an image sensor according to some embodiments of the present invention. Figure 8 is a cross-sectional view taken along the EE' line of Figures 6 and 7, respectively. Figure 9 is a cross-sectional view taken along the FF' line of Figures 6 and 7, respectively. FIG. 10 is a plan view illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention. FIGS. 11 and FIGS. 12 are plan views illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention. FIG. 13 is a cross-sectional view taken along the GG' line in FIG. 11 and FIG. 12, respectively. FIG. 14 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention. FIGS. 15 and 16 are plan views illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention. FIG. 17 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention. FIGS. 18 and 19 are plan views illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention. FIG. 20 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention. FIG. 21 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention. FIG. 22 is a cross-sectional view taken along the HH' line of FIG. 21. Specific details for implementing the invention

[0012] Hereinafter, an image sensor according to several embodiments of the present invention will be described with reference to FIGS. 1 to 9.

[0013] FIG. 1 is an exemplary block diagram illustrating an image sensor according to some embodiment of the present invention. FIG. 2 is a schematic plan view illustrating an image sensor according to some embodiment of the present invention. FIG. 3 is a cross-sectional view cut along lines AA' and BB' of FIG. 2. FIG. 4 is a cross-sectional view cut along lines AA' and CC' of FIG. 2. FIG. 5 is a cross-sectional view cut along lines AA' and DD' of FIG. 2. FIG. 6 and FIG. 7 are plan views illustrating a vertical gate structure of an image sensor according to some embodiment of the present invention. FIG. 8 is a cross-sectional view cut along line EE' of FIG. 6 and FIG. 7, respectively. FIG. 9 is a cross-sectional view cut along line FF' of FIG. 6 and FIG. 7, respectively.

[0014] Referring to FIG. 1, an image sensor according to some embodiments of the present invention includes an active pixel sensor array (10; APS, active pixel sensor array), a row decoder (20; Row Decoder), a row driver (30; Row Driver), a column decoder (40; Column Decoder), a timing generator (50; Timing Generator), a correlated double sampler (60; CDS, correlated double sampler), an analog to digital converter (70; ADS, analog to digital converter), and an input / output buffer (80; I / O Buffer).

[0015] The active pixel sensor array (10) includes a plurality of unit pixels arranged in two dimensions and can convert an optical signal into an electrical signal. The active pixel sensor array (10) can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver (30). Additionally, the electrical signal converted by the active pixel sensor array (10) can be provided to a correlation double sampler (60).

[0016] The row driver (30) can provide a plurality of driving signals to the active pixel sensor array (10) to drive a plurality of unit pixels according to the result decoded by the row decoder (20). If the unit pixels are arranged in a matrix form, driving signals can be provided for each row.

[0017] The timing generator (50) can provide timing signals and control signals to the row decoder (20) and the column decoder (40).

[0018] The correlation double sampler (CDS; 60) can receive, hold, and sample electrical signals generated from the active pixel sensor array (10). The correlation double sampler (60) can double-sample a specific noise level and a signal level from an electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0019] An analog-to-digital converter (ADC; 70) can convert an analog signal corresponding to the difference level output from a correlated double sampler (60) into a digital signal and output it.

[0020] The input / output buffer (80) latches a digital signal, and the latched signal can sequentially output the digital signal to a video signal processing unit (not shown) according to the decoding result in the column decoder (40).

[0021] Referring to FIG. 2, an image sensor according to some embodiments of the present invention may include first to fourth regions (I, II, III, IV).

[0022] The first region (I) and the second region (II) may be sensor array regions. In a plane defined by the first horizontal direction (DR1) and the second horizontal direction (DR2) perpendicular to the first horizontal direction (DR1), the second region (II) may surround the first region (I).

[0023] The first region (I) may be an active pixel sensor region including an active pixel for generating an active signal corresponding to wavelengths of light from the outside. The second region (II) may be an optical black sensor region for generating an optical black signal by blocking light from the outside.

[0024] The fourth region (IV) may be a pad region. A plurality of pads (180) placed in the fourth region (IV) may exchange electrical signals with an external device. In a plane defined by the first horizontal direction (DR1) and the second horizontal direction (DR2), the fourth region (IV) may surround the second region (II).

[0025] The third region (III) may be a connection region. The third region (III) may be electrically connected to a logic circuit region placed on the lower surface (130a) of the second substrate (130). The third region (III) may be placed between the second region (II), which is an optical black sensor region, and the fourth region (IV), which is a pad region.

[0026] Referring to FIGS. 3 through 9, an image sensor according to some embodiments of the present invention comprises a first substrate (100), a first insulating layer (101), a second insulating layer (102), a gate structure (105), a first wiring structure (110), a second wiring structure (120), a second substrate (130), first to fifth photoelectric conversion elements (PD1 to PD5), first to ninth vertical gate structures (VG1 to VG9), a floating diffusion region (FD), a first pixel separation pattern (135), a second pixel separation pattern (140), a passivation layer (150), a first color filter (151), a second color filter (152), a grid pattern (155), a microlens (157), a protective film (158), a transparent layer (159), first to third conductive patterns (161, 162, 163), an adhesive layer (171), a low refractive index layer (172), and a photo It may include a resist (173) and a pad (180).

[0027] The first substrate (100) may be, for example, bulk silicon or SOI (silicon-on-insulator). The first substrate (100) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate (100) may be a base substrate on which an epitaxial layer is formed.

[0028] A first insulating layer (101) may be disposed on a first substrate (100). The first insulating layer (101) may be disposed to cover a gate structure (105) disposed on the first substrate (100). The first insulating layer (101) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low dielectric constant material, and combinations thereof.

[0029] The first wiring structure (110) may be disposed on the first insulating layer (101). The first wiring structure (110) may include a first interlayer insulating film (112) and a plurality of first wiring layers (111) disposed inside the first interlayer insulating film (112).

[0030] The first wiring layer (111) may include, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), etc., but the technical concept of the present invention is not limited thereto. The first interlayer insulating film (112) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low dielectric constant material, and combinations thereof.

[0031] A second wiring structure (120) may be disposed on a first wiring structure (110). The second wiring structure (120) may include a second interlayer insulating film (122) and a plurality of second wiring layers (121) disposed inside the second interlayer insulating film (122).

[0032] The second wiring layer (121) may include, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), etc., but the technical concept of the present invention is not limited thereto. The second interlayer insulating film (122) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low dielectric constant material, and combinations thereof.

[0033] The second insulating layer (102) may be disposed on the second wiring structure (120). The second insulating layer (102) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low dielectric constant material, and combinations thereof.

[0034] A second substrate (130) may be disposed on a second insulating layer (102). The second substrate (130) may be, for example, bulk silicon or a silicon-on-insulator (SOI). The second substrate (130) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate (130) may be an epitaxial layer formed on a base substrate. The second substrate (130) may include a first surface (130a) in contact with the second insulating layer (102) and a second surface (130b) opposite to the first surface (130a).

[0035] For convenience of explanation, the second substrate (130) is defined as including a first region (I) where an active pixel sensor region is formed, a second region (II) where an optical black sensor region is formed, a third region (III) where a connection region is formed, and a fourth region (IV) where a pad region is formed.

[0036] A plurality of photoelectric conversion elements may be disposed inside the second substrate (130). For example, the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) may be disposed inside the first region (I) of the second substrate (130). The first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) may be disposed spaced apart from each other in the first horizontal direction (DR1) or the second horizontal direction (DR2). The fifth photoelectric conversion element (PD5) may be disposed inside the second region (II) of the second substrate (130). Each of the first to fifth photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5) may be a photodiode, but the technical concept of the present invention is not limited thereto.

[0037] The first pixel separation pattern (135) may be disposed between each of the first to fifth photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5). The first pixel separation pattern (135) may surround each of the first to fifth photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5). The first pixel separation pattern (135) may extend in a vertical direction (DR3) from the first surface (130a) of the second substrate (130) into the interior of the second substrate (130). Here, the vertical direction (DR3) may be defined as a direction perpendicular to each of the first horizontal direction (DR1) and the second horizontal direction (DR2).

[0038] For example, the surface of the first pixel separation pattern (135) exposed on the first surface (130a) of the second substrate (130) may be formed coplanarally with the first surface (130a) of the second substrate (130). The first pixel separation pattern (135) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxycarbon (SiOC), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN).

[0039] The second pixel separation pattern (140) may be placed between each of the first to fifth photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5). The second pixel separation pattern (140) may surround each of the first to fifth photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5). The first pixel separation pattern (135) may surround at least a portion of the second pixel separation pattern (140). For example, the width of the first horizontal direction (DR1) of the second pixel separation pattern (140) may be greater than the width of the first horizontal direction (DR1) of the first pixel separation pattern (135).

[0040] The second pixel separation pattern (140) may extend vertically (DR3) from the first surface (130a) of the second substrate (130) into the interior of the second substrate (130). For example, the second pixel separation pattern (140) may extend to the second surface (130b) of the second substrate (130). That is, the surface of the second pixel separation pattern (140) exposed on the first surface (130a) of the second substrate (130) may be formed coplanarally with the first surface (130a) of the second substrate (130). Additionally, the surface of the second pixel separation pattern (140) exposed on the second surface (130b) of the second substrate (130) may be formed coplanarly with the second surface (130b) of the second substrate (130). Each of the first to fifth photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5) can be separated from one another by the first pixel separation pattern (135) and the second pixel separation pattern (140).

[0041] The first and second pixel separation patterns (135, 140) can define a plurality of pixel regions separated from each other within the second substrate (130). For example, as illustrated in FIG. 6, the first and second pixel separation patterns (135, 140) can define first to fourth pixel regions (PX1, PX2, PX3, PX4) separated from each other within the second substrate (130). For example, the second pixel region (PX2) can be spaced apart from the first pixel region (PX1) in the first horizontal direction (DR1). The third pixel region (PX3) can be spaced apart from the first pixel region (PX1) in the second horizontal direction (DR2). The fourth pixel region (PX4) can be spaced apart from the third pixel region (PX3) in the first horizontal direction (DR1). Additionally, the fourth pixel area (PX4) can be spaced apart from the second pixel area (PX2) in the second horizontal direction (DR2).

[0042] For example, a first photoelectric conversion element (PD1) may be placed in a first pixel area (PX1). A second photoelectric conversion element (PD2) may be placed in a second pixel area (PX2). A third photoelectric conversion element (PD3) may be placed in a third pixel area (PX3). A fourth photoelectric conversion element (PD4) may be placed in a fourth pixel area (PX4).

[0043] The second pixel separation pattern (140) may include a barrier layer (141) and a filling layer (142). The barrier layer (141) may form a sidewall of the second pixel separation pattern (140). For example, the barrier layer (141) may include a high dielectric constant insulating material. However, the technical concept of the present invention is not limited thereto.

[0044] The filling layer (142) may be disposed between the barrier layers (141). For example, the barrier layer (141) may extend in a vertical direction (DR3) from the first surface (130a) of the second substrate (130) to the second surface (130b) of the second substrate (130). The filling layer (142) may include a material with excellent gap-fill performance, for example, polysilicon (poly-Si). However, the technical concept of the present invention is not limited thereto.

[0045] The floating diffusion region (FD) may be disposed inside the second substrate (130). For example, the floating diffusion region (FD) may be disposed across each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). For example, the floating diffusion region (FD) may be disposed at the edge of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). For example, the floating diffusion region (FD) may overlap with each of the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) in a vertical direction (DR3).

[0046] For example, as illustrated in FIG. 9, the upper surface of the floating diffusion region (FD) may be formed on the same plane as the first surface (130a) of the second substrate (130). For example, the floating diffusion region (FD) may be formed by doping n-type impurities within the p-type second substrate (130). For example, as illustrated in FIG. 8, the floating diffusion region (FD) may not overlap with the first and second pixel separation patterns (135, 140) in the vertical direction (DR3). That is, the first and second pixel separation patterns (135, 140) may not be placed in the portion where the floating diffusion region (FD) is placed. However, the technical concept of the present invention is not limited thereto.

[0047] For example, the first to eighth vertical gate structures (VG1 to VG8) may be placed in the first region (I) of the second substrate (130). The ninth vertical gate structure (VG9) may be placed in the second region (II) of the second substrate (130). The first to ninth vertical gate structures (VG1 to VG9) may be, for example, the gate of a charge transfer element, the gate of a reset element, the gate of a drive element, etc.

[0048] The first vertical gate structure (VG1) may be disposed in the first pixel area (PX1). The first vertical gate structure (VG1) may extend from the first surface (130a) of the second substrate (130) into the interior of the second substrate (130). The first vertical gate structure (VG1) may include a first portion (VG1_1) disposed inside the second substrate (130) and a second portion (VG1_2) disposed on the first surface (130a) of the second substrate (130).

[0049] The width of the first horizontal direction (DR1) of the first part (VG1_1) of the first vertical gate structure (VG1) may decrease overall as it approaches the floating diffusion region (FD). For example, the width of the first horizontal direction (DR1) of the first part (VG1_1) of the first vertical gate structure (VG1) may decrease from the second width (W2) to the first width (W1) as it approaches the floating diffusion region (FD).

[0050] For example, the planar shape of the first part (VG1_1) of the first vertical gate structure (VG1) may have a triangular shape. Here, the planar shape may be defined as a plane defined by the first horizontal direction (DR1) and the second horizontal direction (DR2). For example, one sidewall of the first part (VG1_1) of the first vertical gate structure (VG1) may be placed along the sidewall of the first pixel separation pattern (135) placed between the first pixel area (PX1) and the second pixel area (PX2), but the technical concept of the present invention is not limited thereto. For example, the first angle (θ1) between two sidewalls of the first part (VG1_1) of the first vertical gate structure (VG1) adjacent to the floating diffusion area (FD) may be greater than or equal to 30 degrees and less than 45 degrees.

[0051] A second part (VG1_2) of a first vertical gate structure (VG1) may be placed on a first part (VG1_1) of a first vertical gate structure (VG1). For example, the planar shape of the second part (VG1_2) of the first vertical gate structure (VG1) may have a triangular shape. For example, the width of the first horizontal direction (DR1) of the second part (VG1_2) of the first vertical gate structure (VG1) may be greater than the width of the first horizontal direction (DR1) of the first part (VG1_1) of the first vertical gate structure (VG1).

[0052] The second vertical gate structure (VG2) may be placed in the first pixel area (PX1). The second vertical gate structure (VG2) may be placed directly adjacent to the first vertical gate structure (VG1) in the first pixel area (PX1). Here, being placed directly adjacent may be defined as not having any other vertical gate structure placed between the first vertical gate structure (VG1) and the second vertical gate structure (VG2).

[0053] The second vertical gate structure (VG2) may extend from the first surface (130a) of the second substrate (130) into the interior of the second substrate (130). The second vertical gate structure (VG2) may include a first portion (VG2_1) disposed inside the second substrate (130) and a second portion (VG2_2) disposed on the first surface (130a) of the second substrate (130).

[0054] The width of the second horizontal direction (DR2) of the first part (VG2_1) of the second vertical gate structure (VG2) may decrease overall as it approaches the floating diffusion region (FD). For example, the planar shape of the first part (VG2_1) of the second vertical gate structure (VG2) may have a triangular shape. For example, one sidewall of the first part (VG2_1) of the second vertical gate structure (VG2) may be positioned along the sidewall of the first pixel separation pattern (135) positioned between the first pixel region (PX1) and the third pixel region (PX3), but the technical concept of the present invention is not limited thereto. For example, the second angle (θ2) between two sidewalls of the first part (VG2_1) of the second vertical gate structure (VG2) adjacent to the floating diffusion region (FD) may be greater than or equal to 30 degrees and less than 45 degrees.

[0055] The second part (VG2_2) of the second vertical gate structure (VG2) may be placed on the first part (VG2_1) of the second vertical gate structure (VG2). For example, the planar shape of the second part (VG2_2) of the second vertical gate structure (VG2) may have a triangular shape. For example, the width of the second horizontal direction (DR2) of the second part (VG2_2) of the second vertical gate structure (VG2) may be greater than the width of the second horizontal direction (DR2) of the first part (VG2_1) of the second vertical gate structure (VG2).

[0056] A first part (VG1_1) of a first vertical gate structure (VG1) may include a first sidewall (VG1_1s) facing a first part (VG2_1) of a second vertical gate structure (VG2). A first part (VG2_1) of a second vertical gate structure (VG2) may include a second sidewall (VG2_1s) facing a first part (VG1_1) of a first vertical gate structure (VG1). The gap between the first part (VG1_1) of the first vertical gate structure (VG1) and the first part (VG2_1) of the second vertical gate structure (VG2) may decrease as it approaches the floating diffusion region (FD). For example, the gap between the first sidewall (VG1_1s) and the second sidewall (VG2_1s) can decrease from the second gap (P2) to the first gap (P1) as it approaches the floating diffusion region (FD).

[0057] Each of the third and fourth vertical gate structures (VG3, VG4) may be placed in the second pixel area (PX2). Each of the third and fourth vertical gate structures (VG3, VG4) may have a structure similar to each of the first and second vertical gate structures (VG1, VG2). Each of the third and fourth vertical gate structures (VG3, VG4) may be placed symmetrically with respect to the first and second vertical gate structures (VG1, VG2) with respect to the first and second pixel separation patterns (135, 140) placed between the first pixel area (PX1) and the second pixel area (PX2).

[0058] The third vertical gate structure (VG3) may include a first portion (VG3_1) disposed inside the second substrate (130) and a second portion (VG3_2) disposed on the first surface (130a) of the second substrate (130). The fourth vertical gate structure (VG4) may include a first portion (VG4_1) disposed inside the second substrate (130) and a second portion (VG4_2) disposed on the first surface (130a) of the second substrate (130).

[0059] A first part (VG3_1) of the third vertical gate structure (VG3) may include a third sidewall (VG3_1s) facing the first part (VG4_1) of the fourth vertical gate structure (VG4). A first part (VG4_1) of the fourth vertical gate structure (VG4) may include a fourth sidewall (VG4_1s) facing the first part (VG3_1) of the third vertical gate structure (VG3). The gap between the third sidewall (VG3_1s) and the fourth sidewall (VG4_1s) may decrease as it approaches the floating diffusion region (FD).

[0060] Each of the fifth and sixth vertical gate structures (VG5, VG6) may be placed in the third pixel area (PX3). Each of the fifth and sixth vertical gate structures (VG5, VG6) may have a structure similar to each of the first and second vertical gate structures (VG1, VG2). Each of the fifth and sixth vertical gate structures (VG5, VG6) may be placed symmetrically with respect to the first and second vertical gate structures (VG1, VG2) around the first and second pixel separation patterns (135, 140) placed between the first pixel area (PX1) and the third pixel area (PX3).

[0061] The fifth vertical gate structure (VG5) may include a first portion (VG5_1) disposed inside the second substrate (130) and a second portion (VG5_2) disposed on the first surface (130a) of the second substrate (130). The sixth vertical gate structure (VG6) may include a first portion (VG6_1) disposed inside the second substrate (130) and a second portion (VG6_2) disposed on the first surface (130a) of the second substrate (130).

[0062] A first part (VG5_1) of the fifth vertical gate structure (VG5) may include a fifth sidewall (VG5_1s) facing the first part (VG6_1) of the sixth vertical gate structure (VG6). A first part (VG6_1) of the sixth vertical gate structure (VG6) may include a sixth sidewall (VG6_1s) facing the first part (VG5_1) of the fifth vertical gate structure (VG5). The gap between the fifth sidewall (VG5_1s) and the sixth sidewall (VG6_1s) may decrease as it approaches the floating diffusion region (FD).

[0063] Each of the 7th and 8th vertical gate structures (VG7, VG8) may be placed in the 4th pixel area (PX4). Each of the 7th and 8th vertical gate structures (VG7, VG8) may have a structure similar to each of the 1st and 2nd vertical gate structures (VG1, VG2). Each of the 7th and 8th vertical gate structures (VG7, VG8) may be placed symmetrically with respect to the 5th and 6th vertical gate structures (VG5, VG6) with respect to the 1st and 2nd pixel separation patterns (135, 140) placed between the 3rd pixel area (PX3) and the 4th pixel area (PX4).

[0064] The seventh vertical gate structure (VG7) may include a first portion (VG7_1) disposed inside the second substrate (130) and a second portion (VG7_2) disposed on the first surface (130a) of the second substrate (130). The eighth vertical gate structure (VG8) may include a first portion (VG8_1) disposed inside the second substrate (130) and a second portion (VG8_2) disposed on the first surface (130a) of the second substrate (130).

[0065] A first part (VG7_1) of the seventh vertical gate structure (VG7) may include a seventh sidewall (VG7_1s) facing the first part (VG8_1) of the eighth vertical gate structure (VG8). A first part (VG8_1) of the eighth vertical gate structure (VG8) may include an eighth sidewall (VG8_1s) facing the first part (VG7_1) of the seventh vertical gate structure (VG7). The gap between the seventh sidewall (VG7_1s) and the eighth sidewall (VG8_1s) may decrease as it approaches the floating diffusion region (FD).

[0066] Each of the first to ninth vertical gate structures (VG1 to VG9) may include a gate insulating film (192) and a gate electrode (191). The gate insulating film (192) may be disposed in the portion of each of the first to ninth vertical gate structures (VG1 to VG9) that contacts the second substrate (130). The gate insulating film (192) may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0067] The gate electrode (191) can be placed on the gate insulating film (192) on the inside of the second substrate (130) and on the first surface (130a) of the second substrate (130). The gate electrode (191) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0068] A gate spacer (193) may be disposed along the sidewalls of the gate electrode (191) and the gate insulating film (192), respectively, on the first surface (130a) of the second substrate (130). The gate spacer (193) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbonitride (SiOC), and combinations thereof. Although not shown in FIGS. 8 and 9, a capping pattern comprising an insulating material may be disposed on the gate electrode (191).

[0069] The passivation layer (150) may be disposed on the second surface (130b) of the second substrate (130). The passivation layer (150) may include, for example, a high dielectric constant insulating material. Additionally, the passivation layer (150) may include an amorphous crystal structure. More specifically, at least a portion of the high dielectric constant insulating material included in the passivation layer (150) may have an amorphous crystal structure. However, the technical concept of the present invention is not limited thereto.

[0070] Although FIGS. 3 to 5 illustrate the passivation layer (150) being formed as a single layer, the technical concept of the present invention is not limited thereto. In some other embodiments, the passivation layer (150) may further include a planarization layer and an anti-reflection layer. In this case, the planarization layer may include, for example, at least one of a silicon oxide film-based material, a silicon nitride film-based material, a resin, or a combination thereof. The anti-reflection layer may include a high dielectric constant material, for example, hafnium oxide (HfO2), but the technical concept of the present invention is not limited thereto.

[0071] The first color filter (151) can be placed on the first region (I) of the second substrate (130), which is the active pixel sensor region. The first color filter (151) is not placed on the second region (II) of the second substrate (130), which is the optical black sensor region.

[0072] The first color filter (151) may be placed on the passivation layer (150). The first color filter (151) may be arranged to correspond to each unit pixel. For example, the first color filter (151) may be arranged two-dimensionally (e.g., in the form of a matrix) in a plane defined by the first horizontal direction (DR1) and the second horizontal direction (DR2).

[0073] The first color filter (151) may include a red, green, or blue color filter depending on the unit pixel. Additionally, the first color filter (151) may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0074] A grid pattern (155) can be formed in a grid shape on the second surface (130b) of the second substrate (130) and arranged to surround each unit pixel. For example, the grid pattern (155) can be placed between the first color filters (151) on the passivation layer (150). The grid pattern (155) can reflect incident light incident obliquely on the second substrate (130) to provide more incident light to each of the first to fourth photoelectric conversion elements (PD1 to PD4).

[0075] The micro lens (157) can be placed on the first region (I) of the second substrate (130), which is the active pixel sensor region. The micro lens (157) is not placed on the second region (II) of the second substrate (130), which is the optical black sensor region.

[0076] Micro lenses (157) may be placed on a first color filter (151). Micro lenses (157) may be arranged to correspond to each unit pixel. For example, one micro lens (157) may be placed on one first color filter (151). However, the technical concept of the present invention is not limited thereto. Micro lenses (157) may be arranged two-dimensionally (e.g., in a matrix form) in a plane defined by a first horizontal direction (DR1) and a second horizontal direction (DR2).

[0077] The micro-lens (157) has a convex shape and may have a predetermined radius of curvature. Accordingly, the micro-lens (157) can concentrate incident light to each of the first to fourth photoelectric conversion elements (PD1 to PD4). The micro-lens (157) may include, for example, an organic material such as a photosensitive resin or an inorganic material, but the technical concept of the present invention is not limited thereto.

[0078] The first conductive pattern (161) can be placed on the second region (II) of the second substrate (130), which is an optical black sensor region. The first conductive pattern (161) can be placed on the passivation layer (150).

[0079] The first conductive pattern (161) may include a metal. For example, the first conductive pattern (161) may include at least one of titanium (Ti) and tungsten (W), but the technical concept of the present invention is not limited thereto.

[0080] A connection trench (CT) may be formed in a second region (II) of a second substrate (130), which is an optical black sensor region. The connection trench (CT) may penetrate the passivation layer (150), the second substrate (130), the second insulating layer (102), and the second wiring structure (120) in a vertical direction (DR3). The connection trench (CT) may extend into the interior of the first wiring structure (110). The connection trench (CT) may expose at least a portion of the first wiring layer (111). The connection trench (CT) may expose at least a portion of the second wiring layer (121). The lower surface of the connection trench (CT) may have a step.

[0081] The second conductive pattern (162) may be arranged along the sidewalls and bottom surfaces of the connecting trench (CT). The second conductive pattern (162) may be formed conformally, for example. At least a portion of the second conductive pattern (162) may extend onto the upper surface of the passivation layer (150). The second conductive pattern (162) may include a metal. For example, the second conductive pattern (162) may include at least one of titanium (Ti) and tungsten (W), but the technical concept of the present invention is not limited thereto.

[0082] A pad trench (PT) may be formed in the fourth region (IV) of the second substrate (130), which is the pad region. The pad trench (PT) may extend into the interior of the second substrate (130) by penetrating the passivation layer (150) in the vertical direction (DR3). A third conductive pattern (163) may be arranged along the sidewall and bottom surface of the pad trench (PT). The third conductive pattern (163) may be formed conformally, for example. At least a portion of the third conductive pattern (163) may extend onto the upper surface of the passivation layer (150). The third conductive pattern (163) may include a metal. For example, the third conductive pattern (163) may include at least one of titanium (Ti) and tungsten (W), but the technical concept of the present invention is not limited thereto.

[0083] The pad (180) can fill the interior of the pad trench (PT) on the third conductive pattern (163). The pad (180) may include a conductive material.

[0084] An adhesive layer (171) may be disposed on the passivation layer (150). The adhesive layer (171) may be disposed to cover a first conductive pattern (161) and a second conductive pattern (162) on the passivation layer (150). Additionally, the adhesive layer (171) may be disposed to cover a third conductive pattern (163) extended on the passivation layer (150).

[0085] The adhesive layer (171) may be disposed on the second conductive pattern (162) inside the connection trench (CT). The adhesive layer (171) may be formed conformally inside the connection trench (CT). However, the technical concept of the present invention is not limited thereto. The adhesive layer (171) may include, for example, aluminum oxide (Al2O3), but the technical concept of the present invention is not limited thereto.

[0086] A low refractive index layer (172) may be placed on the adhesive layer (171) inside the connection trench (CT). The low refractive index layer (172) may fill the interior of the connection trench (CT). The low refractive index layer (172) may include, for example, at least one of oxides, nitrides, and oxynitrides. However, the technical concept of the present invention is not limited thereto.

[0087] The photoresist (173) may be disposed on the low refractive index layer (172). A portion of the photoresist (173) may be disposed to protrude from the upper surface of the adhesive layer (171). However, the technical concept of the present invention is not limited thereto. In some other embodiments, the photoresist (173) may be omitted.

[0088] The second color filter (152) may be placed on the second region (II) of the second substrate (130), which is the optical black sensor region, and the third region (III) of the second substrate (130), which is the connection region. The second color filter (152) may be placed on the adhesive layer (171). The second color filter (152) is not placed on the fourth region (IV) of the second substrate (130), which is the pad region.

[0089] The second color filter (152) may, for example, be in contact with the upper surface of the adhesive layer (171). For example, the upper surface of the second color filter (152) may be formed higher than the upper surface of the first color filter (151). However, the technical concept of the present invention is not limited thereto. The second color filter (152) may, for example, include a blue color filter.

[0090] The transparent layer (159) may be placed on the adhesive layer (171) and the second color filter (152). The transparent layer (159) may be placed, for example, to completely cover the second color filter (152). However, the technical concept of the present invention is not limited thereto. The transparent layer (159) is not placed on the pad (180). The transparent layer (159) may include, for example, a light-transmitting material.

[0091] A protective film (158) may be disposed on a microlens (157) and a transparent layer (159). The protective film (158) may be disposed conformally, for example. For example, the protective film (158) may include an inorganic oxide film. The protective film (158) may include, for example, at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof, but the technical concept of the present invention is not limited thereto.

[0092] An image sensor according to some embodiments of the present invention can improve the transmission characteristics of a vertical gate structure by arranging the vertical gate structure such that two vertical gate structures are placed in one unit pixel and the spacing between the two vertical gate structures decreases as they get closer to a floating diffusion region (FD) in one unit pixel.

[0093] Hereinafter, an image sensor according to several other embodiments of the present invention will be described with reference to FIG. 10. The description will focus on the differences from the image sensors illustrated in FIG. 1 to 9.

[0094] FIG. 10 is a plan view illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention.

[0095] Referring to FIG. 10, in some other embodiments of the present invention, an image sensor may have a first vertical gate structure (VG21) and a second vertical gate structure (VG22) directly connected, a third vertical gate structure (VG23) and a fourth vertical gate structure (VG24) directly connected, a fifth vertical gate structure (VG25) and a sixth vertical gate structure (VG26) directly connected, and a seventh vertical gate structure (VG27) and an eighth vertical gate structure (VG28) directly connected.

[0096] Specifically, in the first pixel area (PX1), the second part (VG21_2) of each of the first and second vertical gate structures (VG21, VG22) can be formed integrally. In the second pixel area (PX2), the second part (VG23_2) of each of the third and fourth vertical gate structures (VG23, VG24) can be formed integrally. In the third pixel area (PX3), the second part (VG25_2) of each of the fifth and sixth vertical gate structures (VG25, VG26) can be formed integrally. In the fourth pixel area (PX4), the second part (VG27_2) of each of the seventh and eighth vertical gate structures (VG27, VG28) can be formed integrally.

[0097] For example, the second part (VG23_2) of each of the third and fourth vertical gate structures (VG23, VG24) may be symmetrically positioned around the second part (VG21_2) of each of the first and second vertical gate structures (VG21, VG22) and the second pixel separation pattern (140). The second part (VG25_2) of each of the fifth and sixth vertical gate structures (VG25, VG26) may be symmetrically positioned around the second part (VG21_2) of each of the first and second vertical gate structures (VG21, VG22) and the second pixel separation pattern (140). The second part (VG27_2) of each of the 7th and 8th vertical gate structures (VG27, VG28) can be arranged symmetrically with respect to the second part (VG25_2) of each of the 5th and 6th vertical gate structures (VG25, VG26) and the second pixel separation pattern (140).

[0098] Hereinafter, an image sensor according to several other embodiments of the present invention will be described with reference to FIGS. 11 to 13. The description will focus on the differences from the image sensor illustrated in FIGS. 1 to 9.

[0099] FIGS. 11 and 12 are plan views illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention. FIG. 13 is a cross-sectional view taken along the GG' line of FIGS. 11 and FIGS. 12, respectively.

[0100] Referring to FIGS. 11 to 13, an image sensor according to another embodiment of the present invention may have separate floating diffusion regions (FD31 to FD34) disposed in each of the first to fourth pixel regions (PX1 to PX4).

[0101] Specifically, a first floating diffusion region (F31) may be disposed between the first vertical gate structure (VG1) and the second vertical gate structure (VG2) at the edge of the first pixel area (PX1). A second floating diffusion region (F32) may be disposed between the third vertical gate structure (VG3) and the fourth vertical gate structure (VG4) at the edge of the second pixel area (PX2). A third floating diffusion region (F33) may be disposed between the fifth vertical gate structure (VG5) and the sixth vertical gate structure (VG6) at the edge of the third pixel area (PX3). A fourth floating diffusion region (F34) may be disposed between the seventh vertical gate structure (VG7) and the eighth vertical gate structure (VG8) at the edge of the fourth pixel area (PX4).

[0102] Each of the first to fourth floating diffusion regions (FD31 to FD34) may be spaced apart from each other in a first horizontal direction (DR1) or a second horizontal direction (DR2). Each of the first to fourth floating diffusion regions (FD31 to FD34) may be arranged symmetrically with respect to the second pixel separation pattern (340). Each of the first to fourth pixel regions (PX1 to PX4) may be completely separated by the first and second pixel separation patterns (335, 340). The second pixel separation pattern (340) may include a barrier layer (341) forming the sidewall of the second pixel separation pattern (340) and a filling layer (342) disposed between the barrier layer (341).

[0103] Hereinafter, an image sensor according to several other embodiments of the present invention is described with reference to FIG. 14. The description focuses on the differences from the image sensor shown in FIG. 10.

[0104] FIG. 14 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention.

[0105] Referring to FIG. 14, in an image sensor according to another embodiment of the present invention, separate floating diffusion regions (FD41 to FD44) may be disposed in each of the first to fourth pixel regions (PX1 to PX4).

[0106] Specifically, a first floating diffusion region (F41) may be disposed between the first vertical gate structure (VG21) and the second vertical gate structure (VG22) at the edge of the first pixel area (PX1). A second floating diffusion region (F42) may be disposed between the third vertical gate structure (VG23) and the fourth vertical gate structure (VG24) at the edge of the second pixel area (PX2). A third floating diffusion region (F43) may be disposed between the fifth vertical gate structure (VG25) and the sixth vertical gate structure (VG26) at the edge of the third pixel area (PX3). A fourth floating diffusion region (F44) may be disposed between the seventh vertical gate structure (VG27) and the eighth vertical gate structure (VG28) at the edge of the fourth pixel area (PX4).

[0107] Each of the first to fourth floating diffusion regions (FD41 to FD44) may be spaced apart from each other in the first horizontal direction (DR1) or the second horizontal direction (DR2). Each of the first to fourth floating diffusion regions (FD41 to FD44) may be arranged symmetrically with respect to the second pixel separation pattern (440). Each of the first to fourth pixel regions (PX1 to PX4) may be completely separated by the first and second pixel separation patterns (435, 440).

[0108] Hereinafter, an image sensor according to several other embodiments of the present invention will be described with reference to FIGS. 15 and 16. The description will focus on the differences from the image sensor illustrated in FIGS. 1 to 9.

[0109] FIGS. 15 and 16 are plan views illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention.

[0110] Referring to FIG. 15 and FIG. 16, in some other embodiments of the present invention, the planar shape of each of the first to eighth vertical gate structures (VG51 to VG58) may have a trapezoidal shape.

[0111] Specifically, the planar shape of the first part (VG51_1) of the first vertical gate structure (VG51) may have a trapezoidal shape. For example, one sidewall of the first part (VG51_1) of the first vertical gate structure (VG51) may be positioned along the sidewall of the first pixel separation pattern (135) positioned between the first pixel area (PX1) and the second pixel area (PX2). The second part (VG51_2) of the first vertical gate structure (VG51) may be positioned on the first part (VG51_1) of the first vertical gate structure (VG51).

[0112] The width of the first horizontal direction (DR1) of the first part (VG51_1) of the first vertical gate structure (VG51) may decrease overall as it approaches the floating diffusion region (FD). For example, the width of the first horizontal direction (DR1) of the first part (VG51_1) of the first vertical gate structure (VG51) may decrease from the second width (W52) to the first width (W51) as it approaches the floating diffusion region (FD).

[0113] The planar shape of the first part (VG52_1) of the second vertical gate structure (VG52) may have a trapezoidal shape. For example, one sidewall of the first part (VG52_1) of the second vertical gate structure (VG52) may be positioned along the sidewall of the first pixel separation pattern (135) positioned between the first pixel area (PX1) and the third pixel area (PX3). The second part (VG52_2) of the second vertical gate structure (VG52) may be positioned on the first part (VG52_1) of the second vertical gate structure (VG52). The width of the second horizontal direction (DR2) of the first part (VG52_1) of the second vertical gate structure (VG52) may decrease overall as it is adjacent to the floating diffusion area (FD). For example, the planar shape of the second part (VG52_2) of the second vertical gate structure (VG52) may have a trapezoidal shape.

[0114] A first part (VG51_1) of the first vertical gate structure (VG51) may include a first sidewall (VG51_1s) facing the first part (VG52_1) of the second vertical gate structure (VG52). A first part (VG52_1) of the second vertical gate structure (VG52) may include a second sidewall (VG52_1s) facing the first part (VG51_1) of the first vertical gate structure (VG51). The gap between the first part (VG51_1) of the first vertical gate structure (VG51) and the first part (VG52_1) of the second vertical gate structure (VG52) may decrease as it approaches the floating diffusion region (FD). For example, the gap between the first sidewall (VG51_1s) and the second sidewall (VG52_1s) can be reduced from the second gap (P52) to the first gap (P51) as it approaches the floating diffusion region (FD).

[0115] Each of the third and fourth vertical gate structures (VG53, VG54) may be placed in the second pixel area (PX2). Each of the third and fourth vertical gate structures (VG53, VG54) may have a structure similar to each of the first and second vertical gate structures (VG51, VG52). Each of the third and fourth vertical gate structures (VG53, VG54) may be placed symmetrically with respect to the first and second vertical gate structures (VG51, VG52) with respect to the first and second pixel separation patterns (135, 140) placed between the first pixel area (PX1) and the second pixel area (PX2).

[0116] The third vertical gate structure (VG53) may include a first portion (VG53_1) disposed inside the second substrate (130) and a second portion (VG53_2) disposed on the first surface (130a) of the second substrate (130). The fourth vertical gate structure (VG54) may include a first portion (VG54_1) disposed inside the second substrate (130) and a second portion (VG54_2) disposed on the first surface (130a) of the second substrate (130).

[0117] A first part (VG53_1) of the third vertical gate structure (VG53) may include a third sidewall (VG53_1s) facing a first part (VG54_1) of the fourth vertical gate structure (VG54). A first part (VG54_1) of the fourth vertical gate structure (VG54) may include a fourth sidewall (VG54_1s) facing a first part (VG53_1) of the third vertical gate structure (VG53). The gap between the third sidewall (VG53_1s) and the fourth sidewall (VG54_1s) may decrease as it approaches the floating diffusion region (FD).

[0118] Each of the fifth and sixth vertical gate structures (VG55, VG56) may be placed in the third pixel area (PX3). Each of the fifth and sixth vertical gate structures (VG55, VG56) may have a structure similar to each of the first and second vertical gate structures (VG51, VG52). Each of the fifth and sixth vertical gate structures (VG55, VG56) may be placed symmetrically with respect to the first and second vertical gate structures (VG51, VG52) with respect to the first and second pixel separation patterns (135, 140) placed between the first pixel area (PX1) and the third pixel area (PX3).

[0119] The fifth vertical gate structure (VG55) may include a first portion (VG55_1) disposed inside the second substrate (130) and a second portion (VG55_2) disposed on the first surface (130a) of the second substrate (130). The sixth vertical gate structure (VG56) may include a first portion (VG56_1) disposed inside the second substrate (130) and a second portion (VG56_2) disposed on the first surface (130a) of the second substrate (130).

[0120] A first part (VG55_1) of the fifth vertical gate structure (VG55) may include a fifth sidewall (VG55_1s) facing a first part (VG56_1) of the sixth vertical gate structure (VG56). A first part (VG56_1) of the sixth vertical gate structure (VG56) may include a sixth sidewall (VG56_1s) facing a first part (VG55_1) of the fifth vertical gate structure (VG55). The gap between the fifth sidewall (VG55_1s) and the sixth sidewall (VG56_1s) may decrease as it approaches the floating diffusion region (FD).

[0121] Each of the 7th and 8th vertical gate structures (VG57, VG58) may be placed in the 4th pixel area (PX4). Each of the 7th and 8th vertical gate structures (VG57, VG58) may have a structure similar to each of the 1st and 2nd vertical gate structures (VG51, VG52). Each of the 7th and 8th vertical gate structures (VG57, VG58) may be placed symmetrically with respect to the 5th and 6th vertical gate structures (VG55, VG56) with respect to the 1st and 2nd pixel separation patterns (135, 140) placed between the 3rd pixel area (PX3) and the 4th pixel area (PX4).

[0122] The seventh vertical gate structure (VG57) may include a first portion (VG57_1) disposed inside the second substrate (130) and a second portion (VG57_2) disposed on the first surface (130a) of the second substrate (130). The eighth vertical gate structure (VG58) may include a first portion (VG58_1) disposed inside the second substrate (130) and a second portion (VG58_2) disposed on the first surface (130a) of the second substrate (130).

[0123] A first part (VG57_1) of the seventh vertical gate structure (VG57) may include a seventh sidewall (VG57_1s) facing a first part (VG58_1) of the eighth vertical gate structure (VG58). A first part (VG58_1) of the eighth vertical gate structure (VG58) may include an eighth sidewall (VG58_1s) facing a first part (VG57_1) of the seventh vertical gate structure (VG57). The gap between the seventh sidewall (VG57_1s) and the eighth sidewall (VG58_1s) may decrease as it approaches the floating diffusion region (FD).

[0124] Hereinafter, an image sensor according to several other embodiments of the present invention is described with reference to FIG. 17. The description focuses on the differences from the image sensor shown in FIG. 15 and FIG. 16.

[0125] FIG. 17 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention.

[0126] Referring to FIG. 17, in some other embodiments of the present invention, an image sensor may have a first vertical gate structure (VG61) and a second vertical gate structure (VG62) directly connected, a third vertical gate structure (VG63) and a fourth vertical gate structure (VG64) directly connected, a fifth vertical gate structure (VG65) and a sixth vertical gate structure (VG66) directly connected, and a seventh vertical gate structure (VG67) and an eighth vertical gate structure (VG68) directly connected.

[0127] Specifically, in the first pixel area (PX1), the second part (VG61_2) of each of the first and second vertical gate structures (VG61, VG62) can be formed integrally. In the second pixel area (PX2), the second part (VG63_2) of each of the third and fourth vertical gate structures (VG63, VG64) can be formed integrally. In the third pixel area (PX3), the second part (VG65_2) of each of the fifth and sixth vertical gate structures (VG65, VG66) can be formed integrally. In the fourth pixel area (PX4), the second part (VG67_2) of each of the seventh and eighth vertical gate structures (VG67, VG68) can be formed integrally.

[0128] For example, the second part (VG63_2) of each of the third and fourth vertical gate structures (VG63, VG64) may be symmetrically positioned around the second part (VG61_2) of each of the first and second vertical gate structures (VG61, VG62) and the second pixel separation pattern (140). The second part (VG65_2) of each of the fifth and sixth vertical gate structures (VG65, VG66) may be symmetrically positioned around the second part (VG61_2) of each of the first and second vertical gate structures (VG61, VG62) and the second pixel separation pattern (140). The second part (VG67_2) of each of the 7th and 8th vertical gate structures (VG67, VG68) can be arranged symmetrically with respect to the second part (VG65_2) of each of the 5th and 6th vertical gate structures (VG65, VG66) and the second pixel separation pattern (140).

[0129] Hereinafter, an image sensor according to several other embodiments of the present invention is described with reference to FIGS. 18 and 19. The description focuses on the differences from the image sensor shown in FIGS. 15 and 16.

[0130] FIGS. 18 and 19 are plan views illustrating a vertical gate structure of an image sensor according to some other embodiments of the present invention.

[0131] Referring to FIGS. 18 and 19, an image sensor according to another embodiment of the present invention may have separate floating diffusion regions (FD71 to FD74) disposed in each of the first to fourth pixel regions (PX1 to PX4).

[0132] Specifically, a first floating diffusion region (F71) may be positioned between the first vertical gate structure (VG51) and the second vertical gate structure (VG52) at the edge of the first pixel area (PX1). A second floating diffusion region (F72) may be positioned between the third vertical gate structure (VG53) and the fourth vertical gate structure (VG54) at the edge of the second pixel area (PX2). A third floating diffusion region (F73) may be positioned between the fifth vertical gate structure (VG55) and the sixth vertical gate structure (VG56) at the edge of the third pixel area (PX3). A fourth floating diffusion region (F74) may be positioned between the seventh vertical gate structure (VG57) and the eighth vertical gate structure (VG58) at the edge of the fourth pixel area (PX4).

[0133] Each of the first to fourth floating diffusion regions (FD71 to FD74) may be spaced apart from each other in the first horizontal direction (DR1) or the second horizontal direction (DR2). Each of the first to fourth floating diffusion regions (FD71 to FD74) may be arranged symmetrically with respect to the second pixel separation pattern (740). Each of the first to fourth pixel regions (PX1 to PX4) may be completely separated by the first and second pixel separation patterns (735, 740).

[0134] Hereinafter, an image sensor according to several other embodiments of the present invention is described with reference to FIG. 20. The description focuses on the differences from the image sensor shown in FIG. 17.

[0135] FIG. 20 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention.

[0136] Referring to FIG. 20, an image sensor according to another embodiment of the present invention may have separate floating diffusion regions (FD81 to FD84) disposed in each of the first to fourth pixel regions (PX1 to PX4).

[0137] Specifically, a first floating diffusion region (F81) may be positioned between the first vertical gate structure (VG61) and the second vertical gate structure (VG62) at the edge of the first pixel area (PX1). A second floating diffusion region (F82) may be positioned between the third vertical gate structure (VG63) and the fourth vertical gate structure (VG64) at the edge of the second pixel area (PX2). A third floating diffusion region (F83) may be positioned between the fifth vertical gate structure (VG65) and the sixth vertical gate structure (VG66) at the edge of the third pixel area (PX3). A fourth floating diffusion region (F84) may be positioned between the seventh vertical gate structure (VG67) and the eighth vertical gate structure (VG68) at the edge of the fourth pixel area (PX4).

[0138] Each of the first to fourth floating diffusion regions (FD81 to FD84) may be spaced apart from each other in the first horizontal direction (DR1) or the second horizontal direction (DR2). Each of the first to fourth floating diffusion regions (FD81 to FD84) may be arranged symmetrically with respect to the second pixel separation pattern (840). Each of the first to fourth pixel regions (PX1 to PX4) may be completely separated by the first and second pixel separation patterns (835, 840).

[0139] Hereinafter, an image sensor according to another embodiment of the present invention will be described with reference to FIGS. 21 and 22. The description will focus on the differences from the image sensor illustrated in FIGS. 1 to 9.

[0140] FIG. 21 is a plan view illustrating a vertical gate structure of an image sensor according to another embodiment of the present invention. FIG. 22 is a cross-sectional view taken along the line HH' of FIG. 21.

[0141] Referring to FIG. 21 and FIG. 22, in some other embodiments of the present invention, an image sensor may have a second pixel separation pattern (940) that overlaps a floating diffusion region (FD) in a vertical direction (DR3). For example, as shown in FIG. 22, the second pixel separation pattern (940) may be positioned below the floating diffusion region (FD).

[0142] Each of the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) can be completely separated by the second pixel separation pattern (940). Additionally, the first to fourth pixel regions (PX1, PX2, PX3, PX4) can be completely separated by the second pixel separation pattern (940). Although FIG. 22 illustrates the second pixel separation pattern (940), which is positioned below the floating diffusion region (FD), being spaced apart from the floating diffusion region (FD) in a vertical direction (DR3), the technical concept of the present invention is not limited thereto. In some other embodiments, the second pixel separation pattern (940), which is positioned below the floating diffusion region (FD), may be in contact with the floating diffusion region (FD).

[0143] The second pixel separation pattern (940) may include a barrier layer (941) forming the sidewall of the second pixel separation pattern (940) and a filling layer (942) disposed between the barrier layer (941). For example, as shown in FIG. 22, the filling layer (942) facing the floating diffusion region (FD) may be in contact with the second substrate (130), but the technical concept of the present invention is not limited thereto. In some other embodiments, the barrier layer (941) may be disposed between the filling layer (942) facing the floating diffusion region (FD) and the floating diffusion region (FD). That is, the barrier layer (941) may completely surround the filling layer (942) inside the second substrate (130).

[0144] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0145] 100: First substrate 110: First wiring structure 120: Second wiring structure 130: Second substrate 135: 1st pixel separation pattern 140: 2nd pixel separation pattern 150: Passivation layer 151: First color filter 152: Second color filter 157: Micro lens 158: Protective layer 171: Adhesive layer 161 to 163: First to third conductive patterns 172: Low refractive index layer 173: Photoresist 180: Pad 191: Gate electrode 192: Gate insulating film 193: Gate spacer FD: Floating Diffusion Region PD1 to PD5: First to fifth photoelectric conversion elements PX1 to PX4: 1st to 4th pixel areas VG1 to VG9: 1st to 9th vertical gate structures

Claims

Claim 1 A substrate having a first photoelectric conversion element disposed therein and a first surface and a second surface opposite to the first surface defined therein; a pixel separation pattern extending from the first surface of the substrate into the interior of the substrate, surrounding the first photoelectric conversion element, and defining a first pixel region on the substrate; a first vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region, comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region, disposed directly adjacent to the first vertical gate structure, comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; An image sensor comprising a floating diffusion region disposed at the edge of the first pixel region within the substrate, disposed between the first part of the first vertical gate structure and the first part of the second vertical gate structure, wherein the upper surface is formed on the same plane as the first surface of the substrate, wherein the horizontal width of the first part of the first vertical gate structure decreases overall as it approaches the floating diffusion region, wherein the first part of the first vertical gate structure includes a first sidewall facing the first part of the second vertical gate structure, and the first part of the second vertical gate structure includes a second sidewall facing the first part of the first vertical gate structure, wherein the gap between the first sidewall and the second sidewall decreases as it approaches the floating diffusion region, and no other vertical gate structure is disposed between the first vertical gate structure and the second vertical gate structure. Claim 2 In claim 1, the planar shape of each of the first part of the first vertical gate structure and the first part of the second vertical gate structure is a triangular shape, an image sensor. Claim 3 In claim 2, an image sensor in which the angle between the two side walls of the first part of the first vertical gate structure adjacent to the floating diffusion region is greater than or equal to 30 degrees and less than 45 degrees. Claim 4 In claim 1, the planar shape of each of the first part of the first vertical gate structure and the first part of the second vertical gate structure has a trapezoidal shape. Claim 5 In claim 1, at least a portion of which is separated from the first pixel region by the pixel separation pattern, and a second pixel region defined on the substrate by the pixel separation pattern; a third vertical gate structure comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate, extending from the second pixel region into the interior of the substrate from the first surface of the substrate; An image sensor further comprising a fourth vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the second pixel area, disposed directly adjacent to the third vertical gate structure, and including a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate, wherein the first portion of the third vertical gate structure includes a third sidewall facing the first portion of the fourth vertical gate structure, and the first portion of the fourth vertical gate structure includes a fourth sidewall facing the first portion of the third vertical gate structure, and the distance between the third sidewall and the fourth sidewall decreases as it becomes closer to the floating diffusion area. Claim 6 An image sensor according to claim 5, wherein the first vertical gate structure and the third vertical gate structure are symmetrically arranged around the pixel separation pattern, and the second vertical gate structure and the fourth vertical gate structure are symmetrically arranged around the pixel separation pattern. Claim 7 In claim 5, the floating diffusion region is an image sensor positioned across the first pixel region and the second pixel region. Claim 8 In claim 5, the floating diffusion region comprises a first floating diffusion region disposed at the edge of the first pixel region and a second floating diffusion region disposed at the edge of the second pixel region and spaced apart from the first floating diffusion region, an image sensor. Claim 9 In claim 8, the first floating diffusion region and the second floating diffusion region are an image sensor symmetrically arranged around the pixel separation pattern. Claim 10 In claim 1, the second part of the first vertical gate structure and the second part of the second vertical gate structure are integrally formed in an image sensor. Claim 11 An image sensor in which the horizontal width of the second part of the first vertical gate structure is larger than the horizontal width of the first part of the first vertical gate structure. Claim 12 A substrate having first and second photoelectric conversion elements disposed therein and a first surface and a second surface facing the first surface defined therein; a pixel separation pattern extending from the first surface of the substrate into the interior of the substrate, surrounding each of the first and second photoelectric conversion elements, and defining each of a first pixel area where the first photoelectric conversion element is disposed on the substrate and a second pixel area where the second photoelectric conversion element is disposed therein; a first vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel area, comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel area, disposed directly adjacent to the first vertical gate structure, comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; and extending from the first surface of the substrate into the interior of the substrate in the second pixel area, and the A third vertical gate structure comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a fourth vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the second pixel area, disposed directly adjacent to the third vertical gate structure, and comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate;An image sensor comprising a floating diffusion region disposed at the edge of each of the first and second pixel regions within the substrate, disposed between the first portion of the first vertical gate structure and the first portion of the second vertical gate structure and between the first portion of the third vertical gate structure and the first portion of the fourth vertical gate structure, wherein the upper surface is formed on the same plane as the first surface of the substrate, wherein the first portion of the first vertical gate structure includes a first sidewall facing the first portion of the second vertical gate structure, and the first portion of the second vertical gate structure includes a second sidewall facing the first portion of the first vertical gate structure, wherein the distance between the first sidewall and the second sidewall decreases as it approaches the floating diffusion region, and no other vertical gate structure is disposed between the first vertical gate structure and the second vertical gate structure. Claim 13 An image sensor according to claim 12, wherein the first part of the third vertical gate structure includes a third side wall facing the first part of the fourth vertical gate structure, the first part of the fourth vertical gate structure includes a fourth side wall facing the first part of the third vertical gate structure, and the distance between the third side wall and the fourth side wall decreases as it becomes closer to the floating diffusion region. Claim 14 In claim 12, the planar shape of each of the first part of the first vertical gate structure, the first part of the second vertical gate structure, the first part of the third vertical gate structure, and the first part of the fourth vertical gate structure has a triangular shape. Claim 15 In claim 12, the planar shape of each of the first part of the first vertical gate structure and the first part of the second vertical gate structure is a trapezoidal shape, an image sensor. Claim 16 In claim 12, the floating diffusion region is an image sensor positioned across the first pixel region and the second pixel region. Claim 17 In claim 12, the floating diffusion region comprises a first floating diffusion region disposed at the edge of the first pixel region and a second floating diffusion region disposed at the edge of the second pixel region and spaced apart from the first floating diffusion region, an image sensor. Claim 18 An image sensor according to claim 12, wherein the second part of the first vertical gate structure and the second part of the second vertical gate structure are formed integrally, and the second part of the third vertical gate structure and the second part of the fourth vertical gate structure are formed integrally. Claim 19 In claim 18, the second part of the first vertical gate structure formed integrally and the second part of the second vertical gate structure are symmetrically arranged with the second part of the third vertical gate structure formed integrally and the second part of the fourth vertical gate structure with respect to the pixel separation pattern. Claim 20 A substrate having a first photoelectric conversion element disposed therein and a first surface and a second surface opposite to the first surface defined therein; a pixel separation pattern extending from the first surface of the substrate into the interior of the substrate, surrounding the first photoelectric conversion element, and defining a first pixel region on the substrate; a first vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region, comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate; a second vertical gate structure extending from the first surface of the substrate into the interior of the substrate in the first pixel region, disposed directly adjacent to the first vertical gate structure, comprising a first portion disposed inside the substrate and a second portion disposed on the first surface of the substrate;and includes a floating diffusion region disposed at the edge of the first pixel region within the substrate, disposed between the first part of the first vertical gate structure and the first part of the second vertical gate structure, wherein the upper surface is formed coplanar with the first surface of the substrate and does not overlap in a vertical direction with the pixel separation pattern, wherein the planar shape of each of the first part of the first vertical gate structure and the first part of the second vertical gate structure has a triangular shape, the angle between two side walls of the first part of the first vertical gate structure adjacent to the floating diffusion region is greater than or equal to 30 degrees and less than 45 degrees, the angle between two side walls of the first part of the second vertical gate structure adjacent to the floating diffusion region is greater than or equal to 30 degrees and less than 45 degrees, the first part of the first vertical gate structure includes a first side wall facing the first part of the second vertical gate structure, and the first part of the second vertical gate structure is the first An image sensor comprising a second side wall facing a portion, wherein the distance between the first side wall and the second side wall decreases as it approaches the floating diffusion region, and no other vertical gate structure is disposed between the first vertical gate structure and the second vertical gate structure.

Images