Image sensor

Abstract

The present invention provides an image sensor with improved performance and reliability. The image sensor of the present invention comprises a first substrate including first and second surfaces facing each other and an active region disposed on the first surface, a plurality of pixel regions including a photoelectric conversion layer on the first surface of the first substrate, a pixel separation pattern defining the plurality of pixel regions in a direction perpendicular to the first surface of the first substrate, and first to third transistors corresponding to each of the plurality of pixel regions, wherein the first to third transistors share a single source / drain region within the active region.

Description

Technology Field

[0001] The present invention relates to an image sensor. Background Technology

[0002] An image sensing device is one of the semiconductor devices that converts optical information into electrical signals. Such image sensing devices may include Charge Coupled Device (CCD) image sensing devices and Complementary Metal-Oxide Semiconductor (CMOS) image sensing devices.

[0003] A CMOS type image sensor may be abbreviated as CIS (CMOS image sensor). A CIS may have multiple pixels arranged in two dimensions. Each pixel may include, for example, a photodiode (PD). The photodiode can convert incident light into an electrical signal.

[0004] Recently, with the development of the computer and telecommunications industries, the demand for image sensing devices with improved performance and miniaturization has been increasing in various fields, including digital cameras, camcorders, smartphones, gaming devices, security cameras, medical micro cameras, and robots. Accordingly, research is being conducted on highly scaled, high-density semiconductor devices within image sensing devices, and the patterns of these semiconductor devices can have fine widths and be spaced at fine pitches. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide an image sensor with improved performance and reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] An image sensor according to some embodiments of the present invention for achieving the above technical problem comprises: a first substrate including first and second surfaces facing each other and an active region disposed on the first surface; a plurality of pixel regions including a photoelectric conversion layer on the first surface of the first substrate; a pixel separation pattern defining the plurality of pixel regions in a direction perpendicular to the first surface of the first substrate; and first to third transistors corresponding to each of the plurality of pixel regions, wherein the first to third transistors share a single source / drain region within the active region.

[0008] An image sensor according to some embodiments of the present invention for achieving the above technical problem comprises: a substrate including a device isolation region and an active region; a plurality of pixel regions including a photoelectric conversion layer, a floating diffusion region, a transfer transistor electrically connected to the floating diffusion region, and first to third source follower transistors on the substrate; and a pixel isolation pattern penetrating the substrate and defining each of the plurality of pixel regions, wherein each of the first to third source follower transistors includes a first to third source region connected to each of the first to third source contacts and a shared drain region connected to one drain contact.

[0009] An image sensor according to some embodiments of the present invention for achieving the above technical problem comprises: a first substrate having a first surface and a second surface facing each other, with an active region formed on the first surface; pixels within the first substrate including a photoelectric conversion layer, a floating diffusion region, and a transfer transistor electrically connecting the photoelectric conversion layer and the floating diffusion region; a pixel separation pattern penetrating the first substrate and separating each pixel; a micro lens disposed on the second surface of the first substrate; a second substrate disposed on the first surface of the first substrate and including a fourth surface facing the first surface and a third surface facing the fourth surface; a plurality of source follower transistors connected to the floating diffusion region on the fourth surface of the second substrate; a third substrate disposed on the third surface of the second substrate; and a plurality of logic circuits controlling the plurality of source follower transistors on the third substrate, wherein the plurality of source follower transistors share a single drain region within the active region.

[0010] Specific details of other embodiments are included in the description of the invention and the drawings. Brief explanation of the drawing

[0011] FIG. 1 is an exemplary block diagram of an image sensor according to some embodiments. Figure 2 is a block diagram illustrating the pixel array, logic circuit, and ADC of Figure 1. Figure 3 is a circuit diagram illustrating the unit pixel area of ​​the pixel array of Figure 1. FIG. 4 is an exemplary plan view of an image sensor according to some embodiments. Figure 5 is a cross-sectional view taken along the lines A-A', B-B', and C-C' of Figure 4. FIG. 6 is a layout diagram schematically showing the unit pixel area of ​​an image sensor according to some embodiments. Figure 7 is a cross-sectional view taken along the line D-D' of Figure 6. Figure 8a is a cross-sectional view taken along the line E-E' of Figure 6. FIG. 8b is a drawing showing an image sensor according to some embodiment, corresponding to a cross-sectional view cut along the line E-E' of FIG. 6. FIG. 9 is an exemplary block diagram of an image sensor according to some embodiments. FIG. 10 is a layout diagram schematically showing the unit pixel area of ​​an image sensor according to some embodiments. Figure 11 is a cross-sectional view taken along the line F-F' of Figure 10. Figure 12 is a cross-sectional view taken along the line G-G' of Figure 10. Specific details for implementing the invention

[0012] Hereinafter, in order to explain the present invention more specifically, it will be described in more detail with reference to the attached drawings according to some embodiments of the present invention. With reference to FIGS. 1 to 8, an image sensor according to some embodiments will be described.

[0013] FIG. 1 is an exemplary block diagram of an image sensor according to some embodiments.

[0014] Referring to FIG. 1, an image sensor according to some embodiments may include a first semiconductor chip (100) and a second semiconductor chip (200). The first semiconductor chip (100) and the second semiconductor chip (200) may be arranged to overlap each other in a planar view. The first semiconductor chip (100) and the second semiconductor chip (200) may be stacked in a vertical direction.

[0015] The first semiconductor chip (100) may be referred to as the top plate, and the second semiconductor chip (200) may be referred to as the bottom plate. In this case, the photoelectric conversion layer (PD), the transfer transistor (TX), the reset transistor (RX), the source follower transistor (SX), the select transistor (AX), and the dual conversion transistor (DCX) of FIG. 6, which will be described later, may be formed on the first semiconductor chip (100).

[0016] The first semiconductor chip (100) may include a pixel array (10). The second semiconductor chip (200) may include a logic circuit (30) and an ADC (Analog Digital Converter; 35). The pixel array (10) may generate an electric charge in proportion to the amount of light entering the pixel array (10). Additionally, the pixel array (10) may convert an optical signal into an electrical signal, i.e., an analog signal, under the control of the logic circuit (30). The pixel array (10) may output an analog signal to the ADC (35). The ADC (35) may convert the analog signal into a digital signal. The ADC (35) may provide data based on the digital signal.

[0017] Although not illustrated, an image sensor according to some embodiments may further include a memory cell array in the second semiconductor chip (200). The memory cell array may store data based on digital signals.

[0018] The above data may be image data generated on a frame-by-frame basis. The number of bits in the data may be determined based on the resolution of the ADC (35). The number of bits in the data may be determined based on the HDR (High Dynamic Range) supported by the image sensor. Additionally, the bits in the data may further include at least one extension bit indicating the data generation location, data information, etc.

[0019] In some embodiments, the second semiconductor chip (200) may further include an embedded processor, such as an image signal processor (ISP) or a digital signal processor (DSP), that processes data output from the pixel array (10). The processor may improve noise in the image data, correct the image, or perform subsequent operations related to the image output from the pixel array (10).

[0020] Figure 2 is a block diagram illustrating the pixel array, logic circuit, and ADC of Figure 1.

[0021] Referring to FIG. 2, the pixel array (10) can be implemented in the first semiconductor chip (100), and the logic circuit (30) can be implemented in the second semiconductor chip (200).

[0022] A pixel array (10) can convert incident light and generate an electrical signal. The pixel array (10) may include unit pixel regions arranged in a matrix form along the row direction and column direction. The pixel array (10) can be driven under the control of a logic circuit (30). Specifically, the logic circuit (30) can control a plurality of transistors included in the pixel array (10).

[0023] The logic circuit (30) can efficiently receive data from the pixel array (10) and generate an image frame. For example, the logic circuit (30) may use a global shutter method in which all unit pixel areas are detected simultaneously, a flutter shutter method that controls the exposure time in which all unit pixel areas are detected simultaneously, a rolling shutter method that controls unit pixel areas in rows, or a coordinated rolling shutter method.

[0024] The second semiconductor chip (200) may include a row driver (21), a timing controller, and an ADC (35).

[0025] The row driver (21) can control the pixel array (10) in rows according to the control of the timing controller (22). The row driver (21) can select at least one row among the rows of the pixel array (10) according to the row address. The row driver (21) can decode the row address and be connected to a select transistor (AX), a reset transistor (RX), and a source follower transistor (SX). The pixel array (10) can be driven by a plurality of driving signals, such as a pixel select signal, a reset signal, and a charge transfer signal, received from the row driver (21).

[0026] The ADC (35) can be connected to the pixel array (10) through column lines (COL). The ADC (35) can convert analog signals received from the pixel array (10) through the column lines (COL) into digital signals. The number of ADCs (35) can be determined based on the number of unit pixel regions arranged along one row and the number of column lines (COL). There may be at least one ADC (35), but it is not limited thereto.

[0027] For example, the ADC (35) may include a reference signal generator (REF), a comparator (CMP), a counter (CNT), and a buffer (BUF). The reference signal generator (REF) may generate a ramp signal having a specific slope and provide the ramp signal as a reference signal to the comparator. The comparator (CMP) may compare the analog signal with the ramp signal of the reference signal generator (REF) and output comparison signals having respective transition points according to valid signal components. The counter (CNT) may perform a counting operation to generate a counting signal and provide the counting signal to the buffer (BUF). The buffer (BUF) may include latch circuits connected to each column line (COL) and may latch the counting signal output from the counter (CNT) for each column in response to a transition of the comparison signal, and output the latched counting signal as data.

[0028] In some embodiments, the logic circuit (30) may further include Correlated Double Sampling (CDS) circuits that perform correlated double sampling by calculating the difference between a reference voltage representing the reset state of unit pixel regions and an output voltage representing a signal component corresponding to the incident light, and output an analog sampling signal corresponding to the valid signal component. The correlated double sampling circuits may be connected to column lines (COL).

[0029] The timing controller (22) can control the operation timing of the row driver (21) and the ADC (35). The timing controller (22) can provide timing signals and control signals to the row driver (21) and the ADC (35). More specifically, the timing controller (22) can control the ADC (35), and the ADC (35) can provide data to the logic circuit (30) according to the control of the timing controller (22). Additionally, the timing controller (22) may further include circuits that provide requests, commands, or addresses to the logic circuit (30) so that data from the ADC (35) is stored in a memory cell array.

[0030] Figure 3 is a circuit diagram illustrating the unit pixel area of ​​the pixel array of Figure 1.

[0031] Referring to FIG. 3, the pixel array may include a photoelectric conversion layer (PD), a transfer transistor (TX), a floating diffusion region (FD), a reset transistor (RX), a source follower transistor (SX), a select transistor (AX), and a dual conversion transistor (DCX). Referring to FIG. 3 and FIG. 6, a unit pixel region may include a plurality of first to eighth pixel regions (PX1 to PX8) comprising eight photoelectric conversion layers (PD) connected in parallel. The transfer transistor (TX) may include a plurality of first to eighth transfer transistors (TX1 to TX8) connected in parallel. However, the number of photoelectric conversion layers, the number of pixel regions, and the number of transistors are not limited thereto.

[0032] The photoelectric conversion layer (PD) can generate charge in proportion to the amount of light incident from the outside. The photoelectric conversion layer (PD) may be a photodiode comprising an n-type impurity region and a p-type impurity region. The photoelectric conversion layer (PD) may be coupled with a transfer transistor (TX) that transfers the generated and accumulated charge to a floating diffusion region (FD). The floating diffusion region (FD) is a region that converts charge into voltage, and because it has parasitic capacitance, charge can be accumulated and stored.

[0033] In some embodiments, the floating diffusion region (FD) may include a first floating diffusion region (FD1) shared by photoelectric conversion layers (PDs) and a second floating diffusion region (FD2) connected to a dual conversion transistor (DCX) and controlling the composite capacitance.

[0034] One end of the transfer transistor (TX) may be connected to the photoelectric conversion layer (PD), and the other end of the transfer transistor (TX) may be connected to the floating diffusion region (FD). The transfer transistor (TX) may be formed as a transistor driven by a predetermined bias, for example, by transfer signals. The transfer signals may be applied through transfer gates (TG). That is, the transfer transistor (TX) may transfer charges generated from the photoelectric conversion layer (PD) to the floating diffusion region (FD) according to the transfer signals.

[0035] The source follower transistor (SX) amplifies the change in the electrical potential of the floating diffusion region (FD), which receives charge from the photoelectric conversion layer (PD), and outputs it to the output line (V OUT It can output as ). When the source follower transistor (SX) is turned on, a predetermined electrical potential provided to the drain of the source follower transistor (SX), e.g., power supply voltage (V DD) can be transferred to the drain region of the select transistor (AX). Multiple source follower gates (SF1, SF2, SF3) of the source follower transistor (SX) can be connected to the floating diffusion region (FD).

[0036] The select transistor (AX) can select a unit pixel area to be read row by row. The select transistor (AX) may be composed of a transistor driven by a select line that applies a predetermined bias, for example, a row selection signal. The row selection signal may be applied through a select gate (SEL).

[0037] The reset transistor (RX) can periodically reset the floating diffusion region (FD). The reset transistor (RX) may consist of a transistor driven by a reset line that applies a predetermined bias, for example, a reset signal. The reset signal may be applied through a reset gate (RG). When the reset transistor (RX) is turned on by the reset signal, a predetermined electrical potential, for example, a power supply voltage (V), is provided at the drain of the reset transistor (RX). DD ) can be transferred to the floating diffusion region (FD).

[0038] The dual conversion transistor (DCX) can adjust the conversion gain. For example, the conversion gain can be adjusted by applying a logic high-level dual gain signal or a logic low-level dual gain signal to the dual conversion gate of the dual conversion transistor (DCX). The dual conversion transistor (DCX) can be placed between the first floating diffusion region (FD1) and the second floating diffusion region (FD2). Depending on whether the dual conversion transistor (DCX) is driven, the conversion gain can be adjusted by adjusting the composite capacitance corresponding to the first and second floating diffusion regions (FD1, FD2).

[0039] The wiring structure described below may be electrically connected to at least one of a transmission gate (TG), a source follower gate (SF), a dual conversion gate (DCG), a reset gate (RG), and a select gate (SEL). The wiring structure is connected to the drain of the reset transistor (RX) or the drain of the source follower transistor (SX) with a power supply voltage (V DD It can be configured to apply ). The wiring structure may include a column line connected to a select transistor (AX).

[0040] In FIG. 3, a configuration in which eight photoelectric conversion layers (PD1 to PD8) electrically share a single floating diffusion region (FD1) is illustrated, but the technical concept of the present invention is not limited thereto. That is, the number of photoelectric conversion layers (PD1 to PD8) electrically sharing a single floating diffusion region (FD1) is not limited to that shown in the present invention.

[0041] FIG. 4 is an exemplary plan view of an image sensor according to some embodiments. FIG. 5 is a cross-sectional view taken along the lines A-A', B-B' and C-C' of FIG. 4.

[0042] Referring to FIG. 4, an image sensor according to some embodiments of the present invention may include a sensor array region (SAR) and a pad region (PR).

[0043] The sensor array region (SAR) may include a region corresponding to the first pixel array (10) and the second pixel array (20) of FIGS. 1 and 2. For example, a plurality of unit pixels arranged two-dimensionally (e.g., in the form of a matrix) may be formed within the sensor array region (SAR).

[0044] The sensor array area (SAR) may include an receiving area (APS) and a blocking area (OB). Active pixels that receive light and generate an active signal may be arranged in the receiving area (APS). Optical black pixels that block light and generate an optical black signal may be arranged in the blocking area (OB). The blocking area (OB) may be formed, for example, along the periphery of the receiving area (APS), but this is merely exemplary. In some embodiments, although not illustrated, dummy pixels may be formed in the receiving area (APS) adjacent to the blocking area (OB). The dummy pixels may be pixels that do not generate an active signal.

[0045] A pad region (PR) may be formed around a sensor array region (SAR). The pad region (PR) may be formed adjacent to the edge of an image sensor according to some embodiments, but this is merely exemplary. The pad region (PR) may be connected to an external device, etc., and configured to transmit and receive electrical signals between the image sensor and the external device according to some embodiments.

[0046] Referring to FIG. 5, an image sensor according to some embodiments may include a first substrate (110), a pixel separation pattern (120), a surface insulating film (150), a first color filter (170), a grid pattern (160), a micro lens (180), a second substrate (210), a first pad pattern (455), and a second pad pattern (555).

[0047] The first substrate (110) may be a semiconductor substrate. For example, the first substrate (110) may be bulk silicon or a silicon-on-insulator (SOI). The first substrate (110) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate (110) may be a base substrate on which an epitaxial layer is formed.

[0048] The first substrate (110) may include a first surface (110a) and a second surface (110b) facing each other. In some embodiments, the second surface (110b) of the first substrate (110) may be a light-receiving surface into which light is incident. That is, the image sensor according to some embodiments may be a back-illuminated (BSI) image sensor.

[0049] A plurality of pixel regions (PX) may be formed within the first substrate (110) of the light receiving region (APS) and the light blocking region (OB). Each pixel region (PX) may include a photoelectric conversion layer (PD). The first substrate (110) of the light blocking region (OB) may include a dummy pixel region that does not include a photoelectric conversion layer (PD), but is not limited thereto. A signal generated in the dummy pixel region may be used as information to remove process noise later.

[0050] A photoelectric conversion layer (PD) can be formed within the first substrate (110) of the light receiving region (APS) and the light blocking region (OB). The photoelectric conversion layer (PD) can generate a charge in proportion to the amount of light incident from the outside. The photoelectric conversion layer (PD) can transfer the generated and accumulated charge to the floating diffusion region (FD).

[0051] A floating diffusion region (FD) may be formed within the first substrate (110) of the light receiving region (APS) and the light blocking region (OB). The floating diffusion region (FD) may be formed within the first surface (110a) of the first substrate (110). The charge transferred to the floating diffusion region (FD) may be applied to a plurality of source follower gates (SF1, SF2, SF3) of FIG. 3.

[0052] A transfer transistor (TX) can be placed on a first substrate (110). One end of the transfer transistor (TX) is connected to a photoelectric conversion layer (PD), and the other end of the transfer transistor (TX) can be connected to a floating diffusion region (FD). The transfer transistor (TX) can transfer charges generated from the photoelectric conversion layer (PD) to the floating diffusion region (FD).

[0053] The transfer transistor (TX) may include a transfer gate, a gate insulating film, and a gate spacer. Although not specifically illustrated, the transfer gate may include a portion embedded within the first substrate (110). The gate insulating film may be placed between the transfer gate and the first substrate (110). The gate spacer may be placed on both side walls of the transfer gate.

[0054] A pixel isolation pattern (120) can be formed within the first substrate (110). The pixel isolation pattern (120) can be formed by embedding an insulating material within a deep trench formed by patterning the first substrate (110). The pixel isolation pattern (120) can penetrate the first substrate (110) in a third direction (DR3). For example, the pixel isolation pattern (120) can extend from the first surface (110a) to the second surface (110b). Such a pixel isolation pattern (120) can be a frontside deep trench isolation (FDTI).

[0055] Although not specifically illustrated, the pixel separation pattern (120) may define multiple pixel regions (PX) and dummy pixel regions. The pixel separation pattern (120) may be formed in a grid shape from a planar perspective to separate multiple pixel regions (PX) and the aforementioned dummy pixel regions from one another.

[0056] In some embodiments, a device isolation pattern (105) may be provided. The device isolation pattern (105) may be disposed within the first substrate (110). For example, the device isolation pattern (105) may be disposed within a recessed trench in a portion of the first substrate (110). The trench may be recessed from a first surface (110a) of the first substrate (110). The device isolation pattern (105) may be a shallow trench isolation (STI) film.

[0057] The width of the device isolation pattern (105) in the second direction (DR2) may be gradually reduced as it moves from the first surface (110a) of the first substrate (110) toward the second surface (110b). The device isolation pattern (105) may overlap with the pixel isolation pattern (120) in the second direction (DR2) or the first direction (DR1). The pixel isolation pattern (120) may penetrate the device isolation pattern (105) in the third direction (DR3). The device isolation pattern (105) may include an insulating material. The device isolation pattern (105) may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0058] Referring to FIG. 5, an image sensor according to some embodiments may include a first wiring structure (IS1) comprising a first wiring insulating film (140), contacts (141, 144), first wiring patterns (145, 146, 147, 148), and vias (149).

[0059] The first wiring insulating film (140) may be formed on the first surface (110a) of the first substrate (110). For example, the first wiring insulating film (140) may cover the first surface (110a) of the first substrate (110). The first substrate (110) and the first wiring insulating film (140) may constitute the first semiconductor chip (100). In FIG. 5, the first wiring insulating film (140) is shown as being separated into one layer, but is not limited thereto. The number of layers of the first wiring insulating film (140) is merely illustrative.

[0060] The first wiring insulating film (140) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0061] Within the first wiring insulating film (140), contacts (141, 144) and first wiring patterns (145, 146, 147, 148) and vias (149) connecting the first wiring patterns (145, 146, 147, 148) may be provided. The contacts (141, 144) may electrically connect the first transistors (TR1) and the floating diffusion region (FD) with the first wiring patterns (145, 146, 147, 148). Some of the first wiring patterns (145, 146, 147, 148) may be connected to the first connection structure (450), but are not limited thereto.

[0062] Each of the first wiring patterns (145, 146, 147, 148), contacts (141, 144), and vias (149) may comprise, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but is not limited thereto.

[0063] The second substrate (210) may be bulk silicon or SOI (silicon-on-insulator). The second substrate (210) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate (210) may be an epitaxial layer formed on a base substrate.

[0064] The second substrate (210) may include an upper surface and a lower surface. The upper surface (210a) of the second substrate (210) may be a surface facing the first semiconductor chip (100).

[0065] A plurality of second transistors (TR2) may be formed on the upper surface (210a) of the second substrate (210). The second transistors (TR2) may be, for example, logic circuits. The second transistors (TR2) may control a transfer transistor (TX), a reset transistor (RX), a select transistor (AX), a source follower transistor (SX), and a dual conversion transistor (DCX).

[0066] A second wiring structure (IS2) including a second wiring insulating film (240), contacts (241), second wiring patterns (245, 246) and vias (249) can be formed on a second substrate (210).

[0067] The second wiring insulating film (240) may cover the upper surface (210a) of the second substrate (210). The second substrate (210) and the second wiring insulating film (240) may constitute a second semiconductor chip (200). The second wiring insulating film (240) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0068] Second wiring patterns (245, 246) may be disposed within the second wiring insulating film (240). The second wiring patterns (245, 246) may each be connected to the second transistors (TR2) through contacts (241) and may also be connected to the floating diffusion region (FD) of the first semiconductor chip (100). Some of the second wiring patterns (245, 246) may be connected to the first connection structure (450). Additionally, other parts of the second wiring patterns (245, 246) may be connected to the second connection structure (550). However, the technical concept of the present invention is not limited thereto.

[0069] Each of the second wiring patterns (245, 246), contacts (241), and vias (249) may comprise, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but is not limited thereto.

[0070] A surface insulating film (150) may be formed on a second surface (110b) of a first substrate (110). The surface insulating film (150) may extend along the second surface (110b) of the first substrate (110). In some embodiments, at least a portion of the surface insulating film (150) may be in contact with a pixel separation pattern (120).

[0071] The surface insulating film (150) may include an insulating material. For example, the surface insulating film (150) may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof, but is not limited thereto.

[0072] The surface insulating film (150) functions as an anti-reflection film, thereby preventing the reflection of light incident on the first substrate (110) and improving the light reception rate of the photoelectric conversion layer (PD). Additionally, the surface insulating film (150) functions as a flattening film, thereby enabling the formation of the first color filter (170) and micro lens (180), which will be described later, at a uniform height.

[0073] A first color filter (170) may be formed on a surface insulating film (150) of a light receiving area (APS). In some embodiments, the first color filter (170) may be arranged to correspond to each pixel area (PX). For example, a plurality of first color filters (170) may be arranged two-dimensionally (e.g., in the form of a matrix).

[0074] The first color filter (170) may have various color filters depending on the pixel area (PX). For example, the first color filter (170) may be arranged in a Bayer pattern including a red color filter, a green color filter, and a blue color filter. However, this is merely exemplary, and the first color filter (170) may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0075] A grid pattern (160) can be formed on a surface insulating film (150). The grid pattern (160) can be formed in a grid shape in a planar view and interposed between a plurality of first color filters (170).

[0076] The grid pattern (160) may include a low refractive index material with a refractive index lower than that of silicon (Si). For example, the grid pattern (160) may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. The grid pattern (160) containing the low refractive index material can improve the quality of the image sensor by refracting or reflecting light incident obliquely on the image sensor.

[0077] In some embodiments, a first protective film (165) may be formed on the surface insulating film (150) and the grid pattern (160). The first protective film (165) may be interposed between the surface insulating film (150) and the first color filter (170) and between the grid pattern (160) and the first color filter (170). For example, the first protective film (165) may extend along the profile of the upper surface of the surface insulating film (150), the side surface of the grid pattern (160), and the upper surface.

[0078] The first protective layer (165) may include, for example, aluminum oxide, but is not limited thereto. The first protective layer (165) can prevent damage to the surface insulating layer (150) and the grid pattern (160).

[0079] Micro lenses (180) can be formed on the first color filter (170). Micro lenses (180) can be arranged to correspond to each pixel area (PX). For example, micro lenses (180) can be arranged two-dimensionally in a plane (e.g., in the form of a matrix).

[0080] The micro lens (180) has a convex shape and may have a predetermined radius of curvature. Accordingly, the micro lens (180) can concentrate light incident on the photoelectric conversion layer (PD). The micro lens (180) may include, for example, a light-transmitting resin, but is not limited thereto.

[0081] In some embodiments, a second protective film (185) may be formed on the microlens (180). The second protective film (185) may extend along the surface of the microlens (180). The second protective film (185) may, for example, comprise an inorganic oxide film. For example, the second protective film (185) may comprise at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof, but is not limited thereto. In some embodiments, the second protective film (185) may comprise a low temperature oxide (LTO).

[0082] The second protective layer (185) can protect the micro lens (180) from the outside. For example, the second protective layer (185) can protect the micro lens (180) containing organic material by including an inorganic oxide film. Additionally, the second protective layer (185) can improve the light-gathering ability of the micro lens (180). For example, the second protective layer (185) can reduce reflection, refraction, scattering, etc. of incident light reaching the space between the micro lenses (180) by filling the space between the micro lenses (180).

[0083] An image sensor according to some embodiments may further include a first connection structure (450) and a second connection structure (550).

[0084] A first connection structure (450) may be formed within a light-shielding area (OB). A first connection structure (450) may be formed on a surface insulating film (150) of the light-shielding area (OB). A first connection structure (450) may be in contact with a pixel separation pattern (120). For example, a first trench exposing a pixel separation pattern (120) may be formed within the first substrate (110) and the surface insulating film (150) of the light-shielding area (OB). A first connection structure (450) may be formed within the first trench to be in contact with a pixel separation pattern (120) within the light-shielding area (OB). A first connection structure (450) may extend along the profile of the side and bottom surfaces of the first trench.

[0085] The first connecting structure (450) may be electrically connected to the first separation pattern (120). For example, the first connecting structure (450) may be electrically connected to the first separation pattern (120). The first connecting structure (450) may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are stacked in sequence.

[0086] In some embodiments, a first pad pattern (455) that fills the first trench may be formed on the first connecting structure (450). The first pad pattern (455) may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but is not limited thereto.

[0087] In some embodiments, the first protective layer (165) may cover the first connection structure (450) and the first pad pattern (455). For example, the first protective layer (165) may extend along the profile of the first connection structure (450) and the first pad pattern (455).

[0088] In some embodiments, a second color filter (170C) may be formed on the first connection structure (450). For example, the second color filter (170C) may be formed to cover a portion of the first protective film (165) within the light-blocking area (OB). The second color filter (170C) may include, for example, a blue color filter, but is not limited thereto.

[0089] In some embodiments, a third protective film (480) may be formed on the second color filter (170C). In some embodiments, the second protective film (185) may extend along the surface of the third protective film (480). The third protective film (480) may, for example, comprise a light-transmitting resin, but is not limited thereto. In some embodiments, the third protective film (480) may comprise the same material as the microlens (180).

[0090] The second connection structure (550) may be formed in the pad area (PR). The second connection structure (550) may be formed on the surface insulating film (150) of the pad area (PR). The second connection structure (550) may be electrically connected to an external device, etc.

[0091] For example, a second trench exposing a second wiring pattern (243) may be formed within the first semiconductor chip (100) and the second semiconductor chip (200) of the pad area (PR). A second connection structure (550) may be formed within the second trench and may come into contact with the second wiring pattern (243). Additionally, a third trench may be formed within the first substrate (110) of the pad area (PR). A second connection structure (550) may be formed within the third trench and exposed. In some embodiments, the second connection structure (550) may extend along the profiles of the side and bottom surfaces of the second trench and the third trench.

[0092] In some embodiments, a filling insulating film (560) that fills the second trench may be formed on the second connecting structure (550). The filling insulating film (560) may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto.

[0093] In some embodiments, a second pad pattern (555) filling the third trench may be formed on the second connecting structure (550). The second pad pattern (555) may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but is not limited thereto. The second connecting structure (550) may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked within the second trench.

[0094] In some embodiments, the second protective layer (185) and the third protective layer (580) may expose the second pad pattern (555). For example, an exposure opening (ER) that exposes the second pad pattern (555) may be formed within the second protective layer (185) and the third protective layer (580). Accordingly, the second pad pattern (555) may be connected to an external device, etc., and configured to transmit and receive electrical signals between the image sensor and the external device according to some embodiments.

[0095] FIG. 6 is a layout diagram schematically showing a unit pixel area of ​​an image sensor according to some embodiments. FIG. 7 is a cross-sectional view taken along the line D-D' of FIG. 6. FIG. 8a is a cross-sectional view taken along the line E-E' of FIG. 6.

[0096] Hereinafter, with reference to FIGS. 6 to 8a, an image sensor according to some embodiments will be described in more detail.

[0097] Referring to FIGS. 6 to 8a, the device isolation pattern (105) within the first substrate (110) can define active regions (ACT). For convenience of explanation, the surface insulating film (150), grid pattern (160), first protective film (165), first color filter (170), micro lens (180), and second protective film (185) may be omitted from the description.

[0098] From a planar perspective, the active regions (ACT) may have a line shape extending in the second direction (DR2). However, the shape of the active regions (ACT) is not limited to the shape shown in FIG. 6 and can be varied.

[0099] Referring to FIGS. 3 and 6, on the active regions (ACT), first and second floating diffusion regions (FD1, FD2), first to eighth transfer transistors (TX1 to TX8) and a select transistor (AX), a reset transistor (RX), first to third source follower transistors (SX1, SX2, SX3) and a dual conversion transistor (DCX) may be provided.

[0100] The first to eighth transmission transistors (TX1 to TX8) include the first to eighth transmission gates (TG1 to TG8), the select transistor (AX) includes the select gate (SEL), the first to third source follower transistors (SX1, SX2, SX3) include the first to third source follower gates (SF1, SF2, SF3), and the dual conversion transistor (DCX) may include the dual conversion gate (DCG). However, the arrangement and number of transistors included in the pixel area (PX) are not limited to those shown in FIGS. 3 and FIGS. 6.

[0101] In FIG. 6, a first floating diffusion region (FD1) may be provided on one side of the first to eighth transmission gates (TG1 to TG8). Each of the first to eighth transmission gates (TG1 to TG8) and the first floating diffusion region (FD1) may be arranged to face each other in a second direction (DR2). The first floating diffusion region (FD1) may have a conductivity type opposite to that of the first substrate (110). For example, n-type impurities may be doped into the first floating diffusion region (FD1). However, the technical concept of the present invention is not limited thereto.

[0102] Referring to FIGS. 3 and FIGS. 6, each of the first to third pixel regions (PX1, PX2, PX3) may include first to third transmission transistors (TX1, TX2, TX3), a first floating diffusion region (FD1), and first to third source follower transistors (SX1, SX2, SX3).

[0103] Referring to FIGS. 6 and 7, the first to third source follower transistors (SX1, SX2, SX3) may share a single source / drain region (S_S / D) within an active region (ACT). The shared source / drain region (S_S / D) may be positioned between a plurality of adjacent pixel regions (PX). In a planar view, the shared source / drain region (S_S / D) of the first to third source follower transistors (SX1, SX2, SX3) may be connected to one another by an active region (ACT) formed radially within the first substrate (110).

[0104] Meanwhile, the shared source / drain region (S_S / D) may not be electrically connected to the fourth pixel region (PX4) due to the device isolation pattern (105). However, the technical concept of the present invention is not limited thereto.

[0105] In some embodiments, the pixel separation pattern (120) may define pixel regions (PX). For example, the pixel separation pattern (120) may be provided between pixel regions (PX). In a planar view, the pixel separation pattern (120) may have a grid structure. In a planar view, the pixel separation pattern (120) may completely surround each pixel region (PX). The pixel separation pattern (120) may be a grid structure extending in a first direction (DR1) and a second direction (DR2).

[0106] The pixel separation pattern (120) may penetrate the first substrate (110) in a third direction (DR3) perpendicular to the first and second surfaces (110a, 110b) of the first substrate (110). However, referring to FIGS. 6 and 7, the shared source / drain region (S_S / D) may not overlap with the pixel separation pattern (120) between the plurality of pixel regions (PX) in the third direction (DR3). This may be a structure resulting from removing the pixel separation pattern (120) in the region where the shared source / drain region (S_S / D) is to be formed. The shared source / drain region (S_S / D) may be merged through an active region (ACT) in the region where the pixel separation pattern (120) has been removed.

[0107] Referring to FIG. 7, in some embodiments, the pixel separation pattern (120) may include a liner film (120L), a first conductive layer (120F), and a capping film (120C). The liner film (120L) may be disposed along the sidewalls and bottom surfaces of the pixel separation trench (t1). The first conductive layer (120F) may be disposed on the liner film (120L). The capping film (120C) may be disposed on the first conductive layer (120F).

[0108] The liner film (120L) may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. The first conductive layer (120F) may include a conductive material. The first conductive layer (120F) may include polysilicon (poly Si), but is not limited thereto. The capping film (120C) may include an insulating material. The capping film (120C) may include a silicon-based insulating material and a high dielectric material.

[0109] In some embodiments, the image sensor may include a gate contact (141) connected to the gate of a transistor in each pixel region (PX) and a source / drain contact (142, 143) connected to the source / drain region of each transistor. The gate contact (141) and the source / drain contact (142, 143) may be disposed on the aforementioned top plate.

[0110] Referring to FIGS. 6 and 7, the source / drain region (S / D) of the first source follower transistor (SX1) can be connected to the first wiring pattern (145) of the first wiring structure (IS1) through the first source / drain contact (142a). The source / drain region (S / D) of the second source follower transistor (SX2) can be connected to the first wiring pattern (145) of the first wiring structure (IS1) through the second source / drain contact (142b).

[0111] A shared source / drain region (S_S / D) can be connected to a first wiring pattern (145) of a first wiring structure (IS1) through a shared source / drain contact (143). In this case, a non-shared source / drain region (S / D) may be disposed on one side of each of the first to third source follower transistors (SX1, SX2, SX3), and a shared source / drain region (S_S / D) may be disposed on the other side of each.

[0112] According to some embodiments, in an image sensor comprising a plurality of transistors, one of the source region and the drain region of the transistors may be shared among the transistors. As a result, the number of contacts connected to the source region or the drain region can be reduced, thereby providing an image sensor with improved performance while securing the area of ​​the transistors.

[0113] Referring to FIG. 6, in a planar view, the gate contacts (141a, 141b, 141c) of each of the first to third source follower transistors (SX1, SX2, SX3) can form a triangular shape.

[0114] Additionally, the distance between the gate contact (141a) of the first source follower transistor (SX1) and the shared source / drain contact (143) may be the same as the distance between the gate contact (141b) of the second source follower transistor (SX2) and the shared source / drain contact (143), and the distance between the gate contact (141c) of the third source follower transistor (SX3) and the shared source / drain contact (143). However, the technical concept of the present invention is not limited thereto, and the distances between the respective gate contacts (141a, 141b, 141c) and the shared source / drain contact (143) of the first to third source follower transistors (SX1, SX2, SX3) may differ from each other.

[0115] Additionally, from a planar perspective, the width of the region where the non-shared source / drain region (S / D) of each of the first to third source follower transistors (SX1, SX2, SX3) is formed in the active region (ACT) may differ from the width of the region connected to the shared source / drain region (S_S / D) in the active region (ACT).

[0116] For example, referring to FIG. 6, the width (W1) of the region where the shared source / drain region (S_S / D) of the first source follower transistor (SX1) is formed in the active region (ACT) may be larger than the width (W2) of the region connected to the non-shared source / drain region (S / D) in the active region (ACT). In this case, the non-shared source / drain regions (S / D) and the shared source / drain region (S_S / D) may be formed asymmetrically in each source follower transistor (SX1, SX2, SX3). However, the technical concept of the present invention is not limited thereto.

[0117] Referring to FIGS. 6 and FIGS. 8a, the first to third source follower transistors (SX1, SX2, SX3) can be connected to the first floating diffusion region (FD1) through the first wiring structure (IS1).

[0118] A first floating diffusion area (FD1) placed in a first pixel area (PX1), a first floating diffusion area (FD1) placed in a second pixel area (PX2), and a first floating diffusion area (FD1) placed in a third pixel area (PX3) can be electrically connected to each other through a first wiring structure (IS1).

[0119] The first floating diffusion region (FD1) of the first pixel region (PX1) and the first source follower transistor (SX1) can be electrically connected to the first wiring pattern (145) through their respective contacts (144, 141a).

[0120] The first source follower transistor (SX1) of the first pixel area (PX1) and the second source follower transistor (SX2) of the second pixel area (PX2) can be electrically connected to the first wiring pattern (145) through their respective gate contacts (141a, 141b).

[0121] The first floating diffusion region (FD1) of the second pixel region (PX2) and the second source follower transistor (SX2) can be electrically connected to the first wiring pattern (145) through their respective contacts (144, 141b).

[0122] The first floating diffusion region (FD1) of the second pixel area (PX2) and the first floating diffusion region (FD1) of the fourth pixel area (PX4) can be electrically connected to each other through the first wiring structure (IS1).

[0123] The source / drain region (S / D) of the first source follower transistor (SX1), the source / drain region (S / D) of the second source follower transistor (SX2), and the source / drain region (S / D) of the third source follower transistor (SX3) can be electrically connected to each other through the first wiring structure (IS1). In this case, each source / drain region (S / D) can be electrically connected by a wiring pattern located on a different layer from the first wiring pattern (145) of the first wiring structure (IS1). However, the technical concept of the present invention is not limited thereto.

[0124] The reset transistor (RX) and the shared source / drain region (S_S / D) can be electrically connected to each other through the shared source / drain contact (143) and the first wiring structure (IS1). In this case, the drain region of the reset transistor (RX) and the shared source / drain region (S_S / D) can be connected to each other through the active region (ACT).

[0125] The second floating diffusion region (FD2) may be placed between the reset transistor (RX) and the dual conversion transistor (DCX) and electrically connected to them. The second floating diffusion region (FD2) may be connected to the first capacitor (C1) for the aforementioned synthetic capacitance control.

[0126] In this case, the second floating diffusion region (FD2) can be connected to the dual conversion transistor (DCX), the reset transistor (RX), and the first capacitor (C1) through the active region (ACT). However, the technical concept of the present invention is not limited thereto.

[0127] In some embodiments, the source / drain region (S / D) of the first source follower transistor (SX1), the source / drain region (S / D) of the second source follower transistor (SX2), and the source / drain region (S / D) of the third source follower transistor (SX3) are each source regions and may be shared source / drain regions (S_S / D) drain regions.

[0128] However, the technical concept of the present invention is not limited thereto, and the source / drain region (S / D) of the first source follower transistor (SX1), the source / drain region (S / D) of the second source follower transistor (SX2), and the source / drain region (S / D) of the third source follower transistor (SX3) are each drain regions, and the shared source / drain region (S_S / D) may be a source region.

[0129] FIG. 8b is a drawing showing an image sensor according to some embodiment, corresponding to a cross-sectional view cut along the line E-E' of FIG. 6. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to FIG. 8a.

[0130] Referring to FIG. 8b, the pixel isolation pattern (120a) penetrates the second surface (110b) of the substrate (110) and may be spaced apart from the first surface (110a). Such a pixel isolation pattern (120a) may be a backside deep trench isolation (BDTI).

[0131] The pixel separation pattern (120a) may include a first insulating layer (120a1), a second insulating layer (120a2), and a third insulating layer (120a3).

[0132] The first insulating layer (120a1) may be conformally formed on the second surface (110b) of the first substrate (110), for example, the surface on which light is incident to the photoelectric conversion layer (PD). The first insulating layer (120a1) may be hafnium oxide (HfO2), hafnium silicon oxide (Hf x Si y O z It may include a metal oxide having a high dielectric constant (high-k), such as titanium oxide (TiO2), zirconium oxide (ZrO2), magnesium oxide (MgO), tantalum oxide (Ta2O5), scandium oxide (Sc2O3), ruthenium oxide (Lu2O3), yttrium oxide (Y2O3), and lanthanum oxide (La2O3).

[0133] The second insulating layer (120a2) may be formed conformally along the top and side surfaces of the first insulating layer (120a1) and along the sidewalls and bottom surfaces of the pixel separation trench (t1a). The pixel separation trench (t1a) may extend from the second surface (110b) of the first substrate (110) between the photoelectric conversion layers (PDs) to define the photoelectric conversion layers (PDs). For example, the second insulating layer (120a2) may comprise an electron-rich metal oxide such as aluminum oxide (Al2O3).

[0134] The first and second insulating layers (120a1, 120a2) may be fixed charge films. In this case, dark current, dark level defects, white spot defects, etc. are prevented, and the photoelectric conversion characteristics of the photoelectric conversion layer (PD) can be improved.

[0135] Additionally, the first insulating layer (120a1) may be an anti-reflection layer. In this case, light incident on the photoelectric conversion layer (PD) may be prevented from being reflected from the surface of the first substrate (110) by the first insulating layer (120a1).

[0136] A third insulating layer (120a3) is formed on the second insulating layer (120a2) and can fill the pixel separation trench (t1a). The third insulating layer (120a3) may be thicker than the first and second insulating layers (120a1, 120a2). The third insulating layer (120a3) may include an insulating material such as silicon oxide (SiO2). The third insulating layer (120a3) may have a lower dielectric constant and better filling characteristics than the first and second insulating layers (120a1, 120a2).

[0137] A first color filter (170) and a micro lens (180) may be formed on the third insulating layer (120a3).

[0138] FIG. 9 is an exemplary block diagram of an image sensor according to some embodiments. FIG. 10 is a layout diagram schematically showing the unit pixel area of ​​an image sensor according to some embodiments. FIG. 11 is a cross-sectional view taken along the line F-F' of FIG. 10. FIG. 12 is a cross-sectional view taken along the line G-G' of FIG. 10. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to FIG. 8. For convenience of explanation, the description of the element isolation pattern (105) may be omitted.

[0139] Referring to FIG. 9, an image sensor according to some embodiments may include a first semiconductor chip (100), a second semiconductor chip (200), and a third semiconductor chip (300). The first semiconductor chip (100), the second semiconductor chip (200), and the third semiconductor chip (300) may be arranged to overlap each other in a planar view. The first semiconductor chip (100), the second semiconductor chip (200), and the third semiconductor chip (300) may be stacked sequentially in a vertical direction. The first semiconductor chip (100) may be referred to as the top plate, the second semiconductor chip (200) as the middle plate, and the third semiconductor chip (300) as the bottom plate.

[0140] Unlike what is illustrated, the first semiconductor chip (100) and the second semiconductor chip (200) can be formed on a single chip. A semiconductor chip including a pixel array and a semiconductor chip including a logic circuit can be stacked together.

[0141] An image sensor according to some embodiments includes a first pixel array (10) and a second pixel array (20), and the first pixel array (10) and the second pixel array (20) may represent a 3-stack image sensor formed on different chips and stacked. FIG. 9 The first and second pixel arrays (10, 20) may be implemented in first and second semiconductor chips (100, 200), and the logic circuit (30) may be implemented in a third semiconductor chip (300).

[0142] In this case, the photoelectric conversion layer (PD) and the transfer transistor (TX) of FIG. 10 may be formed on the first semiconductor chip (100), and the reset transistor (RX), source follower transistor (SX), select transistor (AX), and dual conversion transistor (DCX) may be formed on the second semiconductor chip (200). The first semiconductor chip (100) and the second semiconductor chip (200) may be aligned to form a unit pixel.

[0143] Referring to FIGS. 11 and 12, the first transfer transistor (TX1) can be connected to the first wiring pattern (145) of the first wiring structure (IS1) through a gate contact (141a). The second transfer transistor (TX2) can be connected to the first wiring pattern (145) of the first wiring structure (IS1) through a gate contact (141b).

[0144] The first bonding pad (BP1) may be placed within the first wiring insulating film (140). On the first wiring insulating film (140), one side of the first bonding pad (BP1) may be exposed. The lower surface of the first bonding pad (BP1) may be located in the same plane as the lower surface of the first wiring insulating film (140). The first bonding pad (BP1) may be bonded to the second bonding pad (BP2), which will be described later. The first wiring insulating film (140) and the second wiring insulating film (240) may be bonded to each other using the first bonding pad (BP1) and the second bonding pad (BP2).

[0145] The second substrate (210) may be bulk silicon or SOI (silicon-on-insulator). The second substrate (210) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate (210) may be an epitaxial layer formed on a base substrate.

[0146] The second substrate (210) may include a third surface (210b) and a fourth surface (210a). The fourth surface (210a) of the second substrate (210) may be a surface facing the first semiconductor chip (100). The third surface (210b) of the second substrate (210) may be a surface facing the fourth surface (210a) of the second substrate (210).

[0147] Source follower transistors (SX) may be formed on the fourth surface (210a) of the second substrate (210). The source follower transistors (SX) may be electrically connected to the floating diffusion region (FD) of the first semiconductor chip (100).

[0148] A second wiring structure (IS2) may be formed on a second substrate (210). For example, the second wiring structure (IS2) may cover a fourth surface (210a) of the second substrate (210). The second substrate (210) and the second wiring structure (IS2) may constitute a second semiconductor chip (200).

[0149] The second wiring structure (IS2) can be attached to the first wiring structure (IS1). For example, the upper surface of the second wiring structure (IS2) can be attached to the lower surface of the first wiring structure (IS1). Specifically, the lower surface of the first wiring insulating film (140) and the upper surface of the second wiring insulating film (240) can be bonded to each other.

[0150] The second wiring structure (IS2) may include a second wiring insulating film (240) and second wiring patterns (245), contacts (241a, 241b, 243), and second bonding pads (BP2) disposed within the second wiring insulating film (240). In FIGS. 11 and 12, the number of layers of wiring patterns constituting the second wiring structure (IS2) and their arrangement are merely exemplary and are not limited thereto.

[0151] The second wiring insulating film (240) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0152] In some embodiments, the image sensor may include a gate contact (241) connected to the gate of a transistor in each pixel region (PX) and a source / drain contact (242, 243) connected to the source / drain region of each transistor. The gate contact (241) and the source / drain contact (242, 243) may be disposed on the aforementioned medium plate.

[0153] Referring to FIG. 10, the respective source / drain regions (S / D) of the first to third source follower transistors (SX1, SX2, SX3) can be connected to contacts (242a, 242b, 242c) disposed on the second substrate (210).

[0154] Referring to FIGS. 10 and 11, the first source follower transistor (SX1) can be connected to the second wiring pattern (245) through the gate contact (241a). The second source follower transistor (SX2) can be connected to the second wiring pattern (245) through the gate contact (241b). The third source follower transistor (SX3) can be electrically connected to the second wiring structure (IS2) through the gate contact (241c).

[0155] The first to third source follower transistors (SX1, SX2, SX3) can be electrically connected to a floating diffusion region (FD) using a plurality of contacts, a plurality of wiring patterns, and a bonding pad.

[0156] Referring to FIG. 11, the first to third source follower transistors (SX1, SX2, SX3) may share a single source / drain region (S_S / D) within an active region (ACT). The shared source / drain region (S_S / D) may be placed between a plurality of adjacent pixel regions (PX). The shared source / drain region (S_S / D) may be connected to the second wiring pattern (245) of the second wiring structure (IS2) through a shared source / drain contact (243).

[0157] The contacts (241a, 241b, 243), the second wiring patterns (245) and the vias (249) may each include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag) and alloys thereof, but are not limited thereto.

[0158] The second bonding pad (BP2) may be placed within the second wiring insulating film (240). Within the second wiring insulating film (240), one side of the second bonding pad (BP2) may be exposed. The upper surface of the second bonding pad (BP2) may be located in the same plane as the upper surface of the second wiring insulating film (240). The second bonding pad (BP2) may be bonded to the first bonding pad (BP1). The first wiring insulating film (140) and the second wiring insulating film (240) may be bonded to each other using the first bonding pad (BP1) and the second bonding pad (BP2).

[0159] The first and second bonding pads (BP1, BP2) may include, for example, copper (Cu), but are not limited thereto.

[0160] Although not specifically illustrated, some of the second wiring patterns (245) may extend from the sensor array region (SAR) to the pad region (PR). Some of the second wiring patterns (245) may be electrically connected to the pad region (PR). Some of the second wiring patterns (245) may be connected to the third transistor (TR3) through a through-via (TSV).

[0161] Referring to FIG. 11, the third substrate (310) may include an upper surface (310a) facing the second semiconductor chip (200). Third transistors (TR3) may be formed on the upper surface (310a) of the third substrate (310). The third transistors (TR3) may be, for example, the logic circuit of FIG. 9. The third transistors (TR3) may be electrically connected to the transistors of the second semiconductor chip (200).

[0162] A third wiring structure (IS3) may be formed on a third substrate (310). For example, the third wiring structure (IS3) may cover the upper surface (310a) of the third substrate (310). The third substrate (310) and the third wiring structure (IS3) may constitute a third semiconductor chip (300).

[0163] The third wiring structure (IS3) can be attached to the second substrate (210). For example, the third surface (210b) of the second substrate (210) can be attached to the upper surface (310a) of the third wiring structure (IS3).

[0164] The third wiring structure (IS3) may include a third wiring insulating film (340), contacts (341), third wiring patterns (345), and vias (349).

[0165] In FIGS. 11 and 12, the number of layers of wiring patterns constituting the third wiring structure (IS3) and their arrangement are merely exemplary and are not limited thereto. The third wiring insulating film (340) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material with a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0166] The contacts (341) can be connected to the third transistor (TR3) and the third wiring patterns (345). The third wiring patterns (345), the contacts (341), and the vias (349) may each include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but are not limited thereto.

[0167] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0168] 110: First substrate PD: Photoelectric conversion layer PX: Pixel area 120: Pixel separation pattern 150: Surface insulating film 180: Microlens 210: Second substrate 310: Third substrate

Claims

Claim 1 An image sensor comprising: a first substrate including first and second surfaces facing each other and an active region disposed on the first surface; a plurality of pixel regions including a photoelectric conversion layer on the first surface of the first substrate; a pixel separation pattern defining the plurality of pixel regions in a direction perpendicular to the first surface of the first substrate; and first to third transistors corresponding to each of the plurality of pixel regions, wherein the first to third transistors share a single source / drain region within the active region, and the gate of each of the first to third transistors is connected to a floating diffusion region configured to store a charge generated in the photoelectric conversion layer. Claim 2 An image sensor according to claim 1, wherein the shared source / drain region is disposed between the adjacent plurality of pixel regions, and, from a planar perspective, the shared source / drain region is connected to one another by the active region formed radially within the first substrate. Claim 3 In claim 1, the shared source / drain region is an image sensor that does not overlap with the pixel separation pattern between the plurality of pixel regions in the vertical direction. Claim 4 An image sensor according to claim 1, further comprising a first wiring structure disposed on a first surface of the first substrate, wherein a non-shared source / drain region of the first transistor is connected to the first wiring structure through a first source / drain contact, a non-shared source / drain region of the second transistor is connected to the first wiring structure through a second source / drain contact, and a shared source / drain region is connected to the first wiring structure through a shared source / drain contact. Claim 5 In claim 4, the image sensor further comprises a floating diffusion region on the first surface of the first substrate for storing charges generated by the photoelectric conversion layer, and the first to third transistors are connected to the floating diffusion region through the first wiring structure. Claim 6 An image sensor according to claim 5, further comprising a reset transistor, a select transistor, and a dual conversion transistor connected to the floating diffusion region on the first surface of the first substrate. Claim 7 In claim 6, the reset transistor is an image sensor connected to the shared source / drain region. Claim 8 An image sensor comprising: a substrate including a device isolation region and an active region; a plurality of pixel regions including a photoelectric conversion layer, a floating diffusion region, a transfer transistor electrically connected to the floating diffusion region, and first to third source follower transistors on the substrate; and a pixel isolation pattern penetrating the substrate and defining each of the plurality of pixel regions, wherein each of the first to third source follower transistors includes a first to third source region connected to each of the first to third source contacts and a shared drain region connected to one drain contact, and the gate of each of the first to third transistors is connected to the floating diffusion region. Claim 9 In claim 8, the image sensor in which the gate contacts of each of the first to third source follower transistors form a triangular shape from a planar perspective. Claim 10 In claim 8, the drain contact is an image sensor that does not overlap with the pixel separation pattern between the plurality of pixel regions.

Images